stats: Update stats for DRAM changes
authorAndreas Hansson <andreas.hansson@arm.com>
Sun, 23 Mar 2014 15:12:19 +0000 (11:12 -0400)
committerAndreas Hansson <andreas.hansson@arm.com>
Sun, 23 Mar 2014 15:12:19 +0000 (11:12 -0400)
This patch updates the stats to reflect the changes to the DRAM
controller.

51 files changed:
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt
tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt
tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt
tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt
tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt
tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt
tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/stats.txt

index 4177c2e350c76606d3e39fd7ec8fd7fdd391ab01..bc7291548abf9ff47be0dd6334f15330e8a2c2a8 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.903338                       # Number of seconds simulated
-sim_ticks                                1903338216000                       # Number of ticks simulated
-final_tick                               1903338216000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.905240                       # Number of seconds simulated
+sim_ticks                                1905239522500                       # Number of ticks simulated
+final_tick                               1905239522500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 150214                       # Simulator instruction rate (inst/s)
-host_op_rate                                   150214                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             5096064990                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 314972                       # Number of bytes of host memory used
-host_seconds                                   373.49                       # Real time elapsed on the host
-sim_insts                                    56103611                       # Number of instructions simulated
-sim_ops                                      56103611                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 125426                       # Simulator instruction rate (inst/s)
+host_op_rate                                   125426                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             4213194084                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 351852                       # Number of bytes of host memory used
+host_seconds                                   452.21                       # Real time elapsed on the host
+sim_insts                                    56718526                       # Number of instructions simulated
+sim_ops                                      56718526                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.inst           740992                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         24346432                       # Number of bytes read from this memory
-system.physmem.bytes_read::tsunami.ide        2650176                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           236544                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data           996032                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             28970176                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       740992                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       236544                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          977536                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7923904                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7923904                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst             11578                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            380413                       # Number of read requests responded to by this memory
-system.physmem.num_reads::tsunami.ide           41409                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              3696                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             15563                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                452659                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          123811                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               123811                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst              389312                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            12791438                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide           1392383                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst              124278                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              523308                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                15220719                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         389312                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst         124278                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             513590                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           4163161                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4163161                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           4163161                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             389312                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           12791438                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide          1392383                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst             124278                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             523308                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               19383880                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        452659                       # Number of read requests accepted
-system.physmem.writeReqs                       123811                       # Number of write requests accepted
-system.physmem.readBursts                      452659                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     123811                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 28966400                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      3776                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7923264                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  28970176                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7923904                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                       59                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu0.inst           764480                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         24384256                       # Number of bytes read from this memory
+system.physmem.bytes_read::tsunami.ide        2649344                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           214080                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data           925440                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             28937600                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       764480                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       214080                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          978560                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7885248                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7885248                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst             11945                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            381004                       # Number of read requests responded to by this memory
+system.physmem.num_reads::tsunami.ide           41396                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              3345                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             14460                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                452150                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          123207                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               123207                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst              401251                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data            12798525                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide           1390557                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst              112364                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              485734                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                15188432                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         401251                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst         112364                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             513615                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           4138717                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                4138717                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           4138717                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             401251                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           12798525                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide          1390557                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst             112364                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             485734                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               19327149                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        452150                       # Number of read requests accepted
+system.physmem.writeReqs                       123207                       # Number of write requests accepted
+system.physmem.readBursts                      452150                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     123207                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 28929984                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      7616                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7883136                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  28937600                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7885248                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      119                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           3474                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               28542                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               28115                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               28449                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               28319                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               28001                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               28388                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               28437                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               28681                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               28670                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               28576                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              28034                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              27899                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              27884                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              28245                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              28268                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              28092                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                8222                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7571                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                7821                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                7782                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7428                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7859                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                7924                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                7992                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7912                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                7920                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7418                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               7297                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7319                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               7829                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7922                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7585                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs           5017                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               28700                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               28863                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               29008                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               28541                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               28135                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               28059                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               27918                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               27861                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               27885                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               28003                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              27955                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              28030                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              28165                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              28514                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              28239                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              28155                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                8383                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                8222                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                8291                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                7900                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7506                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7518                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                7426                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                7231                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7193                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                7295                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7315                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               7381                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7680                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8142                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               8013                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7678                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          11                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1903333578000                       # Total gap between requests
+system.physmem.numWrRetry                          10                       # Number of times write queue was full causing retry
+system.physmem.totGap                    1905235063000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  452659                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  452150                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 123811                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    323009                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     67548                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     34699                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      6478                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      2371                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      2334                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      1401                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      1384                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      1370                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      1491                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                     1342                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                     1292                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                     1112                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      975                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      964                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      959                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      957                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                      955                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                      964                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                      962                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                       15                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        9                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        5                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23                        4                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 123207                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    319865                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     54341                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     31702                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      9495                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      1181                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      4300                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      3776                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      3798                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      3977                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                      2606                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                     2173                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                     2035                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                     1927                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                     1842                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                     1542                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                     1515                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                     1493                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                     1512                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                     1685                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                     1253                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        9                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        4                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
@@ -143,461 +143,375 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                      4849                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                      4883                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                      4897                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                      5584                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                      6333                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                      5671                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                      5669                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                      5751                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                      5810                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                      5108                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                     5105                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                     5103                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                     5948                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                     6051                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                     6046                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     6136                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     6172                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5299                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5396                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5248                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     5812                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     6208                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                      343                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                      192                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                       46                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                       30                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                       22                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                       22                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                       18                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                       18                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                       17                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                       24                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        47120                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      782.856367                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     226.112166                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev    1866.075506                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64-67          16751     35.55%     35.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-131         6847     14.53%     50.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192-195         4876     10.35%     60.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-259         2833      6.01%     66.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320-323         1808      3.84%     70.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-387         1449      3.08%     73.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448-451         1103      2.34%     75.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-515          806      1.71%     77.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576-579          633      1.34%     78.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-643          628      1.33%     80.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704-707          650      1.38%     81.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-771          508      1.08%     82.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832-835          311      0.66%     83.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-899          305      0.65%     83.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960-963          262      0.56%     84.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1027          366      0.78%     85.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088-1091          155      0.33%     85.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152-1155          210      0.45%     85.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216-1219          130      0.28%     86.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280-1283          135      0.29%     86.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344-1347          148      0.31%     86.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408-1411          388      0.82%     87.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472-1475          228      0.48%     88.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536-1539          713      1.51%     89.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600-1603          124      0.26%     89.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664-1667           79      0.17%     90.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1728-1731           68      0.14%     90.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1792-1795          140      0.30%     90.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856-1859           59      0.13%     90.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1920-1923           90      0.19%     90.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984-1987           49      0.10%     90.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2048-2051           89      0.19%     91.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112-2115           69      0.15%     91.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2176-2179           88      0.19%     91.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2240-2243           28      0.06%     91.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2304-2307           26      0.06%     91.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2368-2371           54      0.11%     91.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2432-2435           52      0.11%     91.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2496-2499           27      0.06%     91.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2560-2563           28      0.06%     91.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2624-2627           27      0.06%     91.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2688-2691           54      0.11%     92.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2752-2755           53      0.11%     92.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2816-2819           17      0.04%     92.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2880-2883           31      0.07%     92.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2944-2947           83      0.18%     92.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3008-3011           40      0.08%     92.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3072-3075           35      0.07%     92.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3136-3139           42      0.09%     92.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3200-3203           86      0.18%     92.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3264-3267           24      0.05%     92.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3328-3331           15      0.03%     93.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3392-3395           51      0.11%     93.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3456-3459           50      0.11%     93.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3520-3523           24      0.05%     93.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3584-3587           22      0.05%     93.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3648-3651           24      0.05%     93.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3712-3715           52      0.11%     93.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3776-3779           51      0.11%     93.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3840-3843           12      0.03%     93.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3904-3907           29      0.06%     93.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3968-3971           84      0.18%     93.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4032-4035           41      0.09%     93.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4096-4099           31      0.07%     94.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4160-4163           38      0.08%     94.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4224-4227           87      0.18%     94.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4288-4291           24      0.05%     94.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4352-4355           17      0.04%     94.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4416-4419           52      0.11%     94.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4480-4483           51      0.11%     94.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4544-4547           24      0.05%     94.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4608-4611           22      0.05%     94.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4672-4675           23      0.05%     94.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4736-4739           50      0.11%     94.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4800-4803           51      0.11%     94.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4864-4867           12      0.03%     94.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4928-4931           27      0.06%     95.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4992-4995           86      0.18%     95.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5056-5059           41      0.09%     95.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5120-5123           30      0.06%     95.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5184-5187           39      0.08%     95.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5248-5251           84      0.18%     95.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5312-5315           24      0.05%     95.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5376-5379            9      0.02%     95.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5440-5443           53      0.11%     95.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5504-5507           50      0.11%     95.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5568-5571           23      0.05%     95.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5632-5635           22      0.05%     95.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5696-5699           22      0.05%     96.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5760-5763           49      0.10%     96.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5824-5827           50      0.11%     96.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5888-5891            9      0.02%     96.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5952-5955           25      0.05%     96.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6016-6019           85      0.18%     96.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6080-6083           41      0.09%     96.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6144-6147           30      0.06%     96.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6208-6211           42      0.09%     96.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6272-6275           84      0.18%     96.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6336-6339           24      0.05%     96.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6400-6403           10      0.02%     96.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6464-6467           52      0.11%     97.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6528-6531           52      0.11%     97.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6592-6595           24      0.05%     97.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6656-6659           22      0.05%     97.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6720-6723           25      0.05%     97.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6784-6787           49      0.10%     97.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6848-6851           49      0.10%     97.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6912-6915            8      0.02%     97.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6976-6979           27      0.06%     97.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7040-7043           87      0.18%     97.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7104-7107           41      0.09%     97.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7168-7171          317      0.67%     98.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7232-7235            1      0.00%     98.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7296-7299            2      0.00%     98.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7360-7363            1      0.00%     98.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7424-7427            6      0.01%     98.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7488-7491            1      0.00%     98.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7616-7619            1      0.00%     98.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7680-7683           14      0.03%     98.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7744-7747            2      0.00%     98.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7936-7939            8      0.02%     98.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8000-8003            1      0.00%     98.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8128-8131            3      0.01%     98.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8192-8195          322      0.68%     99.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8256-8259            1      0.00%     99.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8384-8387            1      0.00%     99.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8448-8451            1      0.00%     99.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8640-8643            1      0.00%     99.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8704-8707            2      0.00%     99.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8768-8771            1      0.00%     99.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8896-8899            1      0.00%     99.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8960-8963            1      0.00%     99.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9024-9027            1      0.00%     99.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9088-9091            2      0.00%     99.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9216-9219            2      0.00%     99.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9344-9347            3      0.01%     99.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9472-9475            1      0.00%     99.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9664-9667            1      0.00%     99.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9728-9731            2      0.00%     99.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9856-9859            3      0.01%     99.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10176-10179            1      0.00%     99.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10304-10307            2      0.00%     99.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10880-10883            1      0.00%     99.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11328-11331            2      0.00%     99.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11392-11395            2      0.00%     99.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11456-11459            2      0.00%     99.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11520-11523            1      0.00%     99.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11584-11587            2      0.00%     99.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11648-11651            1      0.00%     99.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11712-11715            1      0.00%     99.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11776-11779            1      0.00%     99.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11840-11843            1      0.00%     99.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11904-11907            2      0.00%     99.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11968-11971            1      0.00%     99.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12032-12035            4      0.01%     99.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12416-12419            1      0.00%     99.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12480-12483            1      0.00%     99.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12544-12547            2      0.00%     99.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12672-12675            2      0.00%     99.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13056-13059            2      0.00%     99.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13248-13251            2      0.00%     99.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13312-13315            3      0.01%     99.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13504-13507            1      0.00%     99.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13568-13571            2      0.00%     99.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13696-13699            3      0.01%     99.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13952-13955            1      0.00%     99.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14144-14147            2      0.00%     99.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14208-14211            2      0.00%     99.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14272-14275            2      0.00%     99.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14336-14339            3      0.01%     99.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14592-14595            2      0.00%     99.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14784-14787            1      0.00%     99.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14976-14979            1      0.00%     99.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15040-15043            1      0.00%     99.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15232-15235            2      0.00%     99.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15360-15363           39      0.08%     99.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15552-15555            2      0.00%     99.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16000-16003            2      0.00%     99.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16064-16067            1      0.00%     99.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16192-16195            1      0.00%     99.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16384-16387          175      0.37%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          47120                       # Bytes accessed per row activation
-system.physmem.totQLat                     8783315250                       # Total ticks spent queuing
-system.physmem.totMemAccLat               16310447750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2263000000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                  5264132500                       # Total ticks spent accessing banks
-system.physmem.avgQLat                       19406.35                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    11630.87                       # Average bank access latency per DRAM burst
+system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      778                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      807                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                      994                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     2374                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     3618                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     4468                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     5021                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     5107                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     5152                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     5203                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     5917                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     5811                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     5880                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     6693                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     6628                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6580                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6554                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6131                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     3796                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                     2487                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                     1653                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                     1110                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                     1163                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                     1093                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                     1060                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                     1234                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                     1357                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                     1523                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                     1618                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                     1796                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                     1807                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                     1882                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                     1750                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                     1868                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                     1849                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                     1781                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                     1824                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                     1698                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                     1470                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                     1247                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      893                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      633                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      442                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                      275                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       56                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       38                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       26                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       23                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       24                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        51367                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      630.908404                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     404.510586                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     424.248985                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127           9707     18.90%     18.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         6974     13.58%     32.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         3124      6.08%     38.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         1892      3.68%     42.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         1518      2.96%     45.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          943      1.84%     47.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          823      1.60%     48.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          886      1.72%     50.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        25500     49.64%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          51367                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          7232                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        62.502074                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     2469.163441                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-8191           7229     99.96%     99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::40960-49151            1      0.01%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::57344-65535            1      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::196608-204799            1      0.01%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            7232                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          7232                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.031803                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.787924                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        3.763450                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               6148     85.01%     85.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 35      0.48%     85.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                 69      0.95%     86.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                422      5.84%     92.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                144      1.99%     94.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 50      0.69%     94.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 33      0.46%     95.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 29      0.40%     95.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                 50      0.69%     96.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                 33      0.46%     96.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                 22      0.30%     97.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27                 30      0.41%     97.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28                 23      0.32%     98.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29                 33      0.46%     98.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30                  3      0.04%     98.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::31                 10      0.14%     98.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32                  7      0.10%     98.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::33                  5      0.07%     98.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::34                  2      0.03%     98.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::35                  3      0.04%     98.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36                  4      0.06%     98.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::37                  3      0.04%     98.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::38                  4      0.06%     99.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::39                  6      0.08%     99.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40                  7      0.10%     99.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::41                  2      0.03%     99.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::42                  5      0.07%     99.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::43                  4      0.06%     99.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44                  2      0.03%     99.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::45                  2      0.03%     99.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::46                  2      0.03%     99.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::47                  9      0.12%     99.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48                  8      0.11%     99.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::49                  6      0.08%     99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::50                  1      0.01%     99.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::51                  4      0.06%     99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52                  3      0.04%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::53                  2      0.03%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::54                  1      0.01%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::55                  4      0.06%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56                  2      0.03%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            7232                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    10473139750                       # Total ticks spent queuing
+system.physmem.totMemAccLat               18209837250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2260155000                       # Total ticks spent in databus transfers
+system.physmem.totBankLat                  5476542500                       # Total ticks spent accessing banks
+system.physmem.avgQLat                       23169.07                       # Average queueing delay per DRAM burst
+system.physmem.avgBankLat                    12115.41                       # Average bank access latency per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  36037.22                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          15.22                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           4.16                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       15.22                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        4.16                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  40284.49                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          15.18                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           4.14                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       15.19                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        4.14                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.15                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.12                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         0.01                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                         9.32                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     430734                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     98547                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   95.17                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  79.59                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3301704.47                       # Average gap between requests
-system.physmem.pageHitRate                      91.82                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               0.41                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                     19439855                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq              296479                       # Transaction distribution
-system.membus.trans_dist::ReadResp             296230                       # Transaction distribution
-system.membus.trans_dist::WriteReq              12351                       # Transaction distribution
-system.membus.trans_dist::WriteResp             12351                       # Transaction distribution
-system.membus.trans_dist::Writeback            123811                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             5304                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq           1475                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            3474                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            164353                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           164224                       # Transaction distribution
-system.membus.trans_dist::BadAddressError          249                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        39094                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       915454                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio          498                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       955046                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124656                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       124656                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1079702                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave        68202                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     31586624                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::total     31654826                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      5307456                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::total      5307456                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            36962282                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus               36962282                       # Total data (bytes)
-system.membus.snoop_data_through_bus            38336                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy            36252500                       # Layer occupancy (ticks)
+system.physmem.avgRdQLen                         1.83                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        26.68                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     407908                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     99848                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   90.24                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  81.04                       # Row buffer hit rate for writes
+system.physmem.avgGap                      3311396.34                       # Average gap between requests
+system.physmem.pageHitRate                      88.27                       # Row buffer hit rate, read and write combined
+system.physmem.prechargeAllPercent               0.40                       # Percentage of time for which DRAM has all the banks in precharge state
+system.membus.throughput                     19386335                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq              296672                       # Transaction distribution
+system.membus.trans_dist::ReadResp             296448                       # Transaction distribution
+system.membus.trans_dist::WriteReq              13044                       # Transaction distribution
+system.membus.trans_dist::WriteResp             13044                       # Transaction distribution
+system.membus.trans_dist::Writeback            123207                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             9628                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq           5545                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            5017                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            163957                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           163513                       # Transaction distribution
+system.membus.trans_dist::BadAddressError          224                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        40492                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       924104                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio          448                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       965044                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124646                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       124646                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1089690                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave        73787                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     31516032                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::total     31589819                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      5306816                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::total      5306816                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total            36896635                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               36896635                       # Total data (bytes)
+system.membus.snoop_data_through_bus            38976                       # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy            37949499                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy          1624596499                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy          1621348498                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy              317500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy              283500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         3836772510                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         3837196476                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
-system.membus.respLayer2.occupancy          376321991                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy          376708248                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.l2c.tags.replacements                   345713                       # number of replacements
-system.l2c.tags.tagsinuse                65292.619294                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    2607692                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   410924                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     6.345923                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle               7069563750                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   53648.503329                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     4120.078366                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     5598.798644                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     1365.340117                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data      559.898838                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.818611                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.062867                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.085431                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.020833                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.008543                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.996286                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024        65211                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0          179                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1         2154                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         5524                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         6881                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        50473                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024     0.995041                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 27399611                       # Number of tag accesses
-system.l2c.tags.data_accesses                27399611                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.inst             754547                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             572386                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             313557                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data             249669                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1890159                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          840492                       # number of Writeback hits
-system.l2c.Writeback_hits::total               840492                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data             130                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data              74                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                 204                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data            37                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data            33                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total                70                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           144073                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            44330                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               188403                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.inst              754547                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              716459                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              313557                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              293999                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2078562                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst             754547                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             716459                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             313557                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             293999                       # number of overall hits
-system.l2c.overall_hits::total                2078562                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.inst            11586                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data           272059                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst             3706                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data             1775                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total               289126                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data          2565                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data           587                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              3152                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data           58                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data          107                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total             165                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data         108741                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          14088                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             122829                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.inst             11586                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            380800                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              3706                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data             15863                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                411955                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst            11586                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           380800                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             3706                       # number of overall misses
-system.l2c.overall_misses::cpu1.data            15863                       # number of overall misses
-system.l2c.overall_misses::total               411955                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.inst    929054999                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data  17693461250                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst    314236981                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data    144928247                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total    19081681477                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0.data       842965                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data      1256946                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total      2099911                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data       221993                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data       116495                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total       338488                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data   8947158383                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data   1452475204                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total  10399633587                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.inst    929054999                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data  26640619633                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst    314236981                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data   1597403451                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total     29481315064                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.inst    929054999                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data  26640619633                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst    314236981                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data   1597403451                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    29481315064                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.inst         766133                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data         844445                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst         317263                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data         251444                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2179285                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       840492                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           840492                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data         2695                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data          661                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            3356                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data           95                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data          140                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total           235                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       252814                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data        58418                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           311232                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst          766133                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data         1097259                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          317263                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          309862                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2490517                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         766133                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data        1097259                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         317263                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         309862                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2490517                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.015123                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.322175                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.011681                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.007059                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.132670                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.951763                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.888048                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.939213                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.610526                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.764286                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.702128                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.430123                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.241159                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.394654                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.015123                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.347047                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.011681                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.051194                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.165409                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.015123                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.347047                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.011681                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.051194                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.165409                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 80187.726480                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 65035.382950                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 84791.414193                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 81649.716620                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 65997.805376                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   328.641326                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  2141.304940                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total   666.215419                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  3827.465517                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  1088.738318                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  2051.442424                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 82279.530104                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 103100.170642                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 84667.575141                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 80187.726480                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 69959.610381                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 84791.414193                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 100699.959087                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 71564.406462                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 80187.726480                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 69959.610381                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 84791.414193                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 100699.959087                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 71564.406462                       # average overall miss latency
+system.l2c.tags.replacements                   345233                       # number of replacements
+system.l2c.tags.tagsinuse                65245.285653                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    2551644                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   410415                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     6.217229                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle               7106352750                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks   53519.548176                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     4149.494238                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     5612.081999                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     1358.843164                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data      605.318076                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.816643                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.063316                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.085634                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.020734                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.009236                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.995564                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1024        65182                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0          231                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1         2472                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         5440                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         5794                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        51245                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1024     0.994598                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 26808140                       # Number of tag accesses
+system.l2c.tags.data_accesses                26808140                       # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.inst             890534                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data             623023                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst             181208                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data             171976                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1866741                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          807199                       # number of Writeback hits
+system.l2c.Writeback_hits::total               807199                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data             179                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data             196                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                 375                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data            42                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data            30                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total                72                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data           156975                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            15152                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               172127                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.inst              890534                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              779998                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              181208                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              187128                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 2038868                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.inst             890534                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             779998                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             181208                       # number of overall hits
+system.l2c.overall_hits::cpu1.data             187128                       # number of overall hits
+system.l2c.overall_hits::total                2038868                       # number of overall hits
+system.l2c.ReadReq_misses::cpu0.inst            11953                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data           272223                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst             3356                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data             1782                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total               289314                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data          3186                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data           726                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              3912                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data          379                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data          428                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total             807                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data         109189                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data          13070                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             122259                       # number of ReadExReq misses
+system.l2c.demand_misses::cpu0.inst             11953                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data            381412                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst              3356                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data             14852                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                411573                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.inst            11953                       # number of overall misses
+system.l2c.overall_misses::cpu0.data           381412                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst             3356                       # number of overall misses
+system.l2c.overall_misses::cpu1.data            14852                       # number of overall misses
+system.l2c.overall_misses::total               411573                       # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu0.inst    917004250                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.data  17843471250                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst    269423486                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data    137552496                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total    19167451482                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu0.data      1326945                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data       933461                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total      2260406                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data       265489                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data      2039412                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total      2304901                       # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data   9056624622                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data   1307071580                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total  10363696202                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu0.inst    917004250                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data  26900095872                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst    269423486                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data   1444624076                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total     29531147684                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.inst    917004250                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data  26900095872                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst    269423486                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data   1444624076                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total    29531147684                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.inst         902487                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data         895246                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst         184564                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data         173758                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            2156055                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       807199                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           807199                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data         3365                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data          922                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            4287                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data          421                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data          458                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total           879                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       266164                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data        28222                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           294386                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.inst          902487                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data         1161410                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          184564                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data          201980                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             2450441                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         902487                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data        1161410                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         184564                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data         201980                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            2450441                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.013245                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.304076                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst      0.018183                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data      0.010256                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.134187                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.946805                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.787419                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.912526                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.900238                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.934498                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.918089                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.410232                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.463114                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.415302                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.013245                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.328404                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.018183                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.073532                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.167959                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.013245                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.328404                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.018183                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.073532                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.167959                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu0.inst 76717.497699                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.data 65547.258130                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 80281.134088                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 77189.952862                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 66251.379062                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   416.492467                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  1285.758953                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total   577.813395                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data   700.498681                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  4764.981308                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total  2856.135068                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 82944.478125                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 100005.476664                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 84768.370443                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 76717.497699                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 70527.660042                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 80281.134088                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 97267.982494                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 71751.907156                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 76717.497699                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 70527.660042                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 80281.134088                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 97267.982494                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 71751.907156                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -606,125 +520,125 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               82291                       # number of writebacks
-system.l2c.writebacks::total                    82291                       # number of writebacks
+system.l2c.writebacks::writebacks               81684                       # number of writebacks
+system.l2c.writebacks::total                    81684                       # number of writebacks
 system.l2c.ReadReq_mshr_hits::cpu0.inst             7                       # number of ReadReq MSHR hits
 system.l2c.ReadReq_mshr_hits::cpu0.data             1                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.inst            10                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total                18                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu1.inst            11                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::total                19                       # number of ReadReq MSHR hits
 system.l2c.demand_mshr_hits::cpu0.inst              7                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_hits::cpu0.data              1                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst             10                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                 18                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.inst             11                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                 19                       # number of demand (read+write) MSHR hits
 system.l2c.overall_mshr_hits::cpu0.inst             7                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::cpu0.data             1                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst            10                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                18                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu0.inst        11579                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.data       272058                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst         3696                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data         1775                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total          289108                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data         2565                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data          587                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total         3152                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data           58                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          107                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total          165                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data       108741                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data        14088                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        122829                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst        11579                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data       380799                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst         3696                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data        15863                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           411937                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst        11579                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data       380799                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst         3696                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data        15863                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          411937                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    782519751                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.data  14298950750                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    266998019                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data    147305751                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total  15495774271                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     25723531                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data      5884082                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total     31607613                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data       641556                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      1072106                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total      1713662                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   7614105115                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   1279019296                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   8893124411                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst    782519751                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data  21913055865                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst    266998019                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data   1426325047                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total  24388898682                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst    782519751                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data  21913055865                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst    266998019                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data   1426325047                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  24388898682                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data    931434500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    458421000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   1389855500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   1577498000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    884169000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   2461667000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   2508932500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data   1342590000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   3851522500                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.015114                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.322174                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.011650                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.007059                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.132662                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.951763                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.888048                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.939213                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.610526                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.764286                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.702128                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.430123                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.241159                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.394654                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.015114                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.347046                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.011650                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.051194                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.165402                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.015114                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.347046                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.011650                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.051194                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.165402                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 67580.944037                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52558.464555                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 72239.723755                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 82989.155493                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 53598.566179                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10028.667057                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10023.989779                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10027.796003                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 11061.310345                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10019.682243                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10385.830303                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 70020.554483                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 90787.854628                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 72402.481588                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 67580.944037                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 57544.940677                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72239.723755                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 89915.214461                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 59205.409279                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 67580.944037                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57544.940677                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72239.723755                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 89915.214461                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 59205.409279                       # average overall mshr miss latency
+system.l2c.overall_mshr_hits::cpu1.inst            11                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total                19                       # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses::cpu0.inst        11946                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.data       272222                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.inst         3345                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.data         1782                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total          289295                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data         3186                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data          726                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total         3912                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          379                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          428                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total          807                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data       109189                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data        13070                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        122259                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst        11946                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data       381411                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst         3345                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data        14852                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           411554                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst        11946                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data       381411                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst         3345                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data        14852                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          411554                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    765862000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.data  14447057750                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    226574764                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data    136795504                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total  15576290018                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     31921141                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data      7272722                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total     39193863                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      3803378                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      4284427                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total      8087805                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   7721269876                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   1146179920                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   8867449796                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst    765862000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data  22168327626                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst    226574764                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data   1282975424                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  24443739814                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst    765862000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data  22168327626                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst    226574764                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data   1282975424                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  24443739814                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data    936599500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    454544000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   1391143500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   1663713500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    943761500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   2607475000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   2600313000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data   1398305500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   3998618500                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.013237                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.304075                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.018124                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.010256                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.134178                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.946805                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.787419                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.912526                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.900238                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.934498                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.918089                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.410232                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.463114                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.415302                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.013237                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.328403                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.018124                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.073532                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.167951                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.013237                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.328403                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.018124                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.073532                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.167951                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 64110.329818                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 53070.867711                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 67735.355456                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 76765.153760                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 53842.237225                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10019.190521                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10017.523416                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10018.881135                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10035.298153                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10010.343458                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10022.063197                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 70714.722875                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 87695.479725                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 72530.037020                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 64110.329818                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58121.888530                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 67735.355456                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 86384.017237                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 59393.760756                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 64110.329818                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58121.888530                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 67735.355456                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 86384.017237                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 59393.760756                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -735,15 +649,15 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.iocache.tags.replacements                41695                       # number of replacements
-system.iocache.tags.tagsinuse                0.213166                       # Cycle average of tags in use
+system.iocache.tags.replacements                41698                       # number of replacements
+system.iocache.tags.tagsinuse                0.475429                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                41711                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs                41714                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1712301131000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     0.213166                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.013323                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.013323                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         1712299730000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide     0.475429                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide     0.029714                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.029714                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -757,14 +671,14 @@ system.iocache.demand_misses::tsunami.ide        41727                       # n
 system.iocache.demand_misses::total             41727                       # number of demand (read+write) misses
 system.iocache.overall_misses::tsunami.ide        41727                       # number of overall misses
 system.iocache.overall_misses::total            41727                       # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide     21368383                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     21368383                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::tsunami.ide  13021515788                       # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total  13021515788                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide  13042884171                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total  13042884171                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide  13042884171                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total  13042884171                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::tsunami.ide     21363133                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     21363133                       # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::tsunami.ide  13166015946                       # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total  13166015946                       # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide  13187379079                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total  13187379079                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide  13187379079                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total  13187379079                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::tsunami.ide          175                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            175                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
@@ -781,24 +695,24 @@ system.iocache.demand_miss_rate::tsunami.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122105.045714                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 122105.045714                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::tsunami.ide 313378.797362                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 313378.797362                       # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 312576.609174                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 312576.609174                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 312576.609174                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 312576.609174                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs        407057                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122075.045714                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 122075.045714                       # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::tsunami.ide 316856.371438                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 316856.371438                       # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 316039.472739                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 316039.472739                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 316039.472739                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 316039.472739                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs        391077                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                29358                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                28468                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs    13.865284                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs    13.737424                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks           41520                       # number of writebacks
-system.iocache.writebacks::total                41520                       # number of writebacks
+system.iocache.writebacks::writebacks           41523                       # number of writebacks
+system.iocache.writebacks::total                41523                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::tsunami.ide          175                       # number of ReadReq MSHR misses
 system.iocache.ReadReq_mshr_misses::total          175                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::tsunami.ide        41552                       # number of WriteReq MSHR misses
@@ -807,14 +721,14 @@ system.iocache.demand_mshr_misses::tsunami.ide        41727
 system.iocache.demand_mshr_misses::total        41727                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::tsunami.ide        41727                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total        41727                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12267383                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     12267383                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::tsunami.ide  10859254806                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total  10859254806                       # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide  10871522189                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total  10871522189                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide  10871522189                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total  10871522189                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12262133                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     12262133                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::tsunami.ide  11002982450                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total  11002982450                       # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide  11015244583                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total  11015244583                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide  11015244583                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total  11015244583                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
@@ -823,14 +737,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70099.331429                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 70099.331429                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 261341.326675                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 261341.326675                       # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 260539.271671                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 260539.271671                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 260539.271671                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 260539.271671                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70069.331429                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 70069.331429                       # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 264800.309251                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 264800.309251                       # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 263983.621708                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 263983.621708                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 263983.621708                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 263983.621708                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -844,35 +758,35 @@ system.disk2.dma_read_txs                           0                       # Nu
 system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
 system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
 system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
-system.cpu0.branchPred.lookups               11006012                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted          9319545                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect           291548                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups             7161716                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits                4729334                       # Number of BTB hits
+system.cpu0.branchPred.lookups               12197818                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted         10301308                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect           323625                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups             8091894                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits                5160475                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            66.036324                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS                 682987                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect             26515                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            63.773389                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS                 773216                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect             29770                       # Number of incorrect RAS predictions.
 system.cpu0.dtb.fetch_hits                          0                       # ITB hits
 system.cpu0.dtb.fetch_misses                        0                       # ITB misses
 system.cpu0.dtb.fetch_acv                           0                       # ITB acv
 system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu0.dtb.read_hits                     7888949                       # DTB read hits
-system.cpu0.dtb.read_misses                     30101                       # DTB read misses
-system.cpu0.dtb.read_acv                          574                       # DTB read access violations
-system.cpu0.dtb.read_accesses                  665608                       # DTB read accesses
-system.cpu0.dtb.write_hits                    5247941                       # DTB write hits
-system.cpu0.dtb.write_misses                     8093                       # DTB write misses
-system.cpu0.dtb.write_acv                         365                       # DTB write access violations
-system.cpu0.dtb.write_accesses                 232480                       # DTB write accesses
-system.cpu0.dtb.data_hits                    13136890                       # DTB hits
-system.cpu0.dtb.data_misses                     38194                       # DTB misses
-system.cpu0.dtb.data_acv                          939                       # DTB access violations
-system.cpu0.dtb.data_accesses                  898088                       # DTB accesses
-system.cpu0.itb.fetch_hits                     973403                       # ITB hits
-system.cpu0.itb.fetch_misses                    31216                       # ITB misses
-system.cpu0.itb.fetch_acv                        1004                       # ITB acv
-system.cpu0.itb.fetch_accesses                1004619                       # ITB accesses
+system.cpu0.dtb.read_hits                     8724392                       # DTB read hits
+system.cpu0.dtb.read_misses                     30821                       # DTB read misses
+system.cpu0.dtb.read_acv                          561                       # DTB read access violations
+system.cpu0.dtb.read_accesses                  667825                       # DTB read accesses
+system.cpu0.dtb.write_hits                    5867379                       # DTB write hits
+system.cpu0.dtb.write_misses                     8333                       # DTB write misses
+system.cpu0.dtb.write_acv                         362                       # DTB write access violations
+system.cpu0.dtb.write_accesses                 233878                       # DTB write accesses
+system.cpu0.dtb.data_hits                    14591771                       # DTB hits
+system.cpu0.dtb.data_misses                     39154                       # DTB misses
+system.cpu0.dtb.data_acv                          923                       # DTB access violations
+system.cpu0.dtb.data_accesses                  901703                       # DTB accesses
+system.cpu0.itb.fetch_hits                    1047253                       # ITB hits
+system.cpu0.itb.fetch_misses                    31067                       # ITB misses
+system.cpu0.itb.fetch_acv                         998                       # ITB acv
+system.cpu0.itb.fetch_accesses                1078320                       # ITB accesses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.read_acv                            0                       # DTB read access violations
@@ -885,269 +799,269 @@ system.cpu0.itb.data_hits                           0                       # DT
 system.cpu0.itb.data_misses                         0                       # DTB misses
 system.cpu0.itb.data_acv                            0                       # DTB access violations
 system.cpu0.itb.data_accesses                       0                       # DTB accesses
-system.cpu0.numCycles                       104578589                       # number of cpu cycles simulated
+system.cpu0.numCycles                       112262549                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles          21960114                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                      56555379                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                   11006012                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches           5412321                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                     10656012                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles                1518801                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.BlockedCycles              32354382                       # Number of cycles fetch has spent blocked
-system.cpu0.fetch.MiscStallCycles               30030                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles       204805                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles       243991                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles          103                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                  6896028                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes               198863                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.rateDist::samples          66418859                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             0.851496                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            2.187669                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles          25337690                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                      62232975                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                   12197818                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches           5933691                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                     11660813                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles                1669062                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.BlockedCycles              34963299                       # Number of cycles fetch has spent blocked
+system.cpu0.fetch.MiscStallCycles               31852                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles       204835                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles       245581                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles          284                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                  7519019                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes               220862                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.rateDist::samples          73507816                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             0.846617                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            2.186991                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0                55762847     83.96%     83.96% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                  696881      1.05%     85.01% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                 1363707      2.05%     87.06% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                  607827      0.92%     87.97% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4                 2362378      3.56%     91.53% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5                  460793      0.69%     92.22% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6                  493104      0.74%     92.97% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7                  775074      1.17%     94.13% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8                 3896248      5.87%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0                61847003     84.14%     84.14% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                  769960      1.05%     85.18% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                 1463561      1.99%     87.18% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                  676221      0.92%     88.10% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4                 2490968      3.39%     91.48% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5                  505392      0.69%     92.17% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6                  543861      0.74%     92.91% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7                  933568      1.27%     94.18% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8                 4277282      5.82%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total            66418859                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.105242                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.540793                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles                23145338                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles             31820288                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                  9657130                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles               858074                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles                938028                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved              439220                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred                31710                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts              55497748                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts                98418                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles                938028                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles                24047696                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles               12280609                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles      16434779                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                  9089203                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles              3628542                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts              52477613                       # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents                 6876                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents                427894                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LSQFullEvents              1374075                       # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.RenamedOperands           35152162                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups             63950241                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups        63830636                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups           110747                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps             30925813                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                 4226341                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts           1321793                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts        195129                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                  9844333                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads             8256385                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores            5476723                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads          1002198                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores          667476                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                  46574896                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded            1622063                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                 45553168                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued            69417                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined        5159281                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined      2712846                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved       1098313                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples     66418859                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.685847                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.329893                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total            73507816                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.108654                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.554352                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles                26369028                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles             34601594                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                 10599753                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles               908827                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles               1028613                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved              489342                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred                35202                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts              61098455                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts               108348                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles               1028613                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles                27370799                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles               12650473                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles      18559497                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                  9975684                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles              3922748                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts              57686354                       # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents                 6807                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents                465136                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LSQFullEvents              1446625                       # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.RenamedOperands           38461887                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups             70023385                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups        69867874                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups           145011                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps             33864047                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                 4597832                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts           1504040                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts        221397                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                 10820518                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads             9135753                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores            6149920                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads          1079808                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores          706714                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                  51077926                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded            1853906                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                 49994907                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued           110749                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined        5661802                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined      2962344                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved       1252355                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples     73507816                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.680130                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.328001                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0           46042875     69.32%     69.32% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1            9328009     14.04%     83.37% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2            4252197      6.40%     89.77% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3            2720710      4.10%     93.86% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4            2085310      3.14%     97.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5            1089347      1.64%     98.64% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6             576580      0.87%     99.51% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7             279468      0.42%     99.93% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8              44363      0.07%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0           51188064     69.64%     69.64% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1           10233888     13.92%     83.56% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2            4604901      6.26%     89.82% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3            2962380      4.03%     93.85% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4            2331848      3.17%     97.03% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5            1189595      1.62%     98.64% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6             642601      0.87%     99.52% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7             303208      0.41%     99.93% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8              51331      0.07%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total       66418859                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total       73507816                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu                  65077     10.66%     10.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                     0      0.00%     10.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                      0      0.00%     10.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     10.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     10.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     10.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%     10.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     10.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     10.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     10.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     10.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     10.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     10.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     10.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     10.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%     10.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     10.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%     10.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     10.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     10.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     10.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     10.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     10.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     10.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     10.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     10.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     10.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     10.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     10.66% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead                284948     46.66%     57.32% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite               260601     42.68%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu                  67972     10.01%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                     0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                      0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     10.01% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead                320913     47.27%     57.28% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite               290070     42.72%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass             3785      0.01%      0.01% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu             31229788     68.56%     68.57% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult               47289      0.10%     68.67% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     68.67% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd              14649      0.03%     68.70% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.70% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.70% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.70% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv               1883      0.00%     68.71% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.71% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.71% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.71% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.71% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.71% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.71% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.71% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.71% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.71% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.71% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.71% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.71% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.71% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.71% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.71% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.71% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.71% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     68.71% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.71% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.71% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.71% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead             8205422     18.01%     86.72% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite            5307142     11.65%     98.37% # Type of FU issued
-system.cpu0.iq.FU_type_0::IprAccess            743210      1.63%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass             3770      0.01%      0.01% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu             34052559     68.11%     68.12% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult               53588      0.11%     68.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     68.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd              16727      0.03%     68.26% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.26% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.26% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.26% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv               1883      0.00%     68.26% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.26% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.26% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.26% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.26% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.26% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.26% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.26% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.26% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.26% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.26% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.26% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.26% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.26% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.26% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.26% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.26% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.26% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     68.26% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.26% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.26% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.26% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead             9088781     18.18%     86.44% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite            5934753     11.87%     98.31% # Type of FU issued
+system.cpu0.iq.FU_type_0::IprAccess            842846      1.69%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total              45553168                       # Type of FU issued
-system.cpu0.iq.rate                          0.435588                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                     610626                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.013405                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads         157729759                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes         53136035                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses     44625486                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads             475478                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes            231159                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses       224228                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses              45911492                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                 248517                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads          497947                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total              49994907                       # Type of FU issued
+system.cpu0.iq.rate                          0.445339                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                     678955                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.013580                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads         173664474                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes         58303886                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses     48932524                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads             622859                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes            301167                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses       293964                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses              50344041                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                 326051                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads          531595                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads      1006840                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses         3517                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation        11189                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores       378910                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads      1104780                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses         2697                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation        11676                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores       443054                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads        13584                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked       146356                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads        13921                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked       147330                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles                938028                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles                8572601                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles               702117                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts           50999649                       # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts           565079                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts              8256385                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts             5476723                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts           1432117                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                572819                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents                 5269                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents         11189                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect        141170                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect       315582                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts              456752                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts             45215846                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts              7939970                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts           337321                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles               1028613                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles                8821962                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles               743484                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts           56052726                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts           628552                       # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts              9135753                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts             6149920                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts           1633160                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                601804                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents                 5465                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents         11676                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect        157790                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect       354691                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts              512481                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts             49615767                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts              8780349                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts           379139                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                      2802690                       # number of nop insts executed
-system.cpu0.iew.exec_refs                    13207799                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches                 7146234                       # Number of branches executed
-system.cpu0.iew.exec_stores                   5267829                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.432362                       # Inst execution rate
-system.cpu0.iew.wb_sent                      44934571                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                     44849714                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                 22315831                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                 29845824                       # num instructions consuming a value
+system.cpu0.iew.exec_nop                      3120894                       # number of nop insts executed
+system.cpu0.iew.exec_refs                    14670742                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches                 7826693                       # Number of branches executed
+system.cpu0.iew.exec_stores                   5890393                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.441962                       # Inst execution rate
+system.cpu0.iew.wb_sent                      49317778                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                     49226488                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                 24274382                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                 32670143                       # num instructions consuming a value
 system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate                      0.428861                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.747704                       # average fanout of values written-back
+system.cpu0.iew.wb_rate                      0.438494                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.743014                       # average fanout of values written-back
 system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts        5562563                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls         523750                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts           426483                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples     65480831                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.692465                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.608721                       # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts        6126865                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls         601551                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts           478401                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples     72479203                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.687487                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.606917                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0     48404249     73.92%     73.92% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1      7174588     10.96%     84.88% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2      3839849      5.86%     90.74% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3      2141053      3.27%     94.01% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4      1161993      1.77%     95.79% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5       481151      0.73%     96.52% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6       411214      0.63%     97.15% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7       389126      0.59%     97.74% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8      1477608      2.26%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0     53761554     74.18%     74.18% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1      7891628     10.89%     85.06% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2      4152119      5.73%     90.79% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3      2321486      3.20%     93.99% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4      1304265      1.80%     95.79% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5       530677      0.73%     96.53% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6       447192      0.62%     97.14% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7       447640      0.62%     97.76% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8      1622642      2.24%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total     65480831                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts            45343202                       # Number of instructions committed
-system.cpu0.commit.committedOps              45343202                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total     72479203                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts            49828537                       # Number of instructions committed
+system.cpu0.commit.committedOps              49828537                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                      12347358                       # Number of memory references committed
-system.cpu0.commit.loads                      7249545                       # Number of loads committed
-system.cpu0.commit.membars                     175312                       # Number of memory barriers committed
-system.cpu0.commit.branches                   6808554                       # Number of branches committed
-system.cpu0.commit.fp_insts                    222342                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                 42040123                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls              564734                       # Number of function calls committed.
-system.cpu0.commit.bw_lim_events              1477608                       # number cycles where commit BW limit reached
+system.cpu0.commit.refs                      13737839                       # Number of memory references committed
+system.cpu0.commit.loads                      8030973                       # Number of loads committed
+system.cpu0.commit.membars                     204358                       # Number of memory barriers committed
+system.cpu0.commit.branches                   7461649                       # Number of branches committed
+system.cpu0.commit.fp_insts                    291974                       # Number of committed floating point instructions.
+system.cpu0.commit.int_insts                 46136165                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls              636945                       # Number of function calls committed.
+system.cpu0.commit.bw_lim_events              1622642                       # number cycles where commit BW limit reached
 system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads                   114710793                       # The number of ROB reads
-system.cpu0.rob.rob_writes                  102749676                       # The number of ROB writes
-system.cpu0.timesIdled                         949561                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                       38159730                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                  3702093008                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                   42781436                       # Number of Instructions Simulated
-system.cpu0.committedOps                     42781436                       # Number of Ops (including micro ops) Simulated
-system.cpu0.committedInsts_total             42781436                       # Number of Instructions Simulated
-system.cpu0.cpi                              2.444485                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        2.444485                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.409084                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.409084                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads                59516377                       # number of integer regfile reads
-system.cpu0.int_regfile_writes               32453910                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                   110308                       # number of floating regfile reads
-system.cpu0.fp_regfile_writes                  111090                       # number of floating regfile writes
-system.cpu0.misc_regfile_reads                1625466                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes                747841                       # number of misc regfile writes
+system.cpu0.rob.rob_reads                   126610557                       # The number of ROB reads
+system.cpu0.rob.rob_writes                  112939421                       # The number of ROB writes
+system.cpu0.timesIdled                        1039659                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                       38754733                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                  3698211471                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                   46979170                       # Number of Instructions Simulated
+system.cpu0.committedOps                     46979170                       # Number of Ops (including micro ops) Simulated
+system.cpu0.committedInsts_total             46979170                       # Number of Instructions Simulated
+system.cpu0.cpi                              2.389624                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        2.389624                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.418476                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.418476                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads                65113755                       # number of integer regfile reads
+system.cpu0.int_regfile_writes               35503571                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                   144629                       # number of floating regfile reads
+system.cpu0.fp_regfile_writes                  146446                       # number of floating regfile writes
+system.cpu0.misc_regfile_reads                1885764                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes                851290                       # number of misc regfile writes
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
 system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
@@ -1179,81 +1093,81 @@ system.tsunami.ethernet.totalRxOrn                  0                       # to
 system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
 system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.toL2Bus.throughput                   112873708                       # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq            2210500                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2210236                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             12351                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            12351                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           840492                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq            5351                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq          1545                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp           6896                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           353777                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          312228                       # Transaction distribution
-system.toL2Bus.trans_dist::BadAddressError          249                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1532372                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2827999                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       634560                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side       901176                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               5896107                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     49032512                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    108336621                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     20304832                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     35573309                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size::total          213247274                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus             213236842                       # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus         1600000                       # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy         5059383343                       # Layer occupancy (ticks)
+system.toL2Bus.throughput                   110236199                       # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq            2184890                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2184651                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             13044                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            13044                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           807199                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq            9705                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq          5617                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp          15322                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           337408                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          295861                       # Transaction distribution
+system.toL2Bus.trans_dist::BadAddressError          224                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1805066                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      3017885                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       369158                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side       600045                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               5792154                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     57759168                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    115626954                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     11812096                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     23360753                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size::total          208558971                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus             208548411                       # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus         1477952                       # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy         4893610631                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.3                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy           733500                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy           742500                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        3452114362                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        4065813860                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.2                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        5048329138                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        5358512161                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.3                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy        1429282335                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer2.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy        1486623569                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy         831641640                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
+system.toL2Bus.respLayer3.occupancy         971081953                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.1                       # Layer utilization (%)
-system.iobus.throughput                       1434231                       # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq                 7371                       # Transaction distribution
-system.iobus.trans_dist::ReadResp                7371                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               53903                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              53903                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio        10490                       # Packet count per connected master and slave (bytes)
+system.iobus.throughput                       1435731                       # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq                 7377                       # Transaction distribution
+system.iobus.trans_dist::ReadResp                7377                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               54596                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              54596                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio        11886                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          480                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio          180                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18148                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         2468                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6674                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf          294                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total        39094                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total        40492                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83454                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::total        83454                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  122548                       # Packet count per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio        41960                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  123946                       # Packet count per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio        47544                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio         1920                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio          160                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio         9074                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio         9852                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio         4194                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf          410                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total        68202                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::total        73787                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661624                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.tsunami.ide.dma::total      2661624                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total              2729826                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus                 2729826                       # Total data (bytes)
-system.iobus.reqLayer0.occupancy              9845000                       # Layer occupancy (ticks)
+system.iobus.tot_pkt_size::total              2735411                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus                 2735411                       # Total data (bytes)
+system.iobus.reqLayer0.occupancy             11236000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy               359000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
@@ -1267,7 +1181,7 @@ system.iobus.reqLayer23.occupancy            13505000                       # La
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer24.occupancy             2450000                       # Layer occupancy (ticks)
 system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy             5166000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy             5167000                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy              184000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
@@ -1275,267 +1189,267 @@ system.iobus.reqLayer27.occupancy               76000                       # La
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy              110000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer29.occupancy           377802180                       # Layer occupancy (ticks)
+system.iobus.reqLayer29.occupancy           379995831                       # Layer occupancy (ticks)
 system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer30.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer30.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            26743000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            27448000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            42660009                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            43184752                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.cpu0.icache.tags.replacements           765570                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          509.693534                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs            6090993                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           766079                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs             7.950868                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      26716185250                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   509.693534                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.995495                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.995495                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_task_id_blocks::1024          509                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          109                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1           86                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          314                       # Occupied blocks per task id
-system.cpu0.icache.tags.occ_task_id_percent::1024     0.994141                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses          7662265                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses         7662265                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst      6090993                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total        6090993                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst      6090993                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total         6090993                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst      6090993                       # number of overall hits
-system.cpu0.icache.overall_hits::total        6090993                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       805033                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       805033                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       805033                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        805033                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       805033                       # number of overall misses
-system.cpu0.icache.overall_misses::total       805033                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  11432598915                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  11432598915                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  11432598915                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  11432598915                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  11432598915                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  11432598915                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst      6896026                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total      6896026                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst      6896026                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total      6896026                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst      6896026                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total      6896026                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.116739                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.116739                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.116739                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.116739                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.116739                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.116739                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14201.404060                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 14201.404060                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14201.404060                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 14201.404060                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14201.404060                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 14201.404060                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs         4227                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              138                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    30.630435                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu0.icache.tags.replacements           901902                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          509.676111                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs            6573395                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           902414                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs             7.284234                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      26905725250                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   509.676111                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.995461                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.995461                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0           66                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1           18                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          428                       # Occupied blocks per task id
+system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu0.icache.tags.tag_accesses          8421597                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses         8421597                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst      6573395                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total        6573395                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst      6573395                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total         6573395                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst      6573395                       # number of overall hits
+system.cpu0.icache.overall_hits::total        6573395                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       945623                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       945623                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       945623                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        945623                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       945623                       # number of overall misses
+system.cpu0.icache.overall_misses::total       945623                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  13224491137                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  13224491137                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  13224491137                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  13224491137                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  13224491137                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  13224491137                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst      7519018                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total      7519018                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst      7519018                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total      7519018                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst      7519018                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total      7519018                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.125764                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.125764                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.125764                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.125764                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.125764                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.125764                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13984.950807                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 13984.950807                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13984.950807                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 13984.950807                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13984.950807                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 13984.950807                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs         3461                       # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets          139                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              144                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets              1                       # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    24.034722                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets          139                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        38794                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        38794                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst        38794                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        38794                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst        38794                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        38794                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       766239                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       766239                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       766239                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       766239                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       766239                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       766239                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   9400829636                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total   9400829636                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   9400829636                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total   9400829636                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   9400829636                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total   9400829636                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.111113                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.111113                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.111113                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.111113                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.111113                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.111113                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12268.795553                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12268.795553                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12268.795553                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12268.795553                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12268.795553                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12268.795553                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        43044                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        43044                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst        43044                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        43044                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst        43044                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        43044                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       902579                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       902579                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       902579                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       902579                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       902579                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       902579                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  10909532635                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  10909532635                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  10909532635                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  10909532635                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  10909532635                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  10909532635                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.120039                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.120039                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.120039                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.120039                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.120039                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.120039                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12087.066766                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12087.066766                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12087.066766                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12087.066766                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12087.066766                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12087.066766                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements          1099493                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          471.490981                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs            9327298                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          1100005                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs             8.479323                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle         25754000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   471.490981                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.920881                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.920881                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.replacements          1164537                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          498.695388                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           10555909                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          1165049                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs             9.060485                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle         26173000                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   498.695388                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.974014                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.974014                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          220                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          243                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           49                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          238                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          222                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           52                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         50559091                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        50559091                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data      5751167                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        5751167                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      3244504                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       3244504                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       151160                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       151160                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       174499                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       174499                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data      8995671                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total         8995671                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data      8995671                       # number of overall hits
-system.cpu0.dcache.overall_hits::total        8995671                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      1359261                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      1359261                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1665675                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      1665675                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        17016                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        17016                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data          764                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total          764                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      3024936                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       3024936                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      3024936                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      3024936                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  36687958870                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  36687958870                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  74828467074                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  74828467074                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    254575245                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    254575245                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data      4747557                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total      4747557                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 111516425944                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 111516425944                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 111516425944                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 111516425944                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      7110428                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      7110428                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      4910179                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      4910179                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       168176                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       168176                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       175263                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       175263                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     12020607                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     12020607                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     12020607                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     12020607                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.191164                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.191164                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.339229                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.339229                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.101180                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.101180                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.004359                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.004359                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.251646                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.251646                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.251646                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.251646                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26991.106837                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 26991.106837                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44923.809911                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 44923.809911                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14960.933533                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14960.933533                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  6214.079843                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  6214.079843                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36865.714165                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 36865.714165                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36865.714165                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 36865.714165                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs      2890749                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets          819                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs            46898                       # number of cycles access was blocked
+system.cpu0.dcache.tags.tag_accesses         56283368                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        56283368                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data      6422745                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        6422745                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      3752316                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       3752316                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       172180                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       172180                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       196241                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       196241                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     10175061                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        10175061                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     10175061                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       10175061                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data      1468970                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      1468970                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      1742020                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      1742020                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        20433                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        20433                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data         2875                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total         2875                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      3210990                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       3210990                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      3210990                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      3210990                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  38326965830                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  38326965830                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  76755016444                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  76755016444                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    286872989                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    286872989                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     20380878                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total     20380878                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 115081982274                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 115081982274                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 115081982274                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 115081982274                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      7891715                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      7891715                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      5494336                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      5494336                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       192613                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       192613                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       199116                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       199116                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     13386051                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     13386051                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     13386051                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     13386051                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.186141                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.186141                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.317057                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.317057                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.106083                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.106083                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.014439                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.014439                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.239876                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.239876                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.239876                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.239876                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26091.047353                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 26091.047353                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44060.927225                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 44060.927225                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14039.690158                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14039.690158                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  7089.001043                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  7089.001043                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35840.031353                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 35840.031353                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35840.031353                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 35840.031353                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs      2903843                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets          789                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs            48428                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets              7                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    61.639068                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets          117                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    59.962067                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets   112.714286                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       594718                       # number of writebacks
-system.cpu0.dcache.writebacks::total           594718                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       521771                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       521771                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1409219                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      1409219                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         4206                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total         4206                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      1930990                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      1930990                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      1930990                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      1930990                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       837490                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       837490                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       256456                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       256456                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        12810                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total        12810                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data          764                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total          764                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      1093946                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      1093946                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      1093946                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      1093946                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  24898598196                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  24898598196                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  10973118276                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  10973118276                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    152117754                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    152117754                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data      3219443                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total      3219443                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  35871716472                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  35871716472                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  35871716472                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  35871716472                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data    993486001                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total    993486001                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1673832998                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1673832998                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   2667318999                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   2667318999                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.117783                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.117783                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.052229                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.052229                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.076170                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.076170                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.004359                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.004359                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.091006                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.091006                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.091006                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.091006                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29730.024473                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29730.024473                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42787.527981                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42787.527981                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11874.922248                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11874.922248                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  4213.930628                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  4213.930628                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32791.121748                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32791.121748                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32791.121748                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32791.121748                       # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks       644423                       # number of writebacks
+system.cpu0.dcache.writebacks::total           644423                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       578811                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       578811                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1469624                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      1469624                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         4269                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total         4269                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      2048435                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      2048435                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      2048435                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      2048435                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       890159                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       890159                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       272396                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       272396                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        16164                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total        16164                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         2875                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total         2875                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      1162555                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      1162555                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      1162555                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      1162555                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  25660783347                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  25660783347                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  11256320137                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  11256320137                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    175450760                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    175450760                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     14630122                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     14630122                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  36917103484                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  36917103484                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  36917103484                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  36917103484                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data    999097000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total    999097000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1765340999                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1765340999                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   2764437999                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   2764437999                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.112797                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.112797                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.049578                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.049578                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.083920                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.083920                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.014439                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.014439                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.086848                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.086848                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.086848                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.086848                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28827.190813                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28827.190813                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41323.367953                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41323.367953                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10854.414749                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10854.414749                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  5088.738087                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  5088.738087                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31755.145764                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31755.145764                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31755.145764                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31755.145764                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1543,35 +1457,35 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups                3875512                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted          3181518                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect           119538                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups             2413999                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits                1363069                       # Number of BTB hits
+system.cpu1.branchPred.lookups                2770041                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted          2267711                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect            80921                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups             1482926                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits                 969002                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            56.465185                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS                 281270                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect             11131                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            65.343921                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS                 198874                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect              6522                       # Number of incorrect RAS predictions.
 system.cpu1.dtb.fetch_hits                          0                       # ITB hits
 system.cpu1.dtb.fetch_misses                        0                       # ITB misses
 system.cpu1.dtb.fetch_acv                           0                       # ITB acv
 system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu1.dtb.read_hits                     2756439                       # DTB read hits
-system.cpu1.dtb.read_misses                     11971                       # DTB read misses
+system.cpu1.dtb.read_hits                     2016743                       # DTB read hits
+system.cpu1.dtb.read_misses                      9789                       # DTB read misses
 system.cpu1.dtb.read_acv                            6                       # DTB read access violations
-system.cpu1.dtb.read_accesses                  281635                       # DTB read accesses
-system.cpu1.dtb.write_hits                    1697476                       # DTB write hits
-system.cpu1.dtb.write_misses                     2261                       # DTB write misses
-system.cpu1.dtb.write_acv                          35                       # DTB write access violations
-system.cpu1.dtb.write_accesses                 106637                       # DTB write accesses
-system.cpu1.dtb.data_hits                     4453915                       # DTB hits
-system.cpu1.dtb.data_misses                     14232                       # DTB misses
-system.cpu1.dtb.data_acv                           41                       # DTB access violations
-system.cpu1.dtb.data_accesses                  388272                       # DTB accesses
-system.cpu1.itb.fetch_hits                     435796                       # ITB hits
-system.cpu1.itb.fetch_misses                     5916                       # ITB misses
-system.cpu1.itb.fetch_acv                         132                       # ITB acv
-system.cpu1.itb.fetch_accesses                 441712                       # ITB accesses
+system.cpu1.dtb.read_accesses                  278621                       # DTB read accesses
+system.cpu1.dtb.write_hits                    1132288                       # DTB write hits
+system.cpu1.dtb.write_misses                     1938                       # DTB write misses
+system.cpu1.dtb.write_acv                          37                       # DTB write access violations
+system.cpu1.dtb.write_accesses                 105909                       # DTB write accesses
+system.cpu1.dtb.data_hits                     3149031                       # DTB hits
+system.cpu1.dtb.data_misses                     11727                       # DTB misses
+system.cpu1.dtb.data_acv                           43                       # DTB access violations
+system.cpu1.dtb.data_accesses                  384530                       # DTB accesses
+system.cpu1.itb.fetch_hits                     369710                       # ITB hits
+system.cpu1.itb.fetch_misses                     5636                       # ITB misses
+system.cpu1.itb.fetch_acv                         119                       # ITB acv
+system.cpu1.itb.fetch_accesses                 375346                       # ITB accesses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.read_acv                            0                       # DTB read access violations
@@ -1584,520 +1498,519 @@ system.cpu1.itb.data_hits                           0                       # DT
 system.cpu1.itb.data_misses                         0                       # DTB misses
 system.cpu1.itb.data_acv                            0                       # DTB access violations
 system.cpu1.itb.data_accesses                       0                       # DTB accesses
-system.cpu1.numCycles                        25703316                       # number of cpu cycles simulated
+system.cpu1.numCycles                        18798992                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles           8513027                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                      18550498                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                    3875512                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches           1644339                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                      3370867                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles                 594419                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.BlockedCycles              10509044                       # Number of cycles fetch has spent blocked
-system.cpu1.fetch.MiscStallCycles               24053                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles        56236                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles       158916                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles          118                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                  2181303                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes                77306                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.rateDist::samples          23021613                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             0.805786                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            2.167146                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles           5357256                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                      13511342                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                    2770041                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches           1167876                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                      2476292                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles                 427198                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.BlockedCycles               8263333                       # Number of cycles fetch has spent blocked
+system.cpu1.fetch.MiscStallCycles               26082                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles        54640                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles       162618                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles           35                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                  1630522                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes                50477                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.rateDist::samples          16624070                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             0.812758                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            2.170685                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0                19650746     85.36%     85.36% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                  192109      0.83%     86.19% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                  424155      1.84%     88.03% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                  258878      1.12%     89.16% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4                  512227      2.22%     91.38% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5                  176251      0.77%     92.15% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6                  202668      0.88%     93.03% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7                  249358      1.08%     94.11% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8                 1355221      5.89%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0                14147778     85.10%     85.10% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                  131100      0.79%     85.89% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                  332329      2.00%     87.89% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                  198517      1.19%     89.09% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4                  395957      2.38%     91.47% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5                  132924      0.80%     92.27% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6                  159356      0.96%     93.23% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7                   93423      0.56%     93.79% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8                 1032686      6.21%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total            23021613                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.150779                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       0.721716                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                 8599650                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles             10723354                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                  3129491                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles               191921                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles                377196                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved              176309                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred                12258                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts              18185515                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts                36387                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles                377196                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles                 8917984                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles                3106321                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles       6595327                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                  2921217                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles              1103566                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts              17011608                       # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents                  230                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents                267059                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LSQFullEvents               236234                       # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.RenamedOperands           11254383                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups             20310939                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups        20246817                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups            58360                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps              9542826                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                 1711557                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts            544600                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts         54677                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                  3272980                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads             2918733                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores            1792509                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads           312208                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores          170960                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                  14943030                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded             650638                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                 14484391                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued            37394                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined        2166782                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined      1088105                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved        467114                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples     23021613                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.629165                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.310842                       # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total            16624070                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.147351                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       0.718727                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles                 5556172                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles              8353280                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                  2307081                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles               131115                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles                276421                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved              130911                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred                 7501                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts              13245951                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts                18855                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles                276421                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles                 5775463                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles                2664230                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles       4961239                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                  2147700                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles               799015                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts              12421307                       # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents                  241                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents                220838                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LSQFullEvents               145988                       # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.RenamedOperands            8355946                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups             15113763                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups        15073339                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups            35607                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps              7070748                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                 1285198                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts            385003                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts         30758                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                  2314294                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads             2123178                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores            1208247                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads           244787                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores          150121                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                  10996175                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded             428151                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                 10636944                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued            28046                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined        1617836                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined       831016                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved        312637                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples     16624070                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.639852                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.326685                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0           16750827     72.76%     72.76% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1            2784830     12.10%     84.86% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2            1224236      5.32%     90.18% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3             874900      3.80%     93.98% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4             759442      3.30%     97.27% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5             313710      1.36%     98.64% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6             192948      0.84%     99.48% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7             103377      0.45%     99.92% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8              17343      0.08%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0           12087523     72.71%     72.71% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1            1967089     11.83%     84.54% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2             877391      5.28%     89.82% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3             655455      3.94%     93.76% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4             567827      3.42%     97.18% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5             232884      1.40%     98.58% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6             149324      0.90%     99.48% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7              75580      0.45%     99.93% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8              10997      0.07%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total       23021613                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total       16624070                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                  19111      7.55%      7.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                     0      0.00%      7.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                      0      0.00%      7.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      7.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      7.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      7.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%      7.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      7.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      7.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      7.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      7.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      7.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      7.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      7.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      7.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%      7.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      7.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%      7.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      7.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      7.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      7.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      7.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      7.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      7.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      7.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      7.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      7.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      7.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      7.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead                130840     51.68%     59.23% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite               103199     40.77%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                  16676      8.84%      8.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                     0      0.00%      8.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                      0      0.00%      8.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      8.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      8.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      8.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%      8.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      8.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      8.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      8.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      8.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      8.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      8.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      8.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      8.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%      8.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      8.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%      8.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      8.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      8.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      8.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      8.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      8.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      8.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      8.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      8.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      8.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      8.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      8.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead                 99378     52.65%     61.49% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite                72683     38.51%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass             3518      0.02%      0.02% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu              9521262     65.73%     65.76% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult               23052      0.16%     65.92% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     65.92% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd              11116      0.08%     65.99% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     65.99% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     65.99% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     65.99% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv               1759      0.01%     66.01% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     66.01% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     66.01% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     66.01% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     66.01% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     66.01% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     66.01% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     66.01% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     66.01% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     66.01% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     66.01% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     66.01% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     66.01% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     66.01% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     66.01% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     66.01% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     66.01% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     66.01% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     66.01% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     66.01% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.01% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     66.01% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead             2876494     19.86%     85.87% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite            1724250     11.90%     97.77% # Type of FU issued
-system.cpu1.iq.FU_type_0::IprAccess            322940      2.23%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass             3518      0.03%      0.03% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu              7118581     66.92%     66.96% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult               18880      0.18%     67.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     67.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd               9739      0.09%     67.23% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     67.23% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     67.23% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     67.23% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv               1759      0.02%     67.24% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     67.24% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     67.24% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     67.24% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     67.24% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     67.24% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     67.24% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     67.24% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     67.24% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     67.24% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     67.24% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     67.24% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     67.24% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     67.24% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     67.24% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     67.24% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     67.24% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     67.24% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     67.24% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     67.24% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.24% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     67.24% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead             2093745     19.68%     86.93% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite            1155572     10.86%     97.79% # Type of FU issued
+system.cpu1.iq.FU_type_0::IprAccess            235150      2.21%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total              14484391                       # Type of FU issued
-system.cpu1.iq.rate                          0.563522                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                     253150                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.017477                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads          52052620                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes         17652734                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses     14115090                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads             228319                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes            110924                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses       107745                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses              14614655                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                 119368                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads          134347                       # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total              10636944                       # Type of FU issued
+system.cpu1.iq.rate                          0.565825                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                     188737                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.017744                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads          37986289                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes         12982235                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses     10383881                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads             128452                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes             62754                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses        61527                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses              10755461                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                  66702                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads          101929                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads       418294                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses          981                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation         3304                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores       169372                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads       306426                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses          815                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation         2923                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores       138344                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads         5236                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked        20861                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads         4845                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked        18286                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles                377196                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles                2407064                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles               140680                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts           16469424                       # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts           189598                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts              2918733                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts             1792509                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts            583051                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                 52184                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents                 2431                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents          3304                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect         57543                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect       133828                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts              191371                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts             14348807                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts              2776029                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts           135584                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles                276421                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles                2089253                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles                85247                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts           12015910                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts           137996                       # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts              2123178                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts             1208247                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts            388932                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                 10076                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents                 1666                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents          2923                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect         39900                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect        91880                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts              131780                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts             10541126                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts              2031671                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts            95818                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                       875756                       # number of nop insts executed
-system.cpu1.iew.exec_refs                     4481633                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches                 2254475                       # Number of branches executed
-system.cpu1.iew.exec_stores                   1705604                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.558247                       # Inst execution rate
-system.cpu1.iew.wb_sent                      14259530                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                     14222835                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                  6903248                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                  9726426                       # num instructions consuming a value
+system.cpu1.iew.exec_nop                       591584                       # number of nop insts executed
+system.cpu1.iew.exec_refs                     3170643                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches                 1658996                       # Number of branches executed
+system.cpu1.iew.exec_stores                   1138972                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.560728                       # Inst execution rate
+system.cpu1.iew.wb_sent                      10475567                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                     10445408                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                  5214693                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                  7314185                       # num instructions consuming a value
 system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate                      0.553346                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.709741                       # average fanout of values written-back
+system.cpu1.iew.wb_rate                      0.555637                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.712956                       # average fanout of values written-back
 system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts        2312839                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls         183524                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts           178531                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples     22644417                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.622505                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.551942                       # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts        1685534                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls         115514                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts           123376                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples     16347649                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.627728                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.542862                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0     17386197     76.78%     76.78% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1      2263939     10.00%     86.78% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2      1130304      4.99%     91.77% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3       578693      2.56%     94.32% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4       365284      1.61%     95.94% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5       174241      0.77%     96.71% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6       166825      0.74%     97.44% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7       129123      0.57%     98.01% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8       449811      1.99%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0     12457643     76.20%     76.20% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1      1697144     10.38%     86.59% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2       844179      5.16%     91.75% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3       419187      2.56%     94.31% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4       268727      1.64%     95.96% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5       133453      0.82%     96.77% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6       126834      0.78%     97.55% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7        88227      0.54%     98.09% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8       312255      1.91%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total     22644417                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts            14096266                       # Number of instructions committed
-system.cpu1.commit.committedOps              14096266                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total     16347649                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts            10261869                       # Number of instructions committed
+system.cpu1.commit.committedOps              10261869                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                       4123576                       # Number of memory references committed
-system.cpu1.commit.loads                      2500439                       # Number of loads committed
-system.cpu1.commit.membars                      61456                       # Number of memory barriers committed
-system.cpu1.commit.branches                   2105755                       # Number of branches committed
-system.cpu1.commit.fp_insts                    106451                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                 13014804                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls              225813                       # Number of function calls committed.
-system.cpu1.commit.bw_lim_events               449811                       # number cycles where commit BW limit reached
+system.cpu1.commit.refs                       2886655                       # Number of memory references committed
+system.cpu1.commit.loads                      1816752                       # Number of loads committed
+system.cpu1.commit.membars                      36648                       # Number of memory barriers committed
+system.cpu1.commit.branches                   1542101                       # Number of branches committed
+system.cpu1.commit.fp_insts                     60269                       # Number of committed floating point instructions.
+system.cpu1.commit.int_insts                  9518406                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls              159983                       # Number of function calls committed.
+system.cpu1.commit.bw_lim_events               312255                       # number cycles where commit BW limit reached
 system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads                    38521772                       # The number of ROB reads
-system.cpu1.rob.rob_writes                   33194220                       # The number of ROB writes
-system.cpu1.timesIdled                         266846                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                        2681703                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                  3780938744                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                   13322175                       # Number of Instructions Simulated
-system.cpu1.committedOps                     13322175                       # Number of Ops (including micro ops) Simulated
-system.cpu1.committedInsts_total             13322175                       # Number of Instructions Simulated
-system.cpu1.cpi                              1.929363                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        1.929363                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.518306                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.518306                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads                18552962                       # number of integer regfile reads
-system.cpu1.int_regfile_writes               10191479                       # number of integer regfile writes
-system.cpu1.fp_regfile_reads                    58039                       # number of floating regfile reads
-system.cpu1.fp_regfile_writes                   58174                       # number of floating regfile writes
-system.cpu1.misc_regfile_reads                1024653                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes                265032                       # number of misc regfile writes
-system.cpu1.icache.tags.replacements           316719                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          504.225697                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs            1849767                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs           317231                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs             5.830978                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle      49140510500                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   504.225697                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.984816                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.984816                       # Average percentage of cache occupancy
+system.cpu1.rob.rob_reads                    27899142                       # The number of ROB reads
+system.cpu1.rob.rob_writes                   24169847                       # The number of ROB writes
+system.cpu1.timesIdled                         181051                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                        2174922                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                  3790987217                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                    9739356                       # Number of Instructions Simulated
+system.cpu1.committedOps                      9739356                       # Number of Ops (including micro ops) Simulated
+system.cpu1.committedInsts_total              9739356                       # Number of Instructions Simulated
+system.cpu1.cpi                              1.930209                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        1.930209                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.518079                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.518079                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads                13792462                       # number of integer regfile reads
+system.cpu1.int_regfile_writes                7586165                       # number of integer regfile writes
+system.cpu1.fp_regfile_reads                    35303                       # number of floating regfile reads
+system.cpu1.fp_regfile_writes                   34737                       # number of floating regfile writes
+system.cpu1.misc_regfile_reads                 829246                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes                174995                       # number of misc regfile writes
+system.cpu1.icache.tags.replacements           184023                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          502.144736                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs            1436916                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs           184535                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs             7.786685                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle     1712232500000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   502.144736                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.980751                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.980751                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1           92                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2          420                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2          511                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses          2498600                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses         2498600                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst      1849767                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total        1849767                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst      1849767                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total         1849767                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst      1849767                       # number of overall hits
-system.cpu1.icache.overall_hits::total        1849767                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       331536                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       331536                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       331536                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        331536                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       331536                       # number of overall misses
-system.cpu1.icache.overall_misses::total       331536                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   4647513106                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   4647513106                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   4647513106                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   4647513106                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   4647513106                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   4647513106                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst      2181303                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total      2181303                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst      2181303                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total      2181303                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst      2181303                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total      2181303                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.151990                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.151990                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.151990                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.151990                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.151990                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.151990                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14018.125048                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 14018.125048                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14018.125048                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 14018.125048                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14018.125048                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 14018.125048                       # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs         1365                       # number of cycles access was blocked
+system.cpu1.icache.tags.tag_accesses          1815116                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses         1815116                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst      1436916                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total        1436916                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst      1436916                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total         1436916                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst      1436916                       # number of overall hits
+system.cpu1.icache.overall_hits::total        1436916                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       193606                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       193606                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       193606                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        193606                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       193606                       # number of overall misses
+system.cpu1.icache.overall_misses::total       193606                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   2794361223                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   2794361223                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   2794361223                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   2794361223                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   2794361223                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   2794361223                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst      1630522                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total      1630522                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst      1630522                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total      1630522                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst      1630522                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total      1630522                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.118739                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.118739                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.118739                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.118739                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.118739                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.118739                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14433.236692                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 14433.236692                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14433.236692                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 14433.236692                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14433.236692                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 14433.236692                       # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs         1663                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs               71                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs               63                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs    19.225352                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs    26.396825                       # average number of cycles each access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        14239                       # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total        14239                       # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst        14239                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total        14239                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst        14239                       # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total        14239                       # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       317297                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       317297                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       317297                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       317297                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       317297                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       317297                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   3842042413                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   3842042413                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   3842042413                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   3842042413                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   3842042413                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   3842042413                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.145462                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.145462                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.145462                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.145462                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.145462                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.145462                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12108.662903                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12108.662903                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12108.662903                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 12108.662903                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12108.662903                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 12108.662903                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst         9012                       # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total         9012                       # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst         9012                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total         9012                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst         9012                       # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total         9012                       # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       184594                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       184594                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       184594                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       184594                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       184594                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       184594                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   2304763360                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   2304763360                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   2304763360                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   2304763360                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   2304763360                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   2304763360                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.113212                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.113212                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.113212                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.113212                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.113212                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.113212                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12485.581113                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12485.581113                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12485.581113                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 12485.581113                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12485.581113                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 12485.581113                       # average overall mshr miss latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.tags.replacements           323504                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          495.920224                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs            3389718                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs           323845                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            10.467100                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle      42037852500                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   495.920224                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.968594                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.968594                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          341                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1           35                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2          306                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.666016                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses         17217310                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses        17217310                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data      2089496                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        2089496                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      1222054                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       1222054                       # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        41428                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        41428                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        44398                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        44398                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data      3311550                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total         3311550                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data      3311550                       # number of overall hits
-system.cpu1.dcache.overall_hits::total        3311550                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       467553                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       467553                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data       348721                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total       348721                       # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         7730                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total         7730                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data          782                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total          782                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       816274                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        816274                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       816274                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       816274                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   7286969700                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   7286969700                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  13547153677                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total  13547153677                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    112298247                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total    112298247                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data      5736606                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total      5736606                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data  20834123377                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total  20834123377                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data  20834123377                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total  20834123377                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      2557049                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      2557049                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      1570775                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      1570775                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        49158                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        49158                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        45180                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        45180                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data      4127824                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total      4127824                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data      4127824                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total      4127824                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.182849                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.182849                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.222006                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.222006                       # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.157248                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.157248                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.017309                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.017309                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.197749                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.197749                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.197749                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.197749                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15585.334069                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 15585.334069                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 38848.115476                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 38848.115476                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14527.586934                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14527.586934                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  7335.813299                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  7335.813299                       # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 25523.443570                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 25523.443570                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 25523.443570                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 25523.443570                       # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs       423453                       # number of cycles access was blocked
+system.cpu1.dcache.tags.replacements           203792                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          491.930753                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs            2483389                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs           204116                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            12.166557                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle      43808643250                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   491.930753                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.960802                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.960802                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          324                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2          324                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.632812                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses         12059624                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        12059624                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data      1586410                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        1586410                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data       857564                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total        857564                       # number of WriteReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        22125                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        22125                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        21120                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        21120                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data      2443974                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total         2443974                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data      2443974                       # number of overall hits
+system.cpu1.dcache.overall_hits::total        2443974                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       285731                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       285731                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data       181299                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total       181299                       # number of WriteReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         4484                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total         4484                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data         2742                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total         2742                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data       467030                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        467030                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       467030                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       467030                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   4578373047                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   4578373047                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  10436073649                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total  10436073649                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     56388497                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total     56388497                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     20553927                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total     20553927                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data  15014446696                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total  15014446696                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data  15014446696                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total  15014446696                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      1872141                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      1872141                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      1038863                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      1038863                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        26609                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        26609                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        23862                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        23862                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data      2911004                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total      2911004                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data      2911004                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total      2911004                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.152623                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.152623                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.174517                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.174517                       # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.168514                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.168514                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.114911                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.114911                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.160436                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.160436                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.160436                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.160436                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16023.368297                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 16023.368297                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 57562.775575                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 57562.775575                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12575.489964                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12575.489964                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  7495.961707                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  7495.961707                       # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 32148.784224                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 32148.784224                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 32148.784224                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 32148.784224                       # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs       370227                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs             7447                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs             6127                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs    56.862226                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs    60.425494                       # average number of cycles each access was blocked
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks       245774                       # number of writebacks
-system.cpu1.dcache.writebacks::total           245774                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       203756                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total       203756                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       288423                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total       288423                       # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data         1420                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total         1420                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data       492179                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total       492179                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data       492179                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total       492179                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       263797                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total       263797                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        60298                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total        60298                       # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         6310                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total         6310                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data          781                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total          781                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       324095                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       324095                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       324095                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       324095                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   3377520942                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   3377520942                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2032860866                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2032860866                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     70443003                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     70443003                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data      4174394                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total      4174394                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   5410381808                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   5410381808                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   5410381808                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   5410381808                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    489946000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    489946000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    936242002                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    936242002                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   1426188002                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total   1426188002                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.103165                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.103165                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.038387                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.038387                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.128362                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.128362                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.017286                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.017286                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.078515                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.078515                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.078515                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.078515                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12803.485036                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12803.485036                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33713.570367                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33713.570367                       # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11163.708875                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11163.708875                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  5344.934699                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  5344.934699                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16693.814493                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16693.814493                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16693.814493                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16693.814493                       # average overall mshr miss latency
+system.cpu1.dcache.writebacks::writebacks       162776                       # number of writebacks
+system.cpu1.dcache.writebacks::total           162776                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       104604                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total       104604                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       148843                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total       148843                       # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data          899                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total          899                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data       253447                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total       253447                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data       253447                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total       253447                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       181127                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total       181127                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        32456                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total        32456                       # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         3585                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total         3585                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data         2742                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total         2742                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       213583                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       213583                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       213583                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       213583                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   2418933900                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   2418933900                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   1545787184                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   1545787184                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     26756251                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     26756251                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     15069073                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     15069073                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   3964721084                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   3964721084                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   3964721084                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   3964721084                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    485705000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    485705000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    998872003                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    998872003                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   1484577003                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total   1484577003                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.096749                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.096749                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.031242                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.031242                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.134729                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.134729                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.114911                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.114911                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.073371                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.073371                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.073371                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.073371                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13354.905122                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13354.905122                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 47627.162435                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 47627.162435                       # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  7463.389400                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  7463.389400                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  5495.650255                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  5495.650255                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18562.905681                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18562.905681                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18562.905681                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18562.905681                       # average overall mshr miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
@@ -2106,161 +2019,161 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf
 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    4836                       # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei                    166329                       # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0                   57049     39.81%     39.81% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::21                    131      0.09%     39.90% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::22                   1924      1.34%     41.24% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::30                     16      0.01%     41.25% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31                  84196     58.75%    100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total              143316                       # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0                    56102     49.10%     49.10% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::21                     131      0.11%     49.22% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22                    1924      1.68%     50.90% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::30                      16      0.01%     50.91% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31                   56086     49.09%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total               114259                       # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0            1865433154000     98.01%     98.01% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21               62620000      0.00%     98.01% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22              558222500      0.03%     98.04% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::30                8649500      0.00%     98.04% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31            37274722500      1.96%    100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total        1903337368500                       # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0                 0.983400                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.inst.quiesce                    5026                       # number of quiesce instructions executed
+system.cpu0.kern.inst.hwrei                    189626                       # number of hwrei instructions executed
+system.cpu0.kern.ipl_count::0                   66604     40.25%     40.25% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::21                    133      0.08%     40.33% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::22                   1926      1.16%     41.49% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::30                    191      0.12%     41.61% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31                  96634     58.39%    100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total              165488                       # number of times we switched to this ipl
+system.cpu0.kern.ipl_good::0                    65244     49.22%     49.22% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::21                     133      0.10%     49.32% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::22                    1926      1.45%     50.78% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::30                     191      0.14%     50.92% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::31                   65055     49.08%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::total               132549                       # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks::0            1865394285500     97.91%     97.91% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21               63356500      0.00%     97.91% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22              573165000      0.03%     97.94% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::30               85999500      0.00%     97.95% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31            39121861000      2.05%    100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total        1905238667500                       # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used::0                 0.979581                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31                0.666136                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total             0.797252                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.syscall::2                         8      3.56%      3.56% # number of syscalls executed
-system.cpu0.kern.syscall::3                        19      8.44%     12.00% # number of syscalls executed
-system.cpu0.kern.syscall::4                         4      1.78%     13.78% # number of syscalls executed
-system.cpu0.kern.syscall::6                        33     14.67%     28.44% # number of syscalls executed
-system.cpu0.kern.syscall::12                        1      0.44%     28.89% # number of syscalls executed
-system.cpu0.kern.syscall::17                        9      4.00%     32.89% # number of syscalls executed
-system.cpu0.kern.syscall::19                       10      4.44%     37.33% # number of syscalls executed
-system.cpu0.kern.syscall::20                        6      2.67%     40.00% # number of syscalls executed
-system.cpu0.kern.syscall::23                        1      0.44%     40.44% # number of syscalls executed
-system.cpu0.kern.syscall::24                        3      1.33%     41.78% # number of syscalls executed
-system.cpu0.kern.syscall::33                        7      3.11%     44.89% # number of syscalls executed
-system.cpu0.kern.syscall::41                        2      0.89%     45.78% # number of syscalls executed
-system.cpu0.kern.syscall::45                       36     16.00%     61.78% # number of syscalls executed
-system.cpu0.kern.syscall::47                        3      1.33%     63.11% # number of syscalls executed
-system.cpu0.kern.syscall::48                       10      4.44%     67.56% # number of syscalls executed
-system.cpu0.kern.syscall::54                       10      4.44%     72.00% # number of syscalls executed
-system.cpu0.kern.syscall::58                        1      0.44%     72.44% # number of syscalls executed
-system.cpu0.kern.syscall::59                        6      2.67%     75.11% # number of syscalls executed
-system.cpu0.kern.syscall::71                       25     11.11%     86.22% # number of syscalls executed
-system.cpu0.kern.syscall::73                        3      1.33%     87.56% # number of syscalls executed
-system.cpu0.kern.syscall::74                        6      2.67%     90.22% # number of syscalls executed
-system.cpu0.kern.syscall::87                        1      0.44%     90.67% # number of syscalls executed
-system.cpu0.kern.syscall::90                        3      1.33%     92.00% # number of syscalls executed
-system.cpu0.kern.syscall::92                        9      4.00%     96.00% # number of syscalls executed
-system.cpu0.kern.syscall::97                        2      0.89%     96.89% # number of syscalls executed
-system.cpu0.kern.syscall::98                        2      0.89%     97.78% # number of syscalls executed
-system.cpu0.kern.syscall::132                       1      0.44%     98.22% # number of syscalls executed
-system.cpu0.kern.syscall::144                       2      0.89%     99.11% # number of syscalls executed
-system.cpu0.kern.syscall::147                       2      0.89%    100.00% # number of syscalls executed
-system.cpu0.kern.syscall::total                   225                       # number of syscalls executed
+system.cpu0.kern.ipl_used::31                0.673210                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::total             0.800958                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.syscall::2                         8      3.45%      3.45% # number of syscalls executed
+system.cpu0.kern.syscall::3                        20      8.62%     12.07% # number of syscalls executed
+system.cpu0.kern.syscall::4                         4      1.72%     13.79% # number of syscalls executed
+system.cpu0.kern.syscall::6                        33     14.22%     28.02% # number of syscalls executed
+system.cpu0.kern.syscall::12                        1      0.43%     28.45% # number of syscalls executed
+system.cpu0.kern.syscall::17                        9      3.88%     32.33% # number of syscalls executed
+system.cpu0.kern.syscall::19                       10      4.31%     36.64% # number of syscalls executed
+system.cpu0.kern.syscall::20                        6      2.59%     39.22% # number of syscalls executed
+system.cpu0.kern.syscall::23                        1      0.43%     39.66% # number of syscalls executed
+system.cpu0.kern.syscall::24                        3      1.29%     40.95% # number of syscalls executed
+system.cpu0.kern.syscall::33                        7      3.02%     43.97% # number of syscalls executed
+system.cpu0.kern.syscall::41                        2      0.86%     44.83% # number of syscalls executed
+system.cpu0.kern.syscall::45                       39     16.81%     61.64% # number of syscalls executed
+system.cpu0.kern.syscall::47                        3      1.29%     62.93% # number of syscalls executed
+system.cpu0.kern.syscall::48                       10      4.31%     67.24% # number of syscalls executed
+system.cpu0.kern.syscall::54                       10      4.31%     71.55% # number of syscalls executed
+system.cpu0.kern.syscall::58                        1      0.43%     71.98% # number of syscalls executed
+system.cpu0.kern.syscall::59                        6      2.59%     74.57% # number of syscalls executed
+system.cpu0.kern.syscall::71                       27     11.64%     86.21% # number of syscalls executed
+system.cpu0.kern.syscall::73                        3      1.29%     87.50% # number of syscalls executed
+system.cpu0.kern.syscall::74                        7      3.02%     90.52% # number of syscalls executed
+system.cpu0.kern.syscall::87                        1      0.43%     90.95% # number of syscalls executed
+system.cpu0.kern.syscall::90                        3      1.29%     92.24% # number of syscalls executed
+system.cpu0.kern.syscall::92                        9      3.88%     96.12% # number of syscalls executed
+system.cpu0.kern.syscall::97                        2      0.86%     96.98% # number of syscalls executed
+system.cpu0.kern.syscall::98                        2      0.86%     97.84% # number of syscalls executed
+system.cpu0.kern.syscall::132                       1      0.43%     98.28% # number of syscalls executed
+system.cpu0.kern.syscall::144                       2      0.86%     99.14% # number of syscalls executed
+system.cpu0.kern.syscall::147                       2      0.86%    100.00% # number of syscalls executed
+system.cpu0.kern.syscall::total                   232                       # number of syscalls executed
 system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
-system.cpu0.kern.callpal::wripir                  104      0.07%      0.07% # number of callpals executed
-system.cpu0.kern.callpal::wrmces                    1      0.00%      0.07% # number of callpals executed
-system.cpu0.kern.callpal::wrfen                     1      0.00%      0.07% # number of callpals executed
-system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.07% # number of callpals executed
-system.cpu0.kern.callpal::swpctx                 3010      1.99%      2.06% # number of callpals executed
-system.cpu0.kern.callpal::tbi                      50      0.03%      2.09% # number of callpals executed
-system.cpu0.kern.callpal::wrent                     7      0.00%      2.10% # number of callpals executed
-system.cpu0.kern.callpal::swpipl               136886     90.50%     92.60% # number of callpals executed
-system.cpu0.kern.callpal::rdps                   6293      4.16%     96.76% # number of callpals executed
-system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.77% # number of callpals executed
-system.cpu0.kern.callpal::wrusp                     3      0.00%     96.77% # number of callpals executed
-system.cpu0.kern.callpal::rdusp                     9      0.01%     96.77% # number of callpals executed
-system.cpu0.kern.callpal::whami                     2      0.00%     96.77% # number of callpals executed
-system.cpu0.kern.callpal::rti                    4358      2.88%     99.66% # number of callpals executed
-system.cpu0.kern.callpal::callsys                 382      0.25%     99.91% # number of callpals executed
-system.cpu0.kern.callpal::imb                     138      0.09%    100.00% # number of callpals executed
-system.cpu0.kern.callpal::total                151247                       # number of callpals executed
-system.cpu0.kern.mode_switch::kernel             6436                       # number of protection mode switches
-system.cpu0.kern.mode_switch::user               1343                       # number of protection mode switches
+system.cpu0.kern.callpal::wripir                  273      0.16%      0.16% # number of callpals executed
+system.cpu0.kern.callpal::wrmces                    1      0.00%      0.16% # number of callpals executed
+system.cpu0.kern.callpal::wrfen                     1      0.00%      0.16% # number of callpals executed
+system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.16% # number of callpals executed
+system.cpu0.kern.callpal::swpctx                 3846      2.21%      2.37% # number of callpals executed
+system.cpu0.kern.callpal::tbi                      50      0.03%      2.39% # number of callpals executed
+system.cpu0.kern.callpal::wrent                     7      0.00%      2.40% # number of callpals executed
+system.cpu0.kern.callpal::swpipl               158278     90.80%     93.20% # number of callpals executed
+system.cpu0.kern.callpal::rdps                   6346      3.64%     96.84% # number of callpals executed
+system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.84% # number of callpals executed
+system.cpu0.kern.callpal::wrusp                     3      0.00%     96.84% # number of callpals executed
+system.cpu0.kern.callpal::rdusp                     9      0.01%     96.85% # number of callpals executed
+system.cpu0.kern.callpal::whami                     2      0.00%     96.85% # number of callpals executed
+system.cpu0.kern.callpal::rti                    4961      2.85%     99.70% # number of callpals executed
+system.cpu0.kern.callpal::callsys                 391      0.22%     99.92% # number of callpals executed
+system.cpu0.kern.callpal::imb                     138      0.08%    100.00% # number of callpals executed
+system.cpu0.kern.callpal::total                174309                       # number of callpals executed
+system.cpu0.kern.mode_switch::kernel             7462                       # number of protection mode switches
+system.cpu0.kern.mode_switch::user               1354                       # number of protection mode switches
 system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
-system.cpu0.kern.mode_good::kernel               1342                      
-system.cpu0.kern.mode_good::user                 1343                      
+system.cpu0.kern.mode_good::kernel               1353                      
+system.cpu0.kern.mode_good::user                 1354                      
 system.cpu0.kern.mode_good::idle                    0                      
-system.cpu0.kern.mode_switch_good::kernel     0.208515                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::kernel     0.181319                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total     0.345160                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel      1901289587500     99.89%     99.89% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user          2047773000      0.11%    100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_switch_good::total     0.307055                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel      1903211741000     99.89%     99.89% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user          2026918500      0.11%    100.00% # number of ticks spent at the given mode
 system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context                    3011                       # number of times the context was actually changed
+system.cpu0.kern.swap_context                    3847                       # number of times the context was actually changed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    3850                       # number of quiesce instructions executed
-system.cpu1.kern.inst.hwrei                     71149                       # number of hwrei instructions executed
-system.cpu1.kern.ipl_count::0                   24567     38.92%     38.92% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::22                   1923      3.05%     41.97% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::30                    104      0.16%     42.13% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::31                  36529     57.87%    100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::total               63123                       # number of times we switched to this ipl
-system.cpu1.kern.ipl_good::0                    24137     48.08%     48.08% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::22                    1923      3.83%     51.92% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::30                     104      0.21%     52.12% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::31                   24033     47.88%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::total                50197                       # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0            1869107624500     98.20%     98.20% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22              533184500      0.03%     98.23% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30               48972500      0.00%     98.23% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31            33633158500      1.77%    100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total        1903322940000                       # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used::0                 0.982497                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.inst.quiesce                    3999                       # number of quiesce instructions executed
+system.cpu1.kern.inst.hwrei                     49848                       # number of hwrei instructions executed
+system.cpu1.kern.ipl_count::0                   15658     37.06%     37.06% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::22                   1924      4.55%     41.62% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::30                    273      0.65%     42.26% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::31                  24392     57.74%    100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::total               42247                       # number of times we switched to this ipl
+system.cpu1.kern.ipl_good::0                    15641     47.10%     47.10% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::22                    1924      5.79%     52.90% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::30                     273      0.82%     53.72% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::31                   15369     46.28%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::total                33207                       # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks::0            1871713408000     98.26%     98.26% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::22              533048500      0.03%     98.29% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::30              128777500      0.01%     98.29% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::31            32519855000      1.71%    100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total        1904895089000                       # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used::0                 0.998914                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::31                0.657916                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::total             0.795225                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.syscall::3                        11     10.89%     10.89% # number of syscalls executed
-system.cpu1.kern.syscall::6                         9      8.91%     19.80% # number of syscalls executed
-system.cpu1.kern.syscall::15                        1      0.99%     20.79% # number of syscalls executed
-system.cpu1.kern.syscall::17                        6      5.94%     26.73% # number of syscalls executed
-system.cpu1.kern.syscall::23                        3      2.97%     29.70% # number of syscalls executed
-system.cpu1.kern.syscall::24                        3      2.97%     32.67% # number of syscalls executed
-system.cpu1.kern.syscall::33                        4      3.96%     36.63% # number of syscalls executed
-system.cpu1.kern.syscall::45                       18     17.82%     54.46% # number of syscalls executed
-system.cpu1.kern.syscall::47                        3      2.97%     57.43% # number of syscalls executed
-system.cpu1.kern.syscall::59                        1      0.99%     58.42% # number of syscalls executed
-system.cpu1.kern.syscall::71                       29     28.71%     87.13% # number of syscalls executed
-system.cpu1.kern.syscall::74                       10      9.90%     97.03% # number of syscalls executed
-system.cpu1.kern.syscall::132                       3      2.97%    100.00% # number of syscalls executed
-system.cpu1.kern.syscall::total                   101                       # number of syscalls executed
+system.cpu1.kern.ipl_used::31                0.630084                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::total             0.786020                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.syscall::3                        10     10.64%     10.64% # number of syscalls executed
+system.cpu1.kern.syscall::6                         9      9.57%     20.21% # number of syscalls executed
+system.cpu1.kern.syscall::15                        1      1.06%     21.28% # number of syscalls executed
+system.cpu1.kern.syscall::17                        6      6.38%     27.66% # number of syscalls executed
+system.cpu1.kern.syscall::23                        3      3.19%     30.85% # number of syscalls executed
+system.cpu1.kern.syscall::24                        3      3.19%     34.04% # number of syscalls executed
+system.cpu1.kern.syscall::33                        4      4.26%     38.30% # number of syscalls executed
+system.cpu1.kern.syscall::45                       15     15.96%     54.26% # number of syscalls executed
+system.cpu1.kern.syscall::47                        3      3.19%     57.45% # number of syscalls executed
+system.cpu1.kern.syscall::59                        1      1.06%     58.51% # number of syscalls executed
+system.cpu1.kern.syscall::71                       27     28.72%     87.23% # number of syscalls executed
+system.cpu1.kern.syscall::74                        9      9.57%     96.81% # number of syscalls executed
+system.cpu1.kern.syscall::132                       3      3.19%    100.00% # number of syscalls executed
+system.cpu1.kern.syscall::total                    94                       # number of syscalls executed
 system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
-system.cpu1.kern.callpal::wripir                   16      0.02%      0.03% # number of callpals executed
-system.cpu1.kern.callpal::wrmces                    1      0.00%      0.03% # number of callpals executed
-system.cpu1.kern.callpal::wrfen                     1      0.00%      0.03% # number of callpals executed
-system.cpu1.kern.callpal::swpctx                 1228      1.89%      1.92% # number of callpals executed
-system.cpu1.kern.callpal::tbi                       3      0.00%      1.92% # number of callpals executed
-system.cpu1.kern.callpal::wrent                     7      0.01%      1.93% # number of callpals executed
-system.cpu1.kern.callpal::swpipl                58251     89.62%     91.55% # number of callpals executed
-system.cpu1.kern.callpal::rdps                   2464      3.79%     95.34% # number of callpals executed
-system.cpu1.kern.callpal::wrkgp                     1      0.00%     95.34% # number of callpals executed
-system.cpu1.kern.callpal::wrusp                     4      0.01%     95.35% # number of callpals executed
-system.cpu1.kern.callpal::whami                     3      0.00%     95.35% # number of callpals executed
-system.cpu1.kern.callpal::rti                    2844      4.38%     99.73% # number of callpals executed
-system.cpu1.kern.callpal::callsys                 133      0.20%     99.93% # number of callpals executed
-system.cpu1.kern.callpal::imb                      42      0.06%    100.00% # number of callpals executed
+system.cpu1.kern.callpal::wripir                  191      0.44%      0.44% # number of callpals executed
+system.cpu1.kern.callpal::wrmces                    1      0.00%      0.44% # number of callpals executed
+system.cpu1.kern.callpal::wrfen                     1      0.00%      0.45% # number of callpals executed
+system.cpu1.kern.callpal::swpctx                  742      1.70%      2.15% # number of callpals executed
+system.cpu1.kern.callpal::tbi                       3      0.01%      2.15% # number of callpals executed
+system.cpu1.kern.callpal::wrent                     7      0.02%      2.17% # number of callpals executed
+system.cpu1.kern.callpal::swpipl                37463     85.96%     88.13% # number of callpals executed
+system.cpu1.kern.callpal::rdps                   2409      5.53%     93.66% # number of callpals executed
+system.cpu1.kern.callpal::wrkgp                     1      0.00%     93.66% # number of callpals executed
+system.cpu1.kern.callpal::wrusp                     4      0.01%     93.67% # number of callpals executed
+system.cpu1.kern.callpal::whami                     3      0.01%     93.68% # number of callpals executed
+system.cpu1.kern.callpal::rti                    2587      5.94%     99.62% # number of callpals executed
+system.cpu1.kern.callpal::callsys                 124      0.28%     99.90% # number of callpals executed
+system.cpu1.kern.callpal::imb                      42      0.10%    100.00% # number of callpals executed
 system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
-system.cpu1.kern.callpal::total                 65000                       # number of callpals executed
-system.cpu1.kern.mode_switch::kernel             1608                       # number of protection mode switches
-system.cpu1.kern.mode_switch::user                397                       # number of protection mode switches
-system.cpu1.kern.mode_switch::idle               2054                       # number of protection mode switches
-system.cpu1.kern.mode_good::kernel                463                      
-system.cpu1.kern.mode_good::user                  397                      
-system.cpu1.kern.mode_good::idle                   66                      
-system.cpu1.kern.mode_switch_good::kernel     0.287935                       # fraction of useful protection mode switches
+system.cpu1.kern.callpal::total                 43580                       # number of callpals executed
+system.cpu1.kern.mode_switch::kernel              937                       # number of protection mode switches
+system.cpu1.kern.mode_switch::user                383                       # number of protection mode switches
+system.cpu1.kern.mode_switch::idle               2395                       # number of protection mode switches
+system.cpu1.kern.mode_good::kernel                617                      
+system.cpu1.kern.mode_good::user                  383                      
+system.cpu1.kern.mode_good::idle                  234                      
+system.cpu1.kern.mode_switch_good::kernel     0.658485                       # fraction of useful protection mode switches
 system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::idle      0.032132                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::total     0.228135                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel       38501499500      2.02%      2.02% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user           724848000      0.04%      2.06% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle        1863406690000     97.94%    100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context                    1229                       # number of times the context was actually changed
+system.cpu1.kern.mode_switch_good::idle      0.097704                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good::total     0.332167                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_ticks::kernel       34875641000      1.83%      1.83% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::user           708299500      0.04%      1.87% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::idle        1868990228500     98.13%    100.00% # number of ticks spent at the given mode
+system.cpu1.kern.swap_context                     743                       # number of times the context was actually changed
 
 ---------- End Simulation Statistics   ----------
index 674a7dfd5864cef8d71278ab48c124690407ce1f..0b1609ec3d3148acc7ea19f4a8f7ca1157a7d264 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.860198                       # Number of seconds simulated
-sim_ticks                                1860197780500                       # Number of ticks simulated
-final_tick                               1860197780500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.860192                       # Number of seconds simulated
+sim_ticks                                1860191785500                       # Number of ticks simulated
+final_tick                               1860191785500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 153122                       # Simulator instruction rate (inst/s)
-host_op_rate                                   153122                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             5376333902                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 310876                       # Number of bytes of host memory used
-host_seconds                                   346.00                       # Real time elapsed on the host
-sim_insts                                    52979882                       # Number of instructions simulated
-sim_ops                                      52979882                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 128947                       # Simulator instruction rate (inst/s)
+host_op_rate                                   128947                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             4527634915                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 347764                       # Number of bytes of host memory used
+host_seconds                                   410.85                       # Real time elapsed on the host
+sim_insts                                    52978349                       # Number of instructions simulated
+sim_ops                                      52978349                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            963968                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          24878976                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst            963264                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          24877248                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide        2652288                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             28495232                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       963968                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          963968                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7515456                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7515456                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst              15062                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             388734                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total             28492800                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       963264                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          963264                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7515392                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7515392                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst              15051                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             388707                       # Number of read requests responded to by this memory
 system.physmem.num_reads::tsunami.ide           41442                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                445238                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          117429                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               117429                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               518207                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             13374371                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide           1425810                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                15318388                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          518207                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             518207                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           4040138                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4040138                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           4040138                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              518207                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            13374371                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide          1425810                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               19358526                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        445238                       # Number of read requests accepted
-system.physmem.writeReqs                       117429                       # Number of write requests accepted
-system.physmem.readBursts                      445238                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     117429                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 28492032                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      3200                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7514752                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  28495232                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7515456                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                       50                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.num_reads::total                445200                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          117428                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               117428                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               517830                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             13373486                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide           1425814                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                15317130                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          517830                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             517830                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           4040117                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                4040117                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           4040117                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              517830                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            13373486                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide          1425814                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               19357247                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        445200                       # Number of read requests accepted
+system.physmem.writeReqs                       117428                       # Number of write requests accepted
+system.physmem.readBursts                      445200                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     117428                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 28485504                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      7296                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7513728                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  28492800                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7515392                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      114                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs            179                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               28229                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               27970                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               28433                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               28029                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               27802                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               27222                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               27248                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               27296                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               27665                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               27395                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              27922                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              27539                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              27561                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              28227                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              28327                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              28323                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                7932                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7497                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                7944                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                7517                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7343                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                6680                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6761                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                6683                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7104                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                6801                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7313                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6981                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7123                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               7875                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               8050                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7814                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs            178                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               28210                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               27995                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               28357                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               27829                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               27761                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               27267                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               27371                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               27375                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               27696                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               27269                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              28017                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              27509                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              27546                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              28232                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              28342                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              28310                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                7920                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7516                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                7873                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                7373                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7309                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                6720                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6881                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                6774                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7136                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                6679                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7411                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6967                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7107                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               7877                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               8064                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7795                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           8                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1860192344000                       # Total gap between requests
+system.physmem.numWrRetry                          10                       # Number of times write queue was full causing retry
+system.physmem.totGap                    1860186344000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  445238                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  445200                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 117429                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    332275                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     66533                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     19911                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      5799                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      2385                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      2335                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      1391                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      1359                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      1343                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      1445                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                     1317                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                     1259                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                     1090                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      974                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      964                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      961                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      961                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                      958                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                      957                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                      955                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                       12                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        4                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 117428                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    322906                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     56729                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     22897                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      5869                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      1157                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      4278                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      3757                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      3842                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      3993                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                      2551                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                     2136                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                     2038                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                     1891                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                     1835                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                     1567                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                     1541                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                     1538                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                     1552                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                     1725                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                     1258                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                       16                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                       10                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
@@ -133,230 +133,147 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                      4574                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                      4622                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                      4638                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                      5300                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                      6023                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                      5386                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                      5393                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                      5463                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                      5529                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                      4863                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                     4881                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                     4845                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                     5670                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                     5759                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                     5781                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     5838                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     5862                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5005                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5034                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     4942                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     5452                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5842                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                      354                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                      192                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                       49                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                       28                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                       22                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                       19                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                       17                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                       14                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                       14                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                       18                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        43301                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      831.507817                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     237.255649                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev    1940.687281                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64-67          14819     34.22%     34.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-131         6274     14.49%     48.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192-195         4433     10.24%     58.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-259         2614      6.04%     64.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320-323         1636      3.78%     68.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-387         1435      3.31%     72.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448-451          928      2.14%     74.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-515          854      1.97%     76.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576-579          632      1.46%     77.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-643          524      1.21%     78.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704-707          594      1.37%     80.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-771          623      1.44%     81.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832-835          284      0.66%     82.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-899          262      0.61%     82.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960-963          268      0.62%     83.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1027          398      0.92%     84.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088-1091          204      0.47%     84.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152-1155          163      0.38%     85.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216-1219           93      0.21%     85.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280-1283          193      0.45%     85.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344-1347          100      0.23%     86.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408-1411          353      0.82%     87.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472-1475          186      0.43%     87.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536-1539          655      1.51%     88.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600-1603           89      0.21%     89.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664-1667           28      0.06%     89.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1728-1731           40      0.09%     89.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1792-1795          175      0.40%     89.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856-1859           41      0.09%     89.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1920-1923           79      0.18%     90.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984-1987           86      0.20%     90.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2048-2051           82      0.19%     90.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112-2115          104      0.24%     90.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2176-2179           73      0.17%     90.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2240-2243           16      0.04%     90.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2304-2307          102      0.24%     91.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2368-2371           26      0.06%     91.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2432-2435           14      0.03%     91.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2496-2499            2      0.00%     91.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2560-2563           17      0.04%     91.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2624-2627            4      0.01%     91.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2688-2691           13      0.03%     91.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2752-2755           25      0.06%     91.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2816-2819          100      0.23%     91.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2880-2883           15      0.03%     91.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2944-2947           67      0.15%     91.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3008-3011           82      0.19%     91.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3072-3075           42      0.10%     92.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3136-3139           83      0.19%     92.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3200-3203           68      0.16%     92.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3264-3267           12      0.03%     92.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3328-3331           94      0.22%     92.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3392-3395           22      0.05%     92.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3456-3459            9      0.02%     92.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3520-3523            5      0.01%     92.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3584-3587           12      0.03%     92.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3648-3651            4      0.01%     92.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3712-3715           11      0.03%     92.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3776-3779           22      0.05%     92.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3840-3843           92      0.21%     93.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3904-3907           13      0.03%     93.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3968-3971           66      0.15%     93.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4032-4035           81      0.19%     93.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4096-4099           40      0.09%     93.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4160-4163           80      0.18%     93.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4224-4227           68      0.16%     93.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4288-4291           12      0.03%     93.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4352-4355           95      0.22%     94.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4416-4419           21      0.05%     94.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4480-4483           10      0.02%     94.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4544-4547            1      0.00%     94.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4608-4611           11      0.03%     94.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4672-4675            4      0.01%     94.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4736-4739           13      0.03%     94.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4800-4803           21      0.05%     94.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4864-4867           92      0.21%     94.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4928-4931           14      0.03%     94.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4992-4995           68      0.16%     94.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5056-5059           81      0.19%     94.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5120-5123           35      0.08%     94.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5184-5187           79      0.18%     95.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5248-5251           65      0.15%     95.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5312-5315           12      0.03%     95.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5376-5379           98      0.23%     95.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5440-5443           22      0.05%     95.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5504-5507           10      0.02%     95.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5568-5571            1      0.00%     95.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5632-5635           12      0.03%     95.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5760-5763           11      0.03%     95.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5824-5827           21      0.05%     95.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5888-5891           92      0.21%     95.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5952-5955           13      0.03%     95.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6016-6019           64      0.15%     96.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6080-6083           81      0.19%     96.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6144-6147           41      0.09%     96.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6208-6211           82      0.19%     96.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6272-6275           69      0.16%     96.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6336-6339           14      0.03%     96.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6400-6403           94      0.22%     96.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6464-6467           21      0.05%     97.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6528-6531            8      0.02%     97.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6656-6659           12      0.03%     97.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6720-6723            2      0.00%     97.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6784-6787           10      0.02%     97.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6848-6851           22      0.05%     97.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6912-6915           89      0.21%     97.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6976-6979           14      0.03%     97.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7040-7043           66      0.15%     97.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7104-7107           80      0.18%     97.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7168-7171          307      0.71%     98.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7296-7299            1      0.00%     98.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7360-7363            1      0.00%     98.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7424-7427           17      0.04%     98.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7488-7491            2      0.00%     98.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7552-7555            1      0.00%     98.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7680-7683            5      0.01%     98.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7808-7811            1      0.00%     98.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7872-7875            1      0.00%     98.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7936-7939           16      0.04%     98.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8064-8067            1      0.00%     98.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8128-8131            2      0.00%     98.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8192-8195          330      0.76%     99.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8256-8259            1      0.00%     99.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8320-8323            2      0.00%     99.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8704-8707            3      0.01%     99.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8896-8899            1      0.00%     99.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8960-8963            2      0.00%     99.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9024-9027            1      0.00%     99.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9088-9091            1      0.00%     99.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9216-9219            4      0.01%     99.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9408-9411            2      0.00%     99.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9664-9667            1      0.00%     99.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9856-9859            1      0.00%     99.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9984-9987            1      0.00%     99.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10048-10051            1      0.00%     99.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10112-10115            1      0.00%     99.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10240-10243            1      0.00%     99.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10880-10883            1      0.00%     99.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10944-10947            1      0.00%     99.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11008-11011            1      0.00%     99.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11200-11203            1      0.00%     99.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11392-11395            1      0.00%     99.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11456-11459            1      0.00%     99.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11520-11523            1      0.00%     99.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11648-11651            2      0.00%     99.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11712-11715            1      0.00%     99.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11776-11779            1      0.00%     99.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12032-12035            4      0.01%     99.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12288-12291            1      0.00%     99.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12480-12483            2      0.00%     99.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12544-12547            1      0.00%     99.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12672-12675            2      0.00%     99.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12736-12739            2      0.00%     99.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13056-13059            2      0.00%     99.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13184-13187            2      0.00%     99.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13248-13251            2      0.00%     99.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13312-13315            4      0.01%     99.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13376-13379            1      0.00%     99.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13440-13443            1      0.00%     99.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13632-13635            1      0.00%     99.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13696-13699            7      0.02%     99.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13888-13891            1      0.00%     99.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14208-14211            4      0.01%     99.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14336-14339            3      0.01%     99.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14400-14403            1      0.00%     99.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14656-14659            2      0.00%     99.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14848-14851            1      0.00%     99.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15168-15171            1      0.00%     99.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15360-15363           40      0.09%     99.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15424-15427            2      0.00%     99.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15488-15491            2      0.00%     99.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15808-15811            2      0.00%     99.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16064-16067            1      0.00%     99.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16128-16131            1      0.00%     99.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16192-16195            1      0.00%     99.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16256-16259            1      0.00%     99.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16320-16323            1      0.00%     99.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16384-16387          174      0.40%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          43301                       # Bytes accessed per row activation
-system.physmem.totQLat                     8362787000                       # Total ticks spent queuing
-system.physmem.totMemAccLat               15768695750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2225940000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                  5179968750                       # Total ticks spent accessing banks
-system.physmem.avgQLat                       18784.84                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    11635.46                       # Average bank access latency per DRAM burst
+system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      739                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      765                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                      934                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     2202                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     3347                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     4119                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     4688                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     4756                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     4816                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     4872                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     5562                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     5401                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     5474                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     6284                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     6230                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6245                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6216                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     5759                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     3432                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                     2435                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                     1613                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                     1063                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                     1141                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                     1099                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                     1072                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                     1163                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                     1289                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                     1446                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                     1531                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                     1699                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                     1801                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                     1872                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                     1823                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                     1946                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                     1928                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                     1837                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                     1841                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                     1726                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                     1489                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                     1270                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      915                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      647                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      461                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                      300                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       64                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       34                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       28                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       17                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       22                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        48603                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      651.388927                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     428.580055                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     419.495686                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127           8350     17.18%     17.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         6347     13.06%     30.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         2940      6.05%     36.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         1813      3.73%     40.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         1501      3.09%     43.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          899      1.85%     44.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          723      1.49%     46.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          886      1.82%     48.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        25144     51.73%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          48603                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6893                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        64.568403                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     2543.170744                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-8191           6890     99.96%     99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::40960-49151            1      0.01%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::57344-65535            1      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::196608-204799            1      0.01%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            6893                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6893                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.032062                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.789521                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        3.768510                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               5850     84.87%     84.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 28      0.41%     85.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                 70      1.02%     86.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                418      6.06%     92.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                134      1.94%     94.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 49      0.71%     95.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 24      0.35%     95.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 22      0.32%     95.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                 53      0.77%     96.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                 38      0.55%     97.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                 20      0.29%     97.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27                 34      0.49%     97.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28                 19      0.28%     98.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29                 34      0.49%     98.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30                  7      0.10%     98.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::31                 10      0.15%     98.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32                  2      0.03%     98.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::34                  2      0.03%     98.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::35                  3      0.04%     98.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36                  6      0.09%     98.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::37                  5      0.07%     99.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::38                  5      0.07%     99.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::39                  8      0.12%     99.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40                  4      0.06%     99.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::41                  2      0.03%     99.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::43                  1      0.01%     99.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44                  2      0.03%     99.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::45                  5      0.07%     99.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::46                  2      0.03%     99.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::47                  6      0.09%     99.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48                  6      0.09%     99.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::49                  4      0.06%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::50                  2      0.03%     99.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::51                  1      0.01%     99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52                  2      0.03%     99.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::53                  2      0.03%     99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::54                  3      0.04%     99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::55                  1      0.01%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56                  6      0.09%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::57                  1      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::58                  2      0.03%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6893                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    10196532000                       # Total ticks spent queuing
+system.physmem.totMemAccLat               17805650750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2225430000                       # Total ticks spent in databus transfers
+system.physmem.totBankLat                  5383688750                       # Total ticks spent accessing banks
+system.physmem.avgQLat                       22909.13                       # Average queueing delay per DRAM burst
+system.physmem.avgBankLat                    12095.84                       # Average bank access latency per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  35420.31                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          15.32                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  40004.97                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          15.31                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           4.04                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                       15.32                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        4.04                       # Average system write bandwidth in MiByte/s
@@ -364,61 +281,60 @@ system.physmem.peakBW                        12800.00                       # Th
 system.physmem.busUtil                           0.15                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.12                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         0.01                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        11.24                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     424550                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     94755                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   95.36                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  80.69                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3306027.09                       # Average gap between requests
-system.physmem.pageHitRate                      92.30                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               0.39                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                     19401389                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq              295980                       # Transaction distribution
-system.membus.trans_dist::ReadResp             295901                       # Transaction distribution
-system.membus.trans_dist::WriteReq               9598                       # Transaction distribution
-system.membus.trans_dist::WriteResp              9598                       # Transaction distribution
-system.membus.trans_dist::Writeback            117429                       # Transaction distribution
+system.physmem.avgRdQLen                         1.54                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        26.57                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     402462                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     96189                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   90.42                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  81.91                       # Row buffer hit rate for writes
+system.physmem.avgGap                      3306245.59                       # Average gap between requests
+system.physmem.pageHitRate                      88.65                       # Row buffer hit rate, read and write combined
+system.physmem.prechargeAllPercent               0.41                       # Percentage of time for which DRAM has all the banks in precharge state
+system.membus.throughput                     19400105                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq              295926                       # Transaction distribution
+system.membus.trans_dist::ReadResp             295846                       # Transaction distribution
+system.membus.trans_dist::WriteReq               9597                       # Transaction distribution
+system.membus.trans_dist::WriteResp              9597                       # Transaction distribution
+system.membus.trans_dist::Writeback            117428                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq              181                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq              1                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp             182                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            156823                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           156823                       # Transaction distribution
-system.membus.trans_dist::BadAddressError           79                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33056                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       884143                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio          158                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total       917357                       # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::UpgradeResp             181                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            156840                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           156840                       # Transaction distribution
+system.membus.trans_dist::BadAddressError           80                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33054                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       884064                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio          160                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total       917278                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124679                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total       124679                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1042036                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44148                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30701632                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     30745780                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count::total                1041957                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44140                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30699136                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     30743276                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      5309056                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.iocache.mem_side::total      5309056                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            36054836                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus               36054836                       # Total data (bytes)
+system.membus.tot_pkt_size::total            36052332                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               36052332                       # Total data (bytes)
 system.membus.snoop_data_through_bus            35584                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy            29837500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy            29929000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy          1551324500                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy          1552530249                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy               96500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy              100500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         3763216294                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         3767548549                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
-system.membus.respLayer2.occupancy          376313495                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy          376726994                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                41685                       # number of replacements
-system.iocache.tags.tagsinuse                1.261116                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.261130                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1710341603000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     1.261116                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.078820                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.078820                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         1710337661000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide     1.261130                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide     0.078821                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.078821                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -434,12 +350,12 @@ system.iocache.overall_misses::tsunami.ide        41725                       #
 system.iocache.overall_misses::total            41725                       # number of overall misses
 system.iocache.ReadReq_miss_latency::tsunami.ide     21133883                       # number of ReadReq miss cycles
 system.iocache.ReadReq_miss_latency::total     21133883                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::tsunami.ide  12974928560                       # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total  12974928560                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide  12996062443                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total  12996062443                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide  12996062443                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total  12996062443                       # number of overall miss cycles
+system.iocache.WriteReq_miss_latency::tsunami.ide  13194182648                       # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total  13194182648                       # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide  13215316531                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total  13215316531                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide  13215316531                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total  13215316531                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
@@ -458,17 +374,17 @@ system.iocache.overall_miss_rate::tsunami.ide            1
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
 system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122161.173410                       # average ReadReq miss latency
 system.iocache.ReadReq_avg_miss_latency::total 122161.173410                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::tsunami.ide 312257.618406                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 312257.618406                       # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 311469.441414                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 311469.441414                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 311469.441414                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 311469.441414                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs        401483                       # number of cycles access was blocked
+system.iocache.WriteReq_avg_miss_latency::tsunami.ide 317534.237774                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 317534.237774                       # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 316724.182888                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 316724.182888                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 316724.182888                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 316724.182888                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs        393531                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                29284                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                28535                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs    13.709978                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs    13.791169                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -484,12 +400,12 @@ system.iocache.overall_mshr_misses::tsunami.ide        41725
 system.iocache.overall_mshr_misses::total        41725                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12136883                       # number of ReadReq MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_latency::total     12136883                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::tsunami.ide  10812648570                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total  10812648570                       # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide  10824785453                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total  10824785453                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide  10824785453                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total  10824785453                       # number of overall MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::tsunami.ide  11031075660                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total  11031075660                       # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide  11043212543                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total  11043212543                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide  11043212543                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total  11043212543                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
@@ -500,12 +416,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide            1
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
 system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70155.393064                       # average ReadReq mshr miss latency
 system.iocache.ReadReq_avg_mshr_miss_latency::total 70155.393064                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 260219.690268                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 260219.690268                       # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 259431.646567                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 259431.646567                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 259431.646567                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 259431.646567                       # average overall mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 265476.406912                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 265476.406912                       # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 264666.567837                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 264666.567837                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 264666.567837                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 264666.567837                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -519,36 +435,36 @@ system.disk2.dma_read_txs                           0                       # Nu
 system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
 system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
 system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
-system.cpu.branchPred.lookups                13863448                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          11631259                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            399718                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              9400932                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 5821857                       # Number of BTB hits
+system.cpu.branchPred.lookups                13847711                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          11622265                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            397151                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              9355929                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 5809145                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             61.928509                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                  906521                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              39211                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             62.090520                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                  903416                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              38861                       # Number of incorrect RAS predictions.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                      9926517                       # DTB read hits
-system.cpu.dtb.read_misses                      41406                       # DTB read misses
-system.cpu.dtb.read_acv                           531                       # DTB read access violations
-system.cpu.dtb.read_accesses                   940700                       # DTB read accesses
-system.cpu.dtb.write_hits                     6593963                       # DTB write hits
-system.cpu.dtb.write_misses                     10630                       # DTB write misses
-system.cpu.dtb.write_acv                          410                       # DTB write access violations
-system.cpu.dtb.write_accesses                  338096                       # DTB write accesses
-system.cpu.dtb.data_hits                     16520480                       # DTB hits
-system.cpu.dtb.data_misses                      52036                       # DTB misses
-system.cpu.dtb.data_acv                           941                       # DTB access violations
-system.cpu.dtb.data_accesses                  1278796                       # DTB accesses
-system.cpu.itb.fetch_hits                     1306353                       # ITB hits
-system.cpu.itb.fetch_misses                     36823                       # ITB misses
-system.cpu.itb.fetch_acv                         1069                       # ITB acv
-system.cpu.itb.fetch_accesses                 1343176                       # ITB accesses
+system.cpu.dtb.read_hits                      9926060                       # DTB read hits
+system.cpu.dtb.read_misses                      41229                       # DTB read misses
+system.cpu.dtb.read_acv                           545                       # DTB read access violations
+system.cpu.dtb.read_accesses                   943227                       # DTB read accesses
+system.cpu.dtb.write_hits                     6592681                       # DTB write hits
+system.cpu.dtb.write_misses                     10567                       # DTB write misses
+system.cpu.dtb.write_acv                          408                       # DTB write access violations
+system.cpu.dtb.write_accesses                  338977                       # DTB write accesses
+system.cpu.dtb.data_hits                     16518741                       # DTB hits
+system.cpu.dtb.data_misses                      51796                       # DTB misses
+system.cpu.dtb.data_acv                           953                       # DTB access violations
+system.cpu.dtb.data_accesses                  1282204                       # DTB accesses
+system.cpu.itb.fetch_hits                     1307907                       # ITB hits
+system.cpu.itb.fetch_misses                     36763                       # ITB misses
+system.cpu.itb.fetch_acv                         1058                       # ITB acv
+system.cpu.itb.fetch_accesses                 1344670                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -561,269 +477,269 @@ system.cpu.itb.data_hits                            0                       # DT
 system.cpu.itb.data_misses                          0                       # DTB misses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.numCycles                        121966998                       # number of cpu cycles simulated
+system.cpu.numCycles                        122133073                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           28067964                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                       70813073                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    13863448                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches            6728378                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      13263425                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 1999195                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles               38181411                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                33091                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        255000                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles       364206                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          297                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                   8556045                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                264477                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples           81457086                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.869330                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.212823                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           28029052                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                       70711644                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    13847711                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            6712561                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      13244944                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 1986135                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles               38034896                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                32174                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        253831                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles       364385                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          294                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                   8541461                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                263003                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples           81242947                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.870373                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.213979                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 68193661     83.72%     83.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                   852857      1.05%     84.76% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  1696439      2.08%     86.85% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                   825181      1.01%     87.86% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  2758325      3.39%     91.25% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                   561473      0.69%     91.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                   645881      0.79%     92.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1010308      1.24%     93.97% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                  4912961      6.03%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 67998003     83.70%     83.70% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                   851901      1.05%     84.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  1695578      2.09%     86.83% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                   822984      1.01%     87.85% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  2755109      3.39%     91.24% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                   560259      0.69%     91.93% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                   643349      0.79%     92.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1008302      1.24%     93.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                  4907462      6.04%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total             81457086                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.113666                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.580592                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 29256938                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              37863691                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  12127839                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                959156                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                1249461                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved               584263                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 42640                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts               69481989                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                129319                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                1249461                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 30407522                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                14148846                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       20005990                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  11332374                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               4312891                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts               65679549                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                  7211                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 504797                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               1541440                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands            43855166                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups              79746051                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups         79567055                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups            166544                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps              38180329                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                  5674829                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts            1682909                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts         240455                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  12257327                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             10441163                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores             6908790                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1318239                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores           851396                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                   58211664                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             2050007                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                  56814932                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            114609                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined         6922962                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined      3587498                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved        1389025                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples      81457086                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.697483                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.359485                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total             81242947                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.113382                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.578972                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 29204589                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              37726390                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  12112827                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                958015                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                1241125                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved               582779                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 42656                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts               69393384                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                129440                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                1241125                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 30348079                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                14012797                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       20034433                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  11321379                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               4285132                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts               65602946                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                  7156                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 505213                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               1511728                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands            43797820                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups              79654521                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups         79475437                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups            166633                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps              38179156                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                  5618656                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            1682920                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts         240154                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  12205182                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             10434201                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores             6904424                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1321264                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores           860087                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                   58162225                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             2049609                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                  56784496                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            110090                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined         6876207                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined      3554384                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved        1388666                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples      81242947                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.698947                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.361354                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            56746030     69.66%     69.66% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            10887232     13.37%     83.03% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             5162469      6.34%     89.37% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             3392471      4.16%     93.53% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             2625915      3.22%     96.76% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             1461124      1.79%     98.55% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6              753330      0.92%     99.47% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              332031      0.41%     99.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8               96484      0.12%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            56591956     69.66%     69.66% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            10816248     13.31%     82.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             5164366      6.36%     89.33% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             3390360      4.17%     93.50% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             2636798      3.25%     96.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             1463129      1.80%     98.55% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6              751413      0.92%     99.47% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              332295      0.41%     99.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8               96382      0.12%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total        81457086                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        81242947                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                   91940     11.62%     11.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     11.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     11.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     11.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     11.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     11.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     11.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     11.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     11.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     11.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     11.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     11.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     11.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     11.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     11.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     11.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     11.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     11.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     11.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     11.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     11.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     11.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     11.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     11.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     11.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     11.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     11.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     11.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     11.62% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                 373423     47.20%     58.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                325849     41.18%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                   91428     11.57%     11.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     11.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     11.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     11.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     11.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     11.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     11.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     11.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     11.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     11.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     11.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     11.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     11.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     11.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     11.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     11.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     11.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     11.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     11.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     11.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     11.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     11.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     11.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     11.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     11.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     11.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     11.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     11.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     11.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 372699     47.16%     58.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                326088     41.27%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass              7286      0.01%      0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              38737583     68.18%     68.19% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                61738      0.11%     68.30% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     68.30% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd               25607      0.05%     68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                3636      0.01%     68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             10357242     18.23%     86.58% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             6672763     11.74%     98.33% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess             949077      1.67%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              38710597     68.17%     68.18% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                61705      0.11%     68.29% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     68.29% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd               25607      0.05%     68.34% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     68.34% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     68.34% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     68.34% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                3636      0.01%     68.34% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     68.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     68.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     68.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     68.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     68.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     68.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     68.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     68.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     68.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     68.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     68.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     68.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     68.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     68.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     68.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     68.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     68.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     68.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     68.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     68.34% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             10355398     18.24%     86.58% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             6671255     11.75%     98.33% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess             949012      1.67%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total               56814932                       # Type of FU issued
-system.cpu.iq.rate                           0.465822                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                      791212                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.013926                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          195300199                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes          66861892                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     55573336                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads              692571                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes             336551                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses       327871                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses               57237458                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                  361400                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads           598272                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total               56784496                       # Type of FU issued
+system.cpu.iq.rate                           0.464940                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                      790215                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.013916                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          195020122                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes          66766340                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     55549754                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads              692121                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes             335594                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses       327937                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses               57205980                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                  361445                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads           599867                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      1348718                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         3201                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        14139                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores       530806                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      1342082                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         3325                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        14250                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores       526611                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        17937                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        182742                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        17915                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        172386                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                1249461                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                10237116                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                702035                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts            63785040                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            690324                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              10441163                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts              6908790                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            1805677                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 512237                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 17569                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          14139                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         202047                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       411314                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               613361                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts              56348369                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts               9996094                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts            466562                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                1241125                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                10205447                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                698563                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts            63733516                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            684669                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              10434201                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts              6904424                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            1805473                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 512478                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 17546                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          14250                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         200257                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       411476                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               611733                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts              56321962                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts               9995488                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            462533                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                       3523369                       # number of nop insts executed
-system.cpu.iew.exec_refs                     16615920                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                  8927027                       # Number of branches executed
-system.cpu.iew.exec_stores                    6619826                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.461997                       # Inst execution rate
-system.cpu.iew.wb_sent                       56016387                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      55901207                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  27709617                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  37531222                       # num instructions consuming a value
+system.cpu.iew.exec_nop                       3521682                       # number of nop insts executed
+system.cpu.iew.exec_refs                     16613940                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                  8922207                       # Number of branches executed
+system.cpu.iew.exec_stores                    6618452                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.461152                       # Inst execution rate
+system.cpu.iew.wb_sent                       55993079                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      55877691                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  27722224                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  37565081                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.458331                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.738308                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.457515                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.737979                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts         7496348                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls          660982                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            568504                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples     80207625                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.700316                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.629380                       # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts         7447390                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls          660943                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            565908                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples     80001822                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.702098                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.631989                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     59390670     74.05%     74.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1      8659340     10.80%     84.84% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      4620197      5.76%     90.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      2517886      3.14%     93.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1507376      1.88%     95.62% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5       612052      0.76%     96.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       525608      0.66%     97.04% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       522089      0.65%     97.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      1852407      2.31%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     59240837     74.05%     74.05% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1      8588333     10.74%     84.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      4609463      5.76%     90.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      2533581      3.17%     93.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1517845      1.90%     95.61% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5       611107      0.76%     96.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       522353      0.65%     97.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       526375      0.66%     97.69% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      1851928      2.31%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total     80207625                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts             56170683                       # Number of instructions committed
-system.cpu.commit.committedOps               56170683                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total     80001822                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts             56169084                       # Number of instructions committed
+system.cpu.commit.committedOps               56169084                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       15470429                       # Number of memory references committed
-system.cpu.commit.loads                       9092445                       # Number of loads committed
-system.cpu.commit.membars                      226358                       # Number of memory barriers committed
-system.cpu.commit.branches                    8439899                       # Number of branches committed
+system.cpu.commit.refs                       15469932                       # Number of memory references committed
+system.cpu.commit.loads                       9092119                       # Number of loads committed
+system.cpu.commit.membars                      226344                       # Number of memory barriers committed
+system.cpu.commit.branches                    8439731                       # Number of branches committed
 system.cpu.commit.fp_insts                     324384                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                  52020266                       # Number of committed integer instructions.
-system.cpu.commit.function_calls               740581                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events               1852407                       # number cycles where commit BW limit reached
+system.cpu.commit.int_insts                  52018783                       # Number of committed integer instructions.
+system.cpu.commit.function_calls               740550                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events               1851928                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    141772543                       # The number of ROB reads
-system.cpu.rob.rob_writes                   128585215                       # The number of ROB writes
-system.cpu.timesIdled                         1193212                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        40509912                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   3598422122                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                    52979882                       # Number of Instructions Simulated
-system.cpu.committedOps                      52979882                       # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total              52979882                       # Number of Instructions Simulated
-system.cpu.cpi                               2.302138                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         2.302138                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.434379                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.434379                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                 73881277                       # number of integer regfile reads
-system.cpu.int_regfile_writes                40316653                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                    166009                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                   167434                       # number of floating regfile writes
-system.cpu.misc_regfile_reads                 2028435                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                 938984                       # number of misc regfile writes
+system.cpu.rob.rob_reads                    141516799                       # The number of ROB reads
+system.cpu.rob.rob_writes                   128475885                       # The number of ROB writes
+system.cpu.timesIdled                         1198400                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        40890126                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   3598244060                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                    52978349                       # Number of Instructions Simulated
+system.cpu.committedOps                      52978349                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total              52978349                       # Number of Instructions Simulated
+system.cpu.cpi                               2.305339                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         2.305339                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.433776                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.433776                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                 73853807                       # number of integer regfile reads
+system.cpu.int_regfile_writes                40298046                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                    166062                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                   167446                       # number of floating regfile writes
+system.cpu.misc_regfile_reads                 2027357                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                 938942                       # number of misc regfile writes
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
 system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
@@ -858,9 +774,9 @@ system.tsunami.ethernet.droppedPackets              0                       # nu
 system.iobus.throughput                       1454553                       # Throughput (bytes/s)
 system.iobus.trans_dist::ReadReq                 7103                       # Transaction distribution
 system.iobus.trans_dist::ReadResp                7103                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               51150                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              51150                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5052                       # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::WriteReq               51149                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              51149                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5050                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          472                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
@@ -872,11 +788,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total        33056                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total        33054                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83450                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::total        83450                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  116506                       # Packet count per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio        20208                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  116504                       # Packet count per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio        20200                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio         1888                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
@@ -888,12 +804,12 @@ system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total        44148                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::total        44140                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661608                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.tsunami.ide.dma::total      2661608                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total              2705756                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus                 2705756                       # Total data (bytes)
-system.iobus.reqLayer0.occupancy              4663000                       # Layer occupancy (ticks)
+system.iobus.tot_pkt_size::total              2705748                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus                 2705748                       # Total data (bytes)
+system.iobus.reqLayer0.occupancy              4661000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy               353000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
@@ -915,249 +831,241 @@ system.iobus.reqLayer27.occupancy               76000                       # La
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy              110000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer29.occupancy           377738948                       # Layer occupancy (ticks)
+system.iobus.reqLayer29.occupancy           380111537                       # Layer occupancy (ticks)
 system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer30.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer30.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            23458000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            23457000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            42679505                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            43192006                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.throughput               111941811                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq        2118263                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2118167                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq          9598                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp         9598                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       840743                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq           64                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp           66                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       342536                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       300985                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::BadAddressError           79                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2020543                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3677710                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           5698253                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     64653440                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    143572596                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      208226036                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus         208215988                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus        17920                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy     2480284498                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.throughput               111856774                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq        2116112                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2116015                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq          9597                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp         9597                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       840541                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq           62                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq            1                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp           63                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       342408                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       300857                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::BadAddressError           80                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2017437                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3676056                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           5693493                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     64554304                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    143513388                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      208067692                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         208057644                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus        17408                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy     2478840496                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
 system.cpu.toL2Bus.snoopLayer0.occupancy       235500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    1518802860                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    1516414125                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2192631666                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    2186111163                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
-system.cpu.icache.tags.replacements           1009602                       # number of replacements
-system.cpu.icache.tags.tagsinuse           509.660060                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs             7489391                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           1010110                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              7.414431                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       26489829250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   509.660060                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.995430                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.995430                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements           1008048                       # number of replacements
+system.cpu.icache.tags.tagsinuse           509.665585                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs             7476650                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           1008556                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs              7.413222                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       26682759250                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   509.665585                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.995441                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.995441                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          508                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           72                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          112                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          324                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           73                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          120                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          315                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.992188                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses           9566377                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses          9566377                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst      7489392                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total         7489392                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst       7489392                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total          7489392                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst      7489392                       # number of overall hits
-system.cpu.icache.overall_hits::total         7489392                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1066652                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1066652                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1066652                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1066652                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1066652                       # number of overall misses
-system.cpu.icache.overall_misses::total       1066652                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  14896343949                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  14896343949                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  14896343949                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  14896343949                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  14896343949                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  14896343949                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst      8556044                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total      8556044                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst      8556044                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total      8556044                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst      8556044                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total      8556044                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.124666                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.124666                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.124666                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.124666                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.124666                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.124666                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13965.514478                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13965.514478                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13965.514478                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13965.514478                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13965.514478                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13965.514478                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         4660                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               199                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    23.417085                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.icache.tags.tag_accesses           9550236                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses          9550236                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst      7476651                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total         7476651                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst       7476651                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total          7476651                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst      7476651                       # number of overall hits
+system.cpu.icache.overall_hits::total         7476651                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1064809                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1064809                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1064809                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1064809                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1064809                       # number of overall misses
+system.cpu.icache.overall_misses::total       1064809                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  14791038698                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  14791038698                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  14791038698                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  14791038698                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  14791038698                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  14791038698                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst      8541460                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total      8541460                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst      8541460                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total      8541460                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst      8541460                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total      8541460                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.124664                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.124664                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.124664                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.124664                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.124664                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.124664                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13890.790459                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13890.790459                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13890.790459                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13890.790459                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13890.790459                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13890.790459                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         5929                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets          286                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               183                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               1                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    32.398907                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          286                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        56319                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        56319                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        56319                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        56319                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        56319                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        56319                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1010333                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      1010333                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      1010333                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      1010333                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      1010333                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      1010333                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12206065633                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  12206065633                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12206065633                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  12206065633                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12206065633                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  12206065633                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.118084                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.118084                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.118084                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.118084                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.118084                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.118084                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12081.230281                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12081.230281                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12081.230281                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12081.230281                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12081.230281                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12081.230281                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        56033                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        56033                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        56033                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        56033                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        56033                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        56033                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1008776                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total      1008776                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst      1008776                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total      1008776                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst      1008776                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total      1008776                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12131918870                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  12131918870                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12131918870                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  12131918870                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12131918870                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  12131918870                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.118103                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.118103                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.118103                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.118103                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.118103                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.118103                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12026.375399                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12026.375399                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12026.375399                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 12026.375399                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12026.375399                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 12026.375399                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           338298                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65338.001327                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            2546240                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           403465                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             6.310932                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle       5511908750                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 53847.908430                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  5309.513440                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  6180.579458                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.821654                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.081017                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.094308                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.996979                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.replacements           338266                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65338.058683                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            2543929                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           403433                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             6.305704                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle       5551710750                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 53796.698722                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  5304.345669                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  6237.014293                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.820872                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.080938                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.095169                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.996980                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        65167                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          492                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1         3492                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3315                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2416                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55452                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1         3493                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3306                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2414                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55462                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994370                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         26727370                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        26727370                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst       995146                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data       827013                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1822159                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       840743                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       840743                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data           26                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total           26                       # number of UpgradeReq hits
+system.cpu.l2cache.tags.tag_accesses         26707389                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        26707389                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst       993608                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data       826462                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        1820070                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       840541                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       840541                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data           20                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total           20                       # number of UpgradeReq hits
 system.cpu.l2cache.SCUpgradeReq_hits::cpu.data            1                       # number of SCUpgradeReq hits
 system.cpu.l2cache.SCUpgradeReq_hits::total            1                       # number of SCUpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       185570                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       185570                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst       995146                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      1012583                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2007729                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst       995146                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      1012583                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2007729                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst        15064                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data       273814                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total       288878                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data           38                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total           38                       # number of UpgradeReq misses
-system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            1                       # number of SCUpgradeReq misses
-system.cpu.l2cache.SCUpgradeReq_misses::total            1                       # number of SCUpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       115414                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       115414                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst        15064                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       389228                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        404292                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst        15064                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       389228                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       404292                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   1218545993                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data  17819527728                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total  19038073721                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_hits::cpu.data       185429                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       185429                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst       993608                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      1011891                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2005499                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst       993608                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      1011891                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2005499                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst        15053                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data       273771                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total       288824                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data           42                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total           42                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       115427                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       115427                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst        15053                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       389198                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        404251                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst        15053                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       389198                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       404251                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   1161439993                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data  17964720233                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total  19126160226                       # number of ReadReq miss cycles
 system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       262498                       # number of UpgradeReq miss cycles
 system.cpu.l2cache.UpgradeReq_miss_latency::total       262498                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data        22999                       # number of SCUpgradeReq miss cycles
-system.cpu.l2cache.SCUpgradeReq_miss_latency::total        22999                       # number of SCUpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   9547009857                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   9547009857                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst   1218545993                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  27366537585                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  28585083578                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst   1218545993                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  27366537585                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  28585083578                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst      1010210                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      1100827                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      2111037                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       840743                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       840743                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data           64                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total           64                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            2                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::total            2                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       300984                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       300984                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst      1010210                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      1401811                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2412021                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst      1010210                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      1401811                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2412021                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.014912                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.248735                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.136842                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.593750                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.593750                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.500000                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::total     0.500000                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.383456                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.383456                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.014912                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.277661                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.167615                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.014912                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.277661                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.167615                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80891.263476                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65078.950412                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 65903.508474                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data  6907.842105                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total  6907.842105                       # average UpgradeReq miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        22999                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        22999                       # average SCUpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82719.686147                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82719.686147                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80891.263476                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70309.786513                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 70704.054441                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80891.263476                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70309.786513                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 70704.054441                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   9625411610                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   9625411610                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst   1161439993                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  27590131843                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  28751571836                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst   1161439993                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  27590131843                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  28751571836                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst      1008661                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      1100233                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      2108894                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       840541                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       840541                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data           62                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total           62                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            1                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu.l2cache.SCUpgradeReq_accesses::total            1                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       300856                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       300856                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst      1008661                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      1401089                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2409750                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst      1008661                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      1401089                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2409750                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.014924                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.248830                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.136955                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.677419                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.677419                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.383662                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.383662                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.014924                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.277782                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.167756                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.014924                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.277782                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.167756                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77156.712483                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65619.514971                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 66220.813457                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data  6249.952381                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total  6249.952381                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83389.602173                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83389.602173                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77156.712483                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70889.706121                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 71123.069172                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77156.712483                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70889.706121                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 71123.069172                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1166,80 +1074,72 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        75917                       # number of writebacks
-system.cpu.l2cache.writebacks::total            75917                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks        75916                       # number of writebacks
+system.cpu.l2cache.writebacks::total            75916                       # number of writebacks
 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            1                       # number of ReadReq MSHR hits
 system.cpu.l2cache.ReadReq_mshr_hits::total            1                       # number of ReadReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::total            1                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total            1                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        15063                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       273814                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total       288877                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           38                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total           38                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            1                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            1                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       115414                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       115414                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        15063                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       389228                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       404291                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        15063                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       389228                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       404291                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   1028470757                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  14406345772                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  15434816529                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       532033                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       532033                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data        10001                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total        10001                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   8124534143                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8124534143                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1028470757                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  22530879915                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  23559350672                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1028470757                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  22530879915                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  23559350672                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1333940000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1333940000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   1882589500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   1882589500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   3216529500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3216529500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.014911                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.248735                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.136841                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.593750                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.593750                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.500000                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.500000                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.383456                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.383456                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.014911                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.277661                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.167615                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.014911                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.277661                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.167615                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 68277.949744                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52613.620092                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53430.409929                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14000.868421                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14000.868421                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        10001                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70394.702055                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70394.702055                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68277.949744                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57886.071698                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58273.250386                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68277.949744                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57886.071698                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58273.250386                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        15052                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       273771                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total       288823                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           42                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total           42                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       115427                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       115427                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        15052                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       389198                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       404250                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        15052                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       389198                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       404250                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    971628757                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  14552447267                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  15524076024                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       573037                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       573037                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   8203174390                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8203174390                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    971628757                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  22755621657                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  23727250414                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    971628757                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  22755621657                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  23727250414                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1334007000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1334007000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   1882413000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   1882413000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   3216420000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3216420000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.014923                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.248830                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.136955                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.677419                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.677419                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.383662                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.383662                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.014923                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.277782                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.167756                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.014923                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.277782                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.167756                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64551.472030                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 53155.547034                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53749.445245                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13643.738095                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13643.738095                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71068.072375                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71068.072375                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64551.472030                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58467.981996                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58694.497004                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64551.472030                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58467.981996                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58694.497004                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1247,13 +1147,13 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements           1401219                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.994567                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            11810743                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1401731                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs              8.425827                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle          25477000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.994567                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.replacements           1400496                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.994513                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            11811358                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1401008                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs              8.430614                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle          25856000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.994513                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999989                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999989                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
@@ -1261,154 +1161,154 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0          415
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           94                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2            3                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          63738376                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         63738376                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data      7205308                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total         7205308                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      4203634                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        4203634                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       186044                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       186044                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       215517                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       215517                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      11408942                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         11408942                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     11408942                       # number of overall hits
-system.cpu.dcache.overall_hits::total        11408942                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1806790                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1806790                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1944128                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1944128                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        22738                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        22738                       # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      3750918                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3750918                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      3750918                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3750918                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  40335866684                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  40335866684                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  77256495609                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  77256495609                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    322518001                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    322518001                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data        39001                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total        39001                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 117592362293                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 117592362293                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 117592362293                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 117592362293                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data      9012098                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total      9012098                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      6147762                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      6147762                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       208782                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       208782                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       215519                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       215519                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     15159860                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     15159860                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     15159860                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     15159860                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.200485                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.200485                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.316233                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.316233                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.108908                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.108908                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000009                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total     0.000009                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.247424                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.247424                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.247424                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.247424                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22324.601467                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 22324.601467                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39738.379165                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 39738.379165                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14184.097150                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14184.097150                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19500.500000                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19500.500000                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 31350.288727                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 31350.288727                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 31350.288727                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 31350.288727                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs      3041849                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets          733                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs             98391                       # number of cycles access was blocked
+system.cpu.dcache.tags.tag_accesses          63734677                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         63734677                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data      7206132                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total         7206132                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      4203012                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        4203012                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       186466                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       186466                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       215515                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       215515                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      11409144                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         11409144                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     11409144                       # number of overall hits
+system.cpu.dcache.overall_hits::total        11409144                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1805019                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1805019                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1944584                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1944584                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        22688                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        22688                       # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data            1                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total            1                       # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data      3749603                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3749603                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      3749603                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3749603                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  40356893890                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  40356893890                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  77719104532                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  77719104532                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    321753501                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    321753501                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data        13000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total        13000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 118075998422                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 118075998422                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 118075998422                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 118075998422                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data      9011151                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total      9011151                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      6147596                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      6147596                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       209154                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       209154                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       215516                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       215516                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     15158747                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     15158747                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     15158747                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     15158747                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.200309                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.200309                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.316316                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.316316                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.108475                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.108475                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000005                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total     0.000005                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.247356                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.247356                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.247356                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.247356                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22358.154618                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 22358.154618                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39966.956702                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 39966.956702                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14181.659952                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14181.659952                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        13000                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total        13000                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 31490.266682                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 31490.266682                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 31490.266682                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 31490.266682                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs      3050951                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets          663                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs             86776                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               7                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    30.915927                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets   104.714286                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    35.158926                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    94.714286                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       840743                       # number of writebacks
-system.cpu.dcache.writebacks::total            840743                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       722826                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       722826                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1643736                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      1643736                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         5220                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total         5220                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      2366562                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      2366562                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      2366562                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      2366562                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1083964                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1083964                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       300392                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       300392                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        17518                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total        17518                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            2                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1384356                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1384356                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1384356                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1384356                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  27183263254                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  27183263254                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11761438359                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  11761438359                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    200916999                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    200916999                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data        34999                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total        34999                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  38944701613                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  38944701613                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  38944701613                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  38944701613                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1424030000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1424030000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   1997779498                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   1997779498                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3421809498                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total   3421809498                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.120279                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.120279                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.048862                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.048862                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.083906                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.083906                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000009                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000009                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091317                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.091317                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091317                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.091317                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25077.643957                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25077.643957                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39153.633782                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39153.633782                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11469.174506                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11469.174506                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17499.500000                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17499.500000                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28131.999004                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 28131.999004                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28131.999004                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 28131.999004                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks       840541                       # number of writebacks
+system.cpu.dcache.writebacks::total            840541                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       721694                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       721694                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1644324                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      1644324                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         5123                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total         5123                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      2366018                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      2366018                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      2366018                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      2366018                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1083325                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1083325                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       300260                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       300260                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        17565                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total        17565                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            1                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total            1                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1383585                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1383585                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1383585                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1383585                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  27323478009                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  27323478009                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11844407335                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  11844407335                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    200869499                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    200869499                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data        11000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total        11000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  39167885344                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  39167885344                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  39167885344                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  39167885344                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1424097000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1424097000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   1997590998                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   1997590998                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3421687998                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   3421687998                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.120220                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.120220                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.048842                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.048842                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.083981                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.083981                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000005                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000005                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091273                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.091273                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091273                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.091273                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25221.866023                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25221.866023                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39447.170236                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39447.170236                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11435.781327                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11435.781327                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        11000                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        11000                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28308.983795                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 28308.983795                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28308.983795                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 28308.983795                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1417,28 +1317,28 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                     6442                       # number of quiesce instructions executed
-system.cpu.kern.inst.hwrei                     211017                       # number of hwrei instructions executed
-system.cpu.kern.ipl_count::0                    74665     40.97%     40.97% # number of times we switched to this ipl
+system.cpu.kern.inst.quiesce                     6439                       # number of quiesce instructions executed
+system.cpu.kern.inst.hwrei                     211003                       # number of hwrei instructions executed
+system.cpu.kern.ipl_count::0                    74661     40.97%     40.97% # number of times we switched to this ipl
 system.cpu.kern.ipl_count::21                     131      0.07%     41.04% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::22                    1880      1.03%     42.07% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31                  105572     57.93%    100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total               182248                       # number of times we switched to this ipl
-system.cpu.kern.ipl_good::0                     73298     49.32%     49.32% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_count::22                    1879      1.03%     42.07% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::31                  105563     57.93%    100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::total               182234                       # number of times we switched to this ipl
+system.cpu.kern.ipl_good::0                     73294     49.32%     49.32% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::21                      131      0.09%     49.41% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::22                     1880      1.27%     50.68% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::31                    73298     49.32%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::total                148607                       # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0             1818029044000     97.73%     97.73% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21                64103000      0.00%     97.74% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22               561251500      0.03%     97.77% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31             41542545500      2.23%    100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total         1860196944000                       # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used::0                  0.981692                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_good::22                     1879      1.26%     50.68% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::31                    73294     49.32%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::total                148598                       # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks::0             1817851866500     97.72%     97.72% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::21                64172000      0.00%     97.73% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::22               559556500      0.03%     97.76% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31             41715361500      2.24%    100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total         1860190956500                       # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used::0                  0.981691                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31                 0.694294                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::total              0.815411                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::31                 0.694315                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::total              0.815424                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
 system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
 system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
@@ -1477,29 +1377,29 @@ system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # nu
 system.cpu.kern.callpal::swpctx                  4176      2.18%      2.18% # number of callpals executed
 system.cpu.kern.callpal::tbi                       54      0.03%      2.21% # number of callpals executed
 system.cpu.kern.callpal::wrent                      7      0.00%      2.21% # number of callpals executed
-system.cpu.kern.callpal::swpipl                175131     91.23%     93.43% # number of callpals executed
+system.cpu.kern.callpal::swpipl                175119     91.23%     93.43% # number of callpals executed
 system.cpu.kern.callpal::rdps                    6784      3.53%     96.97% # number of callpals executed
 system.cpu.kern.callpal::wrkgp                      1      0.00%     96.97% # number of callpals executed
 system.cpu.kern.callpal::wrusp                      7      0.00%     96.97% # number of callpals executed
 system.cpu.kern.callpal::rdusp                      9      0.00%     96.98% # number of callpals executed
 system.cpu.kern.callpal::whami                      2      0.00%     96.98% # number of callpals executed
-system.cpu.kern.callpal::rti                     5105      2.66%     99.64% # number of callpals executed
+system.cpu.kern.callpal::rti                     5104      2.66%     99.64% # number of callpals executed
 system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
 system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
-system.cpu.kern.callpal::total                 191976                       # number of callpals executed
-system.cpu.kern.mode_switch::kernel              5852                       # number of protection mode switches
+system.cpu.kern.callpal::total                 191963                       # number of callpals executed
+system.cpu.kern.mode_switch::kernel              5851                       # number of protection mode switches
 system.cpu.kern.mode_switch::user                1740                       # number of protection mode switches
 system.cpu.kern.mode_switch::idle                2095                       # number of protection mode switches
 system.cpu.kern.mode_good::kernel                1910                      
 system.cpu.kern.mode_good::user                  1740                      
 system.cpu.kern.mode_good::idle                   170                      
-system.cpu.kern.mode_switch_good::kernel     0.326384                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::kernel     0.326440                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good::idle       0.081146                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total      0.394343                       # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel        29636227500      1.59%      1.59% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user           2736556500      0.15%      1.74% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle         1827824152000     98.26%    100.00% # number of ticks spent at the given mode
+system.cpu.kern.mode_switch_good::total      0.394384                       # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks::kernel        29573655500      1.59%      1.59% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user           2713841000      0.15%      1.74% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle         1827903452000     98.26%    100.00% # number of ticks spent at the given mode
 system.cpu.kern.swap_context                     4177                       # number of times the context was actually changed
 
 ---------- End Simulation Statistics   ----------
index 76117c4c224658530a49f042276b44372e0aefdf..d0170b803b2dc01b0a24c22f893761fd4180cb75 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.842697                       # Number of seconds simulated
-sim_ticks                                1842697218000                       # Number of ticks simulated
-final_tick                               1842697218000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.842694                       # Number of seconds simulated
+sim_ticks                                1842693728000                       # Number of ticks simulated
+final_tick                               1842693728000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 281851                       # Simulator instruction rate (inst/s)
-host_op_rate                                   281851                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             7098045398                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 310872                       # Number of bytes of host memory used
-host_seconds                                   259.61                       # Real time elapsed on the host
-sim_insts                                    73170192                       # Number of instructions simulated
-sim_ops                                      73170192                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 239111                       # Simulator instruction rate (inst/s)
+host_op_rate                                   239111                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             5964368765                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 346744                       # Number of bytes of host memory used
+host_seconds                                   308.95                       # Real time elapsed on the host
+sim_insts                                    73873335                       # Number of instructions simulated
+sim_ops                                      73873335                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.inst           489152                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         20102912                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           489024                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         20126208                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide        2652352                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           144448                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          2236224                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst           284928                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data          2526528                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             28436544                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       489152                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       144448                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst       284928                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          918528                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7459712                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7459712                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst              7643                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            314108                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::cpu1.inst           143680                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          2232768                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst           285376                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data          2509376                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             28438784                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       489024                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       143680                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst       285376                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          918080                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7463104                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7463104                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst              7641                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            314472                       # Number of read requests responded to by this memory
 system.physmem.num_reads::tsunami.ide           41443                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              2257                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             34941                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst              4452                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data             39477                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                444321                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          116558                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               116558                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst              265454                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            10909504                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide           1439386                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               78389                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             1213560                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst              154626                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data             1371103                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                15432022                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         265454                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          78389                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst         154626                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             498469                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           4048257                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4048257                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           4048257                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             265454                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           10909504                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide          1439386                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              78389                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            1213560                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst             154626                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data            1371103                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               19480279                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                         98018                       # Number of read requests accepted
-system.physmem.writeReqs                        44365                       # Number of write requests accepted
-system.physmem.readBursts                       98018                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      44365                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  6272576                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                       576                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   2838464                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   6273152                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                2839360                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                        9                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.num_reads::cpu1.inst              2245                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             34887                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst              4459                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data             39209                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                444356                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          116611                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               116611                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst              265385                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data            10922167                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide           1439388                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               77973                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             1211687                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst              154869                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data             1361798                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                15433267                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         265385                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          77973                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst         154869                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             498227                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           4050105                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                4050105                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           4050105                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             265385                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           10922167                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide          1439388                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              77973                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            1211687                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst             154869                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data            1361798                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               19483372                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                         97691                       # Number of read requests accepted
+system.physmem.writeReqs                        44282                       # Number of write requests accepted
+system.physmem.readBursts                       97691                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      44282                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  6250944                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      1280                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   2832576                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   6252224                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                2834048                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                       20                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs             42                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                6238                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                6029                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                6222                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                6415                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                5671                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                6259                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                6020                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                6028                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                6370                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                6122                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               6366                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               5871                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               5882                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               6242                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               6237                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               6037                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                2849                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                2656                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                2849                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                3015                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                2565                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                2994                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                2937                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                2695                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                3093                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                2622                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               2879                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               2436                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               2462                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               2714                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               2848                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs             39                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0                6114                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                5899                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                6060                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                6276                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                5549                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                6233                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                6082                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                6075                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                6372                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                6119                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               6443                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               5953                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               5846                       # Per bank write bursts
+system.physmem.perBankRdBursts::13               6273                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               6335                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               6042                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                2746                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                2526                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                2727                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                3010                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                2533                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                2968                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                2994                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                2697                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                3092                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                2617                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               2969                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               2522                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               2428                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               2745                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               2948                       # Per bank write bursts
 system.physmem.perBankWrBursts::15               2737                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           4                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1841684892500                       # Total gap between requests
+system.physmem.numWrRetry                           5                       # Number of times write queue was full causing retry
+system.physmem.totGap                    1841681402500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                   98018                       # Read request sizes (log2)
+system.physmem.readPktSize::6                   97691                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  44365                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     66438                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     14086                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      6897                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      2022                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       974                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                       959                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                       570                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                       558                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                       553                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                       609                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      552                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      526                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      458                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      405                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      402                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      401                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      400                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                      400                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                      398                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                      398                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        3                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  44282                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     65712                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      9632                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      5477                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      1935                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                       488                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      1780                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      1567                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      1574                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      1624                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                      1032                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      859                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      829                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      762                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      744                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                      633                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                      617                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                      601                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                      609                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                      699                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                      495                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
@@ -153,423 +153,391 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                      1794                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                      1779                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                      1773                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                      2070                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                      2377                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                      2093                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                      2091                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                      2114                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                      2131                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                      1839                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                     1836                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                     1834                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                     2181                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                     2225                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                     2215                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2240                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2258                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     1840                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     1844                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     1791                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     1859                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     1924                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                      111                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                       69                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                       17                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                       12                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                        7                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                        7                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                        9                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        17929                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      508.069831                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     168.315652                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev    1577.422962                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64-67           7580     42.28%     42.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-131         2972     16.58%     58.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192-195         1827     10.19%     69.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-259          983      5.48%     74.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320-323          676      3.77%     78.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-387          569      3.17%     81.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448-451          353      1.97%     83.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-515          316      1.76%     85.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576-579          239      1.33%     86.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-643          212      1.18%     87.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704-707          225      1.25%     88.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-771          207      1.15%     90.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832-835           92      0.51%     90.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-899           80      0.45%     91.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960-963           62      0.35%     91.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1027          115      0.64%     92.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088-1091           35      0.20%     92.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152-1155           50      0.28%     92.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216-1219           54      0.30%     92.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280-1283           63      0.35%     93.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344-1347           30      0.17%     93.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408-1411          123      0.69%     94.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472-1475           74      0.41%     94.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536-1539           80      0.45%     94.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600-1603           19      0.11%     95.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664-1667           17      0.09%     95.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1728-1731            7      0.04%     95.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1792-1795           37      0.21%     95.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856-1859            7      0.04%     95.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1920-1923           18      0.10%     95.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984-1987            6      0.03%     95.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2048-2051           15      0.08%     95.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112-2115            9      0.05%     95.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2176-2179           16      0.09%     95.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2240-2243            1      0.01%     95.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2304-2307           23      0.13%     95.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2432-2435           12      0.07%     95.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2496-2499            4      0.02%     95.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2560-2563            9      0.05%     96.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2624-2627            2      0.01%     96.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2688-2691           15      0.08%     96.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2816-2819           22      0.12%     96.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2880-2883            1      0.01%     96.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2944-2947           14      0.08%     96.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3008-3011            3      0.02%     96.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3072-3075           12      0.07%     96.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3136-3139            2      0.01%     96.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3200-3203           12      0.07%     96.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3264-3267            2      0.01%     96.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3328-3331           20      0.11%     96.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3456-3459           11      0.06%     96.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3520-3523            2      0.01%     96.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3584-3587            9      0.05%     96.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3648-3651            1      0.01%     96.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3712-3715           13      0.07%     96.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3840-3843           21      0.12%     96.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3904-3907            1      0.01%     96.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3968-3971           13      0.07%     97.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4032-4035            2      0.01%     97.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4096-4099            8      0.04%     97.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4160-4163            3      0.02%     97.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4224-4227           14      0.08%     97.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4352-4355           22      0.12%     97.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4480-4483           13      0.07%     97.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4544-4547            1      0.01%     97.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4608-4611           77      0.43%     97.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4736-4739            3      0.02%     97.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4864-4867           19      0.11%     97.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4992-4995            5      0.03%     97.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5056-5059            2      0.01%     97.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5120-5123            8      0.04%     98.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5248-5251            4      0.02%     98.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5376-5379           21      0.12%     98.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5504-5507            6      0.03%     98.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5632-5635            9      0.05%     98.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5696-5699            2      0.01%     98.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5760-5763            3      0.02%     98.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5888-5891           21      0.12%     98.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6016-6019            3      0.02%     98.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6144-6147            6      0.03%     98.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6272-6275            5      0.03%     98.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6400-6403           19      0.11%     98.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6528-6531            6      0.03%     98.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6656-6659            6      0.03%     98.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6784-6787           25      0.14%     98.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6848-6851            1      0.01%     98.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6912-6915           15      0.08%     98.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6976-6979            1      0.01%     98.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7040-7043            1      0.01%     98.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7168-7171           21      0.12%     98.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7424-7427            1      0.01%     98.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7680-7683            4      0.02%     99.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8000-8003            1      0.01%     99.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8192-8195           52      0.29%     99.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8960-8963            1      0.01%     99.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9216-9219            1      0.01%     99.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9344-9347            1      0.01%     99.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9408-9411            1      0.01%     99.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9536-9539            1      0.01%     99.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9856-9859            1      0.01%     99.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10880-10883            2      0.01%     99.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11008-11011            1      0.01%     99.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11328-11331            1      0.01%     99.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11392-11395            1      0.01%     99.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11776-11779            1      0.01%     99.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12032-12035            1      0.01%     99.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12096-12099            1      0.01%     99.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12672-12675            1      0.01%     99.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12800-12803            2      0.01%     99.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13056-13059            1      0.01%     99.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13312-13315            2      0.01%     99.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13696-13699            2      0.01%     99.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14208-14211            1      0.01%     99.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14272-14275            1      0.01%     99.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14336-14339            2      0.01%     99.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14464-14467            1      0.01%     99.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14656-14659            1      0.01%     99.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14976-14979            1      0.01%     99.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15104-15107            1      0.01%     99.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15168-15171            1      0.01%     99.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15232-15235            1      0.01%     99.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15360-15363           16      0.09%     99.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15488-15491            1      0.01%     99.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15680-15683            1      0.01%     99.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16128-16131            1      0.01%     99.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16384-16387           75      0.42%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          17929                       # Bytes accessed per row activation
-system.physmem.totQLat                     2679388500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                4331514750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    490045000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                  1162081250                       # Total ticks spent accessing banks
-system.physmem.avgQLat                       27338.19                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    11856.88                       # Average bank access latency per DRAM burst
+system.physmem.wrQLenPdf::0                        80                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                        52                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                        44                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                        43                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                        42                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                        41                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                        40                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                        38                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                        36                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                        36                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                       35                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                       35                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                       35                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                       35                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                       35                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      523                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      562                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                      671                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     1179                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     1375                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     1510                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     1616                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     1649                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     1665                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     1674                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     1985                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     1867                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     1882                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     2279                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     2065                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     2130                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     2146                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     2008                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      918                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      691                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      533                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      419                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      450                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      442                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      400                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      462                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      508                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      598                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      627                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      683                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      690                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      750                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      719                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      789                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      770                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      741                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      761                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      717                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      621                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      531                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      382                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      281                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      203                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                      118                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       22                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       13                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       12                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       10                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        15110                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      511.250298                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     300.938727                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     421.415256                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127           3831     25.35%     25.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         2740     18.13%     43.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         1074      7.11%     50.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511          703      4.65%     55.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639          520      3.44%     58.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          360      2.38%     61.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          225      1.49%     62.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          226      1.50%     64.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         5431     35.94%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          15110                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          2571                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        37.985220                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      914.533013                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           2569     99.92%     99.92% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-4095            1      0.04%     99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::45056-47103            1      0.04%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            2571                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          2571                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.214702                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.506808                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        4.396297                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::1                  28      1.09%      1.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::2                   8      0.31%      1.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::3                   1      0.04%      1.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4                   1      0.04%      1.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::5                   1      0.04%      1.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::6                   1      0.04%      1.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::7                   2      0.08%      1.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8                   2      0.08%      1.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::10                  1      0.04%      1.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::15                  1      0.04%      1.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               1798     69.93%     71.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 69      2.68%     74.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                 74      2.88%     77.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                370     14.39%     91.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                 34      1.32%     93.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 19      0.74%     93.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 12      0.47%     94.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                  7      0.27%     94.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                 34      1.32%     95.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                 15      0.58%     96.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                  5      0.19%     96.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27                 15      0.58%     97.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28                 11      0.43%     97.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29                 14      0.54%     98.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30                  4      0.16%     98.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::31                  5      0.19%     98.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32                  6      0.23%     98.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::33                  3      0.12%     98.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::34                  1      0.04%     98.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::35                  1      0.04%     98.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36                  2      0.08%     98.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::37                  2      0.08%     99.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::39                  3      0.12%     99.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40                  4      0.16%     99.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44                  3      0.12%     99.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::47                  5      0.19%     99.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::49                  2      0.08%     99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::50                  1      0.04%     99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52                  2      0.08%     99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::53                  2      0.08%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56                  2      0.08%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            2571                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     3372876000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                5050468500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    488355000                       # Total ticks spent in databus transfers
+system.physmem.totBankLat                  1189237500                       # Total ticks spent accessing banks
+system.physmem.avgQLat                       34533.03                       # Average queueing delay per DRAM burst
+system.physmem.avgBankLat                    12175.95                       # Average bank access latency per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  44195.07                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           3.40                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  51708.99                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           3.39                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           1.54                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        3.40                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        3.39                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        1.54                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.04                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         0.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                         0.16                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      89637                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     34794                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   91.46                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  78.43                       # Row buffer hit rate for writes
-system.physmem.avgGap                     12934724.60                       # Average gap between requests
-system.physmem.pageHitRate                      87.40                       # Row buffer hit rate, read and write combined
+system.physmem.avgRdQLen                         1.08                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                         4.13                       # Average write queue length when enqueuing
+system.physmem.readRowHits                      85060                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     35225                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   87.09                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  79.55                       # Row buffer hit rate for writes
+system.physmem.avgGap                     12972053.86                       # Average gap between requests
+system.physmem.pageHitRate                      84.74                       # Row buffer hit rate, read and write combined
 system.physmem.prechargeAllPercent               0.21                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                     19524219                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq               44737                       # Transaction distribution
-system.membus.trans_dist::ReadResp              44533                       # Transaction distribution
-system.membus.trans_dist::WriteReq               3749                       # Transaction distribution
-system.membus.trans_dist::WriteResp              3749                       # Transaction distribution
-system.membus.trans_dist::Writeback             44365                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq               45                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp              45                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             56547                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            56547                       # Transaction distribution
-system.membus.trans_dist::BadAddressError          204                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        13310                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       189932                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio          408                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       203650                       # Packet count per connected master and slave (bytes)
+system.membus.throughput                     19527312                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq               44337                       # Transaction distribution
+system.membus.trans_dist::ReadResp              44306                       # Transaction distribution
+system.membus.trans_dist::WriteReq               3779                       # Transaction distribution
+system.membus.trans_dist::WriteResp              3779                       # Transaction distribution
+system.membus.trans_dist::Writeback             44282                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq               42                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp              42                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             56476                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            56476                       # Transaction distribution
+system.membus.trans_dist::BadAddressError           31                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        13428                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       189189                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio           62                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       202679                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        50712                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total        50712                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 254362                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave        15689                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port      6952704                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::total      6968393                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count::total                 253391                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave        15748                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port      6926464                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::total      6942212                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      2159808                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.iocache.mem_side::total      2159808                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total             9128201                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus               35967240                       # Total data (bytes)
+system.membus.tot_pkt_size::total             9102020                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               35972872                       # Total data (bytes)
 system.membus.snoop_data_through_bus             9984                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy            12468500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy            12574500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy           514332500                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy           513408250                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy              252500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy               40000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          764298954                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy          761373958                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy          152995500                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy          153163000                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.l2c.tags.replacements                   337398                       # number of replacements
-system.l2c.tags.tagsinuse                65420.701532                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    2472173                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   402561                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     6.141114                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                   337430                       # number of replacements
+system.l2c.tags.tagsinuse                65422.148259                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    2473441                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   402593                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     6.143775                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                614754000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   54886.932182                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     2458.825580                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     2703.778525                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      528.462620                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data      622.296328                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst     2148.830278                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data     2071.576019                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.837508                       # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::writebacks   54880.563920                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     2458.853214                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     2711.613848                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst      517.416897                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data      618.305247                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst     2161.633442                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data     2073.761691                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.837411                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.inst       0.037519                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.041256                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.008064                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.009495                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst       0.032789                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data       0.031610                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.998241                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.041376                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.007895                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.009435                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.inst       0.032984                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.data       0.031643                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.998263                       # Average percentage of cache occupancy
 system.l2c.tags.occ_task_id_blocks::1024        65163                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1024::0          168                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          988                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         5636                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         2991                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        55380                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1         1047                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         5588                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         2973                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        55387                       # Occupied blocks per task id
 system.l2c.tags.occ_task_id_percent::1024     0.994308                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 26143118                       # Number of tag accesses
-system.l2c.tags.data_accesses                26143118                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.inst             520243                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             493553                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             124286                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data              83912                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.inst             292769                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.data             239004                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1753767                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          835523                       # number of Writeback hits
-system.l2c.Writeback_hits::total               835523                       # number of Writeback hits
+system.l2c.tags.tag_accesses                 26153114                       # Number of tag accesses
+system.l2c.tags.data_accesses                26153114                       # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.inst             521024                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data             493028                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst             125251                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data              84722                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.inst             291154                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.data             239311                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1754490                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          836107                       # number of Writeback hits
+system.l2c.Writeback_hits::total               836107                       # number of Writeback hits
 system.l2c.UpgradeReq_hits::cpu0.data               3                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::cpu1.data               1                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::cpu2.data               3                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::total                   7                       # number of UpgradeReq hits
 system.l2c.SCUpgradeReq_hits::cpu2.data             1                       # number of SCUpgradeReq hits
 system.l2c.SCUpgradeReq_hits::total                 1                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            92938                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            26217                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu2.data            67761                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               186916                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.inst              520243                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              586491                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              124286                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              110129                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst              292769                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data              306765                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1940683                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst             520243                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             586491                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             124286                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             110129                       # number of overall hits
-system.l2c.overall_hits::cpu2.inst             292769                       # number of overall hits
-system.l2c.overall_hits::cpu2.data             306765                       # number of overall hits
-system.l2c.overall_hits::total                1940683                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.inst             7643                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data           238324                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst             2257                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data            16911                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.inst             4452                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.data            18142                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total               287729                       # number of ReadReq misses
+system.l2c.ReadExReq_hits::cpu0.data            93137                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            26426                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu2.data            67420                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               186983                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.inst              521024                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              586165                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              125251                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              111148                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.inst              291154                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.data              306731                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 1941473                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.inst             521024                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             586165                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             125251                       # number of overall hits
+system.l2c.overall_hits::cpu1.data             111148                       # number of overall hits
+system.l2c.overall_hits::cpu2.inst             291154                       # number of overall hits
+system.l2c.overall_hits::cpu2.data             306731                       # number of overall hits
+system.l2c.overall_hits::total                1941473                       # number of overall hits
+system.l2c.ReadReq_misses::cpu0.inst             7641                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data           238596                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst             2245                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data            16796                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.inst             4459                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.data            17833                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total               287570                       # number of ReadReq misses
 system.l2c.UpgradeReq_misses::cpu0.data             8                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2.data            12                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total                20                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          76060                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          18078                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2.data          21606                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             115744                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.inst              7643                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            314384                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              2257                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data             34989                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.inst              4452                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.data             39748                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                403473                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst             7643                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           314384                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             2257                       # number of overall misses
-system.l2c.overall_misses::cpu1.data            34989                       # number of overall misses
-system.l2c.overall_misses::cpu2.inst             4452                       # number of overall misses
-system.l2c.overall_misses::cpu2.data            39748                       # number of overall misses
-system.l2c.overall_misses::total               403473                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu1.inst    176426247                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data   1131345000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.inst    358514250                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.data   1201423499                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total     2867708996                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu2.data       294997                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total       294997                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data   1254698241                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu2.data   1776085226                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   3030783467                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu1.inst    176426247                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data   2386043241                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.inst    358514250                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.data   2977508725                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total      5898492463                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu1.inst    176426247                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data   2386043241                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.inst    358514250                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.data   2977508725                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total     5898492463                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.inst         527886                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data         731877                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst         126543                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data         100823                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.inst         297221                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.data         257146                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2041496                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       835523                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           835523                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_misses::cpu2.data             9                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total                17                       # number of UpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data          76153                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data          18140                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu2.data          21473                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             115766                       # number of ReadExReq misses
+system.l2c.demand_misses::cpu0.inst              7641                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data            314749                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst              2245                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data             34936                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.inst              4459                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.data             39306                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                403336                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.inst             7641                       # number of overall misses
+system.l2c.overall_misses::cpu0.data           314749                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst             2245                       # number of overall misses
+system.l2c.overall_misses::cpu1.data            34936                       # number of overall misses
+system.l2c.overall_misses::cpu2.inst             4459                       # number of overall misses
+system.l2c.overall_misses::cpu2.data            39306                       # number of overall misses
+system.l2c.overall_misses::total               403336                       # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu1.inst    162937747                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data   1122716750                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.inst    340229750                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.data   1192796250                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total     2818680497                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu2.data       286997                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total       286997                       # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data   1236065740                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu2.data   1785443227                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   3021508967                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu1.inst    162937747                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data   2358782490                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.inst    340229750                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.data   2978239477                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total      5840189464                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu1.inst    162937747                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data   2358782490                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.inst    340229750                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.data   2978239477                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total     5840189464                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.inst         528665                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data         731624                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst         127496                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data         101518                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.inst         295613                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.data         257144                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            2042060                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       836107                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           836107                       # number of Writeback accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::cpu0.data           11                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::cpu1.data            1                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2.data           15                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total              27                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu2.data           12                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total              24                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.SCUpgradeReq_accesses::cpu2.data            1                       # number of SCUpgradeReq accesses(hits+misses)
 system.l2c.SCUpgradeReq_accesses::total             1                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       168998                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data        44295                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu2.data        89367                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           302660                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst          527886                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data          900875                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          126543                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          145118                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.inst          297221                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.data          346513                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2344156                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         527886                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data         900875                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         126543                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         145118                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.inst         297221                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.data         346513                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2344156                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.014479                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.325634                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.017836                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.167730                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.inst      0.014979                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.data      0.070551                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.140940                       # miss rate for ReadReq accesses
+system.l2c.ReadExReq_accesses::cpu0.data       169290                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data        44566                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu2.data        88893                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           302749                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.inst          528665                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data          900914                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          127496                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data          146084                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.inst          295613                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.data          346037                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             2344809                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         528665                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data         900914                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         127496                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data         146084                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.inst         295613                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.data         346037                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            2344809                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.014453                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.326118                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst      0.017608                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data      0.165448                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.inst      0.015084                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.data      0.069350                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.140823                       # miss rate for ReadReq accesses
 system.l2c.UpgradeReq_miss_rate::cpu0.data     0.727273                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2.data     0.800000                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.740741                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.450064                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.408127                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2.data     0.241767                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.382423                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.014479                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.348976                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.017836                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.241107                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst       0.014979                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.data       0.114709                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.172119                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.014479                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.348976                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.017836                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.241107                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst      0.014979                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.data      0.114709                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.172119                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 78168.474524                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 66899.946780                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.inst 80528.807278                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.data 66223.321519                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total  9966.701292                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 24583.083333                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 14749.850000                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 69404.704115                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2.data 82203.333611                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 26185.231779                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 78168.474524                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 68194.096459                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.inst 80528.807278                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.data 74909.648913                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 14619.299093                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 78168.474524                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 68194.096459                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.inst 80528.807278                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.data 74909.648913                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 14619.299093                       # average overall miss latency
+system.l2c.UpgradeReq_miss_rate::cpu2.data     0.750000                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.708333                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.449838                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.407037                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu2.data     0.241560                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.382383                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.014453                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.349366                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.017608                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.239150                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.inst       0.015084                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.data       0.113589                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.172012                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.014453                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.349366                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.017608                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.239150                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.inst      0.015084                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.data      0.113589                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.172012                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72578.061024                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 66844.293284                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.inst 76301.805338                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.data 66887.021253                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total  9801.719571                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 31888.555556                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 16882.176471                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 68140.338479                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu2.data 83148.289806                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 26100.141380                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 72578.061024                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 67517.245535                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.inst 76301.805338                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.data 75770.606956                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 14479.712855                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 72578.061024                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 67517.245535                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.inst 76301.805338                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.data 75770.606956                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 14479.712855                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -578,97 +546,97 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               75046                       # number of writebacks
-system.l2c.writebacks::total                    75046                       # number of writebacks
-system.l2c.ReadReq_mshr_misses::cpu1.inst         2257                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data        16911                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.inst         4452                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.data        18142                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total           41762                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu2.data           12                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total           12                       # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data        18078                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu2.data        21606                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total         39684                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst         2257                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data        34989                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.inst         4452                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.data        39748                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total            81446                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst         2257                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data        34989                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.inst         4452                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.data        39748                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total           81446                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    147657253                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data    919546000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.inst    302425250                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.data    999157501                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total   2368786004                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data       279009                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total       279009                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   1027471259                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   1510849774                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   2538321033                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst    147657253                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data   1947017259                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.inst    302425250                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.data   2510007275                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total   4907107037                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst    147657253                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data   1947017259                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.inst    302425250                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.data   2510007275                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total   4907107037                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    277801500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data    291494000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total    569295500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    343786500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data    402097500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total    745884000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data    621588000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu2.data    693591500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   1315179500                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.017836                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.167730                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.014979                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.070551                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.020457                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.800000                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.444444                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.408127                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.241767                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.131117                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.017836                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.241107                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.inst     0.014979                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.data     0.114709                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.034744                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.017836                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.241107                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.inst     0.014979                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.data     0.114709                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.034744                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 65421.910944                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 54375.613506                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 67930.199910                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 55074.275218                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 56721.086251                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 23250.750000                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 23250.750000                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56835.449663                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69927.324539                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 63963.336181                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65421.910944                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 55646.553460                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 67930.199910                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 63148.014366                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 60249.822422                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65421.910944                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 55646.553460                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 67930.199910                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 63148.014366                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 60249.822422                       # average overall mshr miss latency
+system.l2c.writebacks::writebacks               75099                       # number of writebacks
+system.l2c.writebacks::total                    75099                       # number of writebacks
+system.l2c.ReadReq_mshr_misses::cpu1.inst         2245                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.data        16796                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.inst         4459                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.data        17833                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total           41333                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu2.data            9                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total            9                       # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data        18140                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu2.data        21473                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total         39613                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst         2245                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data        34936                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.inst         4459                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.data        39306                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total            80946                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst         2245                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data        34936                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.inst         4459                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.data        39306                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total           80946                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    134357753                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data    912417250                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.inst    284084750                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.data    973268750                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total   2304128503                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data       241006                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total       241006                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   1008170260                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   1522069773                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   2530240033                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst    134357753                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data   1920587510                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.inst    284084750                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.data   2495338523                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   4834368536                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst    134357753                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data   1920587510                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.inst    284084750                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.data   2495338523                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   4834368536                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    279416000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data    295991000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total    575407000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    345820000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data    406371500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total    752191500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data    625236000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2.data    702362500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   1327598500                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.017608                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.165448                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.015084                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.069350                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.020241                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.750000                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.375000                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.407037                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.241560                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.130844                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.017608                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.239150                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst     0.015084                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.data     0.113589                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.034521                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.017608                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.239150                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst     0.015084                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data     0.113589                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.034521                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59847.551448                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 54323.484758                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 63710.417134                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 54576.837885                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 55745.493988                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 26778.444444                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 26778.444444                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55577.191841                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 70882.958739                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 63873.981597                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59847.551448                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 54974.453572                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63710.417134                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 63484.926551                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 59723.377758                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59847.551448                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 54974.453572                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63710.417134                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 63484.926551                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 59723.377758                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -680,14 +648,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data          inf
 system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.iocache.tags.replacements                41685                       # number of replacements
-system.iocache.tags.tagsinuse                1.254904                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.254944                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1694870354000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     1.254904                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.078431                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.078431                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         1694864715000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide     1.254944                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide     0.078434                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.078434                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -703,12 +671,12 @@ system.iocache.overall_misses::tsunami.ide        41725                       #
 system.iocache.overall_misses::total            41725                       # number of overall misses
 system.iocache.ReadReq_miss_latency::tsunami.ide      9303463                       # number of ReadReq miss cycles
 system.iocache.ReadReq_miss_latency::total      9303463                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::tsunami.ide   5314732731                       # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total   5314732731                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide   5324036194                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   5324036194                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide   5324036194                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   5324036194                       # number of overall miss cycles
+system.iocache.WriteReq_miss_latency::tsunami.ide   5375933278                       # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total   5375933278                       # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide   5385236741                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   5385236741                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide   5385236741                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   5385236741                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
@@ -727,17 +695,17 @@ system.iocache.overall_miss_rate::tsunami.ide            1
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
 system.iocache.ReadReq_avg_miss_latency::tsunami.ide 53777.242775                       # average ReadReq miss latency
 system.iocache.ReadReq_avg_miss_latency::total 53777.242775                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::tsunami.ide 127905.581705                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 127905.581705                       # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 127598.231132                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 127598.231132                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 127598.231132                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 127598.231132                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs        168308                       # number of cycles access was blocked
+system.iocache.WriteReq_avg_miss_latency::tsunami.ide 129378.448161                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 129378.448161                       # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 129064.990797                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 129064.990797                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 129064.990797                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 129064.990797                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs        158120                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                12241                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                11558                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs    13.749530                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs    13.680568                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -753,12 +721,12 @@ system.iocache.overall_mshr_misses::tsunami.ide        16965
 system.iocache.overall_mshr_misses::total        16965                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::tsunami.ide      5714463                       # number of ReadReq MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_latency::total      5714463                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::tsunami.ide   4435520731                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total   4435520731                       # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide   4441235194                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   4441235194                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide   4441235194                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   4441235194                       # number of overall MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::tsunami.ide   4496386278                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total   4496386278                       # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide   4502100741                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   4502100741                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide   4502100741                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   4502100741                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide     0.398844                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total     0.398844                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteReq_mshr_miss_rate::tsunami.ide     0.406623                       # mshr miss rate for WriteReq accesses
@@ -769,12 +737,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide     0.406591
 system.iocache.overall_mshr_miss_rate::total     0.406591                       # mshr miss rate for overall accesses
 system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82818.304348                       # average ReadReq mshr miss latency
 system.iocache.ReadReq_avg_mshr_miss_latency::total 82818.304348                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 262518.982659                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 262518.982659                       # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 261788.104568                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 261788.104568                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 261788.104568                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 261788.104568                       # average overall mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 266121.346946                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 266121.346946                       # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 265375.817330                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 265375.817330                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 265375.817330                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 265375.817330                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -792,22 +760,22 @@ system.cpu0.dtb.fetch_hits                          0                       # IT
 system.cpu0.dtb.fetch_misses                        0                       # ITB misses
 system.cpu0.dtb.fetch_acv                           0                       # ITB acv
 system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu0.dtb.read_hits                     4920578                       # DTB read hits
+system.cpu0.dtb.read_hits                     4928404                       # DTB read hits
 system.cpu0.dtb.read_misses                      6099                       # DTB read misses
 system.cpu0.dtb.read_acv                          126                       # DTB read access violations
 system.cpu0.dtb.read_accesses                  428233                       # DTB read accesses
-system.cpu0.dtb.write_hits                    3510258                       # DTB write hits
+system.cpu0.dtb.write_hits                    3518338                       # DTB write hits
 system.cpu0.dtb.write_misses                      670                       # DTB write misses
 system.cpu0.dtb.write_acv                          84                       # DTB write access violations
 system.cpu0.dtb.write_accesses                 163777                       # DTB write accesses
-system.cpu0.dtb.data_hits                     8430836                       # DTB hits
+system.cpu0.dtb.data_hits                     8446742                       # DTB hits
 system.cpu0.dtb.data_misses                      6769                       # DTB misses
 system.cpu0.dtb.data_acv                          210                       # DTB access violations
 system.cpu0.dtb.data_accesses                  592010                       # DTB accesses
-system.cpu0.itb.fetch_hits                    2762930                       # ITB hits
+system.cpu0.itb.fetch_hits                    2763962                       # ITB hits
 system.cpu0.itb.fetch_misses                     3034                       # ITB misses
 system.cpu0.itb.fetch_acv                         104                       # ITB acv
-system.cpu0.itb.fetch_accesses                2765964                       # ITB accesses
+system.cpu0.itb.fetch_accesses                2766996                       # ITB accesses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.read_acv                            0                       # DTB read access violations
@@ -820,52 +788,52 @@ system.cpu0.itb.data_hits                           0                       # DT
 system.cpu0.itb.data_misses                         0                       # DTB misses
 system.cpu0.itb.data_acv                            0                       # DTB access violations
 system.cpu0.itb.data_accesses                       0                       # DTB accesses
-system.cpu0.numCycles                       928345000                       # number of cpu cycles simulated
+system.cpu0.numCycles                       928692350                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   33879417                       # Number of instructions committed
-system.cpu0.committedOps                     33879417                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             31738664                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                170028                       # Number of float alu accesses
-system.cpu0.num_func_calls                     812853                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      4700164                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    31738664                       # number of integer instructions
-system.cpu0.num_fp_insts                       170028                       # number of float instructions
-system.cpu0.num_int_register_reads           44595421                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          23158595                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads               87794                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes              89338                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                      8461010                       # number of memory refs
-system.cpu0.num_load_insts                    4941975                       # Number of load instructions
-system.cpu0.num_store_insts                   3519035                       # Number of store instructions
-system.cpu0.num_idle_cycles              904626845.998199                       # Number of idle cycles
-system.cpu0.num_busy_cycles              23718154.001801                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.025549                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.974451                       # Percentage of idle cycles
-system.cpu0.Branches                          5776800                       # Number of branches fetched
+system.cpu0.committedInsts                   34273964                       # Number of instructions committed
+system.cpu0.committedOps                     34273964                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses             32130742                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                169948                       # Number of float alu accesses
+system.cpu0.num_func_calls                     813899                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      4819398                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    32130742                       # number of integer instructions
+system.cpu0.num_fp_insts                       169948                       # number of float instructions
+system.cpu0.num_int_register_reads           45237353                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          23423813                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads               87792                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes              89256                       # number of times the floating registers were written
+system.cpu0.num_mem_refs                      8476912                       # number of memory refs
+system.cpu0.num_load_insts                    4949798                       # Number of load instructions
+system.cpu0.num_store_insts                   3527114                       # Number of store instructions
+system.cpu0.num_idle_cycles              904863863.789935                       # Number of idle cycles
+system.cpu0.num_busy_cycles              23828486.210065                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.025658                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.974342                       # Percentage of idle cycles
+system.cpu0.Branches                          5897308                       # Number of branches fetched
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    6418                       # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei                    211383                       # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0                   74805     40.97%     40.97% # number of times we switched to this ipl
+system.cpu0.kern.inst.quiesce                    6415                       # number of quiesce instructions executed
+system.cpu0.kern.inst.hwrei                    211374                       # number of hwrei instructions executed
+system.cpu0.kern.ipl_count::0                   74800     40.97%     40.97% # number of times we switched to this ipl
 system.cpu0.kern.ipl_count::21                    203      0.11%     41.08% # number of times we switched to this ipl
 system.cpu0.kern.ipl_count::22                   1879      1.03%     42.11% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31                 105697     57.89%    100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total              182584                       # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0                    73438     49.30%     49.30% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_count::31                 105691     57.89%    100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total              182573                       # number of times we switched to this ipl
+system.cpu0.kern.ipl_good::0                    73433     49.30%     49.30% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::21                     203      0.14%     49.44% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::22                    1879      1.26%     50.70% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31                   73438     49.30%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total               148958                       # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0            1819507118500     98.74%     98.74% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21               38781000      0.00%     98.74% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22              365071000      0.02%     98.76% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31            22785478000      1.24%    100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total        1842696448500                       # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0                 0.981726                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_good::31                   73433     49.30%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::total               148948                       # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks::0            1819462416000     98.74%     98.74% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21               38889500      0.00%     98.74% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22              365010500      0.02%     98.76% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31            22826642500      1.24%    100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total        1842692958500                       # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used::0                 0.981725                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31                0.694797                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total             0.815833                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::31                0.694790                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::total             0.815827                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.syscall::2                         8      2.45%      2.45% # number of syscalls executed
 system.cpu0.kern.syscall::3                        30      9.20%     11.66% # number of syscalls executed
 system.cpu0.kern.syscall::4                         4      1.23%     12.88% # number of syscalls executed
@@ -901,10 +869,10 @@ system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # nu
 system.cpu0.kern.callpal::wrmces                    1      0.00%      0.00% # number of callpals executed
 system.cpu0.kern.callpal::wrfen                     1      0.00%      0.00% # number of callpals executed
 system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.00% # number of callpals executed
-system.cpu0.kern.callpal::swpctx                 4174      2.17%      2.17% # number of callpals executed
+system.cpu0.kern.callpal::swpctx                 4176      2.17%      2.17% # number of callpals executed
 system.cpu0.kern.callpal::tbi                      54      0.03%      2.20% # number of callpals executed
 system.cpu0.kern.callpal::wrent                     7      0.00%      2.21% # number of callpals executed
-system.cpu0.kern.callpal::swpipl               175325     91.20%     93.41% # number of callpals executed
+system.cpu0.kern.callpal::swpipl               175314     91.20%     93.41% # number of callpals executed
 system.cpu0.kern.callpal::rdps                   6783      3.53%     96.94% # number of callpals executed
 system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.94% # number of callpals executed
 system.cpu0.kern.callpal::wrusp                     7      0.00%     96.94% # number of callpals executed
@@ -913,21 +881,21 @@ system.cpu0.kern.callpal::whami                     2      0.00%     96.95% # nu
 system.cpu0.kern.callpal::rti                    5176      2.69%     99.64% # number of callpals executed
 system.cpu0.kern.callpal::callsys                 515      0.27%     99.91% # number of callpals executed
 system.cpu0.kern.callpal::imb                     181      0.09%    100.00% # number of callpals executed
-system.cpu0.kern.callpal::total                192238                       # number of callpals executed
+system.cpu0.kern.callpal::total                192229                       # number of callpals executed
 system.cpu0.kern.mode_switch::kernel             5922                       # number of protection mode switches
-system.cpu0.kern.mode_switch::user               1738                       # number of protection mode switches
-system.cpu0.kern.mode_switch::idle               2094                       # number of protection mode switches
+system.cpu0.kern.mode_switch::user               1737                       # number of protection mode switches
+system.cpu0.kern.mode_switch::idle               2096                       # number of protection mode switches
 system.cpu0.kern.mode_good::kernel               1907                      
-system.cpu0.kern.mode_good::user                 1738                      
-system.cpu0.kern.mode_good::idle                  169                      
+system.cpu0.kern.mode_good::user                 1737                      
+system.cpu0.kern.mode_good::idle                  170                      
 system.cpu0.kern.mode_switch_good::kernel     0.322020                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::idle      0.080707                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total     0.391019                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel       29794763000      1.62%      1.62% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user          2592746500      0.14%      1.76% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::idle        1810308934500     98.24%    100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context                    4175                       # number of times the context was actually changed
+system.cpu0.kern.mode_switch_good::idle      0.081107                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::total     0.390979                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel       29759204500      1.61%      1.61% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user          2578304000      0.14%      1.75% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::idle        1810355445500     98.25%    100.00% # number of ticks spent at the given mode
+system.cpu0.kern.swap_context                    4177                       # number of times the context was actually changed
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
 system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
@@ -959,59 +927,59 @@ system.tsunami.ethernet.totalRxOrn                  0                       # to
 system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
 system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.toL2Bus.throughput                   110459996                       # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq             784722                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp            784503                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq              3749                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp             3749                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           371354                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq              16                       # Transaction distribution
+system.toL2Bus.throughput                   110509038                       # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq             784786                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp            784740                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq              3779                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp             3779                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           372271                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq              13                       # Transaction distribution
 system.toL2Bus.trans_dist::SCUpgradeReq             1                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp             17                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           150558                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          133662                       # Transaction distribution
-system.toL2Bus.trans_dist::BadAddressError          204                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side       847542                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      1368014                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               2215556                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     27120896                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     55237129                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size::total           82358025                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus             203533320                       # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus           11008                       # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy         2134008000                       # Layer occupancy (ticks)
+system.toL2Bus.trans_dist::UpgradeResp             14                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           150355                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          133459                       # Transaction distribution
+system.toL2Bus.trans_dist::BadAddressError           31                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side       846229                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      1370023                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               2216252                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     27078976                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     55338308                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size::total           82417284                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus             203623496                       # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus           10816                       # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy         2138093500                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
 system.toL2Bus.snoopLayer0.occupancy           243000                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        1908780020                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        1905810483                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        2230620167                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        2232783145                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
-system.iobus.throughput                       1469142                       # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq                 2975                       # Transaction distribution
-system.iobus.trans_dist::ReadResp                2975                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               20645                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              20645                       # Transaction distribution
+system.iobus.throughput                       1469145                       # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq                 3004                       # Transaction distribution
+system.iobus.trans_dist::ReadResp                3004                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               20675                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              20675                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         2330                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          136                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio           66                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio         8370                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio         8488                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         2374                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf           34                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total        13310                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total        13428                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        33930                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::total        33930                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                   47240                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                   47358                       # Packet count per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio         9320                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio          544                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio           61                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio         4185                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio         4244                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio         1548                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf           31                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total        15689                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::total        15748                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      1082792                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.tsunami.ide.dma::total      1082792                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total              1098481                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::total              1098540                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.data_through_bus                 2707184                       # Total data (bytes)
 system.iobus.reqLayer0.occupancy              2199000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
@@ -1019,398 +987,398 @@ system.iobus.reqLayer1.occupancy               102000                       # La
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer22.occupancy               57000                       # Layer occupancy (ticks)
 system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer23.occupancy             6237000                       # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy             6326000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer25.occupancy             1789000                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer26.occupancy               20000                       # Layer occupancy (ticks)
 system.iobus.reqLayer26.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer29.occupancy           153613694                       # Layer occupancy (ticks)
+system.iobus.reqLayer29.occupancy           154493741                       # Layer occupancy (ticks)
 system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy             9561000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy             9649000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            17409500                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            17628000                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.cpu0.icache.tags.replacements           951005                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.190319                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           43429541                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           951516                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            45.642471                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      10399272250                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   251.342896                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst    99.592582                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu2.inst   160.254842                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.490904                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.194517                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu2.inst     0.312998                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.998419                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements           951123                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.189701                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           44044625                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           951634                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            46.283156                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      10406456250                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   252.370031                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst    94.623296                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu2.inst   164.196374                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.492910                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.184811                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu2.inst     0.320696                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.998417                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::2          447                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         45349405                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        45349405                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     33358489                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst      7831408                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu2.inst      2239644                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       43429541                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     33358489                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst      7831408                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu2.inst      2239644                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        43429541                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     33358489                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst      7831408                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu2.inst      2239644                       # number of overall hits
-system.cpu0.icache.overall_hits::total       43429541                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       527907                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst       126543                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu2.inst       313729                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       968179                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       527907                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst       126543                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu2.inst       313729                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        968179                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       527907                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst       126543                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu2.inst       313729                       # number of overall misses
-system.cpu0.icache.overall_misses::total       968179                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   1806945253                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   4430503289                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total   6237448542                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst   1806945253                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu2.inst   4430503289                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total   6237448542                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst   1806945253                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu2.inst   4430503289                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total   6237448542                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     33886396                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst      7957951                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu2.inst      2553373                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     44397720                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     33886396                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst      7957951                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu2.inst      2553373                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     44397720                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     33886396                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst      7957951                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu2.inst      2553373                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     44397720                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.015579                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.015901                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.122868                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.021807                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.015579                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.015901                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu2.inst     0.122868                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.021807                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.015579                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.015901                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu2.inst     0.122868                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.021807                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14279.298365                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14122.071243                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  6442.453866                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14279.298365                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14122.071243                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  6442.453866                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14279.298365                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14122.071243                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  6442.453866                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs         3919                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses         45964526                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        45964526                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     33752258                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst      8060384                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu2.inst      2231983                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       44044625                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     33752258                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst      8060384                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu2.inst      2231983                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        44044625                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     33752258                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst      8060384                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu2.inst      2231983                       # number of overall hits
+system.cpu0.icache.overall_hits::total       44044625                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       528685                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst       127496                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu2.inst       311915                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       968096                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       528685                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst       127496                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu2.inst       311915                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        968096                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       528685                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst       127496                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu2.inst       311915                       # number of overall misses
+system.cpu0.icache.overall_misses::total       968096                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   1806037753                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   4386195216                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total   6192232969                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst   1806037753                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu2.inst   4386195216                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total   6192232969                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst   1806037753                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu2.inst   4386195216                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total   6192232969                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     34280943                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst      8187880                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu2.inst      2543898                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     45012721                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     34280943                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst      8187880                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu2.inst      2543898                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     45012721                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     34280943                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst      8187880                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu2.inst      2543898                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     45012721                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.015422                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.015571                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.122613                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.021507                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.015422                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.015571                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu2.inst     0.122613                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.021507                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.015422                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.015571                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu2.inst     0.122613                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.021507                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14165.446390                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14062.149034                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total  6396.300541                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14165.446390                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14062.149034                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total  6396.300541                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14165.446390                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14062.149034                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total  6396.300541                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs         3438                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              159                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              178                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    24.647799                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    19.314607                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        16494                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        16494                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu2.inst        16494                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        16494                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu2.inst        16494                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        16494                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       126543                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       297235                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       423778                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst       126543                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu2.inst       297235                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       423778                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst       126543                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu2.inst       297235                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       423778                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   1552948747                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   3649949474                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total   5202898221                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   1552948747                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   3649949474                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total   5202898221                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   1552948747                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   3649949474                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total   5202898221                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.015901                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.116409                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.009545                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.015901                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.116409                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.009545                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.015901                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.116409                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.009545                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12272.103135                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12279.675926                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12277.414639                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12272.103135                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12279.675926                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12277.414639                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12272.103135                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12279.675926                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12277.414639                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        16291                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        16291                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu2.inst        16291                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        16291                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu2.inst        16291                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        16291                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       127496                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       295624                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       423120                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst       127496                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu2.inst       295624                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       423120                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst       127496                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu2.inst       295624                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       423120                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   1550167247                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   3614174758                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total   5164342005                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   1550167247                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   3614174758                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total   5164342005                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   1550167247                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   3614174758                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total   5164342005                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.015571                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.116209                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.009400                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.015571                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.116209                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.009400                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.015571                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.116209                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.009400                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12158.555931                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12225.579648                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12205.383827                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12158.555931                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12225.579648                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12205.383827                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12158.555931                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12225.579648                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12205.383827                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements          1391788                       # number of replacements
+system.cpu0.dcache.tags.replacements          1392490                       # number of replacements
 system.cpu0.dcache.tags.tagsinuse          511.997811                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           13285278                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          1392300                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs             9.541965                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.total_refs           13295207                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          1393002                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs             9.544284                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle         10840000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   249.411553                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data   131.959093                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu2.data   130.627166                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.487132                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.257733                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu2.data     0.255131                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   249.168016                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data   132.479618                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu2.data   130.350177                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.486656                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.258749                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu2.data     0.254590                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999996                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::0          177                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::1          266                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::2           69                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         63261634                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        63261634                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data      4082373                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data      1085171                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu2.data      2396693                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        7564237                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      3213874                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data       832734                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu2.data      1291048                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       5337656                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       117262                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data        19372                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu2.data        47406                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       184040                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       126440                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data        21396                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu2.data        51446                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       199282                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data      7296247                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data      1917905                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu2.data      3687741                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        12901893                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data      7296247                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data      1917905                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu2.data      3687741                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       12901893                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       722135                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data        98671                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu2.data       532767                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      1353573                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       169009                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data        44296                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu2.data       596502                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       809807                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         9742                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         2152                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu2.data         6843                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        18737                       # number of LoadLockedReq misses
+system.cpu0.dcache.tags.tag_accesses         63289936                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        63289936                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data      4090319                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data      1090270                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu2.data      2387407                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        7567996                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      3221527                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data       836656                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu2.data      1285562                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       5343745                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       117421                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data        19406                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu2.data        47293                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       184120                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       126604                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data        21447                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu2.data        51238                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       199289                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data      7311846                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data      1926926                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu2.data      3672969                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        12911741                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data      7311846                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data      1926926                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu2.data      3672969                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       12911741                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       721875                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data        99348                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu2.data       531757                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      1352980                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       169301                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data        44567                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu2.data       593518                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       807386                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         9749                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         2170                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu2.data         6797                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        18716                       # number of LoadLockedReq misses
 system.cpu0.dcache.StoreCondReq_misses::cpu2.data            1                       # number of StoreCondReq misses
 system.cpu0.dcache.StoreCondReq_misses::total            1                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       891144                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data       142967                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu2.data      1129269                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       2163380                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       891144                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data       142967                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu2.data      1129269                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      2163380                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   2255676500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu2.data   9348290769                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  11603967269                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   1658917259                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu2.data  18089996474                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  19748913733                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     28489000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data    102729249                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    131218249                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.demand_misses::cpu0.data       891176                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data       143915                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu2.data      1125275                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       2160366                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data       891176                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data       143915                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu2.data      1125275                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      2160366                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   2256659500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu2.data   9313664253                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  11570323753                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   1642839260                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu2.data  18220741943                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  19863581203                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     28601250                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data    101979747                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    130580997                       # number of LoadLockedReq miss cycles
 system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data        13000                       # number of StoreCondReq miss cycles
 system.cpu0.dcache.StoreCondReq_miss_latency::total        13000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data   3914593759                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu2.data  27438287243                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  31352881002                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data   3914593759                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu2.data  27438287243                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  31352881002                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      4804508                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data      1183842                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu2.data      2929460                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      8917810                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      3382883                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data       877030                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu2.data      1887550                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      6147463                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       127004                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data        21524                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data        54249                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       202777                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       126440                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data        21396                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu2.data        51447                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       199283                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data      8187391                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data      2060872                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu2.data      4817010                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     15065273                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data      8187391                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data      2060872                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu2.data      4817010                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     15065273                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.150304                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.083348                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.181865                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.151783                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.049960                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.050507                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.316019                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.131730                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.076706                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.099981                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.126141                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.092402                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data     0.000019                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_latency::cpu1.data   3899498760                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu2.data  27534406196                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  31433904956                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data   3899498760                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu2.data  27534406196                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  31433904956                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      4812194                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data      1189618                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu2.data      2919164                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      8920976                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      3390828                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data       881223                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu2.data      1879080                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      6151131                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       127170                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data        21576                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data        54090                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       202836                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       126604                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data        21447                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu2.data        51239                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       199290                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data      8203022                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data      2070841                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu2.data      4798244                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     15072107                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data      8203022                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data      2070841                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu2.data      4798244                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     15072107                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.150010                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.083513                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.182161                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.151663                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.049929                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.050574                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.315856                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.131258                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.076661                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.100575                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.125661                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.092272                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data     0.000020                       # miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000005                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.108843                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.069372                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu2.data     0.234434                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.143600                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.108843                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.069372                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu2.data     0.234434                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.143600                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 22860.582137                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17546.677570                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total  8572.841856                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37450.723745                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30326.799364                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 24387.185753                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13238.382900                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 15012.311705                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  7003.162139                       # average LoadLockedReq miss latency
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.108640                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.069496                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu2.data     0.234518                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.143335                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.108640                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.069496                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu2.data     0.234518                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.143335                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 22714.694810                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17514.887915                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total  8551.733029                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 36862.235735                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30699.560827                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 24602.335442                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13180.299539                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 15003.640871                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  6976.971415                       # average LoadLockedReq miss latency
 system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data        13000                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        13000                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27381.100247                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 24297.388171                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 14492.544538                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27381.100247                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 24297.388171                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 14492.544538                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs       584754                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets          852                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs            17600                       # number of cycles access was blocked
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27095.846576                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 24469.046407                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 14550.268314                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27095.846576                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 24469.046407                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 14550.268314                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs       590264                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets         1528                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs            18149                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets              7                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    33.224659                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets   121.714286                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    32.523224                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets   218.285714                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       835523                       # number of writebacks
-system.cpu0.dcache.writebacks::total           835523                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       280793                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       280793                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data       507370                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total       507370                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data         1423                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total         1423                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu2.data       788163                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total       788163                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu2.data       788163                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total       788163                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data        98671                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       251974                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       350645                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        44296                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        89132                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       133428                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         2152                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data         5420                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         7572                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.writebacks::writebacks       836107                       # number of writebacks
+system.cpu0.dcache.writebacks::total           836107                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       279755                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       279755                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data       504860                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total       504860                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data         1410                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total         1410                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu2.data       784615                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total       784615                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu2.data       784615                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total       784615                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data        99348                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       252002                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       351350                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        44567                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        88658                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       133225                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         2170                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data         5387                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         7557                       # number of LoadLockedReq MSHR misses
 system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data            1                       # number of StoreCondReq MSHR misses
 system.cpu0.dcache.StoreCondReq_mshr_misses::total            1                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data       142967                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu2.data       341106                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       484073                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data       142967                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu2.data       341106                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       484073                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2050323500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   4260770982                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   6311094482                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   1561811741                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   2625415492                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4187227233                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     24184000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data     65650250                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     89834250                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_misses::cpu1.data       143915                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu2.data       340660                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       484575                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data       143915                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu2.data       340660                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       484575                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2050446500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   4236651993                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   6287098493                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   1545558740                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   2630154746                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4175713486                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     24259750                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data     65218003                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     89477753                       # number of LoadLockedReq MSHR miss cycles
 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data        11000                       # number of StoreCondReq MSHR miss cycles
 system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total        11000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   3612135241                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   6886186474                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  10498321715                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   3612135241                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data   6886186474                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  10498321715                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    296522000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data    310560000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total    607082000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    364175500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    426698000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total    790873500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data    660697500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data    737258000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   1397955500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.083348                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.086014                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.039320                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.050507                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.047221                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.021705                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.099981                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.099910                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.037342                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data     0.000019                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   3596005240                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   6866806739                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  10462811979                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   3596005240                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data   6866806739                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  10462811979                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    298253500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data    315317000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total    613570500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    366377000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    431165001                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total    797542001                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data    664630500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data    746482001                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   1411112501                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.083513                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.086327                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.039385                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.050574                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.047182                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.021659                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.100575                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.099593                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.037257                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data     0.000020                       # mshr miss rate for StoreCondReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000005                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.069372                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.070813                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.032132                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.069372                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.070813                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.032132                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 20779.393135                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16909.565995                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17998.529801                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35258.527655                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 29455.363865                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31381.923082                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11237.918216                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12112.592251                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11864.005547                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.069496                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.070997                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.032150                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.069496                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.070997                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.032150                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 20639.031485                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16811.977655                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17894.118381                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34679.443086                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 29666.299104                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31343.317591                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11179.608295                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12106.553369                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11840.380177                       # average LoadLockedReq mshr miss latency
 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data        11000                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        11000                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25265.517504                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20187.819839                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21687.476300                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25265.517504                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20187.819839                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21687.476300                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24987.007887                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20157.361413                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21591.728791                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24987.007887                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20157.361413                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21591.728791                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -1425,22 +1393,22 @@ system.cpu1.dtb.fetch_hits                          0                       # IT
 system.cpu1.dtb.fetch_misses                        0                       # ITB misses
 system.cpu1.dtb.fetch_acv                           0                       # ITB acv
 system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu1.dtb.read_hits                     1203332                       # DTB read hits
-system.cpu1.dtb.read_misses                      1366                       # DTB read misses
+system.cpu1.dtb.read_hits                     1209129                       # DTB read hits
+system.cpu1.dtb.read_misses                      1367                       # DTB read misses
 system.cpu1.dtb.read_acv                           34                       # DTB read access violations
-system.cpu1.dtb.read_accesses                  142940                       # DTB read accesses
-system.cpu1.dtb.write_hits                     898898                       # DTB write hits
-system.cpu1.dtb.write_misses                      183                       # DTB write misses
-system.cpu1.dtb.write_acv                          22                       # DTB write access violations
-system.cpu1.dtb.write_accesses                  58529                       # DTB write accesses
-system.cpu1.dtb.data_hits                     2102230                       # DTB hits
-system.cpu1.dtb.data_misses                      1549                       # DTB misses
-system.cpu1.dtb.data_acv                           56                       # DTB access violations
-system.cpu1.dtb.data_accesses                  201469                       # DTB accesses
-system.cpu1.itb.fetch_hits                     859402                       # ITB hits
-system.cpu1.itb.fetch_misses                      692                       # ITB misses
+system.cpu1.dtb.read_accesses                  142945                       # DTB read accesses
+system.cpu1.dtb.write_hits                     903134                       # DTB write hits
+system.cpu1.dtb.write_misses                      185                       # DTB write misses
+system.cpu1.dtb.write_acv                          23                       # DTB write access violations
+system.cpu1.dtb.write_accesses                  58533                       # DTB write accesses
+system.cpu1.dtb.data_hits                     2112263                       # DTB hits
+system.cpu1.dtb.data_misses                      1552                       # DTB misses
+system.cpu1.dtb.data_acv                           57                       # DTB access violations
+system.cpu1.dtb.data_accesses                  201478                       # DTB accesses
+system.cpu1.itb.fetch_hits                     860790                       # ITB hits
+system.cpu1.itb.fetch_misses                      693                       # ITB misses
 system.cpu1.itb.fetch_acv                          30                       # ITB acv
-system.cpu1.itb.fetch_accesses                 860094                       # ITB accesses
+system.cpu1.itb.fetch_accesses                 861483                       # ITB accesses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.read_acv                            0                       # DTB read access violations
@@ -1453,29 +1421,29 @@ system.cpu1.itb.data_hits                           0                       # DT
 system.cpu1.itb.data_misses                         0                       # DTB misses
 system.cpu1.itb.data_acv                            0                       # DTB access violations
 system.cpu1.itb.data_accesses                       0                       # DTB accesses
-system.cpu1.numCycles                       953617285                       # number of cpu cycles simulated
+system.cpu1.numCycles                       953612854                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                    7956345                       # Number of instructions committed
-system.cpu1.committedOps                      7956345                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses              7412681                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                 44901                       # Number of float alu accesses
-system.cpu1.num_func_calls                     213028                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      1020887                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                     7412681                       # number of integer instructions
-system.cpu1.num_fp_insts                        44901                       # number of float instructions
-system.cpu1.num_int_register_reads           10388601                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes           5388855                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads               24208                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes              24605                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                      2109439                       # number of memory refs
-system.cpu1.num_load_insts                    1208206                       # Number of load instructions
-system.cpu1.num_store_insts                    901233                       # Number of store instructions
-system.cpu1.num_idle_cycles              922131579.439540                       # Number of idle cycles
-system.cpu1.num_busy_cycles              31485705.560460                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.033017                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.966983                       # Percentage of idle cycles
-system.cpu1.Branches                          1300702                       # Number of branches fetched
+system.cpu1.committedInsts                    8186270                       # Number of instructions committed
+system.cpu1.committedOps                      8186270                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses              7639715                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                 45422                       # Number of float alu accesses
+system.cpu1.num_func_calls                     213980                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      1089106                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                     7639715                       # number of integer instructions
+system.cpu1.num_fp_insts                        45422                       # number of float instructions
+system.cpu1.num_int_register_reads           10757840                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes           5542682                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads               24502                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes              24833                       # number of times the floating registers were written
+system.cpu1.num_mem_refs                      2119540                       # number of memory refs
+system.cpu1.num_load_insts                    1214044                       # Number of load instructions
+system.cpu1.num_store_insts                    905496                       # Number of store instructions
+system.cpu1.num_idle_cycles              923510145.865154                       # Number of idle cycles
+system.cpu1.num_busy_cycles              30102708.134846                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.031567                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.968433                       # Percentage of idle cycles
+system.cpu1.Branches                          1370105                       # Number of branches fetched
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
 system.cpu1.kern.inst.hwrei                         0                       # number of hwrei instructions executed
@@ -1493,35 +1461,35 @@ system.cpu1.kern.mode_ticks::kernel                 0                       # nu
 system.cpu1.kern.mode_ticks::user                   0                       # number of ticks spent at the given mode
 system.cpu1.kern.mode_ticks::idle                   0                       # number of ticks spent at the given mode
 system.cpu1.kern.swap_context                       0                       # number of times the context was actually changed
-system.cpu2.branchPred.lookups                9131296                       # Number of BP lookups
-system.cpu2.branchPred.condPredicted          8453261                       # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect           124867                       # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups             7606484                       # Number of BTB lookups
-system.cpu2.branchPred.BTBHits                6524985                       # Number of BTB hits
+system.cpu2.branchPred.lookups                9158053                       # Number of BP lookups
+system.cpu2.branchPred.condPredicted          8481927                       # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect           123683                       # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups             7604727                       # Number of BTB lookups
+system.cpu2.branchPred.BTBHits                6560922                       # Number of BTB hits
 system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct            85.781880                       # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS                 282035                       # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect             13344                       # Number of incorrect RAS predictions.
+system.cpu2.branchPred.BTBHitPct            86.274261                       # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS                 280761                       # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect             13305                       # Number of incorrect RAS predictions.
 system.cpu2.dtb.fetch_hits                          0                       # ITB hits
 system.cpu2.dtb.fetch_misses                        0                       # ITB misses
 system.cpu2.dtb.fetch_acv                           0                       # ITB acv
 system.cpu2.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu2.dtb.read_hits                     3186348                       # DTB read hits
-system.cpu2.dtb.read_misses                     11810                       # DTB read misses
-system.cpu2.dtb.read_acv                          124                       # DTB read access violations
-system.cpu2.dtb.read_accesses                  217745                       # DTB read accesses
-system.cpu2.dtb.write_hits                    2009701                       # DTB write hits
-system.cpu2.dtb.write_misses                     2606                       # DTB write misses
-system.cpu2.dtb.write_acv                         109                       # DTB write access violations
-system.cpu2.dtb.write_accesses                  82375                       # DTB write accesses
-system.cpu2.dtb.data_hits                     5196049                       # DTB hits
-system.cpu2.dtb.data_misses                     14416                       # DTB misses
-system.cpu2.dtb.data_acv                          233                       # DTB access violations
-system.cpu2.dtb.data_accesses                  300120                       # DTB accesses
-system.cpu2.itb.fetch_hits                     370442                       # ITB hits
-system.cpu2.itb.fetch_misses                     5628                       # ITB misses
-system.cpu2.itb.fetch_acv                         253                       # ITB acv
-system.cpu2.itb.fetch_accesses                 376070                       # ITB accesses
+system.cpu2.dtb.read_hits                     3175061                       # DTB read hits
+system.cpu2.dtb.read_misses                     11717                       # DTB read misses
+system.cpu2.dtb.read_acv                          122                       # DTB read access violations
+system.cpu2.dtb.read_accesses                  217137                       # DTB read accesses
+system.cpu2.dtb.write_hits                    2001578                       # DTB write hits
+system.cpu2.dtb.write_misses                     2618                       # DTB write misses
+system.cpu2.dtb.write_acv                         106                       # DTB write access violations
+system.cpu2.dtb.write_accesses                  82142                       # DTB write accesses
+system.cpu2.dtb.data_hits                     5176639                       # DTB hits
+system.cpu2.dtb.data_misses                     14335                       # DTB misses
+system.cpu2.dtb.data_acv                          228                       # DTB access violations
+system.cpu2.dtb.data_accesses                  299279                       # DTB accesses
+system.cpu2.itb.fetch_hits                     368924                       # ITB hits
+system.cpu2.itb.fetch_misses                     5740                       # ITB misses
+system.cpu2.itb.fetch_acv                         243                       # ITB acv
+system.cpu2.itb.fetch_accesses                 374664                       # ITB accesses
 system.cpu2.itb.read_hits                           0                       # DTB read hits
 system.cpu2.itb.read_misses                         0                       # DTB read misses
 system.cpu2.itb.read_acv                            0                       # DTB read access violations
@@ -1534,270 +1502,270 @@ system.cpu2.itb.data_hits                           0                       # DT
 system.cpu2.itb.data_misses                         0                       # DTB misses
 system.cpu2.itb.data_acv                            0                       # DTB access violations
 system.cpu2.itb.data_accesses                       0                       # DTB accesses
-system.cpu2.numCycles                        31313073                       # number of cpu cycles simulated
+system.cpu2.numCycles                        31279022                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles           8328585                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts                      37006400                       # Number of instructions fetch has processed
-system.cpu2.fetch.Branches                    9131296                       # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches           6807020                       # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles                      8851345                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles                 606644                       # Number of cycles fetch has spent squashing
-system.cpu2.fetch.BlockedCycles               9641968                       # Number of cycles fetch has spent blocked
-system.cpu2.fetch.MiscStallCycles               10046                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.PendingDrainCycles             1931                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu2.fetch.PendingTrapStallCycles        63228                       # Number of stall cycles due to pending traps
-system.cpu2.fetch.PendingQuiesceStallCycles        87070                       # Number of stall cycles due to pending quiesce instructions
-system.cpu2.fetch.IcacheWaitRetryStallCycles          340                       # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines                  2553376                       # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes                86779                       # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.rateDist::samples          27379324                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean             1.351618                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev            2.293970                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.icacheStallCycles           8287542                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts                      37055340                       # Number of instructions fetch has processed
+system.cpu2.fetch.Branches                    9158053                       # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches           6841683                       # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles                      8878582                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles                 603474                       # Number of cycles fetch has spent squashing
+system.cpu2.fetch.BlockedCycles               9658598                       # Number of cycles fetch has spent blocked
+system.cpu2.fetch.MiscStallCycles                9919                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.PendingDrainCycles             1948                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu2.fetch.PendingTrapStallCycles        63764                       # Number of stall cycles due to pending traps
+system.cpu2.fetch.PendingQuiesceStallCycles        87901                       # Number of stall cycles due to pending quiesce instructions
+system.cpu2.fetch.IcacheWaitRetryStallCycles          585                       # Number of stall cycles due to full MSHR
+system.cpu2.fetch.CacheLines                  2543899                       # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes                85179                       # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.rateDist::samples          27382085                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean             1.353269                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev            2.291783                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0                18527979     67.67%     67.67% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1                  269262      0.98%     68.65% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2                  428968      1.57%     70.22% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3                 5000608     18.26%     88.49% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4                  759354      2.77%     91.26% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5                  165275      0.60%     91.86% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6                  190932      0.70%     92.56% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7                  427573      1.56%     94.12% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8                 1609373      5.88%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0                18503503     67.58%     67.58% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1                  267960      0.98%     68.55% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2                  427466      1.56%     70.11% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3                 5038940     18.40%     88.52% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4                  758703      2.77%     91.29% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5                  165190      0.60%     91.89% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6                  190909      0.70%     92.59% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7                  425900      1.56%     94.14% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8                 1603514      5.86%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total            27379324                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate                 0.291613                       # Number of branch fetches per cycle
-system.cpu2.fetch.rate                       1.181819                       # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles                 8475609                       # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles              9724872                       # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles                  8241247                       # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles               308907                       # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles                382752                       # Number of cycles decode is squashing
-system.cpu2.decode.BranchResolved              165606                       # Number of times decode resolved a branch
-system.cpu2.decode.BranchMispred                12712                       # Number of times decode detected a branch misprediction
-system.cpu2.decode.DecodedInsts              36612854                       # Number of instructions handled by decode
-system.cpu2.decode.SquashedInsts                39749                       # Number of squashed instructions handled by decode
-system.cpu2.rename.SquashCycles                382752                       # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles                 8834671                       # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles                2773280                       # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles       5760129                       # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles                  8113478                       # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles              1269087                       # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts              35472103                       # Number of instructions processed by rename
-system.cpu2.rename.ROBFullEvents                 2436                       # Number of times rename has blocked due to ROB full
-system.cpu2.rename.IQFullEvents                230799                       # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LSQFullEvents               444723                       # Number of times rename has blocked due to LSQ full
-system.cpu2.rename.RenamedOperands           23769376                       # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups             44394567                       # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups        44338159                       # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups            52651                       # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps             21967508                       # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps                 1801868                       # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts            500326                       # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts         58967                       # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts                  3713170                       # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads             3346051                       # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores            2099971                       # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads           366369                       # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores          258671                       # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded                  32979578                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded             619087                       # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued                 32529976                       # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued            34753                       # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined        2147129                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined      1082645                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved        436861                       # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples     27379324                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean        1.188122                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev       1.575744                       # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total            27382085                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate                 0.292786                       # Number of branch fetches per cycle
+system.cpu2.fetch.rate                       1.184671                       # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles                 8439244                       # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles              9737555                       # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles                  8269995                       # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles               308345                       # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles                381075                       # Number of cycles decode is squashing
+system.cpu2.decode.BranchResolved              165536                       # Number of times decode resolved a branch
+system.cpu2.decode.BranchMispred                12831                       # Number of times decode detected a branch misprediction
+system.cpu2.decode.DecodedInsts              36664015                       # Number of instructions handled by decode
+system.cpu2.decode.SquashedInsts                39751                       # Number of squashed instructions handled by decode
+system.cpu2.rename.SquashCycles                381075                       # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles                 8796739                       # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles                2804819                       # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles       5741072                       # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles                  8142606                       # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles              1269911                       # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts              35531036                       # Number of instructions processed by rename
+system.cpu2.rename.ROBFullEvents                 2469                       # Number of times rename has blocked due to ROB full
+system.cpu2.rename.IQFullEvents                231647                       # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LSQFullEvents               446543                       # Number of times rename has blocked due to LSQ full
+system.cpu2.rename.RenamedOperands           23808302                       # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups             44475961                       # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups        44419812                       # Number of integer rename lookups
+system.cpu2.rename.fp_rename_lookups            52401                       # Number of floating rename lookups
+system.cpu2.rename.CommittedMaps             22020270                       # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps                 1788032                       # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts            498319                       # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts         58753                       # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts                  3705896                       # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads             3335757                       # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores            2091143                       # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads           366529                       # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores          285241                       # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded                  33051386                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded             616780                       # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued                 32598005                       # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued            35098                       # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined        2143170                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined      1082478                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved        435207                       # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples     27382085                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean        1.190487                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev       1.575531                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0           15104518     55.17%     55.17% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1            3059496     11.17%     66.34% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2            1557193      5.69%     72.03% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3            5827645     21.28%     93.31% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4             904106      3.30%     96.62% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5             480512      1.76%     98.37% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6             285612      1.04%     99.41% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7             141433      0.52%     99.93% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8              18809      0.07%    100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0           15085778     55.09%     55.09% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1            3054879     11.16%     66.25% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2            1548873      5.66%     71.91% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3            5868849     21.43%     93.34% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4             901287      3.29%     96.63% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5             476925      1.74%     98.37% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6             288026      1.05%     99.42% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7             138840      0.51%     99.93% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8              18628      0.07%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total       27379324                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total       27382085                       # Number of insts issued each cycle
 system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu                  32920     13.41%     13.41% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult                     0      0.00%     13.41% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv                      0      0.00%     13.41% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     13.41% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     13.41% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     13.41% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult                   0      0.00%     13.41% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     13.41% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     13.41% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     13.41% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     13.41% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     13.41% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     13.41% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     13.41% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     13.41% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult                    0      0.00%     13.41% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     13.41% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift                   0      0.00%     13.41% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     13.41% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     13.41% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     13.41% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     13.41% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     13.41% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     13.41% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     13.41% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     13.41% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     13.41% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     13.41% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     13.41% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead                112185     45.69%     59.09% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite               100449     40.91%    100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu                  33655     13.83%     13.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult                     0      0.00%     13.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv                      0      0.00%     13.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     13.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     13.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     13.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult                   0      0.00%     13.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     13.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     13.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     13.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     13.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     13.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     13.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     13.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     13.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult                    0      0.00%     13.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     13.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift                   0      0.00%     13.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     13.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     13.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     13.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     13.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     13.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     13.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     13.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     13.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     13.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     13.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     13.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead                111431     45.78%     59.60% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite                98340     40.40%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu2.iq.FU_type_0::No_OpClass             2440      0.01%      0.01% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu             26864472     82.58%     82.59% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult               20045      0.06%     82.65% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     82.65% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd               8419      0.03%     82.68% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     82.68% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     82.68% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     82.68% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv               1220      0.00%     82.68% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     82.68% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     82.68% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     82.68% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     82.68% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     82.68% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     82.68% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     82.68% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     82.68% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     82.68% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     82.68% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     82.68% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     82.68% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     82.68% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     82.68% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     82.68% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     82.68% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     82.68% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     82.68% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     82.68% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     82.68% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     82.68% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead             3313279     10.19%     92.87% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite            2032055      6.25%     99.11% # Type of FU issued
-system.cpu2.iq.FU_type_0::IprAccess            288046      0.89%    100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu             26953534     82.68%     82.69% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult               19910      0.06%     82.75% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     82.75% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd               8410      0.03%     82.78% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     82.78% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     82.78% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     82.78% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv               1220      0.00%     82.78% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     82.78% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     82.78% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     82.78% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     82.78% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     82.78% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     82.78% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     82.78% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     82.78% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     82.78% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     82.78% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     82.78% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     82.78% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     82.78% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     82.78% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     82.78% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     82.78% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     82.78% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     82.78% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     82.78% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     82.78% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     82.78% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead             3301438     10.13%     92.91% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite            2024047      6.21%     99.12% # Type of FU issued
+system.cpu2.iq.FU_type_0::IprAccess            287006      0.88%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total              32529976                       # Type of FU issued
-system.cpu2.iq.rate                          1.038862                       # Inst issue rate
-system.cpu2.iq.fu_busy_cnt                     245554                       # FU busy when requested
-system.cpu2.iq.fu_busy_rate                  0.007549                       # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads          92485827                       # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes         35635212                       # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses     32132884                       # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads             233756                       # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes            114401                       # Number of floating instruction queue writes
-system.cpu2.iq.fp_inst_queue_wakeup_accesses       110529                       # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses              32651329                       # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses                 121761                       # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads          186414                       # Number of loads that had data forwarded from stores
+system.cpu2.iq.FU_type_0::total              32598005                       # Type of FU issued
+system.cpu2.iq.rate                          1.042168                       # Inst issue rate
+system.cpu2.iq.fu_busy_cnt                     243426                       # FU busy when requested
+system.cpu2.iq.fu_busy_rate                  0.007468                       # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads          92623863                       # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes         35700994                       # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses     32205742                       # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.fp_inst_queue_reads             232756                       # Number of floating instruction queue reads
+system.cpu2.iq.fp_inst_queue_writes            114085                       # Number of floating instruction queue writes
+system.cpu2.iq.fp_inst_queue_wakeup_accesses       110215                       # Number of floating instruction queue wakeup accesses
+system.cpu2.iq.int_alu_accesses              32717888                       # Number of integer alu accesses
+system.cpu2.iq.fp_alu_accesses                 121103                       # Number of floating point alu accesses
+system.cpu2.iew.lsq.thread0.forwLoads          185687                       # Number of loads that had data forwarded from stores
 system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads       413956                       # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses         1112                       # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation         3936                       # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores       157547                       # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedLoads       410803                       # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses         1083                       # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation         3827                       # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores       157383                       # Number of stores squashed
 system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads         4151                       # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked        27254                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu2.iew.lsq.thread0.rescheduledLoads         4176                       # Number of loads that were rescheduled
+system.cpu2.iew.lsq.thread0.cacheBlocked        27619                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles                382752                       # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles                2003866                       # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles               204399                       # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts           34866454                       # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts           220221                       # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts              3346051                       # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts             2099971                       # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts            549960                       # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents                142228                       # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents                 1969                       # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents          3936                       # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect         63951                       # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect       128015                       # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts              191966                       # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts             32372492                       # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts              3206448                       # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts           157484                       # Number of squashed instructions skipped in execute
+system.cpu2.iew.iewSquashCycles                381075                       # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles                2023183                       # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles               204607                       # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts           34934170                       # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts           220301                       # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts              3335757                       # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts             2091143                       # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts            547666                       # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents                141469                       # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewLSQFullEvents                 2123                       # Number of times the LSQ has become full, causing a stall
+system.cpu2.iew.memOrderViolationEvents          3827                       # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect         63090                       # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect       127121                       # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts              190211                       # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts             32442083                       # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts              3195032                       # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts           155922                       # Number of squashed instructions skipped in execute
 system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu2.iew.exec_nop                      1267789                       # number of nop insts executed
-system.cpu2.iew.exec_refs                     5223192                       # number of memory reference insts executed
-system.cpu2.iew.exec_branches                 7564928                       # Number of branches executed
-system.cpu2.iew.exec_stores                   2016744                       # Number of stores executed
-system.cpu2.iew.exec_rate                    1.033833                       # Inst execution rate
-system.cpu2.iew.wb_sent                      32276755                       # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count                     32243413                       # cumulative count of insts written-back
-system.cpu2.iew.wb_producers                 18781769                       # num instructions producing a value
-system.cpu2.iew.wb_consumers                 21976070                       # num instructions consuming a value
+system.cpu2.iew.exec_nop                      1266004                       # number of nop insts executed
+system.cpu2.iew.exec_refs                     5203645                       # number of memory reference insts executed
+system.cpu2.iew.exec_branches                 7597485                       # Number of branches executed
+system.cpu2.iew.exec_stores                   2008613                       # Number of stores executed
+system.cpu2.iew.exec_rate                    1.037183                       # Inst execution rate
+system.cpu2.iew.wb_sent                      32348485                       # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count                     32315957                       # cumulative count of insts written-back
+system.cpu2.iew.wb_producers                 18839799                       # num instructions producing a value
+system.cpu2.iew.wb_consumers                 22025525                       # num instructions consuming a value
 system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate                      1.029711                       # insts written-back per cycle
-system.cpu2.iew.wb_fanout                    0.854646                       # average fanout of values written-back
+system.cpu2.iew.wb_rate                      1.033151                       # insts written-back per cycle
+system.cpu2.iew.wb_fanout                    0.855362                       # average fanout of values written-back
 system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts        2322975                       # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls         182226                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts           177336                       # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples     26996572                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean     1.203754                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev     1.846865                       # Number of insts commited each cycle
+system.cpu2.commit.commitSquashedInsts        2315429                       # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls         181573                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts           175784                       # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples     27001010                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean     1.206363                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev     1.845727                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0     16110852     59.68%     59.68% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1      2323792      8.61%     68.29% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2      1227035      4.55%     72.83% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3      5572191     20.64%     93.47% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4       501625      1.86%     95.33% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5       185779      0.69%     96.02% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6       177561      0.66%     96.67% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7       179863      0.67%     97.34% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8       717874      2.66%    100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0     16087817     59.58%     59.58% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1      2320535      8.59%     68.18% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2      1221811      4.53%     72.70% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3      5612171     20.79%     93.49% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4       500601      1.85%     95.34% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5       184383      0.68%     96.02% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6       174610      0.65%     96.67% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7       192284      0.71%     97.38% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8       706798      2.62%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total     26996572                       # Number of insts commited each cycle
-system.cpu2.commit.committedInsts            32497229                       # Number of instructions committed
-system.cpu2.commit.committedOps              32497229                       # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total     27001010                       # Number of insts commited each cycle
+system.cpu2.commit.committedInsts            32573021                       # Number of instructions committed
+system.cpu2.commit.committedOps              32573021                       # Number of ops (including micro ops) committed
 system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu2.commit.refs                       4874519                       # Number of memory references committed
-system.cpu2.commit.loads                      2932095                       # Number of loads committed
-system.cpu2.commit.membars                      63814                       # Number of memory barriers committed
-system.cpu2.commit.branches                   7417113                       # Number of branches committed
-system.cpu2.commit.fp_insts                    109328                       # Number of committed floating point instructions.
-system.cpu2.commit.int_insts                 31054650                       # Number of committed integer instructions.
-system.cpu2.commit.function_calls              228340                       # Number of function calls committed.
-system.cpu2.commit.bw_lim_events               717874                       # number cycles where commit BW limit reached
+system.cpu2.commit.refs                       4858714                       # Number of memory references committed
+system.cpu2.commit.loads                      2924954                       # Number of loads committed
+system.cpu2.commit.membars                      63567                       # Number of memory barriers committed
+system.cpu2.commit.branches                   7451291                       # Number of branches committed
+system.cpu2.commit.fp_insts                    109021                       # Number of committed floating point instructions.
+system.cpu2.commit.int_insts                 31134232                       # Number of committed integer instructions.
+system.cpu2.commit.function_calls              227850                       # Number of function calls committed.
+system.cpu2.commit.bw_lim_events               706798                       # number cycles where commit BW limit reached
 system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu2.rob.rob_reads                    61024976                       # The number of ROB reads
-system.cpu2.rob.rob_writes                   70022633                       # The number of ROB writes
-system.cpu2.timesIdled                         244840                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles                        3933749                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles                  1746460059                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts                   31334430                       # Number of Instructions Simulated
-system.cpu2.committedOps                     31334430                       # Number of Ops (including micro ops) Simulated
-system.cpu2.committedInsts_total             31334430                       # Number of Instructions Simulated
-system.cpu2.cpi                              0.999318                       # CPI: Cycles Per Instruction
-system.cpu2.cpi_total                        0.999318                       # CPI: Total CPI of All Threads
-system.cpu2.ipc                              1.000682                       # IPC: Instructions Per Cycle
-system.cpu2.ipc_total                        1.000682                       # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads                42582766                       # number of integer regfile reads
-system.cpu2.int_regfile_writes               22654603                       # number of integer regfile writes
-system.cpu2.fp_regfile_reads                    67639                       # number of floating regfile reads
-system.cpu2.fp_regfile_writes                   67817                       # number of floating regfile writes
-system.cpu2.misc_regfile_reads                5361637                       # number of misc regfile reads
-system.cpu2.misc_regfile_writes                256988                       # number of misc regfile writes
+system.cpu2.rob.rob_reads                    61108801                       # The number of ROB reads
+system.cpu2.rob.rob_writes                   70157468                       # The number of ROB writes
+system.cpu2.timesIdled                         244589                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles                        3896937                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles                  1746488839                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts                   31413101                       # Number of Instructions Simulated
+system.cpu2.committedOps                     31413101                       # Number of Ops (including micro ops) Simulated
+system.cpu2.committedInsts_total             31413101                       # Number of Instructions Simulated
+system.cpu2.cpi                              0.995732                       # CPI: Cycles Per Instruction
+system.cpu2.cpi_total                        0.995732                       # CPI: Total CPI of All Threads
+system.cpu2.ipc                              1.004287                       # IPC: Instructions Per Cycle
+system.cpu2.ipc_total                        1.004287                       # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads                42678646                       # number of integer regfile reads
+system.cpu2.int_regfile_writes               22701958                       # number of integer regfile writes
+system.cpu2.fp_regfile_reads                    67399                       # number of floating regfile reads
+system.cpu2.fp_regfile_writes                   67744                       # number of floating regfile writes
+system.cpu2.misc_regfile_reads                5400058                       # number of misc regfile reads
+system.cpu2.misc_regfile_writes                256035                       # number of misc regfile writes
 system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed
 system.cpu2.kern.inst.hwrei                         0                       # number of hwrei instructions executed
index a0de7ff7f738a38db69a8ed5b28ba682dec5279e..5f9799ffedad1da87b43de8165911f8a502eaab8 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.526127                       # Number of seconds simulated
-sim_ticks                                2526126762000                       # Number of ticks simulated
-final_tick                               2526126762000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.526170                       # Number of seconds simulated
+sim_ticks                                2526169857500                       # Number of ticks simulated
+final_tick                               2526169857500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  50904                       # Simulator instruction rate (inst/s)
-host_op_rate                                    65499                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2132173780                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 425424                       # Number of bytes of host memory used
-host_seconds                                  1184.77                       # Real time elapsed on the host
-sim_insts                                    60309150                       # Number of instructions simulated
-sim_ops                                      77600646                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  46796                       # Simulator instruction rate (inst/s)
+host_op_rate                                    60213                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1960134913                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 468616                       # Number of bytes of host memory used
+host_seconds                                  1288.77                       # Real time elapsed on the host
+sim_insts                                    60309637                       # Number of instructions simulated
+sim_ops                                      77601213                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::realview.clcd    119537664                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker         2752                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker         2880                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst            797888                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9093912                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            129432344                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       797888                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          797888                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      3783552                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.inst            797632                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9095320                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            129433624                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       797632                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          797632                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      3785024                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data        3016072                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6799624                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           6801096                       # Number of bytes written to this memory
 system.physmem.num_reads::realview.clcd      14942208                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker           43                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker           45                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              12467                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             142128                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total              15096848                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           59118                       # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu.inst              12463                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             142150                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total              15096868                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           59141                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data            754018                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               813136                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd        47320533                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker           1089                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               813159                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd        47319725                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker           1140                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.itb.walker             51                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               315854                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3599943                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                51237470                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          315854                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             315854                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1497768                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data             1193951                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2691719                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1497768                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd       47320533                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker          1089                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               315748                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3600439                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                51237103                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          315748                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             315748                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1498325                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data             1193931                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2692256                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1498325                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd       47319725                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker          1140                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.itb.walker            51                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              315854                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             4793894                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               53929189                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                      15096848                       # Number of read requests accepted
-system.physmem.writeReqs                       813136                       # Number of write requests accepted
-system.physmem.readBursts                    15096848                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     813136                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                963809856                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                   2388416                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   6900096                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 129432344                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                6799624                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                    37319                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                  705316                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           4693                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              943581                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              943177                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              939217                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              939246                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              943119                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              943143                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              939192                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              938854                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              943994                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              943547                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             939009                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             937977                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             943925                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             943586                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             939160                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             938802                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                6706                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                6463                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                6599                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                6631                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                6542                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                6795                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6787                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                6728                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7129                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                6879                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               6534                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6185                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7139                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               6761                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7032                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               6904                       # Per bank write bursts
+system.physmem.bw_total::cpu.inst              315748                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             4794370                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               53929359                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                      15096868                       # Number of read requests accepted
+system.physmem.writeReqs                       813159                       # Number of write requests accepted
+system.physmem.readBursts                    15096868                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     813159                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                960809152                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                   5390400                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   6824768                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 129433624                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                6801096                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                    84225                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                  706499                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs           4674                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0              943297                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              937033                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              936962                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              936535                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              942693                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              936569                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              936319                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              936043                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              943596                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              936992                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             936414                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             935912                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             943556                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             937007                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             937039                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             936676                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                6606                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                6375                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                6521                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                6552                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                6461                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                6711                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6720                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                6668                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7045                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                6826                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               6497                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6136                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7072                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               6672                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               6956                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               6819                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2526125654500                       # Total gap between requests
+system.physmem.totGap                    2526168741500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                      38                       # Read request sizes (log2)
 system.physmem.readPktSize::3                14942208                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  154602                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  154622                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                 754018                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  59118                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1175583                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                   1121241                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                   1077080                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                   3628602                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                   2607512                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                   2594359                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                   2599949                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                     53287                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                     57711                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                     21124                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                    20900                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                    20768                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                    20512                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                    20375                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                    20258                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                    20166                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                       91                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        7                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        3                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                        1                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  59141                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1044851                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    985737                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                    938636                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                    947948                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                    933228                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                    933834                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                   2717841                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                   2709185                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                   3589675                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                     37568                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                    33871                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                    34960                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                    32201                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                    30053                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                    21726                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                    21191                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                      119                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                       11                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                        4                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                        4                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
@@ -144,619 +144,147 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                      4767                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                      5448                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                      4894                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                      5081                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                      5199                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                      4872                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                      4884                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                      4873                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                      4830                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                      4808                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                     4806                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                     4793                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                     4788                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                     4799                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                     4794                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     4795                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     4787                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4809                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4821                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     4801                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     4805                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5153                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                      137                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                       65                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                       11                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        85983                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean    11289.547748                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean    1006.032615                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev   16787.302098                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64-71          23431     27.25%     27.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-135        14045     16.33%     43.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192-199         2670      3.11%     46.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-263         2200      2.56%     49.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320-327         1296      1.51%     50.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-391         1149      1.34%     52.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448-455          926      1.08%     53.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-519          910      1.06%     54.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576-583          583      0.68%     54.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-647          573      0.67%     55.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704-711          527      0.61%     56.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-775          540      0.63%     56.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832-839          283      0.33%     57.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-903          315      0.37%     57.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960-967          148      0.17%     57.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1031          512      0.60%     58.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088-1095          103      0.12%     58.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152-1159          143      0.17%     58.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216-1223           77      0.09%     58.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280-1287          250      0.29%     58.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344-1351           57      0.07%     59.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408-1415          507      0.59%     59.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472-1479           36      0.04%     59.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536-1543          193      0.22%     59.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600-1607           17      0.02%     59.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664-1671          103      0.12%     60.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1728-1735           18      0.02%     60.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1792-1799           71      0.08%     60.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856-1863           17      0.02%     60.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1920-1927           58      0.07%     60.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984-1991           16      0.02%     60.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2048-2055          468      0.54%     60.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112-2119           10      0.01%     60.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2176-2183           32      0.04%     60.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2240-2247           13      0.02%     60.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2304-2311          249      0.29%     61.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2368-2375            8      0.01%     61.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2432-2439           28      0.03%     61.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2496-2503            7      0.01%     61.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2560-2567           30      0.03%     61.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2624-2631            8      0.01%     61.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2688-2695           18      0.02%     61.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2752-2759            6      0.01%     61.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2816-2823          116      0.13%     61.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2880-2887           10      0.01%     61.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2944-2951           18      0.02%     61.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3008-3015            4      0.00%     61.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3072-3079          420      0.49%     61.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3136-3143            7      0.01%     61.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3200-3207           24      0.03%     61.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3264-3271            6      0.01%     61.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3328-3335           25      0.03%     61.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3392-3399            6      0.01%     61.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3456-3463           21      0.02%     62.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3520-3527            6      0.01%     62.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3584-3591          157      0.18%     62.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3648-3655            5      0.01%     62.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3712-3719           17      0.02%     62.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3776-3783            9      0.01%     62.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3840-3847           20      0.02%     62.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3904-3911           11      0.01%     62.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3968-3975           15      0.02%     62.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4032-4039           13      0.02%     62.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4096-4103          363      0.42%     62.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4160-4167            9      0.01%     62.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4224-4231           13      0.02%     62.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4288-4295            7      0.01%     62.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4352-4359          108      0.13%     62.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4416-4423           18      0.02%     62.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4480-4487           14      0.02%     62.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4544-4551           12      0.01%     62.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4608-4615          161      0.19%     63.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4672-4679            8      0.01%     63.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4736-4743           15      0.02%     63.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4800-4807            2      0.00%     63.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4864-4871           23      0.03%     63.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4928-4935            6      0.01%     63.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4992-4999           14      0.02%     63.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5056-5063            4      0.00%     63.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5120-5127          356      0.41%     63.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5184-5191            5      0.01%     63.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5248-5255           11      0.01%     63.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5312-5319           11      0.01%     63.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5376-5383          163      0.19%     63.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5440-5447            2      0.00%     63.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5504-5511           16      0.02%     63.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5568-5575            2      0.00%     63.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5632-5639           50      0.06%     63.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5696-5703            6      0.01%     63.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5760-5767           13      0.02%     63.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5824-5831            4      0.00%     63.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5888-5895          197      0.23%     64.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5952-5959            3      0.00%     64.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6016-6023            9      0.01%     64.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6080-6087            7      0.01%     64.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6144-6151          223      0.26%     64.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6208-6215            4      0.00%     64.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6272-6279           13      0.02%     64.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6336-6343            5      0.01%     64.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6400-6407          140      0.16%     64.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6464-6471            2      0.00%     64.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6528-6535            8      0.01%     64.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6592-6599            2      0.00%     64.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6656-6663           88      0.10%     64.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6720-6727            2      0.00%     64.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6784-6791           14      0.02%     64.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6848-6855            3      0.00%     64.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6912-6919          158      0.18%     64.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6976-6983            6      0.01%     64.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7040-7047           14      0.02%     64.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7104-7111            1      0.00%     64.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7168-7175          345      0.40%     65.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7232-7239            1      0.00%     65.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7296-7303            5      0.01%     65.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7360-7367            8      0.01%     65.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7424-7431           13      0.02%     65.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7488-7495            4      0.00%     65.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7552-7559           18      0.02%     65.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7616-7623            6      0.01%     65.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7680-7687          141      0.16%     65.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7744-7751            2      0.00%     65.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7808-7815            6      0.01%     65.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7936-7943           41      0.05%     65.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8000-8007            2      0.00%     65.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8064-8071           10      0.01%     65.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8192-8199          399      0.46%     66.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8256-8263            1      0.00%     66.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8448-8455           36      0.04%     66.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8576-8583            2      0.00%     66.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8704-8711          130      0.15%     66.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8896-8903            2      0.00%     66.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8960-8967            5      0.01%     66.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9088-9095            1      0.00%     66.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9216-9223          341      0.40%     66.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9344-9351            3      0.00%     66.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9472-9479          145      0.17%     66.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9536-9543            1      0.00%     66.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9600-9607            2      0.00%     66.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9728-9735           78      0.09%     67.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9792-9799            2      0.00%     67.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9856-9863            3      0.00%     67.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9984-9991          133      0.15%     67.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10048-10055            2      0.00%     67.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10112-10119            3      0.00%     67.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10240-10247          212      0.25%     67.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10368-10375            2      0.00%     67.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10496-10503          150      0.17%     67.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10688-10695            1      0.00%     67.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10752-10759           41      0.05%     67.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10880-10887            1      0.00%     67.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10944-10951            2      0.00%     67.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11008-11015          153      0.18%     67.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11136-11143            4      0.00%     67.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11264-11271          349      0.41%     68.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11520-11527            8      0.01%     68.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11648-11655            3      0.00%     68.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11776-11783          141      0.16%     68.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11904-11911            3      0.00%     68.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11968-11975            1      0.00%     68.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12032-12039           94      0.11%     68.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12096-12103            2      0.00%     68.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12160-12167            4      0.00%     68.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12288-12295          334      0.39%     68.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12352-12359            1      0.00%     68.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12544-12551           13      0.02%     68.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12672-12679            3      0.00%     68.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12736-12743            1      0.00%     68.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12800-12807          141      0.16%     69.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12864-12871            1      0.00%     69.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12992-12999            1      0.00%     69.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13056-13063            6      0.01%     69.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13120-13127            1      0.00%     69.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13184-13191            2      0.00%     69.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13312-13319          399      0.46%     69.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13376-13383            1      0.00%     69.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13440-13447            1      0.00%     69.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13568-13575           94      0.11%     69.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13760-13767            2      0.00%     69.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13824-13831            2      0.00%     69.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13952-13959            3      0.00%     69.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14016-14023            1      0.00%     69.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14080-14087          214      0.25%     69.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14144-14151            2      0.00%     69.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14208-14215            4      0.00%     69.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14272-14279            1      0.00%     69.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14336-14343          420      0.49%     70.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14592-14599            5      0.01%     70.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14720-14727            1      0.00%     70.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14848-14855           22      0.03%     70.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14976-14983            1      0.00%     70.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15104-15111          141      0.16%     70.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15168-15175            1      0.00%     70.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15232-15239            1      0.00%     70.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15360-15367          335      0.39%     71.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15424-15431            1      0.00%     71.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15488-15495            1      0.00%     71.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15552-15559            1      0.00%     71.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15616-15623           80      0.09%     71.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15808-15815            2      0.00%     71.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15872-15879            5      0.01%     71.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15936-15943            2      0.00%     71.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16000-16007            2      0.00%     71.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16064-16071            1      0.00%     71.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16128-16135          143      0.17%     71.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16256-16263            6      0.01%     71.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16384-16391          673      0.78%     72.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16512-16519            1      0.00%     72.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16640-16647          144      0.17%     72.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16896-16903            7      0.01%     72.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16960-16967            2      0.00%     72.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17024-17031            1      0.00%     72.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17152-17159           81      0.09%     72.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17280-17287            2      0.00%     72.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17408-17415          336      0.39%     72.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17536-17543            2      0.00%     72.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17664-17671          135      0.16%     72.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17728-17735            1      0.00%     72.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17792-17799            4      0.00%     72.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17920-17927           25      0.03%     72.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18048-18055            1      0.00%     72.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18112-18119            1      0.00%     72.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18176-18183            6      0.01%     72.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18240-18247            1      0.00%     72.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18304-18311            2      0.00%     72.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18432-18439          419      0.49%     73.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18560-18567            2      0.00%     73.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18688-18695          214      0.25%     73.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18752-18759            1      0.00%     73.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18944-18951            4      0.00%     73.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19072-19079            1      0.00%     73.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19200-19207           97      0.11%     73.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19264-19271            2      0.00%     73.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19328-19335            2      0.00%     73.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19456-19463          391      0.45%     74.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19584-19591            1      0.00%     74.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19712-19719           10      0.01%     74.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19840-19847            3      0.00%     74.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19904-19911            1      0.00%     74.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19968-19975          139      0.16%     74.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20032-20039            1      0.00%     74.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20160-20167            2      0.00%     74.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20224-20231           13      0.02%     74.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20352-20359            4      0.00%     74.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20480-20487          331      0.38%     74.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20608-20615            1      0.00%     74.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20672-20679            1      0.00%     74.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20736-20743           94      0.11%     75.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20800-20807            1      0.00%     75.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20864-20871            1      0.00%     75.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20928-20935            2      0.00%     75.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20992-20999          142      0.17%     75.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21120-21127            2      0.00%     75.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21184-21191            1      0.00%     75.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21248-21255           13      0.02%     75.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21376-21383            2      0.00%     75.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21504-21511          343      0.40%     75.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21632-21639            3      0.00%     75.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21696-21703            1      0.00%     75.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21760-21767          150      0.17%     75.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21888-21895            1      0.00%     75.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21952-21959            1      0.00%     75.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22016-22023           38      0.04%     75.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22080-22087            1      0.00%     75.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22144-22151            3      0.00%     75.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22272-22279          148      0.17%     76.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22400-22407            2      0.00%     76.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22464-22471            1      0.00%     76.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22528-22535          208      0.24%     76.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22656-22663            1      0.00%     76.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22720-22727            2      0.00%     76.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22784-22791          129      0.15%     76.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22848-22855            1      0.00%     76.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23040-23047           76      0.09%     76.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23104-23111            1      0.00%     76.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23168-23175            2      0.00%     76.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23296-23303          148      0.17%     76.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23424-23431            1      0.00%     76.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23488-23495            1      0.00%     76.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23552-23559          338      0.39%     77.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23808-23815           10      0.01%     77.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23936-23943            2      0.00%     77.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24064-24071          128      0.15%     77.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24128-24135            1      0.00%     77.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24256-24263            2      0.00%     77.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24320-24327           34      0.04%     77.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24448-24455            4      0.00%     77.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24512-24519            1      0.00%     77.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24576-24583          281      0.33%     77.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24640-24647            2      0.00%     77.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24704-24711            3      0.00%     77.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24768-24775            1      0.00%     77.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24832-24839           36      0.04%     77.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24960-24967            1      0.00%     77.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25088-25095          132      0.15%     77.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25152-25159            1      0.00%     77.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25216-25223            1      0.00%     77.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25344-25351            9      0.01%     77.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25472-25479            2      0.00%     77.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25536-25543            1      0.00%     77.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25600-25607          331      0.38%     78.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25728-25735            1      0.00%     78.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25792-25799            1      0.00%     78.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25856-25863          146      0.17%     78.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25920-25927            1      0.00%     78.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25984-25991            1      0.00%     78.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26112-26119           78      0.09%     78.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26176-26183            1      0.00%     78.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26240-26247            2      0.00%     78.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26304-26311            1      0.00%     78.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26368-26375          128      0.15%     78.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26432-26439            1      0.00%     78.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26496-26503            6      0.01%     78.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26560-26567            1      0.00%     78.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26624-26631          207      0.24%     78.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26688-26695            1      0.00%     78.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26752-26759            3      0.00%     78.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26816-26823            1      0.00%     78.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26880-26887          146      0.17%     79.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26944-26951            3      0.00%     79.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27008-27015            1      0.00%     79.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27136-27143           38      0.04%     79.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27264-27271            1      0.00%     79.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27392-27399          151      0.18%     79.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27456-27463            1      0.00%     79.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27520-27527            3      0.00%     79.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27584-27591            2      0.00%     79.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27648-27655          337      0.39%     79.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27712-27719            1      0.00%     79.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27840-27847            2      0.00%     79.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27904-27911           13      0.02%     79.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27968-27975            1      0.00%     79.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28032-28039            1      0.00%     79.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28160-28167          141      0.16%     79.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28224-28231            1      0.00%     79.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28288-28295            1      0.00%     79.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28416-28423           97      0.11%     79.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28544-28551            5      0.01%     79.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28608-28615            4      0.00%     79.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28672-28679          328      0.38%     80.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28800-28807            1      0.00%     80.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28864-28871            1      0.00%     80.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28928-28935           12      0.01%     80.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29056-29063            2      0.00%     80.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29120-29127            1      0.00%     80.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29184-29191          141      0.16%     80.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29312-29319            1      0.00%     80.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29440-29447            7      0.01%     80.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29568-29575            3      0.00%     80.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29696-29703          399      0.46%     81.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29824-29831            1      0.00%     81.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29888-29895            2      0.00%     81.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29952-29959           90      0.10%     81.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30144-30151            2      0.00%     81.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30208-30215            5      0.01%     81.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30336-30343            1      0.00%     81.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30400-30407            1      0.00%     81.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30464-30471          214      0.25%     81.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30528-30535            1      0.00%     81.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30592-30599            3      0.00%     81.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30656-30663            1      0.00%     81.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30720-30727          415      0.48%     81.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30848-30855            2      0.00%     81.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30976-30983            5      0.01%     81.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31040-31047            1      0.00%     81.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31104-31111            1      0.00%     81.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31168-31175            3      0.00%     81.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31232-31239           21      0.02%     81.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31360-31367            2      0.00%     81.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31424-31431            1      0.00%     81.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31488-31495          138      0.16%     82.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31616-31623            3      0.00%     82.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31744-31751          338      0.39%     82.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31872-31879            2      0.00%     82.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31936-31943            1      0.00%     82.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32000-32007           78      0.09%     82.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32192-32199            1      0.00%     82.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32256-32263            9      0.01%     82.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32384-32391            1      0.00%     82.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32448-32455            2      0.00%     82.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32512-32519          145      0.17%     82.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32576-32583            1      0.00%     82.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32640-32647            1      0.00%     82.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32768-32775          671      0.78%     83.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32960-32967            1      0.00%     83.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33024-33031          141      0.16%     83.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33152-33159            1      0.00%     83.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33280-33287            7      0.01%     83.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33344-33351            1      0.00%     83.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33408-33415            4      0.00%     83.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33536-33543           85      0.10%     83.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33600-33607            2      0.00%     83.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33664-33671            1      0.00%     83.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33728-33735            1      0.00%     83.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33792-33799          348      0.40%     84.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34048-34055          136      0.16%     84.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34304-34311           21      0.02%     84.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34368-34375            1      0.00%     84.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34432-34439            3      0.00%     84.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34496-34503            2      0.00%     84.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34560-34567            8      0.01%     84.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34688-34695            2      0.00%     84.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34816-34823          412      0.48%     84.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35072-35079          212      0.25%     85.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35328-35335            5      0.01%     85.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35456-35463            3      0.00%     85.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35584-35591           91      0.11%     85.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35840-35847          392      0.46%     85.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35904-35911            1      0.00%     85.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35968-35975            2      0.00%     85.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36096-36103            8      0.01%     85.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36352-36359          140      0.16%     85.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36480-36487            4      0.00%     85.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36544-36551            1      0.00%     85.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36608-36615           12      0.01%     85.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36864-36871          327      0.38%     86.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36928-36935            1      0.00%     86.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37120-37127           90      0.10%     86.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37248-37255            1      0.00%     86.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37312-37319            1      0.00%     86.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37376-37383          141      0.16%     86.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37440-37447            1      0.00%     86.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37504-37511            3      0.00%     86.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37632-37639           10      0.01%     86.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37696-37703            1      0.00%     86.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37760-37767            1      0.00%     86.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37888-37895          334      0.39%     86.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37952-37959            1      0.00%     86.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38080-38087            1      0.00%     86.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38144-38151          149      0.17%     87.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38272-38279            1      0.00%     87.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38400-38407           37      0.04%     87.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38528-38535            2      0.00%     87.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38592-38599            1      0.00%     87.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38656-38663          150      0.17%     87.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38784-38791            1      0.00%     87.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38848-38855            1      0.00%     87.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38912-38919          205      0.24%     87.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39168-39175          127      0.15%     87.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39424-39431           76      0.09%     87.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39552-39559            2      0.00%     87.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39616-39623            1      0.00%     87.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39680-39687          146      0.17%     88.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39936-39943          330      0.38%     88.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40000-40007            1      0.00%     88.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40064-40071            1      0.00%     88.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40192-40199            7      0.01%     88.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40384-40391            1      0.00%     88.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40448-40455          132      0.15%     88.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40576-40583            4      0.00%     88.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40704-40711           37      0.04%     88.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40896-40903            1      0.00%     88.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40960-40967          277      0.32%     88.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41088-41095            1      0.00%     88.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41152-41159            1      0.00%     88.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41216-41223           34      0.04%     88.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41472-41479          128      0.15%     89.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41600-41607            1      0.00%     89.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41728-41735           10      0.01%     89.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41856-41863            1      0.00%     89.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41920-41927            1      0.00%     89.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41984-41991          332      0.39%     89.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42240-42247          142      0.17%     89.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42368-42375            1      0.00%     89.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42432-42439            1      0.00%     89.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42496-42503           76      0.09%     89.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42624-42631            2      0.00%     89.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42688-42695            1      0.00%     89.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42752-42759          131      0.15%     89.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42816-42823            1      0.00%     89.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42880-42887            2      0.00%     89.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43008-43015          208      0.24%     90.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43264-43271          145      0.17%     90.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43392-43399            1      0.00%     90.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43456-43463            1      0.00%     90.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43520-43527           36      0.04%     90.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43648-43655            2      0.00%     90.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43776-43783          152      0.18%     90.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43840-43847            1      0.00%     90.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44032-44039          340      0.40%     90.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44160-44167            1      0.00%     90.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44224-44231            1      0.00%     90.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44288-44295            8      0.01%     91.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44416-44423            2      0.00%     91.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44544-44551          144      0.17%     91.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44608-44615            2      0.00%     91.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44672-44679            2      0.00%     91.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44800-44807           94      0.11%     91.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45056-45063          328      0.38%     91.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45184-45191            3      0.00%     91.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45312-45319           12      0.01%     91.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45376-45383            1      0.00%     91.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45568-45575          141      0.16%     91.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45632-45639            1      0.00%     91.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45696-45703            1      0.00%     91.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45760-45767            1      0.00%     91.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45824-45831           11      0.01%     91.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45952-45959            1      0.00%     91.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46080-46087          393      0.46%     92.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46272-46279            1      0.00%     92.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46336-46343           91      0.11%     92.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46464-46471            1      0.00%     92.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46528-46535            1      0.00%     92.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46592-46599            4      0.00%     92.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46720-46727            2      0.00%     92.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46848-46855          211      0.25%     92.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47040-47047            2      0.00%     92.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47104-47111          416      0.48%     93.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47168-47175            1      0.00%     93.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47232-47239            1      0.00%     93.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47296-47303            1      0.00%     93.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47360-47367            4      0.00%     93.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47488-47495            2      0.00%     93.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47552-47559            1      0.00%     93.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47616-47623           32      0.04%     93.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47744-47751            1      0.00%     93.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47808-47815            2      0.00%     93.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47872-47879          141      0.16%     93.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47936-47943            1      0.00%     93.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48128-48135          335      0.39%     93.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48192-48199            1      0.00%     93.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48384-48391           74      0.09%     93.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48512-48519            1      0.00%     93.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48640-48647            4      0.00%     93.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48768-48775           71      0.08%     93.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48896-48903          140      0.16%     94.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48960-48967            4      0.00%     94.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::49024-49031            2      0.00%     94.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::49088-49095            1      0.00%     94.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::49152-49159         5017      5.83%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::49280-49287            1      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::49408-49415            1      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::49600-49607            1      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::49792-49799            1      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::50240-50247            1      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::50304-50311            3      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::50368-50375            1      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::50432-50439            2      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::50560-50567            2      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::50624-50631            1      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::50688-50695            4      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::50752-50759            1      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::50880-50887            2      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::51008-51015            3      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::51072-51079            1      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::51136-51143            1      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::51200-51207            1      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::51328-51335            2      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::51392-51399            1      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::51456-51463            2      0.00%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::51520-51527            1      0.00%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::51968-51975            2      0.00%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          85983                       # Bytes accessed per row activation
-system.physmem.totQLat                   365185132750                       # Total ticks spent queuing
-system.physmem.totMemAccLat              457949856500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                  75297645000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                 17467078750                       # Total ticks spent accessing banks
-system.physmem.avgQLat                       24249.44                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                     1159.87                       # Average bank access latency per DRAM burst
+system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     1817                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     1873                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     2182                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     4347                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     5586                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     5682                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     5693                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     5776                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     5810                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     5802                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     6376                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     6039                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     5895                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     6697                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     6177                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     5729                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     5693                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     5648                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     2143                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      730                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      681                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      684                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      666                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      587                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      630                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      595                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      576                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      583                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      547                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      567                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      540                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      538                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      536                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      533                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      534                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      533                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      534                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      533                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      544                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       949853                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean     1012.832967                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     998.129194                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev      95.600820                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127           4614      0.49%      0.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         3555      0.37%      0.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         1868      0.20%      1.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         1270      0.13%      1.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639          998      0.11%      1.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          697      0.07%      1.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          628      0.07%      1.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          802      0.08%      1.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151       935421     98.48%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         949853                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5541                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean      2709.372676                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev    121858.968991                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-524287         5537     99.93%     99.93% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::524288-1.04858e+06            2      0.04%     99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2.09715e+06-2.62144e+06            1      0.02%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06            1      0.02%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            5541                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5541                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        19.245082                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.302826                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        7.619957                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               3691     66.61%     66.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 16      0.29%     66.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                178      3.21%     70.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19               1008     18.19%     88.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                 44      0.79%     89.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 25      0.45%     89.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 20      0.36%     89.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 16      0.29%     90.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                  5      0.09%     90.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                  2      0.04%     90.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                  1      0.02%     90.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32                  1      0.02%     90.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::34                  1      0.02%     90.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::39                  2      0.04%     90.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40                  1      0.02%     90.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::41                143      2.58%     93.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::42                305      5.50%     98.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::43                 21      0.38%     98.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44                 14      0.25%     99.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::45                 20      0.36%     99.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::46                 15      0.27%     99.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::47                  5      0.09%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48                  3      0.05%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::49                  1      0.02%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::50                  3      0.05%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5541                       # Writes before turning the bus around for reads
+system.physmem.totQLat                   571195583500                       # Total ticks spent queuing
+system.physmem.totMemAccLat              674382869750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                  75063215000                       # Total ticks spent in databus transfers
+system.physmem.totBankLat                 28124071250                       # Total ticks spent accessing banks
+system.physmem.avgQLat                       38047.64                       # Average queueing delay per DRAM burst
+system.physmem.avgBankLat                     1873.36                       # Average bank access latency per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  30409.31                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         381.54                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           2.73                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  44921.00                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         380.34                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           2.70                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                       51.24                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        2.69                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           3.00                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       2.98                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           2.99                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       2.97                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         0.18                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        14.56                       # Average write queue length when enqueuing
-system.physmem.readRowHits                   14988012                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     93348                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   99.53                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  86.58                       # Row buffer hit rate for writes
-system.physmem.avgGap                       158776.13                       # Average gap between requests
-system.physmem.pageHitRate                      99.43                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               2.53                       # Percentage of time for which DRAM has all the banks in precharge state
+system.physmem.avgRdQLen                         7.11                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        26.53                       # Average write queue length when enqueuing
+system.physmem.readRowHits                   14041195                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     91389                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   93.53                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  85.68                       # Row buffer hit rate for writes
+system.physmem.avgGap                       158778.41                       # Average gap between requests
+system.physmem.pageHitRate                      93.47                       # Row buffer hit rate, read and write combined
+system.physmem.prechargeAllPercent               4.34                       # Percentage of time for which DRAM has all the banks in precharge state
 system.realview.nvmem.bytes_read::cpu.inst           64                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total            64                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_inst_read::cpu.inst           64                       # Number of instructions bytes read from this memory
@@ -769,58 +297,58 @@ system.realview.nvmem.bw_inst_read::cpu.inst           25
 system.realview.nvmem.bw_inst_read::total           25                       # Instruction read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu.inst           25                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total              25                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                     54878485                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq            16149469                       # Transaction distribution
-system.membus.trans_dist::ReadResp           16149469                       # Transaction distribution
+system.membus.throughput                     54878638                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq            16149508                       # Transaction distribution
+system.membus.trans_dist::ReadResp           16149508                       # Transaction distribution
 system.membus.trans_dist::WriteReq             763349                       # Transaction distribution
 system.membus.trans_dist::WriteResp            763349                       # Transaction distribution
-system.membus.trans_dist::Writeback             59118                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4690                       # Transaction distribution
+system.membus.trans_dist::Writeback             59141                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4671                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              3                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            4693                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            131452                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           131452                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            4674                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            131433                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           131433                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave      2383044                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port            2                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         3760                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio            2                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1885820                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      4272628                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1885845                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      4272653                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     29884416                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total     29884416                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total               34157044                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total               34157069                       # Packet count per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave      2390454                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port           64                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         7520                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio            4                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16694304                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     19092346                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16697056                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     19095098                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port    119537664                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.iocache.mem_side::total    119537664                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total           138630010                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus              138630010                       # Total data (bytes)
+system.membus.tot_pkt_size::total           138632762                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus              138632762                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy          1486866000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy          1487078000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy                1000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             3686500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             3653000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer4.occupancy                1500                       # Layer occupancy (ticks)
 system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer6.occupancy         17361359500                       # Layer occupancy (ticks)
+system.membus.reqLayer6.occupancy         17362845500                       # Layer occupancy (ticks)
 system.membus.reqLayer6.utilization               0.7                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         4731205438                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         4737809043                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
-system.membus.respLayer2.occupancy        33737720957                       # Layer occupancy (ticks)
-system.membus.respLayer2.utilization              1.3                       # Layer utilization (%)
+system.membus.respLayer2.occupancy        37210156152                       # Layer occupancy (ticks)
+system.membus.respLayer2.utilization              1.5                       # Layer utilization (%)
 system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
 system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
-system.iobus.throughput                      48266825                       # Throughput (bytes/s)
+system.iobus.throughput                      48266001                       # Throughput (bytes/s)
 system.iobus.trans_dist::ReadReq             16125556                       # Transaction distribution
 system.iobus.trans_dist::ReadResp            16125556                       # Transaction distribution
 system.iobus.trans_dist::WriteReq                8174                       # Transaction distribution
@@ -930,18 +458,18 @@ system.iobus.reqLayer25.occupancy         14942208000                       # La
 system.iobus.reqLayer25.utilization               0.6                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy          2374870000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.1                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy         40922322043                       # Layer occupancy (ticks)
-system.iobus.respLayer1.utilization               1.6                       # Layer utilization (%)
+system.iobus.respLayer1.occupancy         37245686848                       # Layer occupancy (ticks)
+system.iobus.respLayer1.utilization               1.5                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                14743416                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          11827380                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            704687                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              9504018                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 7655579                       # Number of BTB hits
+system.cpu.branchPred.lookups                14755327                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          11837490                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            706705                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              9530563                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 7665782                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             80.550973                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1397368                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              72480                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             80.433674                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1400618                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              72971                       # Number of incorrect RAS predictions.
 system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -965,9 +493,9 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.misses            0
 system.cpu.checker.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu.checker.dtb.inst_hits                    0                       # ITB inst hits
 system.cpu.checker.dtb.inst_misses                  0                       # ITB inst misses
-system.cpu.checker.dtb.read_hits             14987484                       # DTB read hits
-system.cpu.checker.dtb.read_misses               7307                       # DTB read misses
-system.cpu.checker.dtb.write_hits            11227618                       # DTB write hits
+system.cpu.checker.dtb.read_hits             14987589                       # DTB read hits
+system.cpu.checker.dtb.read_misses               7306                       # DTB read misses
+system.cpu.checker.dtb.write_hits            11227681                       # DTB write hits
 system.cpu.checker.dtb.write_misses              2191                       # DTB write misses
 system.cpu.checker.dtb.flush_tlb                    4                       # Number of times complete TLB was flushed
 system.cpu.checker.dtb.flush_tlb_mva                0                       # Number of times TLB was flushed by MVA
@@ -978,12 +506,12 @@ system.cpu.checker.dtb.align_faults                 0                       # Nu
 system.cpu.checker.dtb.prefetch_faults            180                       # Number of TLB faults due to prefetch
 system.cpu.checker.dtb.domain_faults                0                       # Number of TLB faults due to domain restrictions
 system.cpu.checker.dtb.perms_faults               452                       # Number of TLB faults due to permissions restrictions
-system.cpu.checker.dtb.read_accesses         14994791                       # DTB read accesses
-system.cpu.checker.dtb.write_accesses        11229809                       # DTB write accesses
+system.cpu.checker.dtb.read_accesses         14994895                       # DTB read accesses
+system.cpu.checker.dtb.write_accesses        11229872                       # DTB write accesses
 system.cpu.checker.dtb.inst_accesses                0                       # ITB inst accesses
-system.cpu.checker.dtb.hits                  26215102                       # DTB hits
-system.cpu.checker.dtb.misses                    9498                       # DTB misses
-system.cpu.checker.dtb.accesses              26224600                       # DTB accesses
+system.cpu.checker.dtb.hits                  26215270                       # DTB hits
+system.cpu.checker.dtb.misses                    9497                       # DTB misses
+system.cpu.checker.dtb.accesses              26224767                       # DTB accesses
 system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.checker.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1005,7 +533,7 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.checker.istage2_mmu.stage2_tlb.hits            0                       # DTB hits
 system.cpu.checker.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.checker.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.checker.itb.inst_hits             61483125                       # ITB inst hits
+system.cpu.checker.itb.inst_hits             61483612                       # ITB inst hits
 system.cpu.checker.itb.inst_misses               4473                       # ITB inst misses
 system.cpu.checker.itb.read_hits                    0                       # DTB read hits
 system.cpu.checker.itb.read_misses                  0                       # DTB read misses
@@ -1022,11 +550,11 @@ system.cpu.checker.itb.domain_faults                0                       # Nu
 system.cpu.checker.itb.perms_faults                 0                       # Number of TLB faults due to permissions restrictions
 system.cpu.checker.itb.read_accesses                0                       # DTB read accesses
 system.cpu.checker.itb.write_accesses               0                       # DTB write accesses
-system.cpu.checker.itb.inst_accesses         61487598                       # ITB inst accesses
-system.cpu.checker.itb.hits                  61483125                       # DTB hits
+system.cpu.checker.itb.inst_accesses         61488085                       # ITB inst accesses
+system.cpu.checker.itb.hits                  61483612                       # DTB hits
 system.cpu.checker.itb.misses                    4473                       # DTB misses
-system.cpu.checker.itb.accesses              61487598                       # DTB accesses
-system.cpu.checker.numCycles                 77886440                       # number of cpu cycles simulated
+system.cpu.checker.itb.accesses              61488085                       # DTB accesses
+system.cpu.checker.numCycles                 77887007                       # number of cpu cycles simulated
 system.cpu.checker.numWorkItemsStarted              0                       # number of work items this cpu started
 system.cpu.checker.numWorkItemsCompleted            0                       # number of work items this cpu completed
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
@@ -1052,25 +580,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DT
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     51180405                       # DTB read hits
-system.cpu.dtb.read_misses                      65067                       # DTB read misses
-system.cpu.dtb.write_hits                    11700451                       # DTB write hits
-system.cpu.dtb.write_misses                     15748                       # DTB write misses
+system.cpu.dtb.read_hits                     51187284                       # DTB read hits
+system.cpu.dtb.read_misses                      65383                       # DTB read misses
+system.cpu.dtb.write_hits                    11703682                       # DTB write hits
+system.cpu.dtb.write_misses                     15916                       # DTB write misses
 system.cpu.dtb.flush_tlb                            4                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
 system.cpu.dtb.flush_tlb_mva_asid                2878                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                     126                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                     3477                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                      2401                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                    399                       # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries                     3484                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                      2464                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                    408                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                      1377                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 51245472                       # DTB read accesses
-system.cpu.dtb.write_accesses                11716199                       # DTB write accesses
+system.cpu.dtb.perms_faults                      1363                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                 51252667                       # DTB read accesses
+system.cpu.dtb.write_accesses                11719598                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          62880856                       # DTB hits
-system.cpu.dtb.misses                           80815                       # DTB misses
-system.cpu.dtb.accesses                      62961671                       # DTB accesses
+system.cpu.dtb.hits                          62890966                       # DTB hits
+system.cpu.dtb.misses                           81299                       # DTB misses
+system.cpu.dtb.accesses                      62972265                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1092,8 +620,8 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.inst_hits                     11521970                       # ITB inst hits
-system.cpu.itb.inst_misses                      11115                       # ITB inst misses
+system.cpu.itb.inst_hits                     11527099                       # ITB inst hits
+system.cpu.itb.inst_misses                      11249                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
@@ -1102,114 +630,114 @@ system.cpu.itb.flush_tlb                            4                       # Nu
 system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
 system.cpu.itb.flush_tlb_mva_asid                2878                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.itb.flush_tlb_asid                     126                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                     2502                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries                     2504                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                      2960                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                      2978                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                 11533085                       # ITB inst accesses
-system.cpu.itb.hits                          11521970                       # DTB hits
-system.cpu.itb.misses                           11115                       # DTB misses
-system.cpu.itb.accesses                      11533085                       # DTB accesses
-system.cpu.numCycles                        477047952                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                 11538348                       # ITB inst accesses
+system.cpu.itb.hits                          11527099                       # DTB hits
+system.cpu.itb.misses                           11249                       # DTB misses
+system.cpu.itb.accesses                      11538348                       # DTB accesses
+system.cpu.numCycles                        477119451                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           29756603                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                       90277136                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    14743416                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches            9052947                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      20141800                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 4650225                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                     121200                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles               98195863                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                 2631                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles         87675                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles      2688966                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          386                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  11518528                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                709932                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                    5147                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          154198551                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.729959                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.081572                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           29745347                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                       90343663                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    14755327                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            9066400                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      20160515                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 4659374                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                     121718                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles               98274067                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                 2638                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles         88444                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles      2690508                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          430                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  11523637                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                709778                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                    5230                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          154294046                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.730147                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.081756                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                134072201     86.95%     86.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  1305405      0.85%     87.79% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  1710070      1.11%     88.90% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  2294026      1.49%     90.39% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  2104673      1.36%     91.76% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  1102818      0.72%     92.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  2555300      1.66%     94.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                   746086      0.48%     94.61% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                  8307972      5.39%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                134149007     86.94%     86.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  1305162      0.85%     87.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  1712027      1.11%     88.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  2298089      1.49%     90.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  2109453      1.37%     91.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  1103374      0.72%     92.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  2555030      1.66%     94.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                   746204      0.48%     94.61% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                  8315700      5.39%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            154198551                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.030906                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.189241                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 31769851                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             100064901                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  18067338                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               1262749                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                3033712                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              1957542                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                172175                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              107250920                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                570386                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                3033712                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 33504513                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                38619180                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       55176666                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  17578446                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               6286034                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              102244327                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                   450                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 980082                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               4063460                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents              782                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           106315700                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             473686161                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        432563323                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups             10440                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps              78727135                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 27588564                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts            1170552                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts        1076872                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  12591466                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             19711121                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            13300191                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1936389                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          2436828                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                   95079446                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             1983827                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 122895781                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            165904                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        18895197                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     47144933                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         501515                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     154198551                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.796997                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.515893                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            154294046                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.030926                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.189352                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 31777956                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             100129696                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  18080387                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               1265250                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                3040757                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              1958128                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                172070                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              107328179                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                570705                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                3040757                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 33516419                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                38693091                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       55142047                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  17591419                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               6310313                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              102323009                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                   472                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                1000039                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               4066050                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents              733                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           106393961                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             474042454                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        432890289                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups             10421                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps              78727775                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 27666185                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            1171025                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts        1077190                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  12642564                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             19725934                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            13308899                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1965192                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          2472766                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                   95138203                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             1987496                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 122932074                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            165549                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        18954995                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     47273204                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         505173                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     154294046                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.796739                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.515436                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           109876529     71.26%     71.26% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            14361592      9.31%     80.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             6875815      4.46%     85.03% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             5666847      3.68%     88.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            12323021      7.99%     96.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             2802995      1.82%     98.51% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             1694666      1.10%     99.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              469725      0.30%     99.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              127361      0.08%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           109928517     71.25%     71.25% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            14405522      9.34%     80.58% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             6874407      4.46%     85.04% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             5677816      3.68%     88.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            12311103      7.98%     96.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             2805861      1.82%     98.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             1693952      1.10%     99.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              468083      0.30%     99.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              128785      0.08%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       154198551                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       154294046                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                   61834      0.70%      0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      3      0.00%      0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                   61713      0.70%      0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      4      0.00%      0.70% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.70% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.70% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.70% # attempts to use FU when none available
@@ -1237,437 +765,436 @@ system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      0.70% # at
 system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      0.70% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      0.70% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                8368136     94.62%     95.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                413820      4.68%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                8365366     94.65%     95.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                411034      4.65%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass             28518      0.02%      0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              57946622     47.15%     47.17% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                93414      0.08%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                  24      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc              17      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc           2113      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc           19      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             52506141     42.72%     89.98% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            12318913     10.02%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              57971139     47.16%     47.18% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                93360      0.08%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                  25      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc              18      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc           2113      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc           19      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             52513425     42.72%     89.98% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            12323457     10.02%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              122895781                       # Type of FU issued
-system.cpu.iq.rate                           0.257617                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     8843793                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.071962                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          409057037                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         115975062                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     85458771                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads               23247                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes              12478                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses        10297                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              131698673                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                   12383                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads           624051                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              122932074                       # Type of FU issued
+system.cpu.iq.rate                           0.257655                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     8838117                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.071894                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          409219406                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         116097301                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     85490758                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads               23382                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes              12446                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses        10288                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              131729199                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                   12474                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads           624027                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      4056444                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         6518                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        30236                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      1568197                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      4071144                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         6793                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        30196                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      1576838                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads     34108054                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        680529                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads     34107946                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        680806                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                3033712                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                30168583                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                433803                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts            97285878                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            203457                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              19711121                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             13300191                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            1411588                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 113159                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                  3352                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          30236                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         349021                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       270487                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               619508                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             120819447                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              51867420                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           2076334                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                3040757                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                30225758                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                434257                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts            97346977                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            205962                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              19725934                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             13308899                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            1415361                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 113324                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                  3429                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          30196                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         351437                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       270055                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               621492                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             120854906                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              51874598                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           2077168                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                        222605                       # number of nop insts executed
-system.cpu.iew.exec_refs                     64079545                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 11817660                       # Number of branches executed
-system.cpu.iew.exec_stores                   12212125                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.253265                       # Inst execution rate
-system.cpu.iew.wb_sent                      119878750                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      85469068                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  47006672                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  87538881                       # num instructions consuming a value
+system.cpu.iew.exec_nop                        221278                       # number of nop insts executed
+system.cpu.iew.exec_refs                     64090111                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 11821235                       # Number of branches executed
+system.cpu.iew.exec_stores                   12215513                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.253301                       # Inst execution rate
+system.cpu.iew.wb_sent                      119911072                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      85501046                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  47029089                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  87607932                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.179162                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.536980                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.179203                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.536813                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        18642428                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls         1482312                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            534972                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    151164839                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.514346                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.491788                       # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts        18687715                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         1482323                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            537083                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    151253289                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.514049                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.489960                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    122735782     81.19%     81.19% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     14630083      9.68%     90.87% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      3890528      2.57%     93.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      2132680      1.41%     94.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1607271      1.06%     95.92% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5       973341      0.64%     96.56% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      1599818      1.06%     97.62% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       715537      0.47%     98.09% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      2879799      1.91%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    122784132     81.18%     81.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     14644365      9.68%     90.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      3917692      2.59%     93.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      2132798      1.41%     94.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1620432      1.07%     95.93% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5       975760      0.65%     96.58% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      1598249      1.06%     97.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       715459      0.47%     98.11% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      2864402      1.89%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    151164839                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts             60459531                       # Number of instructions committed
-system.cpu.commit.committedOps               77751027                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    151253289                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts             60460018                       # Number of instructions committed
+system.cpu.commit.committedOps               77751594                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       27386671                       # Number of memory references committed
-system.cpu.commit.loads                      15654677                       # Number of loads committed
-system.cpu.commit.membars                      403573                       # Number of memory barriers committed
-system.cpu.commit.branches                   10306328                       # Number of branches committed
+system.cpu.commit.refs                       27386851                       # Number of memory references committed
+system.cpu.commit.loads                      15654790                       # Number of loads committed
+system.cpu.commit.membars                      403577                       # Number of memory barriers committed
+system.cpu.commit.branches                   10306380                       # Number of branches committed
 system.cpu.commit.fp_insts                      10212                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                  69191102                       # Number of committed integer instructions.
-system.cpu.commit.function_calls               991248                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events               2879799                       # number cycles where commit BW limit reached
+system.cpu.commit.int_insts                  69191623                       # Number of committed integer instructions.
+system.cpu.commit.function_calls               991253                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events               2864402                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    242830080                       # The number of ROB reads
-system.cpu.rob.rob_writes                   195907164                       # The number of ROB writes
-system.cpu.timesIdled                         1776346                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                       322849401                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   4575122538                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                    60309150                       # Number of Instructions Simulated
-system.cpu.committedOps                      77600646                       # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total              60309150                       # Number of Instructions Simulated
-system.cpu.cpi                               7.910043                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         7.910043                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.126422                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.126422                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                548535748                       # number of integer regfile reads
-system.cpu.int_regfile_writes                87515633                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                      8349                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                     2926                       # number of floating regfile writes
-system.cpu.misc_regfile_reads               268179441                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                1173225                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput                58877700                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq        2658609                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2658608                       # Transaction distribution
+system.cpu.rob.rob_reads                    242979782                       # The number of ROB reads
+system.cpu.rob.rob_writes                   196005989                       # The number of ROB writes
+system.cpu.timesIdled                         1777234                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                       322825405                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   4575137230                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                    60309637                       # Number of Instructions Simulated
+system.cpu.committedOps                      77601213                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total              60309637                       # Number of Instructions Simulated
+system.cpu.cpi                               7.911164                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         7.911164                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.126404                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.126404                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                548698002                       # number of integer regfile reads
+system.cpu.int_regfile_writes                87552826                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                      8408                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                     2932                       # number of floating regfile writes
+system.cpu.misc_regfile_reads               268236665                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                1173235                       # number of misc regfile writes
+system.cpu.toL2Bus.throughput                58867266                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq        2659080                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2659079                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq        763349                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp       763349                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       607534                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2957                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq           12                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2969                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       246101                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       246101                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1963183                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      5795840                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        30059                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       127673                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           7916755                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     62784704                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     85494778                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        40536                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       211580                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      148531598                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus         148531598                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus       200936                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy     3128807668                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.trans_dist::Writeback       607635                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2959                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq           16                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2975                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       246069                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       246069                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1961962                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      5796085                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        30498                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       129069                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           7917614                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     62744960                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     85505466                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        40992                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       214572                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      148505990                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         148505990                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus       202724                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy     3129185667                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    1475592252                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    1474638965                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2550083892                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    2549207556                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy      19930988                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy      20255489                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy      74876053                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy      75530794                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu.icache.tags.replacements            981505                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.575357                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            10456797                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            982017                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             10.648285                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle        6907075250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.575357                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.999171                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.999171                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements            980897                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.570903                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            10462766                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            981409                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             10.660964                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle        6958078250                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.570903                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.999162                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.999162                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          132                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          219                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          160                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          133                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          217                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          161                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          12500448                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         12500448                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     10456797                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        10456797                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      10456797                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         10456797                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     10456797                       # number of overall hits
-system.cpu.icache.overall_hits::total        10456797                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1061602                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1061602                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1061602                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1061602                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1061602                       # number of overall misses
-system.cpu.icache.overall_misses::total       1061602                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  14273209676                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  14273209676                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  14273209676                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  14273209676                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  14273209676                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  14273209676                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     11518399                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     11518399                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     11518399                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     11518399                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     11518399                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     11518399                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.092166                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.092166                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.092166                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.092166                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.092166                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.092166                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13444.972481                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13444.972481                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13444.972481                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13444.972481                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13444.972481                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13444.972481                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         6382                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses          12504958                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         12504958                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     10462766                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        10462766                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      10462766                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         10462766                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     10462766                       # number of overall hits
+system.cpu.icache.overall_hits::total        10462766                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1060743                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1060743                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1060743                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1060743                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1060743                       # number of overall misses
+system.cpu.icache.overall_misses::total       1060743                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  14268635888                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  14268635888                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  14268635888                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  14268635888                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  14268635888                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  14268635888                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     11523509                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     11523509                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     11523509                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     11523509                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     11523509                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     11523509                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.092050                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.092050                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.092050                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.092050                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.092050                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.092050                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13451.548479                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13451.548479                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13451.548479                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13451.548479                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13451.548479                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13451.548479                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         7798                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               332                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               344                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    19.222892                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    22.668605                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        79552                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        79552                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        79552                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        79552                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        79552                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        79552                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       982050                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       982050                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       982050                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       982050                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       982050                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       982050                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  11590658741                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  11590658741                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  11590658741                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  11590658741                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  11590658741                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  11590658741                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst      8870000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::total      8870000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst      8870000                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::total      8870000                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.085259                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.085259                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.085259                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.085259                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.085259                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.085259                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11802.513865                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11802.513865                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11802.513865                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11802.513865                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11802.513865                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11802.513865                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        79293                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        79293                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        79293                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        79293                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        79293                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        79293                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       981450                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       981450                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       981450                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       981450                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       981450                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       981450                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  11587546773                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  11587546773                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  11587546773                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  11587546773                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  11587546773                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  11587546773                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst      9345000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::total      9345000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst      9345000                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::total      9345000                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.085169                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.085169                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.085169                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.085169                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.085169                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.085169                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11806.558432                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11806.558432                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11806.558432                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11806.558432                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11806.558432                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11806.558432                       # average overall mshr miss latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements            64371                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        51367.805522                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1886658                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           129763                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            14.539260                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle     2490785434500                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 36937.207333                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    28.555690                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.000373                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  8169.178837                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  6232.863288                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.563617                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000436                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.replacements            64391                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        51374.630920                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            1887139                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           129786                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            14.540390                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle     2490832751500                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 36918.668159                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    31.305745                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.000374                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  8179.061871                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  6245.594773                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.563334                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000478                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.124652                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.095106                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.783811                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1023           21                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        65371                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4           20                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           38                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          355                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3048                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6928                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55002                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000320                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.997482                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         18785683                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        18785683                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        52852                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker        10132                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst       968531                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data       386919                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1418434                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       607534                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       607534                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data           40                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total           40                       # number of UpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::cpu.data            9                       # number of SCUpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::total            9                       # number of SCUpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       112876                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       112876                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker        52852                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker        10132                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst       968531                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       499795                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         1531310                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker        52852                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker        10132                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst       968531                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       499795                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        1531310                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           43                       # number of ReadReq misses
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.124803                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.095300                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.783915                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1023           23                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        65372                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::4           23                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           39                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          352                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3052                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6933                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54996                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000351                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.997498                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         18788998                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        18788998                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        53598                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker        10246                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.inst       967912                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data       386978                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        1418734                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       607635                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       607635                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data           46                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total           46                       # number of UpgradeReq hits
+system.cpu.l2cache.SCUpgradeReq_hits::cpu.data           13                       # number of SCUpgradeReq hits
+system.cpu.l2cache.SCUpgradeReq_hits::total           13                       # number of SCUpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       112878                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       112878                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker        53598                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.itb.walker        10246                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst       967912                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       499856                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         1531612                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.dtb.walker        53598                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.itb.walker        10246                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst       967912                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       499856                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        1531612                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           45                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            2                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.inst        12359                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data        10705                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        23109                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data         2917                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total         2917                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.inst        12357                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data        10744                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        23148                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data         2913                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total         2913                       # number of UpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            3                       # number of SCUpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::total            3                       # number of SCUpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       133225                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       133225                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker           43                       # number of demand (read+write) misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       133191                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       133191                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.dtb.walker           45                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.itb.walker            2                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst        12359                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       143930                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        156334                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker           43                       # number of overall misses
+system.cpu.l2cache.demand_misses::cpu.inst        12357                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       143935                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        156339                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.dtb.walker           45                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.itb.walker            2                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst        12359                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       143930                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       156334                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      3808750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       158000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    901494000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data    813359500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total   1718820250                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       465980                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total       465980                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   9840326977                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   9840326977                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      3808750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       158000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    901494000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  10653686477                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  11559147227                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      3808750                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       158000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    901494000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  10653686477                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  11559147227                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        52895                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker        10134                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.inst       980890                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data       397624                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      1441543                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       607534                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       607534                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2957                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total         2957                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data           12                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::total           12                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       246101                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       246101                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker        52895                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker        10134                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst       980890                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       643725                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      1687644                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker        52895                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker        10134                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst       980890                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       643725                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      1687644                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000813                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000197                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.012600                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.026922                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.016031                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.986473                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.986473                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.250000                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::total     0.250000                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.541343                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.541343                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000813                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000197                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.012600                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.223589                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.092634                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000813                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000197                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.012600                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.223589                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.092634                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 88575.581395                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        79000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72942.309248                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75979.402149                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 74378.824268                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data   159.746315                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   159.746315                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73862.465581                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73862.465581                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 88575.581395                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        79000                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72942.309248                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74019.915772                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 73938.792758                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 88575.581395                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        79000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72942.309248                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74019.915772                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 73938.792758                       # average overall miss latency
+system.cpu.l2cache.overall_misses::cpu.inst        12357                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       143935                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       156339                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      3974500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       412000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    905251250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data    810262998                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   1719900748                       # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       510978                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total       510978                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   9827066492                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   9827066492                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      3974500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       412000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    905251250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  10637329490                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  11546967240                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      3974500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       412000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    905251250                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  10637329490                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  11546967240                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        53643                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker        10248                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.inst       980269                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data       397722                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      1441882                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       607635                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       607635                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2959                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total         2959                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data           16                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu.l2cache.SCUpgradeReq_accesses::total           16                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       246069                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       246069                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker        53643                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.itb.walker        10248                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst       980269                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       643791                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      1687951                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker        53643                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.itb.walker        10248                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst       980269                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       643791                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      1687951                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000839                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000195                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.012606                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.027014                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.016054                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.984454                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.984454                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.187500                       # miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_miss_rate::total     0.187500                       # miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.541275                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.541275                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000839                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000195                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.012606                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.223574                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.092621                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000839                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000195                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.012606                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.223574                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.092621                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 88322.222222                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker       206000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73258.173505                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75415.394453                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 74300.187835                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data   175.412976                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   175.412976                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73781.760720                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73781.760720                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 88322.222222                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker       206000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73258.173505                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73903.702991                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 73858.520523                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 88322.222222                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker       206000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73258.173505                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73903.702991                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 73858.520523                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1676,109 +1203,109 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        59118                       # number of writebacks
-system.cpu.l2cache.writebacks::total            59118                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           13                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           67                       # number of ReadReq MSHR hits
+system.cpu.l2cache.writebacks::writebacks        59141                       # number of writebacks
+system.cpu.l2cache.writebacks::total            59141                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           15                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           65                       # number of ReadReq MSHR hits
 system.cpu.l2cache.ReadReq_mshr_hits::total           80                       # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst           13                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data           67                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst           15                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data           65                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::total           80                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst           13                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data           67                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst           15                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data           65                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total           80                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           43                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           45                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            2                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        12346                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        10638                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        23029                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2917                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total         2917                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        12342                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        10679                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        23068                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2913                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total         2913                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            3                       # number of SCUpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            3                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       133225                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       133225                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           43                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       133191                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       133191                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           45                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            2                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        12346                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       143863                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       156254                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           43                       # number of overall MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        12342                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       143870                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       156259                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           45                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            2                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        12346                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       143863                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       156254                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      3278250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       133500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    745356250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    676470750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1425238750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     29172917                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     29172917                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        12342                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       143870                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       156259                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      3417500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       387500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    749197750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    673040498                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1426043248                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     29132913                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     29132913                       # number of UpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data        30003                       # number of SCUpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total        30003                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   8180809023                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8180809023                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      3278250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       133500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    745356250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   8857279773                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   9606047773                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      3278250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       133500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    745356250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8857279773                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   9606047773                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst      6336999                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166942244250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166948581249                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data  17449661616                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total  17449661616                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst      6336999                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184391905866                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184398242865                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000813                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000197                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.012587                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.026754                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.015975                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.986473                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.986473                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.250000                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.250000                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.541343                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.541343                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000813                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000197                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.012587                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.223485                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.092587                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000813                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000197                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.012587                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.223485                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.092587                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 76238.372093                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        66750                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60372.286571                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63590.031021                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61888.868383                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   8170239508                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8170239508                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      3417500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       387500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    749197750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   8843280006                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   9596282756                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      3417500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       387500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    749197750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8843280006                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   9596282756                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst      6814499                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166942562250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166949376749                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data  17458567530                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total  17458567530                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst      6814499                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184401129780                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184407944279                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000839                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000195                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.012590                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.026850                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.015999                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.984454                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.984454                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.187500                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.187500                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.541275                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.541275                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000839                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000195                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.012590                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.223473                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.092573                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000839                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000195                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.012590                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.223473                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.092573                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 75944.444444                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker       193750                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60703.107276                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63024.674408                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61819.110803                       # average ReadReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        10001                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average SCUpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        10001                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61405.960015                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61405.960015                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 76238.372093                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        66750                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60372.286571                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61567.461912                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61477.131933                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 76238.372093                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        66750                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60372.286571                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61567.461912                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61477.131933                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61342.279193                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61342.279193                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 75944.444444                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker       193750                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60703.107276                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61467.157893                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61412.672268                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 75944.444444                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker       193750                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60703.107276                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61467.157893                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61412.672268                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -1788,168 +1315,168 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements            643213                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.993295                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            21506846                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            643725                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             33.409990                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle          42602250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.993295                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.replacements            643279                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.993228                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            21514190                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            643791                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             33.417973                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle          43094250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.993228                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999987                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999987                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          196                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          193                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          299                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           17                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           20                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         101509393                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        101509393                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     13753990                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        13753990                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      7259407                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        7259407                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       242755                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       242755                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       247595                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       247595                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      21013397                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         21013397                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     21013397                       # number of overall hits
-system.cpu.dcache.overall_hits::total        21013397                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       736321                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        736321                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      2962815                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      2962815                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        13522                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        13522                       # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data           12                       # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total           12                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      3699136                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3699136                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      3699136                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3699136                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  10001713308                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  10001713308                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 140180267525                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 140180267525                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    184727500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    184727500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       193503                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total       193503                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 150181980833                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 150181980833                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 150181980833                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 150181980833                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     14490311                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     14490311                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     10222222                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     10222222                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       256277                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       256277                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       247607                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       247607                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     24712533                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     24712533                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     24712533                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     24712533                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.050815                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.050815                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.289841                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.289841                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.052763                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.052763                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000048                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total     0.000048                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.149687                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.149687                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.149687                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.149687                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13583.360121                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 13583.360121                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47313.202993                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 47313.202993                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13661.255731                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13661.255731                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16125.250000                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16125.250000                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 40599.205012                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 40599.205012                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 40599.205012                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 40599.205012                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs        30576                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets        27091                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs              2628                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets             288                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    11.634703                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    94.065972                       # average number of cycles each access was blocked
+system.cpu.dcache.tags.tag_accesses         101537487                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        101537487                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     13760648                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        13760648                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      7259865                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        7259865                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       242998                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       242998                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       247594                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       247594                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      21020513                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         21020513                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     21020513                       # number of overall hits
+system.cpu.dcache.overall_hits::total        21020513                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       736359                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        736359                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      2962417                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      2962417                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        13527                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        13527                       # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data           16                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total           16                       # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data      3698776                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3698776                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      3698776                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3698776                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   9982812336                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   9982812336                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 139744433579                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 139744433579                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    185287000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    185287000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       245503                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total       245503                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 149727245915                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 149727245915                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 149727245915                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 149727245915                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     14497007                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     14497007                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     10222282                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     10222282                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       256525                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       256525                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       247610                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       247610                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     24719289                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     24719289                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     24719289                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     24719289                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.050794                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.050794                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.289800                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.289800                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.052732                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.052732                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000065                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total     0.000065                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.149631                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.149631                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.149631                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.149631                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13556.991000                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 13556.991000                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47172.438444                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 47172.438444                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13697.567827                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13697.567827                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15343.937500                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15343.937500                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 40480.214513                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 40480.214513                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 40480.214513                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 40480.214513                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs        31777                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets        23524                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              2637                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets             274                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    12.050436                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    85.854015                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       607534                       # number of writebacks
-system.cpu.dcache.writebacks::total            607534                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       350801                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       350801                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      2713841                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      2713841                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         1334                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total         1334                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      3064642                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      3064642                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      3064642                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      3064642                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       385520                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       385520                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       248974                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       248974                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        12188                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total        12188                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data           12                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total           12                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       634494                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       634494                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       634494                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       634494                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   4971012627                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   4971012627                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11323926285                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  11323926285                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    145258250                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    145258250                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       169497                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       169497                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  16294938912                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  16294938912                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  16294938912                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  16294938912                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182335926750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182335926750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data  26847444003                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  26847444003                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209183370753                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 209183370753                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.026605                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.026605                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.024356                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.024356                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.047558                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.047558                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000048                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000048                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.025675                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.025675                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.025675                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.025675                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12894.305424                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12894.305424                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45482.364765                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45482.364765                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11918.136692                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11918.136692                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14124.750000                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14124.750000                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25681.785662                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 25681.785662                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25681.785662                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 25681.785662                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks       607635                       # number of writebacks
+system.cpu.dcache.writebacks::total            607635                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       350728                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       350728                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      2713476                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      2713476                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         1349                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total         1349                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      3064204                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      3064204                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      3064204                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      3064204                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       385631                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       385631                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       248941                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       248941                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        12178                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total        12178                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data           16                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total           16                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       634572                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       634572                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       634572                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       634572                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   4967633608                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   4967633608                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11307381788                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  11307381788                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    145644250                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    145644250                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       213497                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       213497                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  16275015396                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  16275015396                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  16275015396                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  16275015396                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182336207250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182336207250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data  26867769000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  26867769000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209203976250                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 209203976250                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.026601                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.026601                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.024353                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.024353                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.047473                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.047473                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000065                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000065                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.025671                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.025671                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.025671                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.025671                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12881.831616                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12881.831616                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45421.934466                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45421.934466                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11959.619806                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11959.619806                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13343.562500                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13343.562500                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25647.232144                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 25647.232144                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25647.232144                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 25647.232144                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1973,10 +1500,10 @@ system.iocache.avg_blocked_cycles::no_mshrs          nan                       #
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1499139103043                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1499139103043                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1499139103043                       # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1499139103043                       # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1715151162848                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1715151162848                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1715151162848                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1715151162848                       # number of overall MSHR uncacheable cycles
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
index d9a1ddbd2952f85092a155efd1ed4ac59e8a08d2..7d13ac1ec9ed6a458361298978814c821ca00b20 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.605623                       # Number of seconds simulated
-sim_ticks                                2605623216500                       # Number of ticks simulated
-final_tick                               2605623216500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.605649                       # Number of seconds simulated
+sim_ticks                                2605649343000                       # Number of ticks simulated
+final_tick                               2605649343000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  60428                       # Simulator instruction rate (inst/s)
-host_op_rate                                    77810                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2507107577                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 430512                       # Number of bytes of host memory used
-host_seconds                                  1039.29                       # Real time elapsed on the host
-sim_insts                                    62801984                       # Number of instructions simulated
-sim_ops                                      80867321                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  57764                       # Simulator instruction rate (inst/s)
+host_op_rate                                    74374                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2397402056                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 474764                       # Number of bytes of host memory used
+host_seconds                                  1086.86                       # Real time elapsed on the host
+sim_insts                                    62781325                       # Number of instructions simulated
+sim_ops                                      80834116                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::realview.clcd    121110528                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker          832                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker         1024                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           395008                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          4350396                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker         1088                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           426880                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          5253880                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            131538740                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       395008                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       426880                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          821888                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      4261184                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.inst           383680                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          5448188                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker          960                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           438080                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          4125688                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            131508276                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       383680                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       438080                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          821760                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      4229952                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         17000                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data       3012136                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7290320                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7259088                       # Number of bytes written to this memory
 system.physmem.num_reads::realview.clcd      15138816                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker           13                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker           16                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst              6172                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             68049                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker           17                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              6670                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             82120                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total              15301859                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           66581                       # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu0.inst              5995                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             85202                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker           15                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              6845                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             64492                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total              15301383                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           66093                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             4250                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data           753034                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               823865                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd        46480446                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker           319                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               823377                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd        46479979                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker           393                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker            49                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              151598                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             1669618                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker           418                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst              163830                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             2016362                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                50482640                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         151598                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst         163830                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             315429                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1635380                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              147249                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             2090914                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker           368                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst              168127                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             1583363                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                50470443                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         147249                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst         168127                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             315376                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1623377                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.data               6524                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data            1156014                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2797918                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1635380                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd       46480446                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker          319                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data            1156002                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2785904                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1623377                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd       46479979                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker          393                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           49                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             151598                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            1676143                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker          418                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst             163830                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            3172376                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               53280558                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                      15301859                       # Number of read requests accepted
-system.physmem.writeReqs                       823865                       # Number of write requests accepted
-system.physmem.readBursts                    15301859                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     823865                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                976840512                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                   2478464                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7393984                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 131538740                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7290320                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                    38726                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                  708315                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          14211                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              956322                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              955904                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              952374                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              952254                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              956762                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              955994                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              951679                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              951390                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              956653                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              956558                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             951325                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             950816                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             956256                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             956091                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             951432                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             951323                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                7131                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                6969                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                7487                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                7380                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7843                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7402                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                7084                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                7084                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7461                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                7519                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               6987                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6657                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7185                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               7089                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7212                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7041                       # Per bank write bursts
+system.physmem.bw_total::cpu0.inst             147249                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            2097438                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker          368                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst             168127                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            2739365                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               53256346                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                      15301383                       # Number of read requests accepted
+system.physmem.writeReqs                       823377                       # Number of write requests accepted
+system.physmem.readBursts                    15301383                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     823377                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                973889408                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                   5399104                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7284800                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 131508276                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7259088                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                    84361                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                  709522                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs          14082                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0              956098                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              950020                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              950090                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              949980                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              956223                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              949119                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              948884                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              948711                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              956337                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              950158                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             948908                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             948900                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             955944                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             949314                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             949393                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             948943                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                7119                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7037                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                7071                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                7168                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7696                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7220                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                7070                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                6913                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7415                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                7415                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               6887                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6788                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7071                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               6872                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7197                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               6886                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2605622062000                       # Total gap between requests
+system.physmem.totGap                    2605648115500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                     109                       # Read request sizes (log2)
 system.physmem.readPktSize::3                15138816                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  162934                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  162458                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                 757284                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  66581                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1184108                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                   1129171                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                   1082709                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                   3674312                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                   2649053                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                   2636381                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                   2643445                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                     56452                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                     60541                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                     21670                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                    21240                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                    21122                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                    20880                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                    20711                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                    20560                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                    20478                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      196                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                       93                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        5                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                        5                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  66093                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1062706                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    998935                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                    950903                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                    959607                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                    945820                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                    946342                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                   2754714                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                   2746120                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                   3637640                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                     38272                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                    34182                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                    34523                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                    32360                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                    30630                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                    22253                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                    21644                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                      254                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                      101                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                        8                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                        6                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::20                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
@@ -161,609 +161,149 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                      5109                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                      5790                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                      5234                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                      5460                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                      5588                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                      5210                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                      5203                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                      5223                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                      5160                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                      5157                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                     5138                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                     5137                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                     5130                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                     5134                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                     5143                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     5144                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     5140                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5173                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5188                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5156                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     5162                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5520                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                      156                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                       71                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                       21                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        91489                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean    10757.948868                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     916.821036                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev   16539.903542                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64-71          25786     28.18%     28.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-135        14910     16.30%     44.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192-199         3164      3.46%     47.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-263         2339      2.56%     50.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320-327         1506      1.65%     52.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-391         1246      1.36%     53.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448-455         1021      1.12%     54.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-519         1185      1.30%     55.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576-583          667      0.73%     56.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-647          658      0.72%     57.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704-711          602      0.66%     58.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-775          572      0.63%     58.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832-839          315      0.34%     58.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-903          283      0.31%     59.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960-967          170      0.19%     59.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1031          580      0.63%     60.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088-1095          115      0.13%     60.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152-1159          145      0.16%     60.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216-1223           84      0.09%     60.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280-1287          210      0.23%     60.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344-1351           59      0.06%     60.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408-1415          551      0.60%     61.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472-1479           52      0.06%     61.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536-1543          273      0.30%     61.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600-1607           29      0.03%     61.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664-1671          104      0.11%     61.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1728-1735           17      0.02%     61.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1792-1799          169      0.18%     62.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856-1863           21      0.02%     62.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1920-1927           56      0.06%     62.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984-1991           21      0.02%     62.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2048-2055          399      0.44%     62.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112-2119            9      0.01%     62.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2176-2183           43      0.05%     62.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2240-2247           10      0.01%     62.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2304-2311           57      0.06%     62.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2368-2375            5      0.01%     62.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2432-2439           24      0.03%     62.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2496-2503           13      0.01%     62.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2560-2567          166      0.18%     63.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2624-2631            7      0.01%     63.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2688-2695           16      0.02%     63.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2752-2759            4      0.00%     63.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2816-2823           30      0.03%     63.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2880-2887            6      0.01%     63.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2944-2951           23      0.03%     63.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3008-3015            4      0.00%     63.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3072-3079          317      0.35%     63.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3136-3143            3      0.00%     63.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3200-3207           20      0.02%     63.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3264-3271           11      0.01%     63.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3328-3335          167      0.18%     63.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3392-3399           13      0.01%     63.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3456-3463           17      0.02%     63.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3520-3527            7      0.01%     63.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3584-3591          159      0.17%     63.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3648-3655            8      0.01%     63.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3712-3719           17      0.02%     63.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3776-3783           11      0.01%     63.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3840-3847          119      0.13%     64.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3904-3911            7      0.01%     64.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3968-3975           21      0.02%     64.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4032-4039            9      0.01%     64.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4096-4103          498      0.54%     64.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4160-4167            8      0.01%     64.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4224-4231           12      0.01%     64.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4288-4295            9      0.01%     64.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4352-4359           21      0.02%     64.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4416-4423           17      0.02%     64.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4480-4487           15      0.02%     64.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4544-4551           10      0.01%     64.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4608-4615           32      0.03%     64.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4672-4679            2      0.00%     64.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4736-4743           10      0.01%     64.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4800-4807            9      0.01%     64.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4864-4871          144      0.16%     64.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4928-4935           10      0.01%     64.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4992-4999           10      0.01%     64.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5056-5063            5      0.01%     64.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5120-5127          298      0.33%     65.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5184-5191            8      0.01%     65.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5248-5255           12      0.01%     65.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5312-5319            6      0.01%     65.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5376-5383           14      0.02%     65.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5440-5447            7      0.01%     65.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5504-5511            8      0.01%     65.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5568-5575            5      0.01%     65.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5632-5639           74      0.08%     65.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5696-5703            2      0.00%     65.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5760-5767           15      0.02%     65.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5824-5831            4      0.00%     65.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5888-5895          253      0.28%     65.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5952-5959            4      0.00%     65.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6016-6023           13      0.01%     65.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6080-6087           13      0.01%     65.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6144-6151          396      0.43%     66.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6208-6215            4      0.00%     66.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6272-6279           10      0.01%     66.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6336-6343            4      0.00%     66.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6400-6407           85      0.09%     66.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6464-6471            5      0.01%     66.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6528-6535            8      0.01%     66.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6592-6599            5      0.01%     66.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6656-6663          103      0.11%     66.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6720-6727            8      0.01%     66.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6784-6791           22      0.02%     66.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6848-6855            2      0.00%     66.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6912-6919           29      0.03%     66.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6976-6983            4      0.00%     66.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7040-7047            7      0.01%     66.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7104-7111            3      0.00%     66.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7168-7175          296      0.32%     66.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7232-7239            3      0.00%     66.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7296-7303            7      0.01%     66.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7360-7367           10      0.01%     66.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7424-7431          167      0.18%     67.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7488-7495            5      0.01%     67.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7552-7559           11      0.01%     67.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7616-7623            5      0.01%     67.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7680-7687           20      0.02%     67.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7744-7751            1      0.00%     67.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7808-7815            5      0.01%     67.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7936-7943           73      0.08%     67.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8000-8007            3      0.00%     67.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8064-8071            9      0.01%     67.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8192-8199          634      0.69%     67.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8320-8327            2      0.00%     67.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8448-8455           75      0.08%     67.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8576-8583            2      0.00%     67.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8704-8711           13      0.01%     68.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8832-8839            1      0.00%     68.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8960-8967          157      0.17%     68.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9024-9031            1      0.00%     68.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9088-9095            2      0.00%     68.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9152-9159            1      0.00%     68.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9216-9223          285      0.31%     68.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9472-9479           15      0.02%     68.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9536-9543            1      0.00%     68.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9600-9607            1      0.00%     68.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9728-9735           93      0.10%     68.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9792-9799            1      0.00%     68.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9856-9863            1      0.00%     68.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9984-9991           77      0.08%     68.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10048-10055            1      0.00%     68.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10112-10119            4      0.00%     68.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10240-10247          396      0.43%     69.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10368-10375            2      0.00%     69.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10432-10439            1      0.00%     69.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10496-10503          200      0.22%     69.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10688-10695            1      0.00%     69.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10752-10759           71      0.08%     69.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10816-10823            1      0.00%     69.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10880-10887            1      0.00%     69.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10944-10951            1      0.00%     69.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11008-11015           10      0.01%     69.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11136-11143            1      0.00%     69.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11264-11271          289      0.32%     69.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11328-11335            1      0.00%     69.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11392-11399            1      0.00%     69.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11520-11527          139      0.15%     69.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11584-11591            1      0.00%     69.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11776-11783           14      0.02%     69.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12032-12039           10      0.01%     69.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12160-12167            5      0.01%     69.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12224-12231            2      0.00%     69.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12288-12295          463      0.51%     70.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12352-12359            1      0.00%     70.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12480-12487            1      0.00%     70.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12544-12551           93      0.10%     70.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12608-12615            1      0.00%     70.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12672-12679            1      0.00%     70.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12800-12807          146      0.16%     70.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12864-12871            1      0.00%     70.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12928-12935            1      0.00%     70.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12992-12999            1      0.00%     70.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13056-13063          146      0.16%     70.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13120-13127            1      0.00%     70.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13184-13191            1      0.00%     70.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13312-13319          294      0.32%     71.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13568-13575           17      0.02%     71.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13632-13639            1      0.00%     71.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13696-13703            1      0.00%     71.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13824-13831          141      0.15%     71.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13952-13959            1      0.00%     71.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14080-14087           14      0.02%     71.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14208-14215            3      0.00%     71.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14336-14343          345      0.38%     71.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14400-14407            1      0.00%     71.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14464-14471            2      0.00%     71.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14528-14535            1      0.00%     71.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14592-14599           78      0.09%     71.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14656-14663            1      0.00%     71.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14720-14727            2      0.00%     71.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14848-14855           78      0.09%     71.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14976-14983            3      0.00%     71.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15104-15111           81      0.09%     72.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15168-15175            1      0.00%     72.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15232-15239            1      0.00%     72.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15296-15303            2      0.00%     72.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15360-15367          392      0.43%     72.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15616-15623           92      0.10%     72.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15808-15815            1      0.00%     72.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15872-15879           13      0.01%     72.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15936-15943            1      0.00%     72.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16000-16007            1      0.00%     72.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16128-16135           74      0.08%     72.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16192-16199            1      0.00%     72.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16256-16263           10      0.01%     72.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16384-16391          676      0.74%     73.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16640-16647           76      0.08%     73.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16896-16903           13      0.01%     73.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16960-16967            2      0.00%     73.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17152-17159           98      0.11%     73.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17216-17223            1      0.00%     73.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17280-17287            2      0.00%     73.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17344-17351            1      0.00%     73.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17408-17415          394      0.43%     74.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17472-17479            4      0.00%     74.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17536-17543            1      0.00%     74.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17600-17607            2      0.00%     74.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17664-17671           80      0.09%     74.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17728-17735            1      0.00%     74.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17792-17799            1      0.00%     74.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17856-17863            1      0.00%     74.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17920-17927           77      0.08%     74.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18112-18119            1      0.00%     74.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18176-18183           83      0.09%     74.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18304-18311            3      0.00%     74.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18432-18439          341      0.37%     74.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18688-18695           14      0.02%     74.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18816-18823            2      0.00%     74.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18944-18951          141      0.15%     74.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19072-19079            1      0.00%     74.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19200-19207           23      0.03%     74.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19328-19335            2      0.00%     74.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19456-19463          287      0.31%     75.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19520-19527            3      0.00%     75.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19584-19591            3      0.00%     75.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19648-19655            1      0.00%     75.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19712-19719          144      0.16%     75.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19776-19783            2      0.00%     75.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19968-19975          144      0.16%     75.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20160-20167            1      0.00%     75.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20224-20231           97      0.11%     75.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20288-20295            1      0.00%     75.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20352-20359            3      0.00%     75.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20480-20487          470      0.51%     76.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20544-20551            1      0.00%     76.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20672-20679            1      0.00%     76.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20736-20743           10      0.01%     76.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20992-20999           16      0.02%     76.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21056-21063            1      0.00%     76.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21120-21127            1      0.00%     76.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21248-21255          142      0.16%     76.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21376-21383            4      0.00%     76.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21440-21447            3      0.00%     76.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21504-21511          283      0.31%     76.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21760-21767            9      0.01%     76.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21824-21831            1      0.00%     76.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21888-21895            1      0.00%     76.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22016-22023           72      0.08%     76.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22144-22151            2      0.00%     76.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22272-22279          194      0.21%     77.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22400-22407            3      0.00%     77.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22464-22471            1      0.00%     77.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22528-22535          387      0.42%     77.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22592-22599            2      0.00%     77.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22656-22663            1      0.00%     77.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22720-22727            2      0.00%     77.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22784-22791           79      0.09%     77.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22848-22855            1      0.00%     77.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22976-22983            2      0.00%     77.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23040-23047           89      0.10%     77.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23104-23111            1      0.00%     77.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23168-23175            2      0.00%     77.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23296-23303           21      0.02%     77.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23424-23431            1      0.00%     77.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23552-23559          286      0.31%     77.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23680-23687            2      0.00%     77.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23808-23815          151      0.17%     78.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24064-24071           13      0.01%     78.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24256-24263            2      0.00%     78.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24320-24327           73      0.08%     78.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24384-24391            1      0.00%     78.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24448-24455            6      0.01%     78.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24576-24583          527      0.58%     78.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24704-24711            2      0.00%     78.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24768-24775            1      0.00%     78.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24832-24839           73      0.08%     78.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24896-24903            1      0.00%     78.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25088-25095           14      0.02%     78.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25152-25159            1      0.00%     78.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25216-25223            1      0.00%     78.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25280-25287            1      0.00%     78.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25344-25351          156      0.17%     79.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25408-25415            2      0.00%     79.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25472-25479            3      0.00%     79.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25600-25607          278      0.30%     79.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25664-25671            2      0.00%     79.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25856-25863           13      0.01%     79.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25984-25991            3      0.00%     79.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26048-26055            1      0.00%     79.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26112-26119           89      0.10%     79.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26176-26183            4      0.00%     79.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26240-26247            1      0.00%     79.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26368-26375           78      0.09%     79.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26496-26503            4      0.00%     79.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26624-26631          385      0.42%     80.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26752-26759            1      0.00%     80.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26816-26823            2      0.00%     80.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26880-26887          196      0.21%     80.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26944-26951            1      0.00%     80.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27008-27015            1      0.00%     80.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27072-27079            2      0.00%     80.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27136-27143           71      0.08%     80.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27200-27207            1      0.00%     80.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27392-27399           10      0.01%     80.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27456-27463            2      0.00%     80.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27520-27527            2      0.00%     80.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27648-27655          285      0.31%     80.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27712-27719            1      0.00%     80.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27776-27783            2      0.00%     80.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27904-27911          137      0.15%     80.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28096-28103            1      0.00%     80.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28160-28167           20      0.02%     80.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28224-28231            1      0.00%     80.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28288-28295            1      0.00%     80.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28352-28359            1      0.00%     80.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28416-28423           15      0.02%     80.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28544-28551            5      0.01%     80.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28608-28615            1      0.00%     80.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28672-28679          454      0.50%     81.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28800-28807            1      0.00%     81.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28864-28871            1      0.00%     81.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28928-28935           95      0.10%     81.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29056-29063            2      0.00%     81.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29120-29127            2      0.00%     81.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29184-29191          143      0.16%     81.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29312-29319            3      0.00%     81.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29376-29383            2      0.00%     81.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29440-29447          147      0.16%     81.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29568-29575            5      0.01%     81.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29632-29639            1      0.00%     81.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29696-29703          291      0.32%     82.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29760-29767            1      0.00%     82.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29824-29831            1      0.00%     82.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29952-29959           18      0.02%     82.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30080-30087            2      0.00%     82.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30144-30151            1      0.00%     82.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30208-30215          139      0.15%     82.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30272-30279            2      0.00%     82.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30464-30471           17      0.02%     82.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30528-30535            2      0.00%     82.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30592-30599            5      0.01%     82.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30720-30727          334      0.37%     82.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30784-30791            2      0.00%     82.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30976-30983           75      0.08%     82.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31040-31047            2      0.00%     82.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31104-31111            1      0.00%     82.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31168-31175            1      0.00%     82.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31232-31239           77      0.08%     82.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31424-31431            2      0.00%     82.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31488-31495           84      0.09%     82.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31616-31623            6      0.01%     82.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31680-31687            1      0.00%     82.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31744-31751          392      0.43%     83.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31808-31815            1      0.00%     83.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31872-31879            1      0.00%     83.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32000-32007           91      0.10%     83.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32128-32135            2      0.00%     83.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32256-32263           14      0.02%     83.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32384-32391            2      0.00%     83.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32512-32519           81      0.09%     83.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32576-32583            1      0.00%     83.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32640-32647            2      0.00%     83.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32768-32775          668      0.73%     84.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33024-33031           70      0.08%     84.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33280-33287           13      0.01%     84.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33344-33351            1      0.00%     84.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33408-33415            3      0.00%     84.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33536-33543           95      0.10%     84.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33600-33607            1      0.00%     84.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33664-33671            3      0.00%     84.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33792-33799          402      0.44%     84.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33920-33927            1      0.00%     84.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34048-34055           82      0.09%     85.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34304-34311           76      0.08%     85.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34432-34439            4      0.00%     85.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34560-34567           80      0.09%     85.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34688-34695            1      0.00%     85.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34752-34759            1      0.00%     85.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34816-34823          334      0.37%     85.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34944-34951            2      0.00%     85.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35008-35015            1      0.00%     85.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35072-35079           12      0.01%     85.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35136-35143            1      0.00%     85.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35200-35207            1      0.00%     85.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35264-35271            1      0.00%     85.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35328-35335          138      0.15%     85.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35456-35463            3      0.00%     85.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35584-35591           16      0.02%     85.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35712-35719            3      0.00%     85.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35840-35847          289      0.32%     86.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35904-35911            1      0.00%     86.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35968-35975            1      0.00%     86.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36096-36103          143      0.16%     86.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36352-36359          143      0.16%     86.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36416-36423            2      0.00%     86.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36480-36487            4      0.00%     86.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36608-36615          101      0.11%     86.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36864-36871          455      0.50%     87.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37056-37063            1      0.00%     87.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37120-37127            7      0.01%     87.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37248-37255            2      0.00%     87.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37312-37319            1      0.00%     87.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37376-37383           19      0.02%     87.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37504-37511            2      0.00%     87.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37632-37639          137      0.15%     87.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37888-37895          277      0.30%     87.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38016-38023            1      0.00%     87.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38144-38151            9      0.01%     87.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38272-38279            1      0.00%     87.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38336-38343            1      0.00%     87.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38400-38407           70      0.08%     87.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38464-38471            1      0.00%     87.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38528-38535            2      0.00%     87.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38656-38663          197      0.22%     87.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38720-38727            1      0.00%     87.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38784-38791            1      0.00%     87.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38912-38919          387      0.42%     88.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39040-39047            2      0.00%     88.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39168-39175           74      0.08%     88.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39424-39431           86      0.09%     88.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39488-39495            2      0.00%     88.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39552-39559            4      0.00%     88.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39680-39687           16      0.02%     88.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39808-39815            2      0.00%     88.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39872-39879            1      0.00%     88.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39936-39943          277      0.30%     88.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40192-40199          154      0.17%     88.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40320-40327            1      0.00%     88.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40448-40455           11      0.01%     88.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40576-40583            3      0.00%     88.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40704-40711           77      0.08%     89.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40960-40967          525      0.57%     89.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41088-41095            1      0.00%     89.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41216-41223           69      0.08%     89.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41344-41351            3      0.00%     89.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41472-41479           14      0.02%     89.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41600-41607            1      0.00%     89.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41728-41735          154      0.17%     89.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41984-41991          280      0.31%     90.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42112-42119            1      0.00%     90.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42240-42247           18      0.02%     90.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42304-42311            2      0.00%     90.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42368-42375            1      0.00%     90.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42496-42503           88      0.10%     90.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42624-42631            2      0.00%     90.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42752-42759           77      0.08%     90.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42880-42887            2      0.00%     90.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43008-43015          387      0.42%     90.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43136-43143            1      0.00%     90.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43264-43271          193      0.21%     91.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43520-43527           69      0.08%     91.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43648-43655            2      0.00%     91.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43776-43783           13      0.01%     91.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43904-43911            2      0.00%     91.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44032-44039          277      0.30%     91.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44096-44103            1      0.00%     91.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44224-44231            2      0.00%     91.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44288-44295          139      0.15%     91.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44544-44551           17      0.02%     91.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44608-44615            2      0.00%     91.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44672-44679            3      0.00%     91.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44800-44807           11      0.01%     91.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44864-44871            1      0.00%     91.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44992-44999            1      0.00%     91.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45056-45063          459      0.50%     92.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45184-45191            1      0.00%     92.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45312-45319           99      0.11%     92.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45376-45383            3      0.00%     92.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45440-45447            3      0.00%     92.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45568-45575          148      0.16%     92.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45696-45703            2      0.00%     92.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45760-45767            1      0.00%     92.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45824-45831          151      0.17%     92.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46016-46023            1      0.00%     92.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46080-46087          285      0.31%     92.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46208-46215            1      0.00%     92.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46272-46279            1      0.00%     92.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46336-46343           17      0.02%     92.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46528-46535            1      0.00%     92.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46592-46599          140      0.15%     93.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46720-46727            2      0.00%     93.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46848-46855           15      0.02%     93.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47104-47111          339      0.37%     93.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47296-47303            2      0.00%     93.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47360-47367           80      0.09%     93.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47488-47495            1      0.00%     93.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47616-47623           79      0.09%     93.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47744-47751            3      0.00%     93.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47872-47879           82      0.09%     93.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48064-48071            1      0.00%     93.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48128-48135          389      0.43%     94.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48192-48199            1      0.00%     94.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48320-48327            1      0.00%     94.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48384-48391           92      0.10%     94.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48640-48647           12      0.01%     94.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48704-48711            2      0.00%     94.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48768-48775           69      0.08%     94.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48896-48903           72      0.08%     94.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48960-48967            2      0.00%     94.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::49024-49031            3      0.00%     94.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::49088-49095            1      0.00%     94.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::49152-49159         5070      5.54%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::49280-49287            1      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::49344-49351            1      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::49408-49415            1      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::49472-49479            1      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::49920-49927            1      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::50048-50055            2      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::50112-50119            2      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::50176-50183            1      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::50240-50247            1      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::50368-50375            3      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::50496-50503            1      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::50560-50567            1      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::50624-50631            2      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::50688-50695            2      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::50752-50759            2      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::51008-51015            2      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::51072-51079            1      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::51136-51143            1      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::51200-51207            2      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::51264-51271            1      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::51456-51463            1      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::51584-51591            2      0.00%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::51648-51655            1      0.00%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::51840-51847            1      0.00%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::51904-51911            1      0.00%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::52224-52231            1      0.00%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          91489                       # Bytes accessed per row activation
-system.physmem.totQLat                   370803624750                       # Total ticks spent queuing
-system.physmem.totMemAccLat              464795231000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                  76315665000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                 17675941250                       # Total ticks spent accessing banks
-system.physmem.avgQLat                       24294.07                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                     1158.08                       # Average bank access latency per DRAM burst
+system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     1944                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     1998                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     2401                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     4700                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     5971                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6079                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     6148                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     6196                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     6200                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     6189                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     6821                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     6509                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     6365                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     7158                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     6652                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     6157                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6118                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6071                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     2256                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      774                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      680                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      711                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      674                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      604                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      634                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      601                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      590                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      593                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      556                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      578                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      550                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      549                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      549                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      543                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      541                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      540                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      543                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      541                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      547                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       965097                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean     1010.691593                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     992.992769                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     104.599429                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127           5712      0.59%      0.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         4413      0.46%      1.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         2116      0.22%      1.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         1499      0.16%      1.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         1121      0.12%      1.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          815      0.08%      1.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          661      0.07%      1.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          851      0.09%      1.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151       947909     98.22%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         965097                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5955                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean      2555.332662                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev    92927.024688                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-262143         5949     99.90%     99.90% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::262144-524287            1      0.02%     99.92% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::524288-786431            1      0.02%     99.93% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::786432-1.04858e+06            1      0.02%     99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2.3593e+06-2.62144e+06            2      0.03%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::6.02931e+06-6.29146e+06            1      0.02%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            5955                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5955                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        19.114190                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.218740                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        7.431880                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               3971     66.68%     66.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 19      0.32%     67.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                175      2.94%     69.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19               1141     19.16%     89.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                 44      0.74%     89.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 19      0.32%     90.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 21      0.35%     90.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 10      0.17%     90.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                  6      0.10%     90.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                  3      0.05%     90.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                  4      0.07%     90.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27                  1      0.02%     90.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30                  1      0.02%     90.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::34                  1      0.02%     90.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::39                  1      0.02%     90.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40                  1      0.02%     90.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::41                146      2.45%     93.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::42                311      5.22%     98.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::43                 13      0.22%     98.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44                 13      0.22%     99.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::45                 16      0.27%     99.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::46                 22      0.37%     99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::47                  9      0.15%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48                  4      0.07%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::49                  3      0.05%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5955                       # Writes before turning the bus around for reads
+system.physmem.totQLat                   579051796250                       # Total ticks spent queuing
+system.physmem.totMemAccLat              683715373750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                  76085110000                       # Total ticks spent in databus transfers
+system.physmem.totBankLat                 28578467500                       # Total ticks spent accessing banks
+system.physmem.avgQLat                       38052.90                       # Average queueing delay per DRAM burst
+system.physmem.avgBankLat                     1878.06                       # Average bank access latency per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  30452.15                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         374.90                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           2.84                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       50.48                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        2.80                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  44930.96                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         373.76                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           2.80                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       50.47                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        2.79                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           2.95                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       2.93                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           2.94                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       2.92                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         0.18                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        14.44                       # Average write queue length when enqueuing
-system.physmem.readRowHits                   15189237                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     97938                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   99.52                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  84.76                       # Row buffer hit rate for writes
-system.physmem.avgGap                       161581.71                       # Average gap between requests
-system.physmem.pageHitRate                      99.40                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               2.46                       # Percentage of time for which DRAM has all the banks in precharge state
+system.physmem.avgRdQLen                         6.53                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        26.75                       # Average write queue length when enqueuing
+system.physmem.readRowHits                   14231578                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     96073                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   93.52                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  84.38                       # Row buffer hit rate for writes
+system.physmem.avgGap                       161592.99                       # Average gap between requests
+system.physmem.pageHitRate                      93.46                       # Row buffer hit rate, read and write combined
+system.physmem.prechargeAllPercent               4.22                       # Percentage of time for which DRAM has all the banks in precharge state
 system.realview.nvmem.bytes_read::cpu0.inst           64                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu1.inst          384                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total           448                       # Number of bytes read from this memory
@@ -782,299 +322,300 @@ system.realview.nvmem.bw_inst_read::total          172                       # I
 system.realview.nvmem.bw_total::cpu0.inst           25                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu1.inst          147                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total             172                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                     54211188                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq            16352626                       # Transaction distribution
-system.membus.trans_dist::ReadResp           16352626                       # Transaction distribution
-system.membus.trans_dist::WriteReq             769179                       # Transaction distribution
-system.membus.trans_dist::WriteResp            769179                       # Transaction distribution
-system.membus.trans_dist::Writeback             66581                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            35757                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq          18322                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           14211                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            137874                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           137463                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      2384372                       # Packet count per connected master and slave (bytes)
+system.membus.throughput                     54186995                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq            16352581                       # Transaction distribution
+system.membus.trans_dist::ReadResp           16352581                       # Transaction distribution
+system.membus.trans_dist::WriteReq             769189                       # Transaction distribution
+system.membus.trans_dist::WriteResp            769189                       # Transaction distribution
+system.membus.trans_dist::Writeback             66093                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            35785                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq          18271                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           14082                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            137406                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           137045                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      2384396                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           14                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13818                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13840                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio            4                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio         2042                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1975936                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      4376186                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1974294                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      4374590                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     30277632                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total     30277632                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total               34653818                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave      2392693                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count::total               34652222                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave      2392725                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port          448                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio        27636                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio        27680                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio            8                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio         4084                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     17718532                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::total     20143401                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     17656836                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::total     20081781                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port    121110528                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.iocache.mem_side::total    121110528                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total           141253929                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus              141253929                       # Total data (bytes)
+system.membus.tot_pkt_size::total           141192309                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus              141192309                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy          1488197499                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy          1488242000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy                7000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy            11766500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy            11807000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer4.occupancy                3000                       # Layer occupancy (ticks)
 system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy             1797499                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy             1798000                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer6.occupancy         17658492000                       # Layer occupancy (ticks)
+system.membus.reqLayer6.occupancy         17652470999                       # Layer occupancy (ticks)
 system.membus.reqLayer6.utilization               0.7                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         4844234238                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         4843604815                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
-system.membus.respLayer2.occupancy        34183641699                       # Layer occupancy (ticks)
-system.membus.respLayer2.utilization              1.3                       # Layer utilization (%)
+system.membus.respLayer2.occupancy        37703679634                       # Layer occupancy (ticks)
+system.membus.respLayer2.utilization              1.4                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.l2c.tags.replacements                    72645                       # number of replacements
-system.l2c.tags.tagsinuse                53020.689119                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    1874829                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   137818                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    13.603658                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                    72164                       # number of replacements
+system.l2c.tags.tagsinuse                53016.131060                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    1876966                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   137304                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    13.670148                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   37720.403327                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker     5.416210                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000363                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     4180.066464                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     2958.458343                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker    11.364086                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     4038.603525                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     4106.376802                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.575568                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000083                       # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::writebacks   37702.356015                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker     7.377107                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000365                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     4186.473555                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     2957.675740                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker    10.683393                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     4035.806716                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     4115.758170                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.575292                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000113                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.063783                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.045142                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000173                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.061624                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.062658                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.809032                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1023            5                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        65168                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4            5                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           20                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          303                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         3126                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         8643                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        53076                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1023     0.000076                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.994385                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 18857930                       # Number of tag accesses
-system.l2c.tags.data_accesses                18857930                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker        23180                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker         4676                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst             393299                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             166186                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker        33047                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker         5717                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             607435                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data             201334                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1434874                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          583828                       # number of Writeback hits
-system.l2c.Writeback_hits::total               583828                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data            1113                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data             796                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                1909                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data           212                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data           162                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total               374                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            48382                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            59141                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               107523                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker         23180                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker          4676                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              393299                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              214568                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker         33047                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          5717                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              607435                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              260475                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1542397                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker        23180                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker         4676                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             393299                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             214568                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker        33047                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         5717                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             607435                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             260475                       # number of overall hits
-system.l2c.overall_hits::total                1542397                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.dtb.walker           13                       # number of ReadReq misses
+system.l2c.tags.occ_percent::cpu0.inst       0.063881                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.045131                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000163                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.061582                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.062801                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.808962                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1023            4                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        65136                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4            3                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           25                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          297                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         3097                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         8263                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        53454                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1023     0.000061                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.993896                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 18860644                       # Number of tag accesses
+system.l2c.tags.data_accesses                18860644                       # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.dtb.walker        23595                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker         5577                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.inst             409210                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data             169724                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker        33221                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker         5824                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst             593571                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data             196649                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1437371                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          582434                       # number of Writeback hits
+system.l2c.Writeback_hits::total               582434                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data             737                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data            1202                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                1939                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data           203                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data           149                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total               352                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data            52746                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            54725                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               107471                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.dtb.walker         23595                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker          5577                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst              409210                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              222470                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker         33221                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker          5824                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              593571                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              251374                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 1544842                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker        23595                       # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker         5577                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst             409210                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             222470                       # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker        33221                       # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker         5824                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             593571                       # number of overall hits
+system.l2c.overall_hits::cpu1.data             251374                       # number of overall hits
+system.l2c.overall_hits::total                1544842                       # number of overall hits
+system.l2c.ReadReq_misses::cpu0.dtb.walker           16                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu0.itb.walker            2                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst             6052                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data             6313                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.dtb.walker           17                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst             6634                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data             6349                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                25380                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data          5741                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data          4448                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total             10189                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data          772                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data          589                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total            1361                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          63128                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          76996                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             140124                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.dtb.walker           13                       # number of demand (read+write) misses
+system.l2c.ReadReq_misses::cpu0.inst             5877                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data             6190                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.dtb.walker           15                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst             6810                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data             6416                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                25326                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data          5271                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data          4770                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total             10041                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data          769                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data          576                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total            1345                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data          80429                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data          59312                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             139741                       # number of ReadExReq misses
+system.l2c.demand_misses::cpu0.dtb.walker           16                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst              6052                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data             69441                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker           17                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              6634                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data             83345                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                165504                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker           13                       # number of overall misses
+system.l2c.demand_misses::cpu0.inst              5877                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data             86619                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.dtb.walker           15                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst              6810                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data             65728                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                165067                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.dtb.walker           16                       # number of overall misses
 system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst             6052                       # number of overall misses
-system.l2c.overall_misses::cpu0.data            69441                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker           17                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             6634                       # number of overall misses
-system.l2c.overall_misses::cpu1.data            83345                       # number of overall misses
-system.l2c.overall_misses::total               165504                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.dtb.walker      1319500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.itb.walker       448000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.inst    442132250                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data    474613998                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.dtb.walker      1532000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst    492031750                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data    492624500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total     1904701998                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0.data      9247586                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data     12516468                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total     21764054                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data       581975                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data      3187362                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total      3769337                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data   4414635311                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data   6079977271                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total  10494612582                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker      1319500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.itb.walker       448000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst    442132250                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data   4889249309                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker      1532000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst    492031750                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data   6572601771                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total     12399314580                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker      1319500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.itb.walker       448000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst    442132250                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data   4889249309                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker      1532000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst    492031750                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data   6572601771                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    12399314580                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.dtb.walker        23193                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker         4678                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst         399351                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data         172499                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker        33064                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker         5717                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst         614069                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data         207683                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            1460254                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       583828                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           583828                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data         6854                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data         5244                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total           12098                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data          984                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data          751                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total          1735                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       111510                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data       136137                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           247647                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker        23193                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker         4678                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst          399351                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data          284009                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker        33064                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker         5717                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          614069                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          343820                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             1707901                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker        23193                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker         4678                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         399351                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data         284009                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker        33064                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker         5717                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         614069                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         343820                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            1707901                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000561                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000428                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.015155                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.036597                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000514                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.010803                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.030571                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.017381                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.837613                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.848207                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.842205                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.784553                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.784288                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.784438                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.566120                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.565577                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.565822                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000561                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.000428                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.015155                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.244503                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000514                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.010803                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.242409                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.096905                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000561                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.000428                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.015155                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.244503                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000514                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.010803                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.242409                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.096905                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker       101500                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker       224000                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 73055.560145                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 75180.421036                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 90117.647059                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 74168.186614                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 77590.880454                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 75047.360047                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  1610.797074                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  2813.954137                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  2136.034351                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data   753.853627                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  5411.480475                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  2769.534901                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 69931.493331                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 78964.845849                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 74895.182710                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker       101500                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker       224000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 73055.560145                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 70408.682320                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 90117.647059                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 74168.186614                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 78860.180827                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 74918.519069                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker       101500                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker       224000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 73055.560145                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 70408.682320                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 90117.647059                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 74168.186614                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 78860.180827                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 74918.519069                       # average overall miss latency
+system.l2c.overall_misses::cpu0.inst             5877                       # number of overall misses
+system.l2c.overall_misses::cpu0.data            86619                       # number of overall misses
+system.l2c.overall_misses::cpu1.dtb.walker           15                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst             6810                       # number of overall misses
+system.l2c.overall_misses::cpu1.data            65728                       # number of overall misses
+system.l2c.overall_misses::total               165067                       # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu0.dtb.walker      1263000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.itb.walker       158000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.inst    424519750                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.data    461015999                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.dtb.walker      1424250                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst    503203750                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data    495567749                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total     1887152498                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu0.data      8440130                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data     13402927                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total     21843057                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data       510978                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data      2957372                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total      3468350                       # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data   5751042289                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data   4687313508                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total  10438355797                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu0.dtb.walker      1263000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.itb.walker       158000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.inst    424519750                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data   6212058288                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.dtb.walker      1424250                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst    503203750                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data   5182881257                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total     12325508295                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.dtb.walker      1263000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.itb.walker       158000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.inst    424519750                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data   6212058288                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.dtb.walker      1424250                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst    503203750                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data   5182881257                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total    12325508295                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.dtb.walker        23611                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker         5579                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.inst         415087                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data         175914                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker        33236                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker         5824                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst         600381                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data         203065                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            1462697                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       582434                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           582434                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data         6008                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data         5972                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total           11980                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data          972                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data          725                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total          1697                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       133175                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data       114037                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           247212                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker        23611                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker         5579                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst          415087                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data          309089                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker        33236                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker         5824                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          600381                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data          317102                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             1709909                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker        23611                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker         5579                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         415087                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data         309089                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker        33236                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker         5824                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         600381                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data         317102                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            1709909                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000678                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000358                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.014158                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.035188                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000451                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst      0.011343                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data      0.031596                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.017315                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.877330                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.798727                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.838147                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.791152                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.794483                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.792575                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.603935                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.520112                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.565268                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000678                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.000358                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.014158                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.280240                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000451                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.011343                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.207277                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.096536                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000678                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.000358                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.014158                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.280240                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000451                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.011343                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.207277                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.096536                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 78937.500000                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        79000                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.inst 72234.090522                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.data 74477.544265                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        94950                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 73891.886931                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 77239.362375                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 74514.431730                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  1601.238854                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  2809.837945                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  2175.386615                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data   664.470741                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  5134.326389                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total  2578.698885                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 71504.585274                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 79028.080456                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 74697.875334                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 78937.500000                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.itb.walker        79000                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 72234.090522                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 71717.040003                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        94950                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 73891.886931                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 78853.475794                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 74669.729837                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 78937.500000                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.itb.walker        79000                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 72234.090522                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 71717.040003                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        94950                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 73891.886931                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 78853.475794                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 74669.729837                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -1083,168 +624,168 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               66581                       # number of writebacks
-system.l2c.writebacks::total                    66581                       # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu0.inst             4                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu0.data            37                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.inst             7                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.data            28                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total                76                       # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.inst              4                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.data             37                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst              7                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.data             28                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                 76                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.inst             4                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu0.data            37                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst             7                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.data            28                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                76                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker           13                       # number of ReadReq MSHR misses
+system.l2c.writebacks::writebacks               66093                       # number of writebacks
+system.l2c.writebacks::total                    66093                       # number of writebacks
+system.l2c.ReadReq_mshr_hits::cpu0.inst             5                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu0.data            40                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu1.inst             8                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu1.data            26                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::total                79                       # number of ReadReq MSHR hits
+system.l2c.demand_mshr_hits::cpu0.inst              5                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu0.data             40                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.inst              8                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.data             26                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                 79                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu0.inst             5                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu0.data            40                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.inst             8                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.data            26                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total                79                       # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker           16                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            2                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.inst         6048                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.data         6276                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker           17                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst         6627                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data         6321                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total           25304                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data         5741                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data         4448                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total        10189                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          772                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          589                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total         1361                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data        63128                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data        76996                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        140124                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.dtb.walker           13                       # number of demand (read+write) MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.inst         5872                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.data         6150                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker           15                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.inst         6802                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.data         6390                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total           25247                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data         5271                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data         4770                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total        10041                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          769                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          576                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total         1345                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data        80429                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data        59312                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        139741                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.dtb.walker           16                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu0.itb.walker            2                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst         6048                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data        69404                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker           17                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst         6627                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data        83317                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           165428                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.dtb.walker           13                       # number of overall MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst         5872                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data        86579                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.dtb.walker           15                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst         6802                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data        65702                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           164988                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.dtb.walker           16                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu0.itb.walker            2                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst         6048                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data        69404                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.dtb.walker           17                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst         6627                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data        83317                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          165428                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker      1158500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker       423500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    365788500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.data    393596748                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker      1324000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    408302500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data    412139500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total   1582733248                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     57558681                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     44816867                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total    102375548                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      7725271                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      5896085                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total     13621356                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   3622664675                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   5123552719                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   8746217394                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      1158500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       423500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst    365788500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data   4016261423                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker      1324000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst    408302500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data   5535692219                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total  10328950642                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      1158500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       423500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst    365788500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data   4016261423                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker      1324000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst    408302500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data   5535692219                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  10328950642                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst      6844749                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data  12336851490                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      2547499                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154880596991                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 167226840729                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   1073381000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data  16517452398                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total  17590833398                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.inst      6844749                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data  13410232490                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      2547499                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data 171398049389                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 184817674127                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000561                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000428                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.015145                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.036383                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000514                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.010792                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.030436                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.017328                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.837613                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.848207                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.842205                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.784553                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.784288                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.784438                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.566120                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.565577                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.565822                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000561                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000428                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.015145                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.244373                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000514                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.010792                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.242327                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.096860                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000561                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000428                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.015145                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.244373                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000514                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.010792                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.242327                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.096860                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 89115.384615                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker       211750                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60480.902778                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 62714.586998                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 77882.352941                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61611.966199                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65201.629489                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 62548.737275                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10025.898101                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10075.734487                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10047.654137                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10006.827720                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10010.331070                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10008.343865                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 57386.020070                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 66543.102486                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 62417.697140                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 89115.384615                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker       211750                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60480.902778                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 57867.866737                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 77882.352941                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61611.966199                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66441.329129                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 62437.741144                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 89115.384615                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker       211750                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60480.902778                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57867.866737                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 77882.352941                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61611.966199                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66441.329129                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 62437.741144                       # average overall mshr miss latency
+system.l2c.overall_mshr_misses::cpu0.inst         5872                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data        86579                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.dtb.walker           15                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst         6802                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data        65702                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          164988                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker      1063000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker       133500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    350406250                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.data    380974999                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker      1239250                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    417280250                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data    414218499                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total   1565315748                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     52852722                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     48053192                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    100905914                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      7702266                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      5777069                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total     13479335                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   4750287699                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   3948467988                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   8698755687                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      1063000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       133500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst    350406250                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data   5131262698                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker      1239250                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst    417280250                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data   4362686487                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  10264071435                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      1063000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       133500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst    350406250                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data   5131262698                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker      1239250                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst    417280250                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data   4362686487                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  10264071435                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst      6908499                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 110354445727                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      2586249                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  56865414992                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 167229355467                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   1097294498                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data  16505203944                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total  17602498442                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.inst      6908499                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data 111451740225                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      2586249                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data  73370618936                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 184831853909                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000678                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000358                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.014146                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.034960                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000451                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.011329                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.031468                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.017261                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.877330                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.798727                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.838147                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.791152                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.794483                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.792575                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.603935                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.520112                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.565268                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000678                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000358                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.014146                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.280110                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000451                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.011329                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.207195                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.096489                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000678                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000358                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.014146                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.280110                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000451                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.011329                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.207195                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.096489                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 66437.500000                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        66750                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59674.088896                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61947.154309                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 82616.666667                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61346.699500                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64822.926291                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 62000.069236                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10027.076836                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10074.044444                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10049.388905                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10015.950585                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10029.633681                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10021.810409                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 59061.876923                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 66571.148975                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 62249.130084                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 66437.500000                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        66750                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59674.088896                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 59266.827961                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 82616.666667                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61346.699500                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66401.121534                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 62211.017983                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 66437.500000                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        66750                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59674.088896                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 59266.827961                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 82616.666667                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61346.699500                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66401.121534                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 62211.017983                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
@@ -1265,62 +806,62 @@ system.cf0.dma_read_txs                             0                       # Nu
 system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
-system.toL2Bus.throughput                    58734643                       # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq            2740334                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2740333                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq            769179                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp           769179                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           583828                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           35005                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq         18696                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          53701                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           259560                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          259560                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side       799508                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      1075466                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        14045                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        57080                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side      1228838                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side      4820247                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side        15511                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side        75325                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               8086020                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     25566400                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     34789221                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        18712                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        92772                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     39303552                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     48210820                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side        22868                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side       132256                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size::total          148136601                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus             148136601                       # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus         4903748                       # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy         4924229951                       # Layer occupancy (ticks)
+system.toL2Bus.throughput                    58721934                       # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq            2742702                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2742701                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq            769189                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp           769189                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           582434                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           35028                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq         18623                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp          53651                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           259025                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          259025                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side       831060                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2542800                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        15169                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        56113                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side      1201524                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side      3348368                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side        16175                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side        77084                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               8088293                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     26573504                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     39205457                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        22316                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        94444                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     38427456                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     43600612                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side        23296                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side       132944                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size::total          148080029                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus             148080029                       # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus         4928740                       # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy         4918843977                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        1801808391                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        1872939397                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        1518829470                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        2324821689                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy           9386457                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy           9616940                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy          34051657                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy          32646700                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy        2768216654                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer6.occupancy        2706859206                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer6.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy        3257831802                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.occupancy        2444231662                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer7.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer8.occupancy           9819444                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer8.occupancy          10370957                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer8.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer9.occupancy          42547912                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer9.occupancy          44131664                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer9.utilization             0.0                       # Layer utilization (%)
-system.iobus.throughput                      47398726                       # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq             16322919                       # Transaction distribution
-system.iobus.trans_dist::ReadResp            16322919                       # Transaction distribution
-system.iobus.trans_dist::WriteReq                8083                       # Transaction distribution
-system.iobus.trans_dist::WriteResp               8083                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        30944                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         8844                       # Packet count per connected master and slave (bytes)
+system.iobus.throughput                      47398263                       # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq             16322928                       # Transaction distribution
+system.iobus.trans_dist::ReadResp            16322928                       # Transaction distribution
+system.iobus.trans_dist::WriteReq                8086                       # Transaction distribution
+system.iobus.trans_dist::WriteResp               8086                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        30960                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         8852                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio         1030                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio           36                       # Packet count per connected master and slave (bytes)
@@ -1342,12 +883,12 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total      2384372                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total      2384396                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side     30277632                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.clcd.dma::total     30277632                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                32662004                       # Packet count per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio        40713                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio        17688                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                32662028                       # Packet count per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio        40729                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio        17704                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio         2060                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio           72                       # Cumulative packet size per connected master and slave (bytes)
@@ -1369,14 +910,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total      2392693                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::total      2392725                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side    121110528                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.realview.clcd.dma::total    121110528                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total            123503221                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus               123503221                       # Total data (bytes)
-system.iobus.reqLayer0.occupancy             21713000                       # Layer occupancy (ticks)
+system.iobus.tot_pkt_size::total            123503253                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus               123503253                       # Total data (bytes)
+system.iobus.reqLayer0.occupancy             21724000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy              4428000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy              4432000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer2.occupancy                34000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
@@ -1422,19 +963,19 @@ system.iobus.reqLayer23.occupancy                8000                       # La
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer25.occupancy         15138816000                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.6                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy          2376289000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy          2376310000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.1                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy         41457903301                       # Layer occupancy (ticks)
-system.iobus.respLayer1.utilization               1.6                       # Layer utilization (%)
-system.cpu0.branchPred.lookups                6116113                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted          4670014                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect           294465                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups             3791796                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits                2947023                       # Number of BTB hits
+system.iobus.respLayer1.occupancy         37739478366                       # Layer occupancy (ticks)
+system.iobus.respLayer1.utilization               1.4                       # Layer utilization (%)
+system.cpu0.branchPred.lookups                6715650                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted          5214611                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect           297509                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups             4164563                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits                3259277                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            77.721032                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS                 683382                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect             28116                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            78.262161                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS                 722080                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect             28659                       # Number of incorrect RAS predictions.
 system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1458,25 +999,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                     8971213                       # DTB read hits
-system.cpu0.dtb.read_misses                     29038                       # DTB read misses
-system.cpu0.dtb.write_hits                    5214205                       # DTB write hits
-system.cpu0.dtb.write_misses                     5642                       # DTB write misses
+system.cpu0.dtb.read_hits                    30314049                       # DTB read hits
+system.cpu0.dtb.read_misses                     28675                       # DTB read misses
+system.cpu0.dtb.write_hits                    5612279                       # DTB write hits
+system.cpu0.dtb.write_misses                     4120                       # DTB write misses
 system.cpu0.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    1740                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                      972                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                   288                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries                    1934                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                     1024                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                   293                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      602                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                 9000251                       # DTB read accesses
-system.cpu0.dtb.write_accesses                5219847                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      686                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                30342724                       # DTB read accesses
+system.cpu0.dtb.write_accesses                5616399                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         14185418                       # DTB hits
-system.cpu0.dtb.misses                          34680                       # DTB misses
-system.cpu0.dtb.accesses                     14220098                       # DTB accesses
+system.cpu0.dtb.hits                         35926328                       # DTB hits
+system.cpu0.dtb.misses                          32795                       # DTB misses
+system.cpu0.dtb.accesses                     35959123                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1498,8 +1039,8 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.inst_hits                     4275051                       # ITB inst hits
-system.cpu0.itb.inst_misses                      5189                       # ITB inst misses
+system.cpu0.itb.inst_hits                     4601822                       # ITB inst hits
+system.cpu0.itb.inst_misses                      5333                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
@@ -1508,549 +1049,544 @@ system.cpu0.itb.flush_tlb                           4                       # Nu
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
 system.cpu0.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    1217                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries                    1359                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                     1383                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                     1531                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                 4280240                       # ITB inst accesses
-system.cpu0.itb.hits                          4275051                       # DTB hits
-system.cpu0.itb.misses                           5189                       # DTB misses
-system.cpu0.itb.accesses                      4280240                       # DTB accesses
-system.cpu0.numCycles                        70241745                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                 4607155                       # ITB inst accesses
+system.cpu0.itb.hits                          4601822                       # DTB hits
+system.cpu0.itb.misses                           5333                       # DTB misses
+system.cpu0.itb.accesses                      4607155                       # DTB accesses
+system.cpu0.numCycles                       298758505                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles          11929498                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                      32445295                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                    6116113                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches           3630405                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                      7610256                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles                1455955                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles                     63581                       # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.BlockedCycles              20356712                       # Number of cycles fetch has spent blocked
-system.cpu0.fetch.MiscStallCycles                5910                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles        46897                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles      1384514                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles          336                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                  4273539                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes               157097                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes                   2132                       # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples          42442805                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             0.987587                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            2.368800                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles          12556555                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                      35349888                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                    6715650                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches           3981357                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                      8343175                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles                1485021                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles                     73668                       # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.BlockedCycles              62934939                       # Number of cycles fetch has spent blocked
+system.cpu0.fetch.MiscStallCycles                5979                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles        43768                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles      1358657                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles          326                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                  4600051                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes               159705                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes                   2319                       # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples          86381436                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             0.526874                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            1.794731                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0                34839840     82.09%     82.09% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                  572205      1.35%     83.43% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                  825004      1.94%     85.38% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                  684840      1.61%     86.99% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4                  778500      1.83%     88.83% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5                  566486      1.33%     90.16% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6                  678699      1.60%     91.76% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7                  357241      0.84%     92.60% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8                 3139990      7.40%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0                78045507     90.35%     90.35% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                  675063      0.78%     91.13% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                  847046      0.98%     92.11% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                  783211      0.91%     93.02% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4                 1013921      1.17%     94.19% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5                  572462      0.66%     94.86% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6                  659407      0.76%     95.62% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7                  359642      0.42%     96.03% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8                 3425177      3.97%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total            42442805                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.087072                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.461909                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles                12488007                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles             21548451                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                  6870426                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles               554367                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles                981554                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved              948390                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred                64682                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts              40553105                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts               211793                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles                981554                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles                13063645                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles                5927392                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles      13516172                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                  6803229                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles              2150813                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts              39442908                       # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents                  349                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents                442190                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LSQFullEvents              1172580                       # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.FullRegisterEvents             108                       # Number of times there has been no free registers
-system.cpu0.rename.RenamedOperands           39856158                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups            180580051                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups       163873696                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups             4140                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps             31502925                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                 8353232                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts            459972                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts        416665                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                  5510720                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads             7760142                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores            5773435                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads          1130797                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores         1218383                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                  37351008                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded             906143                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                 37719109                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued            82376                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined        6300240                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined     13226792                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved        257129                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples     42442805                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.888704                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.506616                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total            86381436                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.022479                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.118323                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles                13622847                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles             63604727                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                  7412124                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles               742617                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles                999121                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved              974392                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred                66422                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts              44125799                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts               218867                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles                999121                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles                14363042                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles               26099881                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles      33731509                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                  7356267                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles              3831616                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts              43013829                       # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents                  321                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents                629927                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LSQFullEvents              2476084                       # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.FullRegisterEvents              94                       # Number of times there has been no free registers
+system.cpu0.rename.RenamedOperands           43352703                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups            198103413                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups       178854732                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups             5396                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps             34867311                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                 8485392                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts            643580                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts        598183                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                  7434614                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads             8769305                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores            6206849                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads          1218439                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores         1296110                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                  40716219                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded            1133567                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                 61584494                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued            78672                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined        6465857                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined     13399979                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved        300001                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples     86381436                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.712937                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.420531                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0           27084248     63.81%     63.81% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1            5900278     13.90%     77.72% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2            3162124      7.45%     85.17% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3            2465638      5.81%     90.97% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4            2124054      5.00%     95.98% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5             938721      2.21%     98.19% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6             522569      1.23%     99.42% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7             188950      0.45%     99.87% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8              56223      0.13%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0           63313818     73.30%     73.30% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1            8088215      9.36%     82.66% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2            3310781      3.83%     86.49% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3            2721682      3.15%     89.64% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4            7122842      8.25%     97.89% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5            1038791      1.20%     99.09% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6             532976      0.62%     99.71% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7             192156      0.22%     99.93% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8              60175      0.07%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total       42442805                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total       86381436                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu                  27701      2.58%      2.58% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                   461      0.04%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                      0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%      2.62% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead                838727     78.09%     80.71% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite               207210     19.29%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu                  26298      0.46%      0.46% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                   452      0.01%      0.47% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                      0      0.00%      0.47% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%      0.47% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%      0.47% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%      0.47% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%      0.47% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%      0.47% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%      0.47% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%      0.47% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%      0.47% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%      0.47% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%      0.47% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%      0.47% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%      0.47% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%      0.47% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%      0.47% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%      0.47% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%      0.47% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%      0.47% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%      0.47% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%      0.47% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%      0.47% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%      0.47% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%      0.47% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%      0.47% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%      0.47% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%      0.47% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%      0.47% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead               5416194     95.59%     96.06% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite               223026      3.94%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass            14552      0.04%      0.04% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu             22689290     60.15%     60.19% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult               48124      0.13%     60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   1      0.00%     60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                 12      0.00%     60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              9      0.00%     60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc           680      0.00%     60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc           11      0.00%     60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead             9432418     25.01%     85.33% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite            5534012     14.67%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass            15923      0.03%      0.03% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu             24790294     40.25%     40.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult               50109      0.08%     40.36% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     40.36% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     40.36% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     40.36% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     40.36% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     40.36% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     40.36% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     40.36% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     40.36% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     40.36% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     40.36% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     40.36% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     40.36% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                 12      0.00%     40.36% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     40.36% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     40.36% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     40.36% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              9      0.00%     40.36% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     40.36% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     40.36% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     40.36% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     40.36% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     40.36% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     40.36% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc           806      0.00%     40.36% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     40.36% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            9      0.00%     40.36% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     40.36% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead            30788025     49.99%     90.36% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite            5939307      9.64%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total              37719109                       # Type of FU issued
-system.cpu0.iq.rate                          0.536990                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                    1074099                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.028476                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads         119063513                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes         44565262                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses     34855631                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads               8367                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes              4694                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses         3878                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses              38774303                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                   4353                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads          316534                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total              61584494                       # Type of FU issued
+system.cpu0.iq.rate                          0.206135                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                    5665970                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.092003                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads         215315704                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes         48322789                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses     38367249                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads              11842                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes              6226                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses         5089                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses              67228191                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                   6350                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads          325894                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads      1373139                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses         2492                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation        13119                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores       536810                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads      1367932                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses         2587                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation        13911                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores       563678                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads      2149889                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked         5851                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads     22510150                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked         5899                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles                981554                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles                4303712                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles               102086                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts           38375609                       # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts            82190                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts              7760142                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts             5773435                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts            578535                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                 41087                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents                 6130                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents         13119                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect        149567                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect       117143                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts              266710                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts             37339391                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts              9288472                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts           379718                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles                999121                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles               20412775                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles               272757                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts           41952562                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts            83343                       # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts              8769305                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts             6206849                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts            796686                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                 50755                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents                 3694                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents         13911                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect        151015                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect       116203                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts              267218                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts             61206576                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts             30649831                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts           377918                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                       118458                       # number of nop insts executed
-system.cpu0.iew.exec_refs                    14775675                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches                 4960531                       # Number of branches executed
-system.cpu0.iew.exec_stores                   5487203                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.531584                       # Inst execution rate
-system.cpu0.iew.wb_sent                      37145263                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                     34859509                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                 18586335                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                 35686170                       # num instructions consuming a value
+system.cpu0.iew.exec_nop                       102776                       # number of nop insts executed
+system.cpu0.iew.exec_refs                    36543183                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches                 5550332                       # Number of branches executed
+system.cpu0.iew.exec_stores                   5893352                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.204870                       # Inst execution rate
+system.cpu0.iew.wb_sent                      61019070                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                     38372338                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                 20674113                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                 38142518                       # num instructions consuming a value
 system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate                      0.496279                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.520827                       # average fanout of values written-back
+system.cpu0.iew.wb_rate                      0.128439                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.542023                       # average fanout of values written-back
 system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts        6112161                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls         649014                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts           230918                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples     41461251                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.767144                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.727678                       # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts        6195680                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls         833566                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts           232261                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples     85382315                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.412432                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.299663                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0     29511356     71.18%     71.18% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1      5920392     14.28%     85.46% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2      1945303      4.69%     90.15% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3      1006881      2.43%     92.58% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4       766693      1.85%     94.43% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5       514145      1.24%     95.67% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6       405651      0.98%     96.65% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7       222934      0.54%     97.18% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8      1167896      2.82%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0     71262923     83.46%     83.46% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1      7740236      9.07%     92.53% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2      2004904      2.35%     94.88% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3      1114217      1.30%     96.18% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4       806577      0.94%     97.13% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5       503262      0.59%     97.72% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6       497454      0.58%     98.30% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7       227564      0.27%     98.57% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8      1225178      1.43%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total     41461251                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts            24081359                       # Number of instructions committed
-system.cpu0.commit.committedOps              31806750                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total     85382315                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts            26835114                       # Number of instructions committed
+system.cpu0.commit.committedOps              35214409                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                      11623628                       # Number of memory references committed
-system.cpu0.commit.loads                      6387003                       # Number of loads committed
-system.cpu0.commit.membars                     231881                       # Number of memory barriers committed
-system.cpu0.commit.branches                   4353159                       # Number of branches committed
-system.cpu0.commit.fp_insts                      3838                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                 28151052                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls              499153                       # Number of function calls committed.
-system.cpu0.commit.bw_lim_events              1167896                       # number cycles where commit BW limit reached
+system.cpu0.commit.refs                      13044544                       # Number of memory references committed
+system.cpu0.commit.loads                      7401373                       # Number of loads committed
+system.cpu0.commit.membars                     236456                       # Number of memory barriers committed
+system.cpu0.commit.branches                   4918099                       # Number of branches committed
+system.cpu0.commit.fp_insts                      5062                       # Number of committed floating point instructions.
+system.cpu0.commit.int_insts                 31243705                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls              531450                       # Number of function calls committed.
+system.cpu0.commit.bw_lim_events              1225178                       # number cycles where commit BW limit reached
 system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads                    77343282                       # The number of ROB reads
-system.cpu0.rob.rob_writes                   76821100                       # The number of ROB writes
-system.cpu0.timesIdled                         366365                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                       27798940                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                  5140962052                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                   24000617                       # Number of Instructions Simulated
-system.cpu0.committedOps                     31726008                       # Number of Ops (including micro ops) Simulated
-system.cpu0.committedInsts_total             24000617                       # Number of Instructions Simulated
-system.cpu0.cpi                              2.926664                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        2.926664                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.341686                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.341686                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads               174312752                       # number of integer regfile reads
-system.cpu0.int_regfile_writes               34607985                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                     3310                       # number of floating regfile reads
-system.cpu0.fp_regfile_writes                     918                       # number of floating regfile writes
-system.cpu0.misc_regfile_reads               79392098                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes                500989                       # number of misc regfile writes
-system.cpu0.icache.tags.replacements           399371                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.568929                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs            3842185                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           399883                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs             9.608273                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle       7067442000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.568929                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999158                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999158                       # Average percentage of cache occupancy
+system.cpu0.rob.rob_reads                   124649951                       # The number of ROB reads
+system.cpu0.rob.rob_writes                   83821170                       # The number of ROB writes
+system.cpu0.timesIdled                        1018994                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                      212377069                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                  4911896145                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                   26765511                       # Number of Instructions Simulated
+system.cpu0.committedOps                     35144806                       # Number of Ops (including micro ops) Simulated
+system.cpu0.committedInsts_total             26765511                       # Number of Instructions Simulated
+system.cpu0.cpi                             11.162070                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                       11.162070                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.089589                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.089589                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads               273626518                       # number of integer regfile reads
+system.cpu0.int_regfile_writes               37917674                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                     4695                       # number of floating regfile reads
+system.cpu0.fp_regfile_writes                     986                       # number of floating regfile writes
+system.cpu0.misc_regfile_reads              148789996                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes                678362                       # number of misc regfile writes
+system.cpu0.icache.tags.replacements           415188                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.568306                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs            4152259                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           415700                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs             9.988595                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle       7103550250                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.568306                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999157                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.999157                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          127                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          218                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          164                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          512                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses          4673316                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses         4673316                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst      3842185                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total        3842185                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst      3842185                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total         3842185                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst      3842185                       # number of overall hits
-system.cpu0.icache.overall_hits::total        3842185                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       431224                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       431224                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       431224                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        431224                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       431224                       # number of overall misses
-system.cpu0.icache.overall_misses::total       431224                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   5969029520                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total   5969029520                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst   5969029520                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total   5969029520                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst   5969029520                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total   5969029520                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst      4273409                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total      4273409                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst      4273409                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total      4273409                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst      4273409                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total      4273409                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.100909                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.100909                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.100909                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.100909                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.100909                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.100909                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13842.062408                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 13842.062408                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13842.062408                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 13842.062408                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13842.062408                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 13842.062408                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs         4009                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses          5015647                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses         5015647                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst      4152259                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total        4152259                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst      4152259                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total         4152259                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst      4152259                       # number of overall hits
+system.cpu0.icache.overall_hits::total        4152259                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       447663                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       447663                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       447663                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        447663                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       447663                       # number of overall misses
+system.cpu0.icache.overall_misses::total       447663                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   6158685000                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total   6158685000                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst   6158685000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total   6158685000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst   6158685000                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total   6158685000                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst      4599922                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total      4599922                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst      4599922                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total      4599922                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst      4599922                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total      4599922                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.097320                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.097320                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.097320                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.097320                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.097320                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.097320                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13757.413501                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 13757.413501                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13757.413501                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 13757.413501                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13757.413501                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 13757.413501                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs         4464                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              172                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              167                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    23.308140                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    26.730539                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        31316                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        31316                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst        31316                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        31316                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst        31316                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        31316                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       399908                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       399908                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       399908                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       399908                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       399908                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       399908                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   4860978096                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total   4860978096                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   4860978096                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total   4860978096                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   4860978096                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total   4860978096                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst      9448000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total      9448000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst      9448000                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total      9448000                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.093581                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.093581                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.093581                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.093581                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.093581                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.093581                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12155.240945                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12155.240945                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12155.240945                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12155.240945                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12155.240945                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12155.240945                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        31938                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        31938                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst        31938                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        31938                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst        31938                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        31938                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       415725                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       415725                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       415725                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       415725                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       415725                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       415725                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   5022987594                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total   5022987594                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   5022987594                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total   5022987594                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   5022987594                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total   5022987594                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst      9487250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total      9487250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst      9487250                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total      9487250                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.090377                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.090377                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.090377                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.090377                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.090377                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.090377                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12082.476623                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12082.476623                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12082.476623                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12082.476623                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12082.476623                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12082.476623                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements           275793                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          480.388822                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs            9427243                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           276305                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            34.118974                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle         43744250                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   480.388822                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.938259                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.938259                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          182                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          305                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           25                       # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         45827663                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        45827663                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data      5876905                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        5876905                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      3228758                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       3228758                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       139532                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       139532                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       137231                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       137231                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data      9105663                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total         9105663                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data      9105663                       # number of overall hits
-system.cpu0.dcache.overall_hits::total        9105663                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       393187                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       393187                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1586487                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      1586487                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         8903                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total         8903                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data         7768                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total         7768                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      1979674                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       1979674                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      1979674                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      1979674                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   5526786247                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total   5526786247                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  79724845605                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  79724845605                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data     91251732                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total     91251732                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     50083768                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total     50083768                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  85251631852                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  85251631852                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  85251631852                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  85251631852                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      6270092                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      6270092                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      4815245                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      4815245                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       148435                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       148435                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       144999                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       144999                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     11085337                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     11085337                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     11085337                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     11085337                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.062708                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.062708                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.329472                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.329472                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.059979                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.059979                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.053573                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.053573                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.178585                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.178585                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.178585                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.178585                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14056.380926                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 14056.380926                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50252.441782                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 50252.441782                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10249.548691                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10249.548691                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  6447.446962                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  6447.446962                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 43063.469971                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 43063.469971                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 43063.469971                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 43063.469971                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs         8922                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets         7566                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs              589                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets            136                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    15.147708                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    55.632353                       # average number of cycles each access was blocked
+system.cpu0.dcache.tags.replacements           298882                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          483.456705                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           10027143                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           299266                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            33.505787                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle         44230250                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   483.456705                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.944251                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.944251                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024          384                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2          384                       # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024     0.750000                       # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses         48541082                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        48541082                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data      6144970                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        6144970                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      3563655                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       3563655                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       144672                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       144672                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       142233                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       142233                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data      9708625                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total         9708625                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data      9708625                       # number of overall hits
+system.cpu0.dcache.overall_hits::total        9708625                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       393929                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       393929                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      1644577                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      1644577                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         9244                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total         9244                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data         7866                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total         7866                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      2038506                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       2038506                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      2038506                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      2038506                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   5542234631                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total   5542234631                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  82471404032                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  82471404032                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data     94602484                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total     94602484                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     50293768                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total     50293768                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  88013638663                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  88013638663                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  88013638663                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  88013638663                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      6538899                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      6538899                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      5208232                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      5208232                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       153916                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       153916                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       150099                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       150099                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     11747131                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     11747131                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     11747131                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     11747131                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.060244                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.060244                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.315765                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.315765                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.060059                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.060059                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.052405                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.052405                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.173532                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.173532                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.173532                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.173532                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14069.120656                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 14069.120656                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50147.487185                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 50147.487185                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10233.933795                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10233.933795                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  6393.817442                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  6393.817442                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 43175.560270                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 43175.560270                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 43175.560270                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 43175.560270                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs        10878                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets         5936                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs              678                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets            116                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    16.044248                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    51.172414                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       256103                       # number of writebacks
-system.cpu0.dcache.writebacks::total           256103                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       203673                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       203673                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1455296                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      1455296                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data          469                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total          469                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      1658969                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      1658969                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      1658969                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      1658969                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       189514                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       189514                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       131191                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       131191                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         8434                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8434                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         7768                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total         7768                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       320705                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       320705                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       320705                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       320705                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2409533443                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   2409533443                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   5292752283                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   5292752283                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     69541268                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     69541268                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     34547232                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     34547232                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data         2000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total         2000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   7702285726                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total   7702285726                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   7702285726                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total   7702285726                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  13436185037                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  13436185037                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1206083884                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1206083884                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  14642268921                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  14642268921                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.030225                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.030225                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.027245                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.027245                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.056819                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.056819                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.053573                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.053573                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.028931                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.028931                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.028931                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.028931                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12714.276745                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12714.276745                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40343.867209                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40343.867209                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data  8245.348352                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8245.348352                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  4447.377961                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  4447.377961                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks       278268                       # number of writebacks
+system.cpu0.dcache.writebacks::total           278268                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       201648                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       201648                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1493557                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      1493557                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data          632                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total          632                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      1695205                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      1695205                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      1695205                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      1695205                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       192281                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       192281                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       151020                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       151020                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         8612                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8612                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         7866                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total         7866                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       343301                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       343301                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       343301                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       343301                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2438332267                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   2438332267                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   6681240000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   6681240000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     70543016                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     70543016                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     34562232                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     34562232                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data         1000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total         1000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   9119572267                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total   9119572267                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   9119572267                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total   9119572267                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 120538982283                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 120538982283                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1232045382                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1232045382                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 121771027665                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 121771027665                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.029406                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.029406                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.028996                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.028996                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.055953                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.055953                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.052405                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.052405                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.029224                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.029224                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.029224                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.029224                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12681.087923                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12681.087923                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44240.762813                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 44240.762813                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data  8191.246633                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8191.246633                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  4393.876430                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  4393.876430                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24016.731033                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24016.731033                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24016.731033                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24016.731033                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26564.362664                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26564.362664                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26564.362664                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26564.362664                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
@@ -2058,15 +1594,15 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups                9293568                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted          7630023                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect           416409                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups             5939121                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits                5050753                       # Number of BTB hits
+system.cpu1.branchPred.lookups                8689698                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted          7082612                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect           415349                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups             5570453                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits                4730059                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            85.042096                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS                 798930                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect             43976                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            84.913363                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS                 759549                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect             43595                       # Number of incorrect RAS predictions.
 system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -2090,25 +1626,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    42973192                       # DTB read hits
-system.cpu1.dtb.read_misses                     37885                       # DTB read misses
-system.cpu1.dtb.write_hits                    6980403                       # DTB write hits
-system.cpu1.dtb.write_misses                    10788                       # DTB write misses
+system.cpu1.dtb.read_hits                    21626734                       # DTB read hits
+system.cpu1.dtb.read_misses                     38691                       # DTB read misses
+system.cpu1.dtb.write_hits                    6575784                       # DTB write hits
+system.cpu1.dtb.write_misses                    12298                       # DTB write misses
 system.cpu1.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    1925                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                     2835                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.flush_entries                    1712                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                     3023                       # Number of TLB faults due to alignment restrictions
 system.cpu1.dtb.prefetch_faults                   279                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                      681                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                43011077                       # DTB read accesses
-system.cpu1.dtb.write_accesses                6991191                       # DTB write accesses
+system.cpu1.dtb.perms_faults                      600                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                21665425                       # DTB read accesses
+system.cpu1.dtb.write_accesses                6588082                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         49953595                       # DTB hits
-system.cpu1.dtb.misses                          48673                       # DTB misses
-system.cpu1.dtb.accesses                     50002268                       # DTB accesses
+system.cpu1.dtb.hits                         28202518                       # DTB hits
+system.cpu1.dtb.misses                          50989                       # DTB misses
+system.cpu1.dtb.accesses                     28253507                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -2130,8 +1666,8 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.inst_hits                     7723190                       # ITB inst hits
-system.cpu1.itb.inst_misses                      5562                       # ITB inst misses
+system.cpu1.itb.inst_hits                     7394895                       # ITB inst hits
+system.cpu1.itb.inst_misses                      5860                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
@@ -2140,544 +1676,546 @@ system.cpu1.itb.flush_tlb                           4                       # Nu
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
 system.cpu1.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                    1359                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                    1207                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                     1471                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                     1503                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                 7728752                       # ITB inst accesses
-system.cpu1.itb.hits                          7723190                       # DTB hits
-system.cpu1.itb.misses                           5562                       # DTB misses
-system.cpu1.itb.accesses                      7728752                       # DTB accesses
-system.cpu1.numCycles                       413796923                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                 7400755                       # ITB inst accesses
+system.cpu1.itb.hits                          7394895                       # DTB hits
+system.cpu1.itb.misses                           5860                       # DTB misses
+system.cpu1.itb.accesses                      7400755                       # DTB accesses
+system.cpu1.numCycles                       185247782                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles          19367440                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                      61322975                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                    9293568                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches           5849683                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                     13369526                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles                3346649                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles                     69265                       # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.BlockedCycles              80967245                       # Number of cycles fetch has spent blocked
-system.cpu1.fetch.MiscStallCycles                6008                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles        41697                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles      1506074                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles          288                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                  7721399                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes               552563                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes                   2913                       # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples         117616541                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             0.638291                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            1.959867                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles          18767441                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                      58413381                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                    8689698                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches           5489608                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                     12630025                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles                3326163                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles                     70879                       # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.BlockedCycles              38401480                       # Number of cycles fetch has spent blocked
+system.cpu1.fetch.MiscStallCycles                5864                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles        46813                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles      1518730                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles          309                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                  7393189                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes               549179                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes                   3073                       # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples          73717325                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             0.969397                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            2.351920                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0               104254528     88.64%     88.64% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                  816257      0.69%     89.33% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                  960958      0.82%     90.15% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                 1713992      1.46%     91.61% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4                 1419991      1.21%     92.81% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5                  586388      0.50%     93.31% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6                 1955965      1.66%     94.98% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7                  421912      0.36%     95.34% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8                 5486550      4.66%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0                61095045     82.88%     82.88% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                  712004      0.97%     83.84% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                  939814      1.27%     85.12% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                 1614257      2.19%     87.31% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4                 1180828      1.60%     88.91% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5                  579149      0.79%     89.70% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6                 1971485      2.67%     92.37% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7                  418985      0.57%     92.94% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8                 5205758      7.06%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total           117616541                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.022459                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       0.148196                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                20958094                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles             81738883                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                 11922126                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles               807725                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles               2189713                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved             1139186                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred               101010                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts              71114524                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts               335626                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles               2189713                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles                22150930                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles               33873368                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles      43341870                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                 11481154                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles              4579506                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts              67156903                       # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents                  160                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents                681335                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LSQFullEvents              3069410                       # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.FullRegisterEvents             515                       # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands           70770910                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups            313189992                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups       286825978                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups             6578                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps             50413534                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                20357376                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts            766049                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts        705865                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                  8415941                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads            12847707                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores            8121662                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads          1063533                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores         1519311                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                  61868936                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded            1182413                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                 88920941                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued            95302                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined       13575964                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined     36252507                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved        283075                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples    117616541                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.756024                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.499146                       # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total            73717325                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.046909                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       0.315326                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles                19856835                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles             39689565                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                 11370888                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles               621997                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles               2178040                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved             1113164                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred                99384                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts              67504859                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts               329486                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles               2178040                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles                20884497                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles               13732674                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles      23091492                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                 10921071                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles              2909551                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts              63553177                       # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents                  150                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents                495727                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LSQFullEvents              1775459                       # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.FullRegisterEvents             454                       # Number of times there has been no free registers
+system.cpu1.rename.RenamedOperands           67243012                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups            295535307                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups       271726361                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups             4962                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps             47019288                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                20223723                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts            581683                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts        523637                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                  6484055                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads            11835207                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores            7683859                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads           982260                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores         1485488                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                  58475771                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded             951228                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                 65019700                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued            99369                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined       13400197                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined     36106127                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved        236520                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples     73717325                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.882014                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.585621                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0           86757290     73.76%     73.76% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1            9288969      7.90%     81.66% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2            4169197      3.54%     85.21% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3            3602778      3.06%     88.27% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4           10372979      8.82%     97.09% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5            1998574      1.70%     98.79% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6            1065464      0.91%     99.69% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7             282646      0.24%     99.93% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8              78644      0.07%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0           50542925     68.56%     68.56% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1            7121407      9.66%     78.22% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2            4031042      5.47%     83.69% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3            3362905      4.56%     88.25% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4            5367239      7.28%     95.53% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5            1894348      2.57%     98.10% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6            1048738      1.42%     99.53% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7             275398      0.37%     99.90% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8              73323      0.10%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total      117616541                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total       73717325                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                  32554      0.41%      0.41% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                   991      0.01%      0.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                      0      0.00%      0.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      0.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      0.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      0.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%      0.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      0.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      0.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      0.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      0.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      0.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      0.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      0.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      0.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%      0.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      0.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%      0.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      0.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      0.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      0.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      0.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      0.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      0.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      0.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      0.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      0.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      0.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      0.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead               7574498     95.71%     96.13% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite               306293      3.87%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                  33869      1.02%      1.02% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                   996      0.03%      1.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                      0      0.00%      1.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      1.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      1.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      1.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%      1.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      1.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      1.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      1.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      1.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      1.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      1.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      1.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      1.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%      1.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      1.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%      1.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      1.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      1.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      1.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      1.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      1.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      1.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      1.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      1.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      1.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      1.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      1.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead               2994112     90.44%     91.49% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite               281623      8.51%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass            14269      0.02%      0.02% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu             37628828     42.32%     42.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult               61233      0.07%     42.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     42.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     42.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     42.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     42.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     42.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     42.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     42.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     42.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     42.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     42.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     42.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     42.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                 12      0.00%     42.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     42.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     42.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     42.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc             10      0.00%     42.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     42.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     42.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     42.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     42.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     42.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     42.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc          1700      0.00%     42.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     42.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc           10      0.00%     42.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     42.40% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead            43862772     49.33%     91.73% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite            7352107      8.27%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass            12895      0.02%      0.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu             35505233     54.61%     54.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult               59031      0.09%     54.72% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     54.72% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     54.72% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     54.72% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     54.72% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     54.72% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     54.72% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     54.72% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     54.72% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     54.72% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   1      0.00%     54.72% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     54.72% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     54.72% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                 14      0.00%     54.72% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     54.72% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     54.72% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     54.72% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc             10      0.00%     54.72% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     54.72% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     54.72% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     54.72% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     54.72% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     54.72% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     54.72% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc          1556      0.00%     54.72% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     54.72% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc           11      0.00%     54.72% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     54.72% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead            22501549     34.61%     89.33% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite            6939400     10.67%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total              88920941                       # Type of FU issued
-system.cpu1.iq.rate                          0.214890                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                    7914336                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.089004                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads         303501191                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes         76636250                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses     54272980                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads              15357                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes              8072                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses         6822                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses              96812856                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                   8152                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads          352971                       # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total              65019700                       # Type of FU issued
+system.cpu1.iq.rate                          0.350988                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                    3310600                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.050917                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads         207206368                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes         72837982                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses     50730101                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads              11167                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes              5978                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses         5058                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses              68311542                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                   5863                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads          343642                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads      2867339                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses         4206                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation        17562                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores      1118674                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads      2877094                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses         3994                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation        17361                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores      1094953                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads     31965666                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked       675765                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads     11606945                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked       675630                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles               2189713                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles               26359334                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles               362918                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts           63155083                       # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts           115853                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts             12847707                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts             8121662                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts            886435                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                 65883                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents                 4133                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents         17562                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect        204959                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect       158107                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts              363066                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts             87182630                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts             43355393                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts          1738311                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles               2178040                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles               10295917                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles               191116                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts           59545170                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts           114100                       # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts             11835207                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts             7683859                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts            664311                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                 56460                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents                 4454                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents         17361                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect        204103                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect       160517                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts              364620                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts             63283569                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts             21990431                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts          1736131                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                       103734                       # number of nop insts executed
-system.cpu1.iew.exec_refs                    50641864                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches                 7379983                       # Number of branches executed
-system.cpu1.iew.exec_stores                   7286471                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.210689                       # Inst execution rate
-system.cpu1.iew.wb_sent                      86418752                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                     54279802                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                 30301489                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                 53896999                       # num instructions consuming a value
+system.cpu1.iew.exec_nop                       118171                       # number of nop insts executed
+system.cpu1.iew.exec_refs                    28863200                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches                 6787528                       # Number of branches executed
+system.cpu1.iew.exec_stores                   6872769                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.341616                       # Inst execution rate
+system.cpu1.iew.wb_sent                      62514610                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                     50735159                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                 28199774                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                 51433237                       # num instructions consuming a value
 system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate                      0.131175                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.562211                       # average fanout of values written-back
+system.cpu1.iew.wb_rate                      0.273877                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.548279                       # average fanout of values written-back
 system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts       13446942                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls         899338                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts           317124                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples    115426828                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.426339                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.379011                       # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts       13377367                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls         714708                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts           317605                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples     71539285                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.639790                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.672504                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0     97406330     84.39%     84.39% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1      9593486      8.31%     92.70% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2      2169699      1.88%     94.58% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3      1301842      1.13%     95.71% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4       990133      0.86%     96.56% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5       584983      0.51%     97.07% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6      1011097      0.88%     97.95% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7       533551      0.46%     98.41% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8      1835707      1.59%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0     55665383     77.81%     77.81% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1      7811223     10.92%     88.73% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2      2101815      2.94%     91.67% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3      1189986      1.66%     93.33% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4       946066      1.32%     94.65% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5       613597      0.86%     95.51% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6       912617      1.28%     96.79% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7       531458      0.74%     97.53% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8      1767140      2.47%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total    115426828                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts            38871006                       # Number of instructions committed
-system.cpu1.commit.committedOps              49210952                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total     71539285                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts            36096592                       # Number of instructions committed
+system.cpu1.commit.committedOps              45770088                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                      16983356                       # Number of memory references committed
-system.cpu1.commit.loads                      9980368                       # Number of loads committed
-system.cpu1.commit.membars                     195496                       # Number of memory barriers committed
-system.cpu1.commit.branches                   6424614                       # Number of branches committed
-system.cpu1.commit.fp_insts                      6758                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                 43923604                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls              553281                       # Number of function calls committed.
-system.cpu1.commit.bw_lim_events              1835707                       # number cycles where commit BW limit reached
+system.cpu1.commit.refs                      15547019                       # Number of memory references committed
+system.cpu1.commit.loads                      8958113                       # Number of loads committed
+system.cpu1.commit.membars                     191016                       # Number of memory barriers committed
+system.cpu1.commit.branches                   5856523                       # Number of branches committed
+system.cpu1.commit.fp_insts                      5022                       # Number of committed floating point instructions.
+system.cpu1.commit.int_insts                 40800338                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls              520894                       # Number of function calls committed.
+system.cpu1.commit.bw_lim_events              1767140                       # number cycles where commit BW limit reached
 system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads                   175182622                       # The number of ROB reads
-system.cpu1.rob.rob_writes                  127588630                       # The number of ROB writes
-system.cpu1.timesIdled                        1428402                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                      296180382                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                  4796803337                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                   38801367                       # Number of Instructions Simulated
-system.cpu1.committedOps                     49141313                       # Number of Ops (including micro ops) Simulated
-system.cpu1.committedInsts_total             38801367                       # Number of Instructions Simulated
-system.cpu1.cpi                             10.664493                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                       10.664493                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.093769                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.093769                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads               391717330                       # number of integer regfile reads
-system.cpu1.int_regfile_writes               56386728                       # number of integer regfile writes
-system.cpu1.fp_regfile_reads                     5093                       # number of floating regfile reads
-system.cpu1.fp_regfile_writes                    2344                       # number of floating regfile writes
-system.cpu1.misc_regfile_reads              202967536                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes                722997                       # number of misc regfile writes
-system.cpu1.icache.tags.replacements           614130                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          498.669942                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs            7060189                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs           614642                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            11.486669                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle      74938249500                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   498.669942                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.973965                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.973965                       # Average percentage of cache occupancy
+system.cpu1.rob.rob_reads                   127901171                       # The number of ROB reads
+system.cpu1.rob.rob_writes                  120555711                       # The number of ROB writes
+system.cpu1.timesIdled                         777241                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                      111530457                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                  5026003021                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                   36015814                       # Number of Instructions Simulated
+system.cpu1.committedOps                     45689310                       # Number of Ops (including micro ops) Simulated
+system.cpu1.committedInsts_total             36015814                       # Number of Instructions Simulated
+system.cpu1.cpi                              5.143512                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        5.143512                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.194420                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.194420                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads               292255401                       # number of integer regfile reads
+system.cpu1.int_regfile_writes               53047565                       # number of integer regfile writes
+system.cpu1.fp_regfile_reads                     3797                       # number of floating regfile reads
+system.cpu1.fp_regfile_writes                    1766                       # number of floating regfile writes
+system.cpu1.misc_regfile_reads              133121160                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes                545345                       # number of misc regfile writes
+system.cpu1.icache.tags.replacements           600500                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          498.750005                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs            6745926                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs           601012                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            11.224278                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle      74974413000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   498.750005                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.974121                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.974121                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2          512                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0          130                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1          225                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2          151                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::3            6                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses          8336018                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses         8336018                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst      7060189                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total        7060189                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst      7060189                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total         7060189                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst      7060189                       # number of overall hits
-system.cpu1.icache.overall_hits::total        7060189                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       661158                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       661158                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       661158                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        661158                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       661158                       # number of overall misses
-system.cpu1.icache.overall_misses::total       661158                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   8979670253                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   8979670253                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   8979670253                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   8979670253                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   8979670253                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   8979670253                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst      7721347                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total      7721347                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst      7721347                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total      7721347                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst      7721347                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total      7721347                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.085627                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.085627                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.085627                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.085627                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.085627                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.085627                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13581.731225                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 13581.731225                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13581.731225                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 13581.731225                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13581.731225                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 13581.731225                       # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs         3157                       # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets          541                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs              208                       # number of cycles access was blocked
+system.cpu1.icache.tags.tag_accesses          7994182                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses         7994182                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst      6745926                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total        6745926                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst      6745926                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total         6745926                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst      6745926                       # number of overall hits
+system.cpu1.icache.overall_hits::total        6745926                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       647211                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       647211                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       647211                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        647211                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       647211                       # number of overall misses
+system.cpu1.icache.overall_misses::total       647211                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   8801556837                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   8801556837                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   8801556837                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   8801556837                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   8801556837                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   8801556837                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst      7393137                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total      7393137                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst      7393137                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total      7393137                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst      7393137                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total      7393137                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.087542                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.087542                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.087542                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.087542                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.087542                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.087542                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13599.207734                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 13599.207734                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13599.207734                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 13599.207734                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13599.207734                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 13599.207734                       # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs         3107                       # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles::no_targets          341                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs              199                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_targets              1                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs    15.177885                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets          541                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs    15.613065                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets          341                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        46487                       # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total        46487                       # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst        46487                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total        46487                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst        46487                       # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total        46487                       # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       614671                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       614671                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       614671                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       614671                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       614671                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       614671                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   7323309836                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   7323309836                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   7323309836                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   7323309836                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   7323309836                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   7323309836                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      3568000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      3568000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      3568000                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total      3568000                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.079607                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.079607                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.079607                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.079607                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.079607                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.079607                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11914.194481                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11914.194481                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11914.194481                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 11914.194481                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11914.194481                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 11914.194481                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        46165                       # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total        46165                       # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst        46165                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total        46165                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst        46165                       # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total        46165                       # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       601046                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       601046                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       601046                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       601046                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       601046                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       601046                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   7178040035                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   7178040035                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   7178040035                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   7178040035                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   7178040035                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   7178040035                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      3605250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      3605250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      3605250                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total      3605250                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.081298                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.081298                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.081298                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.081298                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.081298                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.081298                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11942.580160                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11942.580160                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11942.580160                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 11942.580160                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11942.580160                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 11942.580160                       # average overall mshr miss latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.tags.replacements           363457                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          485.510277                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs           13025047                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs           363822                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            35.800603                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle      70981354000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   485.510277                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.948262                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.948262                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          365                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2          365                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.712891                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses         60307713                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses        60307713                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data      8518372                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        8518372                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      4270609                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       4270609                       # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        99866                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        99866                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        97035                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        97035                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data     12788981                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total        12788981                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data     12788981                       # number of overall hits
-system.cpu1.dcache.overall_hits::total       12788981                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       402659                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       402659                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data      1566002                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total      1566002                       # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        14224                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total        14224                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data        10931                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total        10931                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data      1968661                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total       1968661                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data      1968661                       # number of overall misses
-system.cpu1.dcache.overall_misses::total      1968661                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   6122123976                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   6122123976                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  79209493026                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total  79209493026                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    131211992                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total    131211992                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     58251087                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total     58251087                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data  85331617002                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total  85331617002                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data  85331617002                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total  85331617002                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      8921031                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      8921031                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      5836611                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      5836611                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data       114090                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total       114090                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data       107966                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total       107966                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data     14757642                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total     14757642                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data     14757642                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total     14757642                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.045136                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.045136                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.268307                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.268307                       # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.124674                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.124674                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.101245                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.101245                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.133399                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.133399                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.133399                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.133399                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15204.239756                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 15204.239756                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 50580.710003                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 50580.710003                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  9224.690101                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  9224.690101                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  5328.980606                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  5328.980606                       # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 43345.003026                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 43345.003026                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 43345.003026                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 43345.003026                       # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs        29359                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets        20069                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs             3274                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets            177                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs     8.967318                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets   113.384181                       # average number of cycles each access was blocked
+system.cpu1.dcache.tags.replacements           339082                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          482.965075                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs           12423447                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs           339594                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            36.583235                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle      71024759250                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   482.965075                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.943291                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.943291                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0          174                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::1          319                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2           18                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses         57544569                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        57544569                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data      8247311                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        8247311                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      3935666                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       3935666                       # number of WriteReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        94453                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        94453                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        92037                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        92037                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data     12182977                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total        12182977                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data     12182977                       # number of overall hits
+system.cpu1.dcache.overall_hits::total       12182977                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       400036                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       400036                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data      1501327                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total      1501327                       # number of WriteReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        13642                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total        13642                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data        10758                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total        10758                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data      1901363                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total       1901363                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data      1901363                       # number of overall misses
+system.cpu1.dcache.overall_misses::total      1901363                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   6052529769                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   6052529769                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  75305143416                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total  75305143416                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    124772740                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total    124772740                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     57202570                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total     57202570                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data  81357673185                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total  81357673185                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data  81357673185                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total  81357673185                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      8647347                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      8647347                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      5436993                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      5436993                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data       108095                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total       108095                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data       102795                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total       102795                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data     14084340                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total     14084340                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data     14084340                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total     14084340                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.046261                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.046261                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.276132                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.276132                       # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.126204                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.126204                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.104655                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.104655                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.134998                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.134998                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.134998                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.134998                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15129.962726                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 15129.962726                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 50159.054900                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 50159.054900                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  9146.220496                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  9146.220496                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  5317.212307                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  5317.212307                       # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 42789.132420                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 42789.132420                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 42789.132420                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 42789.132420                       # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs        27478                       # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets        17677                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs             3226                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets            175                       # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs     8.517669                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets   101.011429                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks       327725                       # number of writebacks
-system.cpu1.dcache.writebacks::total           327725                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       171279                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total       171279                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data      1402802                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total      1402802                       # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data         1455                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total         1455                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data      1574081                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total      1574081                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data      1574081                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total      1574081                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       231380                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total       231380                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       163200                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total       163200                       # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data        12769                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total        12769                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        10931                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total        10931                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       394580                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       394580                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       394580                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       394580                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   2885564133                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   2885564133                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   7076211500                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   7076211500                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     89844256                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     89844256                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     36388913                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     36388913                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data         1000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total         1000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   9961775633                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   9961775633                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   9961775633                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   9961775633                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169230997009                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169230997009                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  25854670209                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total  25854670209                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 195085667218                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 195085667218                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.025936                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.025936                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.027961                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.027961                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.111920                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.111920                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.101245                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.101245                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.026737                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.026737                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.026737                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.026737                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12471.104387                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12471.104387                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 43359.139093                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 43359.139093                       # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  7036.123111                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  7036.123111                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  3328.964688                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  3328.964688                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25246.529558                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25246.529558                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 25246.529558                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 25246.529558                       # average overall mshr miss latency
+system.cpu1.dcache.writebacks::writebacks       304166                       # number of writebacks
+system.cpu1.dcache.writebacks::total           304166                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       172051                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total       172051                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data      1358464                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total      1358464                       # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data         1244                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total         1244                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data      1530515                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total      1530515                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data      1530515                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total      1530515                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       227985                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total       227985                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       142863                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total       142863                       # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data        12398                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total        12398                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        10758                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total        10758                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       370848                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       370848                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       370848                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       370848                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   2835218608                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   2835218608                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   5632564954                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   5632564954                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     86730259                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     86730259                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     35684430                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     35684430                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   8467783562                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   8467783562                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   8467783562                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   8467783562                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  62130810008                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total  62130810008                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  25850406364                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total  25850406364                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data  87981216372                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total  87981216372                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.026365                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.026365                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.026276                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.026276                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.114695                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.114695                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.104655                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.104655                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.026331                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.026331                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.026331                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.026331                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12435.987490                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12435.987490                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 39426.338198                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 39426.338198                       # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  6995.504033                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  6995.504033                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  3317.013385                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  3317.013385                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22833.569446                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22833.569446                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22833.569446                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22833.569446                       # average overall mshr miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
@@ -2701,18 +2239,18 @@ system.iocache.avg_blocked_cycles::no_mshrs          nan                       #
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1519280505301                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1519280505301                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1519280505301                       # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1519280505301                       # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1737834287366                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1737834287366                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1737834287366                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1737834287366                       # number of overall MSHR uncacheable cycles
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   42637                       # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce                   45161                       # number of quiesce instructions executed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                   50394                       # number of quiesce instructions executed
+system.cpu1.kern.inst.quiesce                   47884                       # number of quiesce instructions executed
 
 ---------- End Simulation Statistics   ----------
index 2c40bbbf1e87b62e635297ab77b96de4db38faa3..0d3018ad7b67f0756f51b1c803b62ea0302f5f96 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.526127                       # Number of seconds simulated
-sim_ticks                                2526126762000                       # Number of ticks simulated
-final_tick                               2526126762000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.526170                       # Number of seconds simulated
+sim_ticks                                2526169857500                       # Number of ticks simulated
+final_tick                               2526169857500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  60304                       # Simulator instruction rate (inst/s)
-host_op_rate                                    77594                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2525902204                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 424400                       # Number of bytes of host memory used
-host_seconds                                  1000.09                       # Real time elapsed on the host
-sim_insts                                    60309150                       # Number of instructions simulated
-sim_ops                                      77600646                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  58326                       # Simulator instruction rate (inst/s)
+host_op_rate                                    75048                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2443063970                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 467448                       # Number of bytes of host memory used
+host_seconds                                  1034.02                       # Real time elapsed on the host
+sim_insts                                    60309637                       # Number of instructions simulated
+sim_ops                                      77601213                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::realview.clcd    119537664                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker         2752                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker         2880                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst            797888                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9093912                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            129432344                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       797888                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          797888                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      3783552                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.inst            797632                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9095320                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            129433624                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       797632                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          797632                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      3785024                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data        3016072                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6799624                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           6801096                       # Number of bytes written to this memory
 system.physmem.num_reads::realview.clcd      14942208                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker           43                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker           45                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              12467                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             142128                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total              15096848                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           59118                       # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu.inst              12463                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             142150                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total              15096868                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           59141                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data            754018                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               813136                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd        47320533                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker           1089                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               813159                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd        47319725                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker           1140                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.itb.walker             51                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               315854                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3599943                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                51237470                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          315854                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             315854                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1497768                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data             1193951                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2691719                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1497768                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd       47320533                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker          1089                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               315748                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3600439                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                51237103                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          315748                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             315748                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1498325                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data             1193931                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2692256                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1498325                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd       47319725                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker          1140                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.itb.walker            51                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              315854                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             4793894                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               53929189                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                      15096848                       # Number of read requests accepted
-system.physmem.writeReqs                       813136                       # Number of write requests accepted
-system.physmem.readBursts                    15096848                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     813136                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                963809856                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                   2388416                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   6900096                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 129432344                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                6799624                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                    37319                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                  705316                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           4693                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              943581                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              943177                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              939217                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              939246                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              943119                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              943143                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              939192                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              938854                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              943994                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              943547                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             939009                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             937977                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             943925                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             943586                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             939160                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             938802                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                6706                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                6463                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                6599                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                6631                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                6542                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                6795                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6787                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                6728                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7129                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                6879                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               6534                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6185                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7139                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               6761                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7032                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               6904                       # Per bank write bursts
+system.physmem.bw_total::cpu.inst              315748                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             4794370                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               53929359                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                      15096868                       # Number of read requests accepted
+system.physmem.writeReqs                       813159                       # Number of write requests accepted
+system.physmem.readBursts                    15096868                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     813159                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                960809152                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                   5390400                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   6824768                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 129433624                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                6801096                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                    84225                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                  706499                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs           4674                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0              943297                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              937033                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              936962                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              936535                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              942693                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              936569                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              936319                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              936043                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              943596                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              936992                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             936414                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             935912                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             943556                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             937007                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             937039                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             936676                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                6606                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                6375                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                6521                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                6552                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                6461                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                6711                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6720                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                6668                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7045                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                6826                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               6497                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6136                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7072                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               6672                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               6956                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               6819                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2526125654500                       # Total gap between requests
+system.physmem.totGap                    2526168741500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                      38                       # Read request sizes (log2)
 system.physmem.readPktSize::3                14942208                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  154602                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  154622                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                 754018                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  59118                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1175583                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                   1121241                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                   1077080                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                   3628602                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                   2607512                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                   2594359                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                   2599949                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                     53287                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                     57711                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                     21124                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                    20900                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                    20768                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                    20512                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                    20375                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                    20258                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                    20166                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                       91                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        7                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                        3                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                        1                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  59141                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1044851                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    985737                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                    938636                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                    947948                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                    933228                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                    933834                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                   2717841                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                   2709185                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                   3589675                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                     37568                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                    33871                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                    34960                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                    32201                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                    30053                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                    21726                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                    21191                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                      119                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                       11                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                        4                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                        4                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
@@ -144,619 +144,147 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                      4767                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                      5448                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                      4894                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                      5081                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                      5199                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                      4872                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                      4884                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                      4873                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                      4830                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                      4808                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                     4806                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                     4793                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                     4788                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                     4799                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                     4794                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     4795                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     4787                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4809                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4821                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     4801                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     4805                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5153                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                      137                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                       65                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                       11                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        85983                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean    11289.547748                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean    1006.032615                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev   16787.302098                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64-71          23431     27.25%     27.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-135        14045     16.33%     43.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192-199         2670      3.11%     46.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-263         2200      2.56%     49.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320-327         1296      1.51%     50.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-391         1149      1.34%     52.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448-455          926      1.08%     53.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-519          910      1.06%     54.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576-583          583      0.68%     54.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-647          573      0.67%     55.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704-711          527      0.61%     56.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-775          540      0.63%     56.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832-839          283      0.33%     57.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-903          315      0.37%     57.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960-967          148      0.17%     57.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1031          512      0.60%     58.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088-1095          103      0.12%     58.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152-1159          143      0.17%     58.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216-1223           77      0.09%     58.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280-1287          250      0.29%     58.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344-1351           57      0.07%     59.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408-1415          507      0.59%     59.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472-1479           36      0.04%     59.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536-1543          193      0.22%     59.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600-1607           17      0.02%     59.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664-1671          103      0.12%     60.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1728-1735           18      0.02%     60.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1792-1799           71      0.08%     60.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856-1863           17      0.02%     60.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1920-1927           58      0.07%     60.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984-1991           16      0.02%     60.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2048-2055          468      0.54%     60.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112-2119           10      0.01%     60.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2176-2183           32      0.04%     60.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2240-2247           13      0.02%     60.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2304-2311          249      0.29%     61.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2368-2375            8      0.01%     61.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2432-2439           28      0.03%     61.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2496-2503            7      0.01%     61.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2560-2567           30      0.03%     61.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2624-2631            8      0.01%     61.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2688-2695           18      0.02%     61.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2752-2759            6      0.01%     61.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2816-2823          116      0.13%     61.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2880-2887           10      0.01%     61.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2944-2951           18      0.02%     61.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3008-3015            4      0.00%     61.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3072-3079          420      0.49%     61.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3136-3143            7      0.01%     61.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3200-3207           24      0.03%     61.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3264-3271            6      0.01%     61.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3328-3335           25      0.03%     61.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3392-3399            6      0.01%     61.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3456-3463           21      0.02%     62.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3520-3527            6      0.01%     62.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3584-3591          157      0.18%     62.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3648-3655            5      0.01%     62.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3712-3719           17      0.02%     62.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3776-3783            9      0.01%     62.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3840-3847           20      0.02%     62.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3904-3911           11      0.01%     62.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3968-3975           15      0.02%     62.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4032-4039           13      0.02%     62.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4096-4103          363      0.42%     62.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4160-4167            9      0.01%     62.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4224-4231           13      0.02%     62.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4288-4295            7      0.01%     62.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4352-4359          108      0.13%     62.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4416-4423           18      0.02%     62.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4480-4487           14      0.02%     62.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4544-4551           12      0.01%     62.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4608-4615          161      0.19%     63.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4672-4679            8      0.01%     63.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4736-4743           15      0.02%     63.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4800-4807            2      0.00%     63.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4864-4871           23      0.03%     63.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4928-4935            6      0.01%     63.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4992-4999           14      0.02%     63.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5056-5063            4      0.00%     63.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5120-5127          356      0.41%     63.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5184-5191            5      0.01%     63.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5248-5255           11      0.01%     63.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5312-5319           11      0.01%     63.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5376-5383          163      0.19%     63.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5440-5447            2      0.00%     63.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5504-5511           16      0.02%     63.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5568-5575            2      0.00%     63.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5632-5639           50      0.06%     63.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5696-5703            6      0.01%     63.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5760-5767           13      0.02%     63.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5824-5831            4      0.00%     63.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5888-5895          197      0.23%     64.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5952-5959            3      0.00%     64.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6016-6023            9      0.01%     64.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6080-6087            7      0.01%     64.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6144-6151          223      0.26%     64.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6208-6215            4      0.00%     64.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6272-6279           13      0.02%     64.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6336-6343            5      0.01%     64.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6400-6407          140      0.16%     64.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6464-6471            2      0.00%     64.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6528-6535            8      0.01%     64.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6592-6599            2      0.00%     64.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6656-6663           88      0.10%     64.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6720-6727            2      0.00%     64.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6784-6791           14      0.02%     64.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6848-6855            3      0.00%     64.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6912-6919          158      0.18%     64.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6976-6983            6      0.01%     64.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7040-7047           14      0.02%     64.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7104-7111            1      0.00%     64.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7168-7175          345      0.40%     65.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7232-7239            1      0.00%     65.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7296-7303            5      0.01%     65.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7360-7367            8      0.01%     65.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7424-7431           13      0.02%     65.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7488-7495            4      0.00%     65.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7552-7559           18      0.02%     65.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7616-7623            6      0.01%     65.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7680-7687          141      0.16%     65.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7744-7751            2      0.00%     65.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7808-7815            6      0.01%     65.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7936-7943           41      0.05%     65.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8000-8007            2      0.00%     65.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8064-8071           10      0.01%     65.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8192-8199          399      0.46%     66.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8256-8263            1      0.00%     66.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8448-8455           36      0.04%     66.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8576-8583            2      0.00%     66.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8704-8711          130      0.15%     66.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8896-8903            2      0.00%     66.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8960-8967            5      0.01%     66.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9088-9095            1      0.00%     66.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9216-9223          341      0.40%     66.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9344-9351            3      0.00%     66.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9472-9479          145      0.17%     66.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9536-9543            1      0.00%     66.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9600-9607            2      0.00%     66.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9728-9735           78      0.09%     67.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9792-9799            2      0.00%     67.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9856-9863            3      0.00%     67.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9984-9991          133      0.15%     67.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10048-10055            2      0.00%     67.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10112-10119            3      0.00%     67.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10240-10247          212      0.25%     67.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10368-10375            2      0.00%     67.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10496-10503          150      0.17%     67.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10688-10695            1      0.00%     67.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10752-10759           41      0.05%     67.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10880-10887            1      0.00%     67.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10944-10951            2      0.00%     67.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11008-11015          153      0.18%     67.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11136-11143            4      0.00%     67.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11264-11271          349      0.41%     68.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11520-11527            8      0.01%     68.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11648-11655            3      0.00%     68.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11776-11783          141      0.16%     68.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11904-11911            3      0.00%     68.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11968-11975            1      0.00%     68.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12032-12039           94      0.11%     68.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12096-12103            2      0.00%     68.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12160-12167            4      0.00%     68.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12288-12295          334      0.39%     68.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12352-12359            1      0.00%     68.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12544-12551           13      0.02%     68.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12672-12679            3      0.00%     68.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12736-12743            1      0.00%     68.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12800-12807          141      0.16%     69.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12864-12871            1      0.00%     69.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12992-12999            1      0.00%     69.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13056-13063            6      0.01%     69.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13120-13127            1      0.00%     69.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13184-13191            2      0.00%     69.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13312-13319          399      0.46%     69.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13376-13383            1      0.00%     69.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13440-13447            1      0.00%     69.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13568-13575           94      0.11%     69.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13760-13767            2      0.00%     69.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13824-13831            2      0.00%     69.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13952-13959            3      0.00%     69.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14016-14023            1      0.00%     69.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14080-14087          214      0.25%     69.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14144-14151            2      0.00%     69.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14208-14215            4      0.00%     69.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14272-14279            1      0.00%     69.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14336-14343          420      0.49%     70.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14592-14599            5      0.01%     70.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14720-14727            1      0.00%     70.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14848-14855           22      0.03%     70.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14976-14983            1      0.00%     70.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15104-15111          141      0.16%     70.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15168-15175            1      0.00%     70.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15232-15239            1      0.00%     70.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15360-15367          335      0.39%     71.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15424-15431            1      0.00%     71.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15488-15495            1      0.00%     71.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15552-15559            1      0.00%     71.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15616-15623           80      0.09%     71.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15808-15815            2      0.00%     71.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15872-15879            5      0.01%     71.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15936-15943            2      0.00%     71.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16000-16007            2      0.00%     71.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16064-16071            1      0.00%     71.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16128-16135          143      0.17%     71.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16256-16263            6      0.01%     71.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16384-16391          673      0.78%     72.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16512-16519            1      0.00%     72.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16640-16647          144      0.17%     72.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16896-16903            7      0.01%     72.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16960-16967            2      0.00%     72.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17024-17031            1      0.00%     72.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17152-17159           81      0.09%     72.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17280-17287            2      0.00%     72.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17408-17415          336      0.39%     72.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17536-17543            2      0.00%     72.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17664-17671          135      0.16%     72.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17728-17735            1      0.00%     72.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17792-17799            4      0.00%     72.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17920-17927           25      0.03%     72.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18048-18055            1      0.00%     72.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18112-18119            1      0.00%     72.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18176-18183            6      0.01%     72.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18240-18247            1      0.00%     72.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18304-18311            2      0.00%     72.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18432-18439          419      0.49%     73.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18560-18567            2      0.00%     73.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18688-18695          214      0.25%     73.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18752-18759            1      0.00%     73.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18944-18951            4      0.00%     73.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19072-19079            1      0.00%     73.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19200-19207           97      0.11%     73.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19264-19271            2      0.00%     73.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19328-19335            2      0.00%     73.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19456-19463          391      0.45%     74.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19584-19591            1      0.00%     74.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19712-19719           10      0.01%     74.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19840-19847            3      0.00%     74.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19904-19911            1      0.00%     74.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19968-19975          139      0.16%     74.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20032-20039            1      0.00%     74.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20160-20167            2      0.00%     74.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20224-20231           13      0.02%     74.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20352-20359            4      0.00%     74.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20480-20487          331      0.38%     74.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20608-20615            1      0.00%     74.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20672-20679            1      0.00%     74.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20736-20743           94      0.11%     75.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20800-20807            1      0.00%     75.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20864-20871            1      0.00%     75.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20928-20935            2      0.00%     75.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20992-20999          142      0.17%     75.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21120-21127            2      0.00%     75.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21184-21191            1      0.00%     75.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21248-21255           13      0.02%     75.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21376-21383            2      0.00%     75.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21504-21511          343      0.40%     75.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21632-21639            3      0.00%     75.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21696-21703            1      0.00%     75.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21760-21767          150      0.17%     75.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21888-21895            1      0.00%     75.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21952-21959            1      0.00%     75.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22016-22023           38      0.04%     75.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22080-22087            1      0.00%     75.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22144-22151            3      0.00%     75.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22272-22279          148      0.17%     76.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22400-22407            2      0.00%     76.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22464-22471            1      0.00%     76.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22528-22535          208      0.24%     76.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22656-22663            1      0.00%     76.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22720-22727            2      0.00%     76.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22784-22791          129      0.15%     76.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22848-22855            1      0.00%     76.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23040-23047           76      0.09%     76.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23104-23111            1      0.00%     76.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23168-23175            2      0.00%     76.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23296-23303          148      0.17%     76.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23424-23431            1      0.00%     76.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23488-23495            1      0.00%     76.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23552-23559          338      0.39%     77.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23808-23815           10      0.01%     77.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23936-23943            2      0.00%     77.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24064-24071          128      0.15%     77.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24128-24135            1      0.00%     77.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24256-24263            2      0.00%     77.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24320-24327           34      0.04%     77.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24448-24455            4      0.00%     77.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24512-24519            1      0.00%     77.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24576-24583          281      0.33%     77.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24640-24647            2      0.00%     77.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24704-24711            3      0.00%     77.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24768-24775            1      0.00%     77.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24832-24839           36      0.04%     77.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24960-24967            1      0.00%     77.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25088-25095          132      0.15%     77.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25152-25159            1      0.00%     77.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25216-25223            1      0.00%     77.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25344-25351            9      0.01%     77.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25472-25479            2      0.00%     77.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25536-25543            1      0.00%     77.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25600-25607          331      0.38%     78.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25728-25735            1      0.00%     78.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25792-25799            1      0.00%     78.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25856-25863          146      0.17%     78.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25920-25927            1      0.00%     78.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25984-25991            1      0.00%     78.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26112-26119           78      0.09%     78.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26176-26183            1      0.00%     78.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26240-26247            2      0.00%     78.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26304-26311            1      0.00%     78.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26368-26375          128      0.15%     78.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26432-26439            1      0.00%     78.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26496-26503            6      0.01%     78.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26560-26567            1      0.00%     78.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26624-26631          207      0.24%     78.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26688-26695            1      0.00%     78.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26752-26759            3      0.00%     78.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26816-26823            1      0.00%     78.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26880-26887          146      0.17%     79.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26944-26951            3      0.00%     79.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27008-27015            1      0.00%     79.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27136-27143           38      0.04%     79.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27264-27271            1      0.00%     79.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27392-27399          151      0.18%     79.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27456-27463            1      0.00%     79.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27520-27527            3      0.00%     79.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27584-27591            2      0.00%     79.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27648-27655          337      0.39%     79.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27712-27719            1      0.00%     79.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27840-27847            2      0.00%     79.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27904-27911           13      0.02%     79.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27968-27975            1      0.00%     79.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28032-28039            1      0.00%     79.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28160-28167          141      0.16%     79.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28224-28231            1      0.00%     79.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28288-28295            1      0.00%     79.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28416-28423           97      0.11%     79.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28544-28551            5      0.01%     79.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28608-28615            4      0.00%     79.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28672-28679          328      0.38%     80.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28800-28807            1      0.00%     80.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28864-28871            1      0.00%     80.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28928-28935           12      0.01%     80.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29056-29063            2      0.00%     80.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29120-29127            1      0.00%     80.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29184-29191          141      0.16%     80.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29312-29319            1      0.00%     80.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29440-29447            7      0.01%     80.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29568-29575            3      0.00%     80.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29696-29703          399      0.46%     81.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29824-29831            1      0.00%     81.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29888-29895            2      0.00%     81.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29952-29959           90      0.10%     81.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30144-30151            2      0.00%     81.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30208-30215            5      0.01%     81.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30336-30343            1      0.00%     81.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30400-30407            1      0.00%     81.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30464-30471          214      0.25%     81.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30528-30535            1      0.00%     81.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30592-30599            3      0.00%     81.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30656-30663            1      0.00%     81.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30720-30727          415      0.48%     81.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30848-30855            2      0.00%     81.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30976-30983            5      0.01%     81.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31040-31047            1      0.00%     81.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31104-31111            1      0.00%     81.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31168-31175            3      0.00%     81.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31232-31239           21      0.02%     81.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31360-31367            2      0.00%     81.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31424-31431            1      0.00%     81.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31488-31495          138      0.16%     82.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31616-31623            3      0.00%     82.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31744-31751          338      0.39%     82.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31872-31879            2      0.00%     82.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31936-31943            1      0.00%     82.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32000-32007           78      0.09%     82.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32192-32199            1      0.00%     82.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32256-32263            9      0.01%     82.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32384-32391            1      0.00%     82.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32448-32455            2      0.00%     82.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32512-32519          145      0.17%     82.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32576-32583            1      0.00%     82.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32640-32647            1      0.00%     82.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32768-32775          671      0.78%     83.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32960-32967            1      0.00%     83.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33024-33031          141      0.16%     83.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33152-33159            1      0.00%     83.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33280-33287            7      0.01%     83.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33344-33351            1      0.00%     83.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33408-33415            4      0.00%     83.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33536-33543           85      0.10%     83.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33600-33607            2      0.00%     83.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33664-33671            1      0.00%     83.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33728-33735            1      0.00%     83.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33792-33799          348      0.40%     84.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34048-34055          136      0.16%     84.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34304-34311           21      0.02%     84.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34368-34375            1      0.00%     84.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34432-34439            3      0.00%     84.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34496-34503            2      0.00%     84.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34560-34567            8      0.01%     84.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34688-34695            2      0.00%     84.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34816-34823          412      0.48%     84.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35072-35079          212      0.25%     85.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35328-35335            5      0.01%     85.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35456-35463            3      0.00%     85.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35584-35591           91      0.11%     85.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35840-35847          392      0.46%     85.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35904-35911            1      0.00%     85.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35968-35975            2      0.00%     85.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36096-36103            8      0.01%     85.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36352-36359          140      0.16%     85.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36480-36487            4      0.00%     85.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36544-36551            1      0.00%     85.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36608-36615           12      0.01%     85.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36864-36871          327      0.38%     86.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36928-36935            1      0.00%     86.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37120-37127           90      0.10%     86.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37248-37255            1      0.00%     86.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37312-37319            1      0.00%     86.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37376-37383          141      0.16%     86.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37440-37447            1      0.00%     86.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37504-37511            3      0.00%     86.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37632-37639           10      0.01%     86.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37696-37703            1      0.00%     86.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37760-37767            1      0.00%     86.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37888-37895          334      0.39%     86.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37952-37959            1      0.00%     86.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38080-38087            1      0.00%     86.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38144-38151          149      0.17%     87.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38272-38279            1      0.00%     87.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38400-38407           37      0.04%     87.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38528-38535            2      0.00%     87.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38592-38599            1      0.00%     87.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38656-38663          150      0.17%     87.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38784-38791            1      0.00%     87.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38848-38855            1      0.00%     87.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38912-38919          205      0.24%     87.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39168-39175          127      0.15%     87.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39424-39431           76      0.09%     87.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39552-39559            2      0.00%     87.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39616-39623            1      0.00%     87.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39680-39687          146      0.17%     88.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39936-39943          330      0.38%     88.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40000-40007            1      0.00%     88.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40064-40071            1      0.00%     88.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40192-40199            7      0.01%     88.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40384-40391            1      0.00%     88.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40448-40455          132      0.15%     88.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40576-40583            4      0.00%     88.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40704-40711           37      0.04%     88.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40896-40903            1      0.00%     88.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40960-40967          277      0.32%     88.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41088-41095            1      0.00%     88.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41152-41159            1      0.00%     88.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41216-41223           34      0.04%     88.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41472-41479          128      0.15%     89.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41600-41607            1      0.00%     89.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41728-41735           10      0.01%     89.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41856-41863            1      0.00%     89.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41920-41927            1      0.00%     89.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41984-41991          332      0.39%     89.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42240-42247          142      0.17%     89.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42368-42375            1      0.00%     89.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42432-42439            1      0.00%     89.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42496-42503           76      0.09%     89.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42624-42631            2      0.00%     89.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42688-42695            1      0.00%     89.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42752-42759          131      0.15%     89.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42816-42823            1      0.00%     89.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42880-42887            2      0.00%     89.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43008-43015          208      0.24%     90.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43264-43271          145      0.17%     90.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43392-43399            1      0.00%     90.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43456-43463            1      0.00%     90.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43520-43527           36      0.04%     90.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43648-43655            2      0.00%     90.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43776-43783          152      0.18%     90.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43840-43847            1      0.00%     90.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44032-44039          340      0.40%     90.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44160-44167            1      0.00%     90.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44224-44231            1      0.00%     90.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44288-44295            8      0.01%     91.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44416-44423            2      0.00%     91.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44544-44551          144      0.17%     91.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44608-44615            2      0.00%     91.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44672-44679            2      0.00%     91.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44800-44807           94      0.11%     91.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45056-45063          328      0.38%     91.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45184-45191            3      0.00%     91.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45312-45319           12      0.01%     91.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45376-45383            1      0.00%     91.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45568-45575          141      0.16%     91.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45632-45639            1      0.00%     91.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45696-45703            1      0.00%     91.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45760-45767            1      0.00%     91.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45824-45831           11      0.01%     91.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45952-45959            1      0.00%     91.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46080-46087          393      0.46%     92.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46272-46279            1      0.00%     92.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46336-46343           91      0.11%     92.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46464-46471            1      0.00%     92.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46528-46535            1      0.00%     92.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46592-46599            4      0.00%     92.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46720-46727            2      0.00%     92.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46848-46855          211      0.25%     92.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47040-47047            2      0.00%     92.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47104-47111          416      0.48%     93.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47168-47175            1      0.00%     93.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47232-47239            1      0.00%     93.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47296-47303            1      0.00%     93.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47360-47367            4      0.00%     93.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47488-47495            2      0.00%     93.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47552-47559            1      0.00%     93.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47616-47623           32      0.04%     93.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47744-47751            1      0.00%     93.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47808-47815            2      0.00%     93.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47872-47879          141      0.16%     93.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47936-47943            1      0.00%     93.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48128-48135          335      0.39%     93.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48192-48199            1      0.00%     93.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48384-48391           74      0.09%     93.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48512-48519            1      0.00%     93.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48640-48647            4      0.00%     93.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48768-48775           71      0.08%     93.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48896-48903          140      0.16%     94.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48960-48967            4      0.00%     94.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::49024-49031            2      0.00%     94.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::49088-49095            1      0.00%     94.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::49152-49159         5017      5.83%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::49280-49287            1      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::49408-49415            1      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::49600-49607            1      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::49792-49799            1      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::50240-50247            1      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::50304-50311            3      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::50368-50375            1      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::50432-50439            2      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::50560-50567            2      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::50624-50631            1      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::50688-50695            4      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::50752-50759            1      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::50880-50887            2      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::51008-51015            3      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::51072-51079            1      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::51136-51143            1      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::51200-51207            1      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::51328-51335            2      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::51392-51399            1      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::51456-51463            2      0.00%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::51520-51527            1      0.00%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::51968-51975            2      0.00%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          85983                       # Bytes accessed per row activation
-system.physmem.totQLat                   365185132750                       # Total ticks spent queuing
-system.physmem.totMemAccLat              457949856500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                  75297645000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                 17467078750                       # Total ticks spent accessing banks
-system.physmem.avgQLat                       24249.44                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                     1159.87                       # Average bank access latency per DRAM burst
+system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     1817                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     1873                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     2182                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     4347                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     5586                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     5682                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     5693                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     5776                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     5810                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     5802                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     6376                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     6039                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     5895                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     6697                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     6177                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     5729                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     5693                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     5648                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     2143                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      730                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      681                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      684                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      666                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      587                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      630                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      595                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      576                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      583                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      547                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      567                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      540                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      538                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      536                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      533                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      534                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      533                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      534                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      533                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      544                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       949853                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean     1012.832967                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     998.129194                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev      95.600820                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127           4614      0.49%      0.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         3555      0.37%      0.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         1868      0.20%      1.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         1270      0.13%      1.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639          998      0.11%      1.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          697      0.07%      1.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          628      0.07%      1.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          802      0.08%      1.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151       935421     98.48%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         949853                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5541                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean      2709.372676                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev    121858.968991                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-524287         5537     99.93%     99.93% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::524288-1.04858e+06            2      0.04%     99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2.09715e+06-2.62144e+06            1      0.02%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06            1      0.02%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            5541                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5541                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        19.245082                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.302826                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        7.619957                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               3691     66.61%     66.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 16      0.29%     66.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                178      3.21%     70.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19               1008     18.19%     88.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                 44      0.79%     89.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 25      0.45%     89.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 20      0.36%     89.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 16      0.29%     90.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                  5      0.09%     90.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                  2      0.04%     90.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                  1      0.02%     90.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32                  1      0.02%     90.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::34                  1      0.02%     90.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::39                  2      0.04%     90.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40                  1      0.02%     90.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::41                143      2.58%     93.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::42                305      5.50%     98.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::43                 21      0.38%     98.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44                 14      0.25%     99.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::45                 20      0.36%     99.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::46                 15      0.27%     99.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::47                  5      0.09%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48                  3      0.05%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::49                  1      0.02%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::50                  3      0.05%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5541                       # Writes before turning the bus around for reads
+system.physmem.totQLat                   571195583500                       # Total ticks spent queuing
+system.physmem.totMemAccLat              674382869750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                  75063215000                       # Total ticks spent in databus transfers
+system.physmem.totBankLat                 28124071250                       # Total ticks spent accessing banks
+system.physmem.avgQLat                       38047.64                       # Average queueing delay per DRAM burst
+system.physmem.avgBankLat                     1873.36                       # Average bank access latency per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  30409.31                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         381.54                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           2.73                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  44921.00                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         380.34                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           2.70                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                       51.24                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        2.69                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           3.00                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       2.98                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           2.99                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       2.97                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         0.18                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        14.56                       # Average write queue length when enqueuing
-system.physmem.readRowHits                   14988012                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     93348                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   99.53                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  86.58                       # Row buffer hit rate for writes
-system.physmem.avgGap                       158776.13                       # Average gap between requests
-system.physmem.pageHitRate                      99.43                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               2.53                       # Percentage of time for which DRAM has all the banks in precharge state
+system.physmem.avgRdQLen                         7.11                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        26.53                       # Average write queue length when enqueuing
+system.physmem.readRowHits                   14041195                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     91389                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   93.53                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  85.68                       # Row buffer hit rate for writes
+system.physmem.avgGap                       158778.41                       # Average gap between requests
+system.physmem.pageHitRate                      93.47                       # Row buffer hit rate, read and write combined
+system.physmem.prechargeAllPercent               4.34                       # Percentage of time for which DRAM has all the banks in precharge state
 system.realview.nvmem.bytes_read::cpu.inst           64                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total            64                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_inst_read::cpu.inst           64                       # Number of instructions bytes read from this memory
@@ -769,58 +297,58 @@ system.realview.nvmem.bw_inst_read::cpu.inst           25
 system.realview.nvmem.bw_inst_read::total           25                       # Instruction read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu.inst           25                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total              25                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                     54878485                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq            16149469                       # Transaction distribution
-system.membus.trans_dist::ReadResp           16149469                       # Transaction distribution
+system.membus.throughput                     54878638                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq            16149508                       # Transaction distribution
+system.membus.trans_dist::ReadResp           16149508                       # Transaction distribution
 system.membus.trans_dist::WriteReq             763349                       # Transaction distribution
 system.membus.trans_dist::WriteResp            763349                       # Transaction distribution
-system.membus.trans_dist::Writeback             59118                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4690                       # Transaction distribution
+system.membus.trans_dist::Writeback             59141                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4671                       # Transaction distribution
 system.membus.trans_dist::SCUpgradeReq              3                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            4693                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            131452                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           131452                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            4674                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            131433                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           131433                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave      2383044                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port            2                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         3760                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio            2                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1885820                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      4272628                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1885845                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      4272653                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     29884416                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total     29884416                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total               34157044                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total               34157069                       # Packet count per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave      2390454                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port           64                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         7520                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio            4                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16694304                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     19092346                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16697056                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     19095098                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port    119537664                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.iocache.mem_side::total    119537664                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total           138630010                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus              138630010                       # Total data (bytes)
+system.membus.tot_pkt_size::total           138632762                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus              138632762                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy          1486866000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy          1487078000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy                1000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             3686500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             3653000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer4.occupancy                1500                       # Layer occupancy (ticks)
 system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer6.occupancy         17361359500                       # Layer occupancy (ticks)
+system.membus.reqLayer6.occupancy         17362845500                       # Layer occupancy (ticks)
 system.membus.reqLayer6.utilization               0.7                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         4731205438                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         4737809043                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
-system.membus.respLayer2.occupancy        33737720957                       # Layer occupancy (ticks)
-system.membus.respLayer2.utilization              1.3                       # Layer utilization (%)
+system.membus.respLayer2.occupancy        37210156152                       # Layer occupancy (ticks)
+system.membus.respLayer2.utilization              1.5                       # Layer utilization (%)
 system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
 system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
-system.iobus.throughput                      48266825                       # Throughput (bytes/s)
+system.iobus.throughput                      48266001                       # Throughput (bytes/s)
 system.iobus.trans_dist::ReadReq             16125556                       # Transaction distribution
 system.iobus.trans_dist::ReadResp            16125556                       # Transaction distribution
 system.iobus.trans_dist::WriteReq                8174                       # Transaction distribution
@@ -930,18 +458,18 @@ system.iobus.reqLayer25.occupancy         14942208000                       # La
 system.iobus.reqLayer25.utilization               0.6                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy          2374870000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.1                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy         40922322043                       # Layer occupancy (ticks)
-system.iobus.respLayer1.utilization               1.6                       # Layer utilization (%)
+system.iobus.respLayer1.occupancy         37245686848                       # Layer occupancy (ticks)
+system.iobus.respLayer1.utilization               1.5                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                14743416                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          11827380                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            704687                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              9504018                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 7655579                       # Number of BTB hits
+system.cpu.branchPred.lookups                14755327                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          11837490                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            706705                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              9530563                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 7665782                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             80.550973                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1397368                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              72480                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             80.433674                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1400618                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              72971                       # Number of incorrect RAS predictions.
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -965,25 +493,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DT
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     51180405                       # DTB read hits
-system.cpu.dtb.read_misses                      65067                       # DTB read misses
-system.cpu.dtb.write_hits                    11700451                       # DTB write hits
-system.cpu.dtb.write_misses                     15748                       # DTB write misses
+system.cpu.dtb.read_hits                     51187284                       # DTB read hits
+system.cpu.dtb.read_misses                      65383                       # DTB read misses
+system.cpu.dtb.write_hits                    11703682                       # DTB write hits
+system.cpu.dtb.write_misses                     15916                       # DTB write misses
 system.cpu.dtb.flush_tlb                            2                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
 system.cpu.dtb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                     3477                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                      2401                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                    399                       # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries                     3484                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                      2464                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                    408                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                      1377                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 51245472                       # DTB read accesses
-system.cpu.dtb.write_accesses                11716199                       # DTB write accesses
+system.cpu.dtb.perms_faults                      1363                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                 51252667                       # DTB read accesses
+system.cpu.dtb.write_accesses                11719598                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          62880856                       # DTB hits
-system.cpu.dtb.misses                           80815                       # DTB misses
-system.cpu.dtb.accesses                      62961671                       # DTB accesses
+system.cpu.dtb.hits                          62890966                       # DTB hits
+system.cpu.dtb.misses                           81299                       # DTB misses
+system.cpu.dtb.accesses                      62972265                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1005,8 +533,8 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.inst_hits                     11521970                       # ITB inst hits
-system.cpu.itb.inst_misses                      11115                       # ITB inst misses
+system.cpu.itb.inst_hits                     11527099                       # ITB inst hits
+system.cpu.itb.inst_misses                      11249                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
@@ -1015,114 +543,114 @@ system.cpu.itb.flush_tlb                            2                       # Nu
 system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
 system.cpu.itb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.itb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                     2502                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries                     2504                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                      2960                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                      2978                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                 11533085                       # ITB inst accesses
-system.cpu.itb.hits                          11521970                       # DTB hits
-system.cpu.itb.misses                           11115                       # DTB misses
-system.cpu.itb.accesses                      11533085                       # DTB accesses
-system.cpu.numCycles                        477047952                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                 11538348                       # ITB inst accesses
+system.cpu.itb.hits                          11527099                       # DTB hits
+system.cpu.itb.misses                           11249                       # DTB misses
+system.cpu.itb.accesses                      11538348                       # DTB accesses
+system.cpu.numCycles                        477119451                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           29756603                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                       90277136                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    14743416                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches            9052947                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      20141800                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 4650225                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                     121200                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles               98195863                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                 2631                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles         87675                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles      2688966                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          386                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  11518528                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                709932                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                    5147                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          154198551                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.729959                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.081572                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           29745347                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                       90343663                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    14755327                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            9066400                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      20160515                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 4659374                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                     121718                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles               98274067                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                 2638                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles         88444                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles      2690508                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          430                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  11523637                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                709778                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                    5230                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          154294046                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.730147                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.081756                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                134072201     86.95%     86.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  1305405      0.85%     87.79% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  1710070      1.11%     88.90% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  2294026      1.49%     90.39% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  2104673      1.36%     91.76% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  1102818      0.72%     92.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  2555300      1.66%     94.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                   746086      0.48%     94.61% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                  8307972      5.39%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                134149007     86.94%     86.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  1305162      0.85%     87.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  1712027      1.11%     88.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  2298089      1.49%     90.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  2109453      1.37%     91.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  1103374      0.72%     92.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  2555030      1.66%     94.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                   746204      0.48%     94.61% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                  8315700      5.39%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            154198551                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.030906                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.189241                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 31769851                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             100064901                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  18067338                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               1262749                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                3033712                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              1957542                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                172175                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              107250920                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                570386                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                3033712                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 33504513                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                38619180                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       55176666                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  17578446                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               6286034                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              102244327                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                   450                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 980082                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               4063460                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents              782                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           106315700                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             473686161                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        432563323                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups             10440                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps              78727135                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 27588564                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts            1170552                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts        1076872                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  12591466                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             19711121                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            13300191                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1936389                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          2436828                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                   95079446                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             1983827                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 122895781                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            165904                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        18895197                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     47144933                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         501515                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     154198551                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.796997                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.515893                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            154294046                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.030926                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.189352                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 31777956                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             100129696                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  18080387                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               1265250                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                3040757                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              1958128                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                172070                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              107328179                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                570705                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                3040757                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 33516419                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                38693091                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       55142047                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  17591419                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               6310313                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              102323009                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                   472                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                1000039                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               4066050                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents              733                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           106393961                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             474042454                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        432890289                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups             10421                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps              78727775                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 27666185                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            1171025                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts        1077190                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  12642564                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             19725934                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            13308899                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1965192                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          2472766                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                   95138203                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             1987496                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 122932074                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            165549                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        18954995                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     47273204                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         505173                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     154294046                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.796739                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.515436                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           109876529     71.26%     71.26% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            14361592      9.31%     80.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             6875815      4.46%     85.03% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             5666847      3.68%     88.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            12323021      7.99%     96.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             2802995      1.82%     98.51% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             1694666      1.10%     99.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              469725      0.30%     99.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              127361      0.08%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           109928517     71.25%     71.25% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            14405522      9.34%     80.58% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             6874407      4.46%     85.04% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             5677816      3.68%     88.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            12311103      7.98%     96.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             2805861      1.82%     98.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             1693952      1.10%     99.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              468083      0.30%     99.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              128785      0.08%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       154198551                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       154294046                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                   61834      0.70%      0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      3      0.00%      0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                   61713      0.70%      0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      4      0.00%      0.70% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.70% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.70% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.70% # attempts to use FU when none available
@@ -1150,437 +678,436 @@ system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      0.70% # at
 system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      0.70% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      0.70% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                8368136     94.62%     95.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                413820      4.68%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                8365366     94.65%     95.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                411034      4.65%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass             28518      0.02%      0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              57946622     47.15%     47.17% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                93414      0.08%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                  24      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc              17      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc           2113      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc           19      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     47.25% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             52506141     42.72%     89.98% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            12318913     10.02%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              57971139     47.16%     47.18% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                93360      0.08%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                  25      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc              18      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc           2113      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc           19      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     47.26% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             52513425     42.72%     89.98% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            12323457     10.02%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              122895781                       # Type of FU issued
-system.cpu.iq.rate                           0.257617                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     8843793                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.071962                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          409057037                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         115975062                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     85458771                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads               23247                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes              12478                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses        10297                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              131698673                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                   12383                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads           624051                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              122932074                       # Type of FU issued
+system.cpu.iq.rate                           0.257655                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     8838117                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.071894                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          409219406                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         116097301                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     85490758                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads               23382                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes              12446                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses        10288                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              131729199                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                   12474                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads           624027                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      4056444                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         6518                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        30236                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      1568197                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      4071144                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         6793                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        30196                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      1576838                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads     34108054                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        680529                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads     34107946                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        680806                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                3033712                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                30168583                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                433803                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts            97285878                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            203457                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              19711121                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             13300191                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            1411588                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 113159                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                  3352                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          30236                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         349021                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       270487                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               619508                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             120819447                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              51867420                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           2076334                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                3040757                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                30225758                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                434257                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts            97346977                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            205962                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              19725934                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             13308899                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            1415361                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 113324                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                  3429                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          30196                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         351437                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       270055                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               621492                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             120854906                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              51874598                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           2077168                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                        222605                       # number of nop insts executed
-system.cpu.iew.exec_refs                     64079545                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 11817660                       # Number of branches executed
-system.cpu.iew.exec_stores                   12212125                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.253265                       # Inst execution rate
-system.cpu.iew.wb_sent                      119878750                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      85469068                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  47006672                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  87538881                       # num instructions consuming a value
+system.cpu.iew.exec_nop                        221278                       # number of nop insts executed
+system.cpu.iew.exec_refs                     64090111                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 11821235                       # Number of branches executed
+system.cpu.iew.exec_stores                   12215513                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.253301                       # Inst execution rate
+system.cpu.iew.wb_sent                      119911072                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      85501046                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  47029089                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  87607932                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.179162                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.536980                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.179203                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.536813                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        18642428                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls         1482312                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            534972                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    151164839                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.514346                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.491788                       # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts        18687715                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         1482323                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            537083                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    151253289                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.514049                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.489960                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    122735782     81.19%     81.19% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     14630083      9.68%     90.87% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      3890528      2.57%     93.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      2132680      1.41%     94.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1607271      1.06%     95.92% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5       973341      0.64%     96.56% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      1599818      1.06%     97.62% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       715537      0.47%     98.09% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      2879799      1.91%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    122784132     81.18%     81.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     14644365      9.68%     90.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      3917692      2.59%     93.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      2132798      1.41%     94.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1620432      1.07%     95.93% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5       975760      0.65%     96.58% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      1598249      1.06%     97.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       715459      0.47%     98.11% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      2864402      1.89%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    151164839                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts             60459531                       # Number of instructions committed
-system.cpu.commit.committedOps               77751027                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    151253289                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts             60460018                       # Number of instructions committed
+system.cpu.commit.committedOps               77751594                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       27386671                       # Number of memory references committed
-system.cpu.commit.loads                      15654677                       # Number of loads committed
-system.cpu.commit.membars                      403573                       # Number of memory barriers committed
-system.cpu.commit.branches                   10306328                       # Number of branches committed
+system.cpu.commit.refs                       27386851                       # Number of memory references committed
+system.cpu.commit.loads                      15654790                       # Number of loads committed
+system.cpu.commit.membars                      403577                       # Number of memory barriers committed
+system.cpu.commit.branches                   10306380                       # Number of branches committed
 system.cpu.commit.fp_insts                      10212                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                  69191102                       # Number of committed integer instructions.
-system.cpu.commit.function_calls               991248                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events               2879799                       # number cycles where commit BW limit reached
+system.cpu.commit.int_insts                  69191623                       # Number of committed integer instructions.
+system.cpu.commit.function_calls               991253                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events               2864402                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    242830080                       # The number of ROB reads
-system.cpu.rob.rob_writes                   195907164                       # The number of ROB writes
-system.cpu.timesIdled                         1776346                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                       322849401                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   4575122538                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                    60309150                       # Number of Instructions Simulated
-system.cpu.committedOps                      77600646                       # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total              60309150                       # Number of Instructions Simulated
-system.cpu.cpi                               7.910043                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         7.910043                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.126422                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.126422                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                548535745                       # number of integer regfile reads
-system.cpu.int_regfile_writes                87515632                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                      8349                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                     2926                       # number of floating regfile writes
-system.cpu.misc_regfile_reads               268179441                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                1173225                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput                58877700                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq        2658609                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2658608                       # Transaction distribution
+system.cpu.rob.rob_reads                    242979782                       # The number of ROB reads
+system.cpu.rob.rob_writes                   196005989                       # The number of ROB writes
+system.cpu.timesIdled                         1777234                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                       322825405                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   4575137230                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                    60309637                       # Number of Instructions Simulated
+system.cpu.committedOps                      77601213                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total              60309637                       # Number of Instructions Simulated
+system.cpu.cpi                               7.911164                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         7.911164                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.126404                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.126404                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                548697999                       # number of integer regfile reads
+system.cpu.int_regfile_writes                87552825                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                      8408                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                     2932                       # number of floating regfile writes
+system.cpu.misc_regfile_reads               268236665                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                1173235                       # number of misc regfile writes
+system.cpu.toL2Bus.throughput                58867266                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq        2659080                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2659079                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq        763349                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp       763349                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       607534                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2957                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq           12                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2969                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       246101                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       246101                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1963183                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      5795840                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        30059                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       127673                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           7916755                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     62784704                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     85494778                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        40536                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       211580                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      148531598                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus         148531598                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus       200936                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy     3128807668                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.trans_dist::Writeback       607635                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2959                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq           16                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2975                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       246069                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       246069                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1961962                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      5796085                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        30498                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       129069                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           7917614                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     62744960                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     85505466                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        40992                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       214572                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      148505990                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         148505990                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus       202724                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy     3129185667                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    1475592252                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    1474638965                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2550083892                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    2549207556                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy      19930988                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy      20255489                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy      74876053                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy      75530794                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu.icache.tags.replacements            981505                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.575357                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            10456797                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            982017                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             10.648285                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle        6907075250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.575357                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.999171                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.999171                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements            980897                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.570903                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            10462766                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            981409                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             10.660964                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle        6958078250                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.570903                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.999162                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.999162                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          132                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          219                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          160                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          133                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          217                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          161                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          12500448                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         12500448                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     10456797                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        10456797                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      10456797                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         10456797                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     10456797                       # number of overall hits
-system.cpu.icache.overall_hits::total        10456797                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1061602                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1061602                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1061602                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1061602                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1061602                       # number of overall misses
-system.cpu.icache.overall_misses::total       1061602                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  14273209676                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  14273209676                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  14273209676                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  14273209676                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  14273209676                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  14273209676                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     11518399                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     11518399                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     11518399                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     11518399                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     11518399                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     11518399                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.092166                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.092166                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.092166                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.092166                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.092166                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.092166                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13444.972481                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13444.972481                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13444.972481                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13444.972481                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13444.972481                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13444.972481                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         6382                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses          12504958                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         12504958                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     10462766                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        10462766                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      10462766                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         10462766                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     10462766                       # number of overall hits
+system.cpu.icache.overall_hits::total        10462766                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1060743                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1060743                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1060743                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1060743                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1060743                       # number of overall misses
+system.cpu.icache.overall_misses::total       1060743                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  14268635888                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  14268635888                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  14268635888                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  14268635888                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  14268635888                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  14268635888                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     11523509                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     11523509                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     11523509                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     11523509                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     11523509                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     11523509                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.092050                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.092050                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.092050                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.092050                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.092050                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.092050                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13451.548479                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13451.548479                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13451.548479                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13451.548479                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13451.548479                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13451.548479                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         7798                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               332                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               344                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    19.222892                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    22.668605                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        79552                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        79552                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        79552                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        79552                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        79552                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        79552                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       982050                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       982050                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       982050                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       982050                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       982050                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       982050                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  11590658741                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  11590658741                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  11590658741                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  11590658741                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  11590658741                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  11590658741                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst      8870000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::total      8870000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst      8870000                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::total      8870000                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.085259                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.085259                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.085259                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.085259                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.085259                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.085259                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11802.513865                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11802.513865                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11802.513865                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11802.513865                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11802.513865                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11802.513865                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        79293                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        79293                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        79293                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        79293                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        79293                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        79293                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       981450                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       981450                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       981450                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       981450                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       981450                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       981450                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  11587546773                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  11587546773                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  11587546773                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  11587546773                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  11587546773                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  11587546773                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst      9345000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::total      9345000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst      9345000                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::total      9345000                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.085169                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.085169                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.085169                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.085169                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.085169                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.085169                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11806.558432                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11806.558432                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11806.558432                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11806.558432                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11806.558432                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11806.558432                       # average overall mshr miss latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements            64371                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        51367.805522                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1886658                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           129763                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            14.539260                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle     2490785434500                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 36937.207333                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    28.555690                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.000373                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  8169.178837                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  6232.863288                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.563617                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000436                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.replacements            64391                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        51374.630920                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            1887139                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           129786                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            14.540390                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle     2490832751500                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 36918.668159                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    31.305745                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.000374                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  8179.061871                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  6245.594773                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.563334                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000478                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.124652                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.095106                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.783811                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1023           21                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        65371                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1023::4           20                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           38                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          355                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3048                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6928                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55002                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000320                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.997482                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         18785683                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        18785683                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        52852                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker        10132                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst       968531                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data       386919                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1418434                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       607534                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       607534                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data           40                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total           40                       # number of UpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::cpu.data            9                       # number of SCUpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::total            9                       # number of SCUpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       112876                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       112876                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker        52852                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker        10132                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst       968531                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       499795                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         1531310                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker        52852                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker        10132                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst       968531                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       499795                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        1531310                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           43                       # number of ReadReq misses
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.124803                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.095300                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.783915                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1023           23                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        65372                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::4           23                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           39                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          352                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3052                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6933                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54996                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000351                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.997498                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         18788998                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        18788998                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        53598                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker        10246                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.inst       967912                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data       386978                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        1418734                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       607635                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       607635                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data           46                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total           46                       # number of UpgradeReq hits
+system.cpu.l2cache.SCUpgradeReq_hits::cpu.data           13                       # number of SCUpgradeReq hits
+system.cpu.l2cache.SCUpgradeReq_hits::total           13                       # number of SCUpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       112878                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       112878                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker        53598                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.itb.walker        10246                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst       967912                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       499856                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         1531612                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.dtb.walker        53598                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.itb.walker        10246                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst       967912                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       499856                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        1531612                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           45                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            2                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.inst        12359                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data        10705                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        23109                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data         2917                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total         2917                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.inst        12357                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data        10744                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        23148                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data         2913                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total         2913                       # number of UpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            3                       # number of SCUpgradeReq misses
 system.cpu.l2cache.SCUpgradeReq_misses::total            3                       # number of SCUpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       133225                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       133225                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker           43                       # number of demand (read+write) misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       133191                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       133191                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.dtb.walker           45                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.itb.walker            2                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst        12359                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       143930                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        156334                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker           43                       # number of overall misses
+system.cpu.l2cache.demand_misses::cpu.inst        12357                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       143935                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        156339                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.dtb.walker           45                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.itb.walker            2                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst        12359                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       143930                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       156334                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      3808750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       158000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    901494000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data    813359500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total   1718820250                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       465980                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total       465980                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   9840326977                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   9840326977                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      3808750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       158000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    901494000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  10653686477                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  11559147227                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      3808750                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       158000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    901494000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  10653686477                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  11559147227                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        52895                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker        10134                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.inst       980890                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data       397624                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      1441543                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       607534                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       607534                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2957                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total         2957                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data           12                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::total           12                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       246101                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       246101                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker        52895                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker        10134                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst       980890                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       643725                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      1687644                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker        52895                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker        10134                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst       980890                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       643725                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      1687644                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000813                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000197                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.012600                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.026922                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.016031                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.986473                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.986473                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.250000                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::total     0.250000                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.541343                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.541343                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000813                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000197                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.012600                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.223589                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.092634                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000813                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000197                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.012600                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.223589                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.092634                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 88575.581395                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        79000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72942.309248                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75979.402149                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 74378.824268                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data   159.746315                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   159.746315                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73862.465581                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73862.465581                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 88575.581395                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        79000                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72942.309248                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74019.915772                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 73938.792758                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 88575.581395                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        79000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72942.309248                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74019.915772                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 73938.792758                       # average overall miss latency
+system.cpu.l2cache.overall_misses::cpu.inst        12357                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       143935                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       156339                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      3974500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       412000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    905251250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data    810262998                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   1719900748                       # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       510978                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total       510978                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   9827066492                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   9827066492                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      3974500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       412000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    905251250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  10637329490                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  11546967240                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      3974500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       412000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    905251250                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  10637329490                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  11546967240                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        53643                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker        10248                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.inst       980269                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data       397722                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      1441882                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       607635                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       607635                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2959                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total         2959                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data           16                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu.l2cache.SCUpgradeReq_accesses::total           16                       # number of SCUpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       246069                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       246069                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker        53643                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.itb.walker        10248                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst       980269                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       643791                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      1687951                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker        53643                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.itb.walker        10248                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst       980269                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       643791                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      1687951                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000839                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000195                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.012606                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.027014                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.016054                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.984454                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.984454                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.187500                       # miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_miss_rate::total     0.187500                       # miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.541275                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.541275                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000839                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000195                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.012606                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.223574                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.092621                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000839                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000195                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.012606                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.223574                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.092621                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 88322.222222                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker       206000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73258.173505                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75415.394453                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 74300.187835                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data   175.412976                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   175.412976                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73781.760720                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73781.760720                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 88322.222222                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker       206000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73258.173505                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73903.702991                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 73858.520523                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 88322.222222                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker       206000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73258.173505                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73903.702991                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 73858.520523                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1589,109 +1116,109 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        59118                       # number of writebacks
-system.cpu.l2cache.writebacks::total            59118                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           13                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           67                       # number of ReadReq MSHR hits
+system.cpu.l2cache.writebacks::writebacks        59141                       # number of writebacks
+system.cpu.l2cache.writebacks::total            59141                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           15                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           65                       # number of ReadReq MSHR hits
 system.cpu.l2cache.ReadReq_mshr_hits::total           80                       # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst           13                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data           67                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst           15                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data           65                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::total           80                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst           13                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data           67                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst           15                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data           65                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total           80                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           43                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           45                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            2                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        12346                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        10638                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        23029                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2917                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total         2917                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        12342                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        10679                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        23068                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2913                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total         2913                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            3                       # number of SCUpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            3                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       133225                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       133225                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           43                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       133191                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       133191                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           45                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            2                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        12346                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       143863                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       156254                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           43                       # number of overall MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        12342                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       143870                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       156259                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           45                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            2                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        12346                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       143863                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       156254                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      3278250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       133500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    745356250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    676470750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1425238750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     29172917                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     29172917                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        12342                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       143870                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       156259                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      3417500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       387500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    749197750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    673040498                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1426043248                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     29132913                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     29132913                       # number of UpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data        30003                       # number of SCUpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total        30003                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   8180809023                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8180809023                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      3278250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       133500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    745356250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   8857279773                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   9606047773                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      3278250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       133500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    745356250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8857279773                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   9606047773                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst      6336999                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166942244250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166948581249                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data  17449661616                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total  17449661616                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst      6336999                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184391905866                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184398242865                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000813                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000197                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.012587                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.026754                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.015975                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.986473                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.986473                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.250000                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.250000                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.541343                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.541343                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000813                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000197                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.012587                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.223485                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.092587                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000813                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000197                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.012587                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.223485                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.092587                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 76238.372093                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        66750                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60372.286571                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63590.031021                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61888.868383                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   8170239508                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   8170239508                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      3417500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       387500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    749197750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   8843280006                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   9596282756                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      3417500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       387500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    749197750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8843280006                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   9596282756                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst      6814499                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166942562250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166949376749                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data  17458567530                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total  17458567530                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst      6814499                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184401129780                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184407944279                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000839                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000195                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.012590                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.026850                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.015999                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.984454                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.984454                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.187500                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.187500                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.541275                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.541275                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000839                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000195                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.012590                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.223473                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.092573                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000839                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000195                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.012590                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.223473                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.092573                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 75944.444444                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker       193750                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60703.107276                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63024.674408                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61819.110803                       # average ReadReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        10001                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average SCUpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        10001                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61405.960015                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61405.960015                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 76238.372093                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        66750                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60372.286571                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61567.461912                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61477.131933                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 76238.372093                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        66750                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60372.286571                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61567.461912                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61477.131933                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61342.279193                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61342.279193                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 75944.444444                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker       193750                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60703.107276                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61467.157893                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61412.672268                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 75944.444444                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker       193750                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60703.107276                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61467.157893                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61412.672268                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -1701,168 +1228,168 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements            643213                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.993295                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            21506846                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            643725                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             33.409990                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle          42602250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.993295                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.replacements            643279                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.993228                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            21514190                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            643791                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             33.417973                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle          43094250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.993228                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999987                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999987                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          196                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          193                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          299                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           17                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           20                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         101509393                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        101509393                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     13753990                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        13753990                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      7259407                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        7259407                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       242755                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       242755                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       247595                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       247595                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      21013397                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         21013397                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     21013397                       # number of overall hits
-system.cpu.dcache.overall_hits::total        21013397                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       736321                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        736321                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      2962815                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      2962815                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        13522                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        13522                       # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data           12                       # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total           12                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      3699136                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3699136                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      3699136                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3699136                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  10001713308                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  10001713308                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 140180267525                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 140180267525                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    184727500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    184727500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       193503                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total       193503                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 150181980833                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 150181980833                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 150181980833                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 150181980833                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     14490311                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     14490311                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     10222222                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     10222222                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       256277                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       256277                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       247607                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       247607                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     24712533                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     24712533                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     24712533                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     24712533                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.050815                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.050815                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.289841                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.289841                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.052763                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.052763                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000048                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total     0.000048                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.149687                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.149687                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.149687                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.149687                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13583.360121                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 13583.360121                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47313.202993                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 47313.202993                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13661.255731                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13661.255731                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16125.250000                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16125.250000                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 40599.205012                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 40599.205012                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 40599.205012                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 40599.205012                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs        30576                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets        27091                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs              2628                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets             288                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    11.634703                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    94.065972                       # average number of cycles each access was blocked
+system.cpu.dcache.tags.tag_accesses         101537487                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        101537487                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     13760648                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        13760648                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      7259865                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        7259865                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       242998                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       242998                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       247594                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       247594                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      21020513                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         21020513                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     21020513                       # number of overall hits
+system.cpu.dcache.overall_hits::total        21020513                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       736359                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        736359                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      2962417                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      2962417                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        13527                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        13527                       # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data           16                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total           16                       # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data      3698776                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3698776                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      3698776                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3698776                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   9982812336                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   9982812336                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 139744433579                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 139744433579                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    185287000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    185287000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       245503                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total       245503                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 149727245915                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 149727245915                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 149727245915                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 149727245915                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     14497007                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     14497007                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     10222282                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     10222282                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       256525                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       256525                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       247610                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       247610                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     24719289                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     24719289                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     24719289                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     24719289                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.050794                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.050794                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.289800                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.289800                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.052732                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.052732                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000065                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total     0.000065                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.149631                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.149631                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.149631                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.149631                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13556.991000                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 13556.991000                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47172.438444                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 47172.438444                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13697.567827                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13697.567827                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15343.937500                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15343.937500                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 40480.214513                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 40480.214513                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 40480.214513                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 40480.214513                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs        31777                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets        23524                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              2637                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets             274                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    12.050436                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    85.854015                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       607534                       # number of writebacks
-system.cpu.dcache.writebacks::total            607534                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       350801                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       350801                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      2713841                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      2713841                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         1334                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total         1334                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      3064642                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      3064642                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      3064642                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      3064642                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       385520                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       385520                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       248974                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       248974                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        12188                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total        12188                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data           12                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total           12                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       634494                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       634494                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       634494                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       634494                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   4971012627                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   4971012627                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11323926285                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  11323926285                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    145258250                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    145258250                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       169497                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       169497                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  16294938912                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  16294938912                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  16294938912                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  16294938912                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182335926750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182335926750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data  26847444003                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  26847444003                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209183370753                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 209183370753                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.026605                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.026605                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.024356                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.024356                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.047558                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.047558                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000048                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000048                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.025675                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.025675                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.025675                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.025675                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12894.305424                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12894.305424                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45482.364765                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45482.364765                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11918.136692                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11918.136692                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14124.750000                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14124.750000                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25681.785662                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 25681.785662                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25681.785662                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 25681.785662                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks       607635                       # number of writebacks
+system.cpu.dcache.writebacks::total            607635                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       350728                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       350728                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      2713476                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      2713476                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         1349                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total         1349                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      3064204                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      3064204                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      3064204                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      3064204                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       385631                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       385631                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       248941                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       248941                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        12178                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total        12178                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data           16                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total           16                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       634572                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       634572                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       634572                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       634572                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   4967633608                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   4967633608                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11307381788                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  11307381788                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    145644250                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    145644250                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       213497                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       213497                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  16275015396                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  16275015396                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  16275015396                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  16275015396                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182336207250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182336207250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data  26867769000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  26867769000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209203976250                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 209203976250                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.026601                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.026601                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.024353                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.024353                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.047473                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.047473                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000065                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000065                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.025671                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.025671                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.025671                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.025671                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12881.831616                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12881.831616                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45421.934466                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45421.934466                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11959.619806                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11959.619806                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13343.562500                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13343.562500                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25647.232144                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 25647.232144                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25647.232144                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 25647.232144                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1886,10 +1413,10 @@ system.iocache.avg_blocked_cycles::no_mshrs          nan                       #
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1499139103043                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1499139103043                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1499139103043                       # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1499139103043                       # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1715151162848                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1715151162848                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1715151162848                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1715151162848                       # number of overall MSHR uncacheable cycles
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
index c90f786a8747ac65760a13889090aa1f16d42265..8e01cba8d10e15dbc6dd7140700df91c801fa2b9 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.403672                       # Number of seconds simulated
-sim_ticks                                2403671650000                       # Number of ticks simulated
-final_tick                               2403671650000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.403854                       # Number of seconds simulated
+sim_ticks                                2403853586500                       # Number of ticks simulated
+final_tick                               2403853586500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 179946                       # Simulator instruction rate (inst/s)
-host_op_rate                                   231118                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             7169234406                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 425424                       # Number of bytes of host memory used
-host_seconds                                   335.28                       # Real time elapsed on the host
-sim_insts                                    60331512                       # Number of instructions simulated
-sim_ops                                      77488235                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 171159                       # Simulator instruction rate (inst/s)
+host_op_rate                                   219830                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             6819657603                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 469520                       # Number of bytes of host memory used
+host_seconds                                   352.49                       # Real time elapsed on the host
+sim_insts                                    60331708                       # Number of instructions simulated
+sim_ops                                      77487722                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::realview.clcd    114819072                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.dtb.walker           64                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           512456                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          7063576                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           512776                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          7053720                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.dtb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst            64640                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data           678080                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst            63616                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data           681152                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu2.dtb.walker          640                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst           186240                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data          1335136                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            124660096                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       512456                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst        64640                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst       186240                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          763336                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      3743616                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data       1298488                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data        159300                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu2.data       1558028                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6759432                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu2.itb.walker           64                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst           186368                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data          1342304                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            124659968                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       512776                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst        63616                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst       186368                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          762760                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      3743360                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data       1298364                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data        159256                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu2.data       1558196                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           6759176                       # Number of bytes written to this memory
 system.physmem.num_reads::realview.clcd      14352384                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.dtb.walker            1                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             14219                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            110404                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             14224                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            110250                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.dtb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              1010                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             10595                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst               994                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             10643                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu2.dtb.walker           10                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst              2910                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data             20869                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total              14512405                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           58494                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data           324622                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data            39825                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu2.data           389507                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               812448                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd        47768202                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::cpu2.itb.walker            1                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst              2912                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data             20981                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total              14512403                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           58490                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data           324591                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data            39814                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu2.data           389549                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               812444                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd        47764586                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.dtb.walker            27                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker            53                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              213197                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             2938661                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              213314                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             2934338                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu1.dtb.walker            27                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               26892                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              282102                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               26464                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              283358                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu2.dtb.walker           266                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst               77481                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data              555457                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                51862365                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         213197                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          26892                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst          77481                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             317571                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1557457                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data             540210                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data              66274                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu2.data             648187                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2812128                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1557457                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd       47768202                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu2.itb.walker            27                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst               77529                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data              558397                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                51858386                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         213314                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          26464                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst          77529                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             317307                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1557233                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data             540118                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data              66250                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu2.data             648208                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2811809                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1557233                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd       47764586                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.dtb.walker           27                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           53                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             213197                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            3478871                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             213314                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            3474456                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu1.dtb.walker           27                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              26892                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             348375                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              26464                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             349609                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu2.dtb.walker          266                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst              77481                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data            1203644                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               54674493                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                      13478771                       # Number of read requests accepted
-system.physmem.writeReqs                       446331                       # Number of write requests accepted
-system.physmem.readBursts                    13478771                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     446331                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                862641344                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   2859200                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 109811808                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                2805264                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                  401653                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           2355                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              837730                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              837384                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              837568                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              837998                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              839137                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              839827                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              839940                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              841195                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              842685                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              845257                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             845425                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             845905                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             847162                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             848062                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             846854                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             846642                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                2730                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                2572                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                2588                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                3028                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                3463                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                3194                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                2521                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                2322                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                2234                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                2386                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               2377                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               2814                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               3729                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               3501                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               2651                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               2565                       # Per bank write bursts
+system.physmem.bw_total::cpu2.itb.walker           27                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst              77529                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data            1206604                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               54670195                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                      13446822                       # Number of read requests accepted
+system.physmem.writeReqs                       446449                       # Number of write requests accepted
+system.physmem.readBursts                    13446822                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     446449                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                860596480                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                       128                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   2823168                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 109564448                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                2810956                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                        2                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                  402307                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs           2362                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0              835680                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              835344                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              835508                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              835965                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              837088                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              837779                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              837907                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              839147                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              840641                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              843268                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             843373                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             843869                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             845852                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             846016                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             844806                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             844577                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                2668                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                2526                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                2530                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                3005                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                3419                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                3167                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                2515                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                2303                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                2186                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                2396                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               2346                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               2792                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               3710                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               3446                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               2600                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               2503                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2402635561500                       # Total gap between requests
+system.physmem.totGap                    2402817511500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       8                       # Read request sizes (log2)
-system.physmem.readPktSize::3                13443376                       # Read request sizes (log2)
+system.physmem.readPktSize::3                13411280                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                   35387                       # Read request sizes (log2)
+system.physmem.readPktSize::6                   35534                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::2                 429332                       # Write request sizes (log2)
+system.physmem.writePktSize::2                 429363                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  16999                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    985231                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    962596                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                    957159                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                   3278666                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                   2351782                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                   2351346                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                   2368287                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                     47071                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                     52789                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                     17803                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                    17814                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                    17764                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                    17625                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                    17616                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                    17601                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                    17598                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                       23                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  17086                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    867414                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    844196                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                    838512                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                    839224                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                    838671                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                    838847                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                   2475363                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                   2475187                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                   3292199                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                     20391                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                    19694                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                    19741                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                    19565                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                    19474                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                    19175                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                    19145                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                       22                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
@@ -178,369 +182,159 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                      2018                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                      2412                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                      2043                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                      2191                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                      2298                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                      2012                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                      2026                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                      2035                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                      1989                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                      1980                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                     1974                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                     1969                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                     1962                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                     1958                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                     1955                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1952                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     1953                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     1961                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     1959                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     1949                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     1945                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     2054                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                       57                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                       26                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        48736                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean    17758.945502                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean    3164.892038                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev   18326.287457                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64-71           8690     17.83%     17.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-135         4827      9.90%     27.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192-199         1035      2.12%     29.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-263          694      1.42%     31.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320-327          398      0.82%     32.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-391          429      0.88%     32.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448-455          259      0.53%     33.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-519          302      0.62%     34.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576-583          176      0.36%     34.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-647          149      0.31%     34.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704-711          171      0.35%     35.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-775          272      0.56%     35.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832-839           78      0.16%     35.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-903           84      0.17%     36.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960-967           41      0.08%     36.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1031          422      0.87%     36.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088-1095           26      0.05%     37.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152-1159           34      0.07%     37.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216-1223           22      0.05%     37.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280-1287          232      0.48%     37.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344-1351           28      0.06%     37.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408-1415          166      0.34%     38.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472-1479           13      0.03%     38.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536-1543          104      0.21%     38.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600-1607           12      0.02%     38.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664-1671           32      0.07%     38.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1728-1735            7      0.01%     38.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1792-1799           80      0.16%     38.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856-1863           11      0.02%     38.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1920-1927           11      0.02%     38.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984-1991            7      0.01%     38.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2048-2055          239      0.49%     39.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112-2119            4      0.01%     39.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2176-2183           11      0.02%     39.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2240-2247            7      0.01%     39.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2304-2311           71      0.15%     39.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2368-2375            4      0.01%     39.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2432-2439            5      0.01%     39.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2496-2503            2      0.00%     39.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2560-2567           72      0.15%     39.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2624-2631            2      0.00%     39.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2688-2695            3      0.01%     39.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2752-2759            1      0.00%     39.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2816-2823            3      0.01%     39.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2880-2887            2      0.00%     39.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2944-2951            6      0.01%     39.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3008-3015            4      0.01%     39.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3072-3079          360      0.74%     40.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3136-3143            3      0.01%     40.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3200-3207            3      0.01%     40.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3264-3271            2      0.00%     40.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3328-3335           69      0.14%     40.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3392-3399            3      0.01%     40.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3456-3463            6      0.01%     40.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3520-3527            6      0.01%     40.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3584-3591           67      0.14%     40.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3648-3655            5      0.01%     40.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3712-3719            8      0.02%     40.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3776-3783            5      0.01%     40.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3840-3847           67      0.14%     40.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3904-3911            5      0.01%     40.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3968-3975            9      0.02%     40.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4032-4039            4      0.01%     40.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4096-4103          338      0.69%     41.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4160-4167            3      0.01%     41.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4224-4231            7      0.01%     41.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4288-4295            5      0.01%     41.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4352-4359           70      0.14%     41.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4416-4423           13      0.03%     41.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4480-4487            5      0.01%     41.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4544-4551            7      0.01%     41.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4608-4615           72      0.15%     41.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4672-4679            1      0.00%     41.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4736-4743            5      0.01%     41.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4800-4807            3      0.01%     41.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4864-4871           64      0.13%     41.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4928-4935            3      0.01%     41.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4992-4999            4      0.01%     42.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5056-5063            3      0.01%     42.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5120-5127          280      0.57%     42.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5184-5191            1      0.00%     42.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5248-5255            2      0.00%     42.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5376-5383           73      0.15%     42.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5440-5447            4      0.01%     42.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5504-5511            4      0.01%     42.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5568-5575            1      0.00%     42.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5632-5639          129      0.26%     43.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5760-5767            2      0.00%     43.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5824-5831            4      0.01%     43.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5888-5895          176      0.36%     43.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6016-6023            1      0.00%     43.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6080-6087           10      0.02%     43.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6144-6151          327      0.67%     44.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6208-6215            5      0.01%     44.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6272-6279            7      0.01%     44.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6336-6343            1      0.00%     44.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6400-6407           98      0.20%     44.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6464-6471            1      0.00%     44.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6528-6535            1      0.00%     44.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6592-6599            2      0.00%     44.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6656-6663           73      0.15%     44.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6720-6727            4      0.01%     44.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6784-6791            8      0.02%     44.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6848-6855            2      0.00%     44.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6912-6919           60      0.12%     44.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6976-6983            5      0.01%     44.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7040-7047            2      0.00%     44.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7104-7111            3      0.01%     44.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7168-7175          268      0.55%     45.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7296-7303            1      0.00%     45.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7360-7367            7      0.01%     45.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7424-7431           66      0.14%     45.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7552-7559            2      0.00%     45.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7616-7623            1      0.00%     45.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7680-7687           64      0.13%     45.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7936-7943           42      0.09%     45.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8064-8071            2      0.00%     45.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8192-8199          515      1.06%     46.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8448-8455           42      0.09%     46.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8704-8711           66      0.14%     46.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8960-8967           65      0.13%     46.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9216-9223          267      0.55%     47.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9472-9479           59      0.12%     47.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9728-9735           69      0.14%     47.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9984-9991           94      0.19%     47.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10240-10247          322      0.66%     48.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10496-10503          138      0.28%     48.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10752-10759          128      0.26%     49.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11008-11015           70      0.14%     49.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11264-11271          279      0.57%     49.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11520-11527           60      0.12%     50.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11648-11655            1      0.00%     50.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11776-11783           64      0.13%     50.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12032-12039           65      0.13%     50.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12288-12295          328      0.67%     50.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12544-12551           63      0.13%     51.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12608-12615            1      0.00%     51.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12800-12807           64      0.13%     51.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13056-13063           64      0.13%     51.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13312-13319          357      0.73%     52.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13824-13831           65      0.13%     52.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13952-13959            1      0.00%     52.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14080-14087           64      0.13%     52.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14208-14215            1      0.00%     52.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14336-14343          229      0.47%     52.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14592-14599           64      0.13%     52.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14848-14855           64      0.13%     53.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15104-15111          190      0.39%     53.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15360-15367          321      0.66%     54.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15616-15623           65      0.13%     54.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16128-16135           64      0.13%     54.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16384-16391          672      1.38%     55.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16640-16647           64      0.13%     55.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17152-17159           64      0.13%     56.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17408-17415          321      0.66%     56.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17664-17671          189      0.39%     57.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17920-17927           65      0.13%     57.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18176-18183           64      0.13%     57.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18304-18311            1      0.00%     57.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18368-18375            1      0.00%     57.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18432-18439          229      0.47%     57.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18688-18695           64      0.13%     57.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18944-18951           63      0.13%     58.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19008-19015            1      0.00%     58.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19200-19207            1      0.00%     58.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19456-19463          357      0.73%     58.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19712-19719           65      0.13%     58.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19904-19911            1      0.00%     58.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19968-19975           65      0.13%     59.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20224-20231           64      0.13%     59.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20288-20295            1      0.00%     59.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20352-20359            1      0.00%     59.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20480-20487          327      0.67%     59.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20608-20615            1      0.00%     59.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20736-20743           64      0.13%     60.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20992-20999           64      0.13%     60.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21248-21255           61      0.13%     60.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21504-21511          274      0.56%     60.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21760-21767           69      0.14%     61.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22016-22023          128      0.26%     61.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22272-22279          137      0.28%     61.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22336-22343            1      0.00%     61.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22528-22535          323      0.66%     62.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22784-22791           93      0.19%     62.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22848-22855            1      0.00%     62.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23040-23047           68      0.14%     62.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23296-23303           57      0.12%     62.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23552-23559          268      0.55%     63.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23808-23815           65      0.13%     63.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24064-24071           65      0.13%     63.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24320-24327           43      0.09%     63.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24576-24583          514      1.05%     64.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24768-24775            1      0.00%     64.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24832-24839           42      0.09%     64.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25088-25095           66      0.14%     64.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25344-25351           64      0.13%     64.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25408-25415            1      0.00%     64.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25472-25479            1      0.00%     64.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25600-25607          264      0.54%     65.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25728-25735            1      0.00%     65.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25856-25863           57      0.12%     65.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26112-26119           69      0.14%     65.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26368-26375           95      0.19%     65.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26624-26631          323      0.66%     66.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26752-26759            1      0.00%     66.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26880-26887          137      0.28%     66.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27008-27015            1      0.00%     66.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27136-27143          127      0.26%     67.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27392-27399           68      0.14%     67.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27648-27655          275      0.56%     67.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27904-27911           61      0.13%     68.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28160-28167           64      0.13%     68.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28416-28423           65      0.13%     68.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28672-28679          329      0.68%     68.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28928-28935           65      0.13%     69.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29184-29191           64      0.13%     69.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29440-29447           64      0.13%     69.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29696-29703          356      0.73%     70.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30208-30215           65      0.13%     70.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30464-30471           64      0.13%     70.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30720-30727          228      0.47%     70.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30976-30983           64      0.13%     70.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31232-31239           64      0.13%     71.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31488-31495          189      0.39%     71.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31744-31751          321      0.66%     72.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32000-32007           63      0.13%     72.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32128-32135            1      0.00%     72.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32512-32519           64      0.13%     72.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32768-32775          673      1.38%     73.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33024-33031           64      0.13%     73.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33408-33415            1      0.00%     73.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33536-33543           64      0.13%     74.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33792-33799          321      0.66%     74.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34048-34055          189      0.39%     75.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34304-34311           64      0.13%     75.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34560-34567           65      0.13%     75.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34816-34823          229      0.47%     75.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35072-35079           64      0.13%     75.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35328-35335           65      0.13%     76.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35840-35847          356      0.73%     76.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36096-36103           64      0.13%     76.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36352-36359           64      0.13%     77.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36608-36615           65      0.13%     77.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36864-36871          329      0.68%     77.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37120-37127           65      0.13%     78.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37376-37383           64      0.13%     78.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37632-37639           61      0.13%     78.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37888-37895          276      0.57%     78.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38144-38151           68      0.14%     78.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38400-38407          127      0.26%     79.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38528-38535            1      0.00%     79.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38656-38663          137      0.28%     79.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38912-38919          322      0.66%     80.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39168-39175           94      0.19%     80.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39424-39431           69      0.14%     80.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39680-39687           57      0.12%     80.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39808-39815            1      0.00%     80.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39936-39943          264      0.54%     81.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40128-40135            1      0.00%     81.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40192-40199           64      0.13%     81.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40448-40455           65      0.13%     81.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40704-40711           42      0.09%     81.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40960-40967          513      1.05%     82.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41216-41223           43      0.09%     82.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41472-41479           64      0.13%     82.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41728-41735           65      0.13%     82.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41984-41991          266      0.55%     83.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42240-42247           57      0.12%     83.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42496-42503           68      0.14%     83.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42688-42695            1      0.00%     83.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42752-42759           93      0.19%     83.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43008-43015          323      0.66%     84.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43264-43271          137      0.28%     84.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43520-43527          128      0.26%     85.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43776-43783           69      0.14%     85.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44032-44039          274      0.56%     85.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44288-44295           61      0.13%     85.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44544-44551           64      0.13%     86.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44800-44807           64      0.13%     86.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44928-44935            1      0.00%     86.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45056-45063          327      0.67%     86.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45184-45191            1      0.00%     86.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45248-45255            1      0.00%     86.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45312-45319           64      0.13%     87.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45568-45575           64      0.13%     87.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45632-45639            1      0.00%     87.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45824-45831           64      0.13%     87.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46080-46087          356      0.73%     88.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46528-46535            1      0.00%     88.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46592-46599           63      0.13%     88.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46848-46855           64      0.13%     88.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47104-47111          228      0.47%     88.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47360-47367           64      0.13%     88.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47616-47623           65      0.13%     89.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47872-47879          190      0.39%     89.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48128-48135          322      0.66%     90.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48384-48391           67      0.14%     90.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48896-48903           64      0.13%     90.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::49024-49031            1      0.00%     90.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::49088-49095            1      0.00%     90.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::49152-49159         4701      9.65%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          48736                       # Bytes accessed per row activation
-system.physmem.totQLat                   326317088000                       # Total ticks spent queuing
-system.physmem.totMemAccLat              407972525500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                  67393855000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                 14261582500                       # Total ticks spent accessing banks
-system.physmem.avgQLat                       24209.71                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                     1058.08                       # Average bank access latency per DRAM burst
+system.physmem.wrQLenPdf::0                        99                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                        99                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                        97                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                        97                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                        96                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                        95                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                        95                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                        94                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                        94                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                        93                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                       93                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                       93                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                       92                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                       92                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                       94                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     1109                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     1147                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     1244                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     1477                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     1625                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     1655                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     1647                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     1678                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     1696                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     1634                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     1798                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     1677                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     1653                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     1860                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     1651                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     1605                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     1601                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     1586                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      921                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      694                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      710                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      756                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      736                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      686                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      713                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      689                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      683                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      692                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      654                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      671                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      647                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      642                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      640                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      638                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      638                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      635                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      635                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      638                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      646                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       10                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       844644                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean     1019.942660                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean    1014.395909                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev      58.300980                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127           1516      0.18%      0.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         1237      0.15%      0.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383          570      0.07%      0.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511          375      0.04%      0.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639          256      0.03%      0.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          198      0.02%      0.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          155      0.02%      0.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          158      0.02%      0.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151       840179     99.47%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         844644                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          1621                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean      8295.373226                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev    315033.644502                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-524287         1620     99.94%     99.94% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1.25829e+07-1.31072e+07            1      0.06%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            1621                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          1621                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        27.212832                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       24.563019                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev       12.121341                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::1                   1      0.06%      0.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::2                   2      0.12%      0.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::3                   1      0.06%      0.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4                   1      0.06%      0.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::5                   1      0.06%      0.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::7                   1      0.06%      0.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::9                   1      0.06%      0.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12                  2      0.12%      0.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::15                  6      0.37%      0.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16                488     30.10%     31.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 27      1.67%     32.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                 60      3.70%     36.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                333     20.54%     57.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                 10      0.62%     57.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                  3      0.19%     57.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                  2      0.12%     57.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                  3      0.19%     58.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                  2      0.12%     58.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                  3      0.19%     58.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                  5      0.31%     58.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27                  4      0.25%     58.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28                  5      0.31%     59.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29                  7      0.43%     59.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30                  3      0.19%     59.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::31                  2      0.12%     60.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32                  8      0.49%     60.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::33                  2      0.12%     60.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::34                  1      0.06%     60.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::39                 50      3.08%     63.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40                  4      0.25%     64.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::41                167     10.30%     74.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::42                328     20.23%     94.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::43                 16      0.99%     95.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44                 15      0.93%     96.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::45                 23      1.42%     97.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::46                 17      1.05%     98.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::47                 13      0.80%     99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48                  2      0.12%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::49                  2      0.12%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            1621                       # Writes before turning the bus around for reads
+system.physmem.totQLat                   510864117000                       # Total ticks spent queuing
+system.physmem.totMemAccLat              601782495750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                  67234100000                       # Total ticks spent in databus transfers
+system.physmem.totBankLat                 23684278750                       # Total ticks spent accessing banks
+system.physmem.avgQLat                       37991.44                       # Average queueing delay per DRAM burst
+system.physmem.avgBankLat                     1761.33                       # Average bank access latency per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  30267.78                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         358.88                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           1.19                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       45.69                       # Average system read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  44752.77                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         358.01                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           1.17                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       45.58                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        1.17                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           2.81                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       2.80                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         0.17                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                         0.37                       # Average write queue length when enqueuing
-system.physmem.readRowHits                   13435330                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     39380                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   99.68                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  88.14                       # Row buffer hit rate for writes
-system.physmem.avgGap                       172539.89                       # Average gap between requests
-system.physmem.pageHitRate                      99.64                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               0.87                       # Percentage of time for which DRAM has all the banks in precharge state
+system.physmem.avgRdQLen                         8.42                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                         5.41                       # Average write queue length when enqueuing
+system.physmem.readRowHits                   12595156                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     38053                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   93.67                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  86.21                       # Row buffer hit rate for writes
+system.physmem.avgGap                       172948.29                       # Average gap between requests
+system.physmem.pageHitRate                      93.64                       # Row buffer hit rate, read and write combined
+system.physmem.prechargeAllPercent               2.74                       # Percentage of time for which DRAM has all the banks in precharge state
 system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
@@ -553,322 +347,341 @@ system.realview.nvmem.bw_inst_read::cpu0.inst            8
 system.realview.nvmem.bw_inst_read::total            8                       # Instruction read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu0.inst            8                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total               8                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                     55671828                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq            13814146                       # Transaction distribution
-system.membus.trans_dist::ReadResp           13814146                       # Transaction distribution
-system.membus.trans_dist::WriteReq             432166                       # Transaction distribution
-system.membus.trans_dist::WriteResp            432166                       # Transaction distribution
-system.membus.trans_dist::Writeback             16999                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             2355                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            2355                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             27802                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            27802                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       731808                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio          214                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       951163                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      1683185                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     26886752                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total     26886752                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total               28569937                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave       735681                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio          428                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port      5070064                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::total      5806173                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port    107547008                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::total    107547008                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total           113353181                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus              133816795                       # Total data (bytes)
+system.membus.throughput                     55667457                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq            13781916                       # Transaction distribution
+system.membus.trans_dist::ReadResp           13781916                       # Transaction distribution
+system.membus.trans_dist::WriteReq             432200                       # Transaction distribution
+system.membus.trans_dist::WriteResp            432200                       # Transaction distribution
+system.membus.trans_dist::Writeback             17086                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             2361                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq              1                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            2362                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             27973                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            27973                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       731598                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio          210                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       951620                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      1683428                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     26822560                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total     26822560                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total               28505988                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave       735468                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio          420                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port      5085164                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::total      5821052                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port    107290240                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::total    107290240                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total           113111292                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus              133816415                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy           416936000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy           416850000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy              202000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy              198000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer6.occupancy         14607946000                       # Layer occupancy (ticks)
+system.membus.reqLayer6.occupancy         14576843000                       # Layer occupancy (ticks)
 system.membus.reqLayer6.utilization               0.6                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         1594364889                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         1595419615                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
-system.membus.respLayer2.occupancy        30360976750                       # Layer occupancy (ticks)
-system.membus.respLayer2.utilization              1.3                       # Layer utilization (%)
+system.membus.respLayer2.occupancy        33523642000                       # Layer occupancy (ticks)
+system.membus.respLayer2.utilization              1.4                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.l2c.tags.replacements                    63237                       # number of replacements
-system.l2c.tags.tagsinuse                50379.569066                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    1749643                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   128631                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    13.602032                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle             2375594870500                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   36839.610574                       # Average occupied blocks per requestor
+system.l2c.tags.replacements                    63235                       # number of replacements
+system.l2c.tags.tagsinuse                50381.174231                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    1749008                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   128627                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    13.597518                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle             2375559570500                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks   36838.397677                       # Average occupied blocks per requestor
 system.l2c.tags.occ_blocks::cpu0.dtb.walker     0.000018                       # Average occupied blocks per requestor
 system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000124                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     5231.934240                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     3832.971184                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     5238.516596                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     3833.196793                       # Average occupied blocks per requestor
 system.l2c.tags.occ_blocks::cpu1.dtb.walker     0.993316                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      504.116293                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data      687.425497                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.dtb.walker     7.900489                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst     1683.581513                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data     1591.035818                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.562128                       # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::cpu1.inst      493.229672                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data      688.317801                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.dtb.walker     8.879272                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.itb.walker     0.004789                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst     1684.639749                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data     1594.998425                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.562109                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000000                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.079833                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.058486                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.079933                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.058490                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000015                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.007692                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.010489                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.dtb.walker     0.000121                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst       0.025689                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data       0.024277                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.768731                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1023            2                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        65392                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4            2                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           40                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          340                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         2635                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         6494                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        55883                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1023     0.000031                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.997803                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 17683980                       # Number of tag accesses
-system.l2c.tags.data_accesses                17683980                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker         8701                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker         3143                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst             467937                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             177040                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker         2608                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker         1169                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             128901                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data              64374                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.dtb.walker        18792                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.itb.walker         4308                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.inst             282422                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.data             131846                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1291241                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          597674                       # number of Writeback hits
-system.l2c.Writeback_hits::total               597674                       # number of Writeback hits
+system.l2c.tags.occ_percent::cpu1.inst       0.007526                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.010503                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.dtb.walker     0.000135                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.itb.walker     0.000000                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.inst       0.025706                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.data       0.024338                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.768756                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1023            6                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        65386                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4            6                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           37                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          337                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         2640                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         6490                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        55882                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1023     0.000092                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.997711                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 17681539                       # Number of tag accesses
+system.l2c.tags.data_accesses                17681539                       # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.dtb.walker         8692                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker         3137                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.inst             468000                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data             177035                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker         2622                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker         1183                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst             129681                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data              64527                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.dtb.walker        18896                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.itb.walker         4217                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.inst             281169                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.data             131701                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1290860                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          597704                       # number of Writeback hits
+system.l2c.Writeback_hits::total               597704                       # number of Writeback hits
 system.l2c.UpgradeReq_hits::cpu0.data              14                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::cpu1.data               4                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2.data              11                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                  29                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu2.data             2                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total                 2                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            62009                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            18402                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu2.data            33187                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               113598                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker          8701                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker          3143                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              467937                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              239049                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker          2608                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          1169                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              128901                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data               82776                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.dtb.walker         18792                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.itb.walker          4308                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst              282422                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data              165033                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1404839                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker         8701                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker         3143                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             467937                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             239049                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker         2608                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         1169                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             128901                       # number of overall hits
-system.l2c.overall_hits::cpu1.data              82776                       # number of overall hits
-system.l2c.overall_hits::cpu2.dtb.walker        18792                       # number of overall hits
-system.l2c.overall_hits::cpu2.itb.walker         4308                       # number of overall hits
-system.l2c.overall_hits::cpu2.inst             282422                       # number of overall hits
-system.l2c.overall_hits::cpu2.data             165033                       # number of overall hits
-system.l2c.overall_hits::total                1404839                       # number of overall hits
+system.l2c.UpgradeReq_hits::cpu2.data              15                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                  33                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu2.data             3                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total                 3                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data            61997                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            18431                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu2.data            33199                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               113627                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.dtb.walker          8692                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker          3137                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst              468000                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              239032                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker          2622                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker          1183                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              129681                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data               82958                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.dtb.walker         18896                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.itb.walker          4217                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.inst              281169                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.data              164900                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 1404487                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker         8692                       # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker         3137                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst             468000                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             239032                       # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker         2622                       # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker         1183                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             129681                       # number of overall hits
+system.l2c.overall_hits::cpu1.data              82958                       # number of overall hits
+system.l2c.overall_hits::cpu2.dtb.walker        18896                       # number of overall hits
+system.l2c.overall_hits::cpu2.itb.walker         4217                       # number of overall hits
+system.l2c.overall_hits::cpu2.inst             281169                       # number of overall hits
+system.l2c.overall_hits::cpu2.data             164900                       # number of overall hits
+system.l2c.overall_hits::total                1404487                       # number of overall hits
 system.l2c.ReadReq_misses::cpu0.dtb.walker            1                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu0.itb.walker            2                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst             7593                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data             6469                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.inst             7598                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data             6467                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu1.dtb.walker            1                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst             1010                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data             1115                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst              994                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data             1116                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu2.dtb.walker           10                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.inst             2911                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.data             2551                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                21663                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data          1419                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data           466                       # number of UpgradeReq misses
+system.l2c.ReadReq_misses::cpu2.itb.walker            1                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.inst             2913                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.data             2538                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                21641                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data          1418                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data           468                       # number of UpgradeReq misses
 system.l2c.UpgradeReq_misses::cpu2.data          1020                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              2905                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data         104688                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data           9751                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2.data          18920                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             133359                       # number of ReadExReq misses
+system.l2c.UpgradeReq_misses::total              2906                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu2.data            1                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total               1                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data         104538                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data           9799                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu2.data          19047                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             133384                       # number of ReadExReq misses
 system.l2c.demand_misses::cpu0.dtb.walker            1                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst              7593                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            111157                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst              7598                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data            111005                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu1.dtb.walker            1                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              1010                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data             10866                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst               994                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data             10915                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu2.dtb.walker           10                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.inst              2911                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.data             21471                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                155022                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.itb.walker            1                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.inst              2913                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.data             21585                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                155025                       # number of demand (read+write) misses
 system.l2c.overall_misses::cpu0.dtb.walker            1                       # number of overall misses
 system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst             7593                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           111157                       # number of overall misses
+system.l2c.overall_misses::cpu0.inst             7598                       # number of overall misses
+system.l2c.overall_misses::cpu0.data           111005                       # number of overall misses
 system.l2c.overall_misses::cpu1.dtb.walker            1                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             1010                       # number of overall misses
-system.l2c.overall_misses::cpu1.data            10866                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst              994                       # number of overall misses
+system.l2c.overall_misses::cpu1.data            10915                       # number of overall misses
 system.l2c.overall_misses::cpu2.dtb.walker           10                       # number of overall misses
-system.l2c.overall_misses::cpu2.inst             2911                       # number of overall misses
-system.l2c.overall_misses::cpu2.data            21471                       # number of overall misses
-system.l2c.overall_misses::total               155022                       # number of overall misses
+system.l2c.overall_misses::cpu2.itb.walker            1                       # number of overall misses
+system.l2c.overall_misses::cpu2.inst             2913                       # number of overall misses
+system.l2c.overall_misses::cpu2.data            21585                       # number of overall misses
+system.l2c.overall_misses::total               155025                       # number of overall misses
 system.l2c.ReadReq_miss_latency::cpu1.dtb.walker        74500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst     72979250                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data     86304000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.dtb.walker       805500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.inst    221738500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.data    199604750                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total      581506500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst     70385750                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data     86555000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.dtb.walker       790250                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.itb.walker        75000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.inst    219321000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.data    195686250                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total      572887750                       # number of ReadReq miss cycles
 system.l2c.UpgradeReq_miss_latency::cpu1.data        93996                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu2.data       139494                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total       233490                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data    736617229                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu2.data   1419662152                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   2156279381                       # number of ReadExReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu2.data       139994                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total       233990                       # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data    724629978                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu2.data   1410364149                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   2134994127                       # number of ReadExReq miss cycles
 system.l2c.demand_miss_latency::cpu1.dtb.walker        74500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst     72979250                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data    822921229                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.dtb.walker       805500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.inst    221738500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.data   1619266902                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total      2737785881                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst     70385750                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data    811184978                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.dtb.walker       790250                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.itb.walker        75000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.inst    219321000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.data   1606050399                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total      2707881877                       # number of demand (read+write) miss cycles
 system.l2c.overall_miss_latency::cpu1.dtb.walker        74500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst     72979250                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data    822921229                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.dtb.walker       805500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.inst    221738500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.data   1619266902                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total     2737785881                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.dtb.walker         8702                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker         3145                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst         475530                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data         183509                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker         2609                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker         1169                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst         129911                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data          65489                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.dtb.walker        18802                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.itb.walker         4308                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.inst         285333                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.data         134397                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            1312904                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       597674                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           597674                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data         1433                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data          470                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2.data         1031                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            2934                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu2.data            2                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total             2                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       166697                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data        28153                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu2.data        52107                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           246957                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker         8702                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker         3145                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst          475530                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data          350206                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker         2609                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker         1169                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          129911                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data           93642                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.dtb.walker        18802                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.itb.walker         4308                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.inst          285333                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.data          186504                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             1559861                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker         8702                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker         3145                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         475530                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data         350206                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker         2609                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker         1169                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         129911                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data          93642                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.dtb.walker        18802                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.itb.walker         4308                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.inst         285333                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.data         186504                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            1559861                       # number of overall (read+write) accesses
+system.l2c.overall_miss_latency::cpu1.inst     70385750                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data    811184978                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.dtb.walker       790250                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.itb.walker        75000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.inst    219321000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.data   1606050399                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total     2707881877                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.dtb.walker         8693                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker         3139                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.inst         475598                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data         183502                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker         2623                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker         1183                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst         130675                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data          65643                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.dtb.walker        18906                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.itb.walker         4218                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.inst         284082                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.data         134239                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            1312501                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       597704                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           597704                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data         1432                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data          472                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu2.data         1035                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            2939                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu2.data            4                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total             4                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       166535                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data        28230                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu2.data        52246                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           247011                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker         8693                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker         3139                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst          475598                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data          350037                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker         2623                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker         1183                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          130675                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data           93873                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.dtb.walker        18906                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.itb.walker         4218                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.inst          284082                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.data          186485                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             1559512                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker         8693                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker         3139                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         475598                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data         350037                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker         2623                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker         1183                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         130675                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data          93873                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.dtb.walker        18906                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.itb.walker         4218                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.inst         284082                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.data         186485                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            1559512                       # number of overall (read+write) accesses
 system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000115                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000636                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.015967                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.035252                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000383                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.007775                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.017026                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.000532                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.inst      0.010202                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.data      0.018981                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.016500                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.990230                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.991489                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2.data     0.989331                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.990116                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.628014                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.346357                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2.data     0.363099                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.540009                       # miss rate for ReadExReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000637                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.015976                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.035242                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000381                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst      0.007607                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data      0.017001                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.000529                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.itb.walker     0.000237                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.inst      0.010254                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.data      0.018907                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.016488                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.990223                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.991525                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu2.data     0.985507                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.988772                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu2.data     0.250000                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.250000                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.627724                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.347113                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu2.data     0.364564                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.539992                       # miss rate for ReadExReq accesses
 system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000115                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.000636                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.015967                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.317405                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000383                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.007775                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.116038                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.dtb.walker     0.000532                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst       0.010202                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.data       0.115124                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.099382                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.000637                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.015976                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.317124                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000381                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.007607                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.116274                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.dtb.walker     0.000529                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.itb.walker     0.000237                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.inst       0.010254                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.data       0.115747                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.099406                       # miss rate for demand accesses
 system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000115                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.000636                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.015967                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.317405                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000383                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.007775                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.116038                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.dtb.walker     0.000532                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst      0.010202                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.data      0.115124                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.099382                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.000637                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.015976                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.317124                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000381                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.007607                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.116274                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.dtb.walker     0.000529                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.itb.walker     0.000237                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.inst      0.010254                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.data      0.115747                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.099406                       # miss rate for overall accesses
 system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        74500                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72256.683168                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 77402.690583                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker        80550                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.inst 76172.621092                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.data 78245.687966                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 26843.304251                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   201.708155                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu2.data   136.758824                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total    80.375215                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 75542.737053                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2.data 75034.997463                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 16168.982828                       # average ReadExReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 70810.613682                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 77558.243728                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker        79025                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker        75000                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.inst 75290.422245                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.data 77102.541371                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 26472.332609                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   200.846154                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu2.data   137.249020                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total    80.519615                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 73949.380345                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu2.data 74046.524335                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 16006.373531                       # average ReadExReq miss latency
 system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        74500                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 72256.683168                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 75733.593687                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.dtb.walker        80550                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.inst 76172.621092                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.data 75416.464161                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 17660.628046                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 70810.613682                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 74318.367201                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.dtb.walker        79025                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.itb.walker        75000                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.inst 75290.422245                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.data 74405.855872                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 17467.388337                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        74500                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 72256.683168                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 75733.593687                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.dtb.walker        80550                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.inst 76172.621092                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.data 75416.464161                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 17660.628046                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 70810.613682                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 74318.367201                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.dtb.walker        79025                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.itb.walker        75000                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.inst 75290.422245                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.data 74405.855872                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 17467.388337                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -877,134 +690,154 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               58494                       # number of writebacks
-system.l2c.writebacks::total                    58494                       # number of writebacks
+system.l2c.writebacks::writebacks               58490                       # number of writebacks
+system.l2c.writebacks::total                    58490                       # number of writebacks
 system.l2c.ReadReq_mshr_hits::cpu2.inst             1                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu2.data            12                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total                13                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu2.data            11                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::total                12                       # number of ReadReq MSHR hits
 system.l2c.demand_mshr_hits::cpu2.inst              1                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu2.data             12                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                 13                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu2.data             11                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                 12                       # number of demand (read+write) MSHR hits
 system.l2c.overall_mshr_hits::cpu2.inst             1                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu2.data            12                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                13                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu2.data            11                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total                12                       # number of overall MSHR hits
 system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker            1                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst         1010                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data         1115                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.inst          994                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.data         1116                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker           10                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.inst         2910                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.data         2539                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total            7585                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data          466                       # number of UpgradeReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.itb.walker            1                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.inst         2912                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.data         2527                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total            7561                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data          468                       # number of UpgradeReq MSHR misses
 system.l2c.UpgradeReq_mshr_misses::cpu2.data         1020                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total         1486                       # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data         9751                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu2.data        18920                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total         28671                       # number of ReadExReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total         1488                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu2.data            1                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total            1                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data         9799                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu2.data        19047                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total         28846                       # number of ReadExReq MSHR misses
 system.l2c.demand_mshr_misses::cpu1.dtb.walker            1                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst         1010                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data        10866                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst          994                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data        10915                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu2.dtb.walker           10                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.inst         2910                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.data        21459                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total            36256                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.itb.walker            1                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.inst         2912                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.data        21574                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total            36407                       # number of demand (read+write) MSHR misses
 system.l2c.overall_mshr_misses::cpu1.dtb.walker            1                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst         1010                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data        10866                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst          994                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data        10915                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu2.dtb.walker           10                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.inst         2910                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.data        21459                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total           36256                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.itb.walker            1                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.inst         2912                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.data        21574                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total           36407                       # number of overall MSHR misses
 system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker        62500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst     60167250                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data     72428000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker       680000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.inst    185219250                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.data    167287000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total    485844000                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data      4660466                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst     57779750                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data     72669000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker       666250                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker        62500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.inst    182779750                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.data    163556500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total    477576250                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data      4680468                       # number of UpgradeReq MSHR miss cycles
 system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data     10201020                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total     14861486                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    613187771                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   1183833848                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   1797021619                       # number of ReadExReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total     14881488                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu2.data        10001                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total        10001                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    600655022                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   1172932351                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   1773587373                       # number of ReadExReq MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker        62500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst     60167250                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data    685615771                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker       680000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.inst    185219250                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.data   1351120848                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total   2282865619                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst     57779750                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data    673324022                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker       666250                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.itb.walker        62500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.inst    182779750                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.data   1336488851                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   2251163623                       # number of demand (read+write) MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker        62500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst     60167250                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data    685615771                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker       680000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.inst    185219250                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.data   1351120848                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total   2282865619                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  25080786000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data  26172240000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total  51253026000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    932356006                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data   8515525000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   9447881006                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data  26013142006                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu2.data  34687765000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  60700907006                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000383                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.007775                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.017026                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.000532                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.010199                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.018892                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.005777                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.991489                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.989331                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.506476                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.346357                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.363099                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.116097                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000383                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.007775                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.116038                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.000532                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.inst     0.010199                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.data     0.115059                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.023243                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000383                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.007775                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.116038                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.000532                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.inst     0.010199                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.data     0.115059                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.023243                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_latency::cpu1.inst     57779750                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data    673324022                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker       666250                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.itb.walker        62500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.inst    182779750                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.data   1336488851                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   2251163623                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  25059808500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data  26177769250                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total  51237577750                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    932383523                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data   8518108000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   9450491523                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data  25992192023                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2.data  34695877250                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  60688069273                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000381                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.007607                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.017001                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.000529                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker     0.000237                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.010251                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.018825                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.005761                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.991525                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.985507                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.506295                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data     0.250000                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.250000                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.347113                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.364564                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.116780                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000381                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.007607                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.116274                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.000529                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.itb.walker     0.000237                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst     0.010251                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.data     0.115688                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.023345                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000381                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.007607                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.116274                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.000529                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.itb.walker     0.000237                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst     0.010251                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data     0.115688                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.023345                       # mshr miss rate for overall accesses
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        62500                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59571.534653                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64957.847534                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker        68000                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 63649.226804                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 65886.963371                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 64053.263019                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58128.521127                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65115.591398                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker        66625                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker        62500                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 62767.771291                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 64723.585279                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 63163.106732                       # average ReadReq mshr miss latency
 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data        10001                       # average UpgradeReq mshr miss latency
 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data        10001                       # average UpgradeReq mshr miss latency
 system.l2c.UpgradeReq_avg_mshr_miss_latency::total        10001                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62884.603733                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 62570.499366                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 62677.326183                       # average ReadExReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data        10001                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        10001                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61297.583631                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 61580.949808                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 61484.690182                       # average ReadExReq mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        62500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59571.534653                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63097.346862                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker        68000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63649.226804                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 62962.898924                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 62965.181460                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58128.521127                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61687.954375                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker        66625                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker        62500                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 62767.771291                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 61949.052146                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 61833.263466                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        62500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59571.534653                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63097.346862                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker        68000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63649.226804                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62962.898924                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 62965.181460                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58128.521127                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61687.954375                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker        66625                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker        62500                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 62767.771291                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 61949.052146                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 61833.263466                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -1021,52 +854,52 @@ system.cf0.dma_read_txs                             0                       # Nu
 system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
-system.toL2Bus.throughput                    58818769                       # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq            1020134                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           1020133                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq            432166                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp           432166                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           265053                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq            1501                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq             2                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp           1503                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq            80260                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp           80260                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side       831165                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2419053                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        15627                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        52402                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               3318247                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     26575552                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     37346205                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        21908                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        85644                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size::total           64029309                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus             141280603                       # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus          100404                       # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy         2176001251                       # Layer occupancy (ticks)
+system.toL2Bus.throughput                    58805312                       # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq            1019677                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           1019676                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq            432200                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp           432200                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           265274                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq            1507                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq             4                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp           1511                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq            80476                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp           80476                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side       830192                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      2419562                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        15560                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        52654                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               3317968                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     26544384                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     37373820                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        21604                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        86116                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size::total           64025924                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus             141258487                       # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus          100872                       # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy         2176910263                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        1872526171                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        1870334166                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        1845075146                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        1845880168                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy          10168460                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy          10179455                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy          31121231                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy          31260469                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
-system.iobus.throughput                      48762623                       # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq             13806510                       # Transaction distribution
-system.iobus.trans_dist::ReadResp            13806510                       # Transaction distribution
-system.iobus.trans_dist::WriteReq                2770                       # Transaction distribution
-system.iobus.trans_dist::WriteResp               2770                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        11390                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         3024                       # Packet count per connected master and slave (bytes)
+system.iobus.throughput                      48758934                       # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq             13774305                       # Transaction distribution
+system.iobus.trans_dist::ReadResp            13774305                       # Transaction distribution
+system.iobus.trans_dist::WriteReq                2774                       # Transaction distribution
+system.iobus.trans_dist::WriteResp               2774                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        11404                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         3022                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           18                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio          254                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio          252                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio       716834                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio       716614                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
@@ -1082,18 +915,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       731808                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side     26886752                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.clcd.dma::total     26886752                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                27618560                       # Packet count per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio        15354                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio         6048                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       731598                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side     26822560                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.clcd.dma::total     26822560                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                27554158                       # Packet count per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio        15368                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio         6044                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio           36                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio          508                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio          504                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio       713159                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio       712940                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
@@ -1109,18 +942,18 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total       735681                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side    107547008                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.realview.clcd.dma::total    107547008                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total            108282689                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus               117209335                       # Total data (bytes)
-system.iobus.reqLayer0.occupancy              7953000                       # Layer occupancy (ticks)
+system.iobus.tot_pkt_size_system.bridge.master::total       735468                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side    107290240                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.realview.clcd.dma::total    107290240                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::total            108025708                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus               117209339                       # Total data (bytes)
+system.iobus.reqLayer0.occupancy              7964000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy              1512000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy              1511000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer2.occupancy                18000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy               127000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy               126000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer4.occupancy                 8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
@@ -1128,7 +961,7 @@ system.iobus.reqLayer5.occupancy                 8000                       # La
 system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer6.occupancy                 8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy            358920000                       # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy            358810000                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer9.occupancy                 8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
@@ -1160,12 +993,12 @@ system.iobus.reqLayer22.occupancy                8000                       # La
 system.iobus.reqLayer22.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer23.occupancy                8000                       # Layer occupancy (ticks)
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer25.occupancy         13443376000                       # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy         13411280000                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.6                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy           729038000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy           728824000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy         36855449250                       # Layer occupancy (ticks)
-system.iobus.respLayer1.utilization               1.5                       # Layer utilization (%)
+system.iobus.respLayer1.occupancy         33525822000                       # Layer occupancy (ticks)
+system.iobus.respLayer1.utilization               1.4                       # Layer utilization (%)
 system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1189,25 +1022,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                     7998897                       # DTB read hits
+system.cpu0.dtb.read_hits                     7997782                       # DTB read hits
 system.cpu0.dtb.read_misses                      6203                       # DTB read misses
-system.cpu0.dtb.write_hits                    6598042                       # DTB write hits
-system.cpu0.dtb.write_misses                     1992                       # DTB write misses
+system.cpu0.dtb.write_hits                    6595987                       # DTB write hits
+system.cpu0.dtb.write_misses                     1983                       # DTB write misses
 system.cpu0.dtb.flush_tlb                         556                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid                678                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_mva_asid                676                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                     30                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    5672                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_entries                    5673                       # Number of entries that have been flushed from TLB
 system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.dtb.prefetch_faults                   123                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.dtb.perms_faults                      209                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                 8005100                       # DTB read accesses
-system.cpu0.dtb.write_accesses                6600034                       # DTB write accesses
+system.cpu0.dtb.read_accesses                 8003985                       # DTB read accesses
+system.cpu0.dtb.write_accesses                6597970                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         14596939                       # DTB hits
-system.cpu0.dtb.misses                           8195                       # DTB misses
-system.cpu0.dtb.accesses                     14605134                       # DTB accesses
+system.cpu0.dtb.hits                         14593769                       # DTB hits
+system.cpu0.dtb.misses                           8186                       # DTB misses
+system.cpu0.dtb.accesses                     14601955                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1229,15 +1062,15 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.inst_hits                    32342389                       # ITB inst hits
-system.cpu0.itb.inst_misses                      3452                       # ITB inst misses
+system.cpu0.itb.inst_hits                    32336935                       # ITB inst hits
+system.cpu0.itb.inst_misses                      3451                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
 system.cpu0.itb.flush_tlb                         556                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid                678                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_mva_asid                676                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.itb.flush_tlb_asid                     30                       # Number of times TLB was flushed by ASID
 system.cpu0.itb.flush_entries                    2628                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
@@ -1246,416 +1079,416 @@ system.cpu0.itb.domain_faults                       0                       # Nu
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                32345841                       # ITB inst accesses
-system.cpu0.itb.hits                         32342389                       # DTB hits
-system.cpu0.itb.misses                           3452                       # DTB misses
-system.cpu0.itb.accesses                     32345841                       # DTB accesses
-system.cpu0.numCycles                       113704712                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                32340386                       # ITB inst accesses
+system.cpu0.itb.hits                         32336935                       # DTB hits
+system.cpu0.itb.misses                           3451                       # DTB misses
+system.cpu0.itb.accesses                     32340386                       # DTB accesses
+system.cpu0.numCycles                       113724377                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   31867189                       # Number of instructions committed
-system.cpu0.committedOps                     42038889                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             37421309                       # Number of integer alu accesses
+system.cpu0.committedInsts                   31861763                       # Number of instructions committed
+system.cpu0.committedOps                     42032224                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses             37415212                       # Number of integer alu accesses
 system.cpu0.num_fp_alu_accesses                  4937                       # Number of float alu accesses
-system.cpu0.num_func_calls                    1198994                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      4247035                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    37421309                       # number of integer instructions
+system.cpu0.num_func_calls                    1199152                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      4246542                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    37415212                       # number of integer instructions
 system.cpu0.num_fp_insts                         4937                       # number of float instructions
-system.cpu0.num_int_register_reads          193973220                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          39529492                       # number of times the integer registers were written
+system.cpu0.num_int_register_reads          193939915                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          39523913                       # number of times the integer registers were written
 system.cpu0.num_fp_register_reads                3572                       # number of times the floating registers were read
 system.cpu0.num_fp_register_writes               1366                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                     15264742                       # number of memory refs
-system.cpu0.num_load_insts                    8367651                       # Number of load instructions
-system.cpu0.num_store_insts                   6897091                       # Number of store instructions
-system.cpu0.num_idle_cycles              111017320.581957                       # Number of idle cycles
-system.cpu0.num_busy_cycles              2687391.418043                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.023635                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.976365                       # Percentage of idle cycles
-system.cpu0.Branches                          5615714                       # Number of branches fetched
+system.cpu0.num_mem_refs                     15261638                       # number of memory refs
+system.cpu0.num_load_insts                    8366552                       # Number of load instructions
+system.cpu0.num_store_insts                   6895086                       # Number of store instructions
+system.cpu0.num_idle_cycles              110931893.434026                       # Number of idle cycles
+system.cpu0.num_busy_cycles              2792483.565974                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.024555                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.975445                       # Percentage of idle cycles
+system.cpu0.Branches                          5615139                       # Number of branches fetched
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu0.kern.inst.quiesce                   82892                       # number of quiesce instructions executed
-system.cpu0.icache.tags.replacements           891676                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.602493                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           43661110                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           892188                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            48.937119                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.replacements           891249                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.602369                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           43668526                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           891761                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            48.968867                       # Average number of references to valid blocks.
 system.cpu0.icache.tags.warmup_cycle       8187850250                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   495.418624                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst     7.559512                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu2.inst     8.624357                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.967615                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.014765                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu2.inst     0.016844                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999224                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   494.923201                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst     7.626935                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu2.inst     9.052233                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.966647                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.014896                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu2.inst     0.017680                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.999223                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          132                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          217                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          160                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          134                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          209                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          166                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         45469557                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        45469557                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     31868764                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst      8050810                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu2.inst      3741536                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       43661110                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     31868764                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst      8050810                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu2.inst      3741536                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        43661110                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     31868764                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst      8050810                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu2.inst      3741536                       # number of overall hits
-system.cpu0.icache.overall_hits::total       43661110                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       476273                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst       130180                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu2.inst       309800                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       916253                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       476273                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst       130180                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu2.inst       309800                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        916253                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       476273                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst       130180                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu2.inst       309800                       # number of overall misses
-system.cpu0.icache.overall_misses::total       916253                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   1759106250                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   4179473576                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total   5938579826                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst   1759106250                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu2.inst   4179473576                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total   5938579826                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst   1759106250                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu2.inst   4179473576                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total   5938579826                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     32345037                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst      8180990                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu2.inst      4051336                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     44577363                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     32345037                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst      8180990                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu2.inst      4051336                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     44577363                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     32345037                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst      8180990                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu2.inst      4051336                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     44577363                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014725                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.015912                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.076469                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.020554                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014725                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.015912                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu2.inst     0.076469                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.020554                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014725                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.015912                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu2.inst     0.076469                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.020554                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13512.876402                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13490.876617                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  6481.375587                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13512.876402                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13490.876617                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  6481.375587                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13512.876402                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13490.876617                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  6481.375587                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs         4072                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses         45475856                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        45475856                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     31863243                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst      8064619                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu2.inst      3740664                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       43668526                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     31863243                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst      8064619                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu2.inst      3740664                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        43668526                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     31863243                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst      8064619                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu2.inst      3740664                       # number of overall hits
+system.cpu0.icache.overall_hits::total       43668526                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       476340                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst       130939                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu2.inst       308276                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       915555                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       476340                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst       130939                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu2.inst       308276                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        915555                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       476340                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst       130939                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu2.inst       308276                       # number of overall misses
+system.cpu0.icache.overall_misses::total       915555                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   1766616750                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   4157487812                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total   5924104562                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst   1766616750                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu2.inst   4157487812                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total   5924104562                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst   1766616750                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu2.inst   4157487812                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total   5924104562                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     32339583                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst      8195558                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu2.inst      4048940                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     44584081                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     32339583                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst      8195558                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu2.inst      4048940                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     44584081                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     32339583                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst      8195558                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu2.inst      4048940                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     44584081                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014729                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.015977                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.076137                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.020535                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014729                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.015977                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu2.inst     0.076137                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.020535                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014729                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.015977                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu2.inst     0.076137                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.020535                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13491.906537                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13486.251969                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total  6470.506482                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13491.906537                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13486.251969                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total  6470.506482                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13491.906537                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13486.251969                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total  6470.506482                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs         4144                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              221                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              217                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    18.425339                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    19.096774                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        24058                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        24058                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu2.inst        24058                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        24058                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu2.inst        24058                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        24058                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       130180                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       285742                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       415922                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst       130180                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu2.inst       285742                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       415922                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst       130180                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu2.inst       285742                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       415922                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   1498352750                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   3400846060                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total   4899198810                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   1498352750                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   3400846060                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total   4899198810                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   1498352750                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   3400846060                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total   4899198810                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.015912                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.070530                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.009330                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.015912                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.070530                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.009330                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.015912                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.070530                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.009330                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11509.853664                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11901.806735                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11779.128803                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11509.853664                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11901.806735                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 11779.128803                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11509.853664                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11901.806735                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 11779.128803                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        23779                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        23779                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu2.inst        23779                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        23779                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu2.inst        23779                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        23779                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       130939                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       284497                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       415436                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst       130939                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu2.inst       284497                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       415436                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst       130939                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu2.inst       284497                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       415436                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   1504362250                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   3384633315                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total   4888995565                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   1504362250                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   3384633315                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total   4888995565                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   1504362250                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   3384633315                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total   4888995565                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.015977                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.070265                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.009318                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.015977                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.070265                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.009318                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.015977                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.070265                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.009318                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11489.031152                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11896.903359                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11768.348350                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11489.031152                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11896.903359                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 11768.348350                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11489.031152                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11896.903359                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 11768.348350                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements           629840                       # number of replacements
+system.cpu0.dcache.tags.replacements           629883                       # number of replacements
 system.cpu0.dcache.tags.tagsinuse          511.997118                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           23225212                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           630352                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            36.844830                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.total_refs           23225674                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           630395                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            36.843049                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle         21768000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   497.071711                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data     8.097941                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu2.data     6.827465                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.970843                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.015816                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu2.data     0.013335                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   497.048952                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data     8.104316                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu2.data     6.843850                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.970799                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.015829                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu2.data     0.013367                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999994                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          198                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          296                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          192                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          302                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::2           18                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         98826568                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        98826568                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data      6868032                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data      1817018                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu2.data      4638626                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       13323676                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      5966375                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data      1312197                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu2.data      2134420                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       9412992                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       131825                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data        32972                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu2.data        73365                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       238162                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       138288                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data        34722                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu2.data        74382                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       247392                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     12834407                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data      3129215                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu2.data      6773046                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        22736668                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     12834407                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data      3129215                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu2.data      6773046                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       22736668                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       177045                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data        63739                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu2.data       270648                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       511432                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       168130                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data        28623                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu2.data       606733                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       803486                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         6464                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         1750                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu2.data         3698                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        11912                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu2.data            2                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       345175                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data        92362                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu2.data       877381                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       1314918                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       345175                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data        92362                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu2.data       877381                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      1314918                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data    908043250                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu2.data   3905088066                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total   4813131316                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   1020010237                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu2.data  23150589506                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  24170599743                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     23020750                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data     49421249                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total     72441999                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data        26000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total        26000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data   1928053487                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu2.data  27055677572                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  28983731059                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data   1928053487                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu2.data  27055677572                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  28983731059                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      7045077                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data      1880757                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu2.data      4909274                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     13835108                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      6134505                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data      1340820                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu2.data      2741153                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     10216478                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       138289                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data        34722                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data        77063                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       250074                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       138288                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data        34722                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu2.data        74384                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       247394                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     13179582                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data      3221577                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu2.data      7650427                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     24051586                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     13179582                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data      3221577                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu2.data      7650427                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     24051586                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.025130                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.033890                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.055130                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.036966                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.027407                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.021347                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.221342                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.078646                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.046743                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.050400                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.047987                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.047634                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data     0.000027                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000008                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.026190                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.028670                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu2.data     0.114684                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.054671                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.026190                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.028670                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu2.data     0.114684                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.054671                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14246.273867                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14428.660348                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total  9411.087527                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 35636.035251                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 38156.140355                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 30082.166638                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13154.714286                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13364.318280                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  6081.430406                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data        13000                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        13000                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 20874.964672                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 30836.862859                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 22042.234618                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 20874.964672                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 30836.862859                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 22042.234618                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs         7997                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets         3099                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs              875                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets             50                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs     9.139429                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    61.980000                       # average number of cycles each access was blocked
+system.cpu0.dcache.tags.tag_accesses         98832175                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        98832175                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data      6866825                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data      1820637                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu2.data      4638025                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       13325487                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      5964516                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data      1315550                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu2.data      2131525                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       9411591                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       131816                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data        33033                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu2.data        73362                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       238211                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       138281                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data        34792                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu2.data        74313                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       247386                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     12831341                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data      3136187                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu2.data      6769550                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        22737078                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     12831341                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data      3136187                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu2.data      6769550                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       22737078                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       177037                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data        63884                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu2.data       270059                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       510980                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       167967                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data        28702                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu2.data       608180                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       804849                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         6465                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         1759                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu2.data         3713                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        11937                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu2.data            4                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total            4                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data       345004                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data        92586                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu2.data       878239                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       1315829                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data       345004                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data        92586                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu2.data       878239                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      1315829                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data    910211000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu2.data   3890836807                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total   4801047807                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   1008525490                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu2.data  22983455032                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  23991980522                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     23124000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data     49531749                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total     72655749                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data        64501                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total        64501                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data   1918736490                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu2.data  26874291839                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  28793028329                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data   1918736490                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu2.data  26874291839                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  28793028329                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      7043862                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data      1884521                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu2.data      4908084                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     13836467                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      6132483                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data      1344252                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu2.data      2739705                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     10216440                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       138281                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data        34792                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data        77075                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       250148                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       138281                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data        34792                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu2.data        74317                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       247390                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     13176345                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data      3228773                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu2.data      7647789                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     24052907                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     13176345                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data      3228773                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu2.data      7647789                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     24052907                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.025134                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.033899                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.055023                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.036930                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.027390                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.021352                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.221987                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.078780                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.046753                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.050558                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data     0.048174                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.047720                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data     0.000054                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000016                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.026184                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.028675                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu2.data     0.114836                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.054706                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.026184                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.028675                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu2.data     0.114836                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.054706                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14247.871141                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14407.358418                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total  9395.764623                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 35137.812348                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 37790.547259                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 29809.294069                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13146.105742                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13340.088608                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  6086.600402                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 16125.250000                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 16125.250000                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 20723.829629                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 30600.203178                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 21882.044193                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 20723.829629                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 30600.203178                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 21882.044193                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs         7912                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets         2132                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs              872                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets             43                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs     9.073394                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    49.581395                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       597674                       # number of writebacks
-system.cpu0.dcache.writebacks::total           597674                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       139516                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       139516                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data       553631                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total       553631                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data          397                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total          397                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu2.data       693147                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total       693147                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu2.data       693147                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total       693147                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data        63739                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       131132                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       194871                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        28623                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        53102                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total        81725                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         1750                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data         3301                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         5051                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data            2                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data        92362                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu2.data       184234                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       276596                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data        92362                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu2.data       184234                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       276596                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data    780368750                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   1698635349                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   2479004099                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data    960165763                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   1859721243                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   2819887006                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     19520250                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data     38036501                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     57556751                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data        22000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total        22000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   1740534513                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   3558356592                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total   5298891105                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   1740534513                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data   3558356592                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total   5298891105                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  27401033000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data  28573458500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  55974491500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   1439106494                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data  13338859363                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total  14777965857                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data  28840139494                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data  41912317863                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  70752457357                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.033890                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.026711                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.014085                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.021347                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.019372                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.007999                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.050400                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.042835                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.020198                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data     0.000027                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000008                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.028670                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.024082                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.011500                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.028670                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.024082                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.011500                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12243.190982                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12953.629541                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12721.257134                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33545.252524                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 35021.679843                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34504.582515                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11154.428571                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11522.720691                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11395.119976                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data        11000                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        11000                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18844.703590                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19314.331730                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19157.511696                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18844.703590                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19314.331730                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19157.511696                       # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks       597704                       # number of writebacks
+system.cpu0.dcache.writebacks::total           597704                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       139099                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       139099                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data       554931                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total       554931                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data          402                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total          402                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu2.data       694030                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total       694030                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu2.data       694030                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total       694030                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data        63884                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       130960                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       194844                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        28702                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        53249                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total        81951                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         1759                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data         3311                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         5070                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data            4                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total            4                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data        92586                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu2.data       184209                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       276795                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data        92586                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu2.data       184209                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       276795                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data    782254000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   1693207098                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   2475461098                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data    948597510                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   1850547743                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   2799145253                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     19606000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data     38066251                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     57672251                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data        56499                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total        56499                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   1730851510                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data   3543754841                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total   5274606351                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   1730851510                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data   3543754841                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total   5274606351                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  27378129500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data  28579482250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  55957611750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data   1439295977                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data  13341687506                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total  14780983483                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data  28817425477                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data  41921169756                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  70738595233                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.033899                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.026683                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.014082                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.021352                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.019436                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.008021                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.050558                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data     0.042958                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.020268                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data     0.000054                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000016                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.028675                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.024087                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.011508                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.028675                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.024087                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.011508                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12244.912654                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12929.192868                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12704.836166                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33049.874922                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 34752.722924                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34156.328208                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11146.105742                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11496.904561                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11375.197436                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 14124.750000                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14124.750000                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18694.527358                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19237.685678                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19056.003002                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18694.527358                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19237.685678                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19056.003002                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -1689,25 +1522,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                     2093956                       # DTB read hits
-system.cpu1.dtb.read_misses                      2077                       # DTB read misses
-system.cpu1.dtb.write_hits                    1416211                       # DTB write hits
+system.cpu1.dtb.read_hits                     2097642                       # DTB read hits
+system.cpu1.dtb.read_misses                      2089                       # DTB read misses
+system.cpu1.dtb.write_hits                    1419704                       # DTB write hits
 system.cpu1.dtb.write_misses                      373                       # DTB write misses
 system.cpu1.dtb.flush_tlb                         554                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid                221                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                     12                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    1760                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries                    1767                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                    36                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                    39                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.dtb.perms_faults                       79                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                 2096033                       # DTB read accesses
-system.cpu1.dtb.write_accesses                1416584                       # DTB write accesses
+system.cpu1.dtb.read_accesses                 2099731                       # DTB read accesses
+system.cpu1.dtb.write_accesses                1420077                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                          3510167                       # DTB hits
-system.cpu1.dtb.misses                           2450                       # DTB misses
-system.cpu1.dtb.accesses                      3512617                       # DTB accesses
+system.cpu1.dtb.hits                          3517346                       # DTB hits
+system.cpu1.dtb.misses                           2462                       # DTB misses
+system.cpu1.dtb.accesses                      3519808                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1729,8 +1562,8 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.inst_hits                     8180990                       # ITB inst hits
-system.cpu1.itb.inst_misses                      1185                       # ITB inst misses
+system.cpu1.itb.inst_hits                     8195558                       # ITB inst hits
+system.cpu1.itb.inst_misses                      1195                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
@@ -1739,51 +1572,51 @@ system.cpu1.itb.flush_tlb                         554                       # Nu
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
 system.cpu1.itb.flush_tlb_mva_asid                221                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                     12                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                     944                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                     946                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                 8182175                       # ITB inst accesses
-system.cpu1.itb.hits                          8180990                       # DTB hits
-system.cpu1.itb.misses                           1185                       # DTB misses
-system.cpu1.itb.accesses                      8182175                       # DTB accesses
-system.cpu1.numCycles                       581419148                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                 8196753                       # ITB inst accesses
+system.cpu1.itb.hits                          8195558                       # DTB hits
+system.cpu1.itb.misses                           1195                       # DTB misses
+system.cpu1.itb.accesses                      8196753                       # DTB accesses
+system.cpu1.numCycles                       584703165                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                    7970398                       # Number of instructions committed
-system.cpu1.committedOps                     10116193                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses              9089557                       # Number of integer alu accesses
+system.cpu1.committedInsts                    7984738                       # Number of instructions committed
+system.cpu1.committedOps                     10135701                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses              9107037                       # Number of integer alu accesses
 system.cpu1.num_fp_alu_accesses                  2019                       # Number of float alu accesses
-system.cpu1.num_func_calls                     304010                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      1112792                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                     9089557                       # number of integer instructions
+system.cpu1.num_func_calls                     304651                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      1115193                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                     9107037                       # number of integer instructions
 system.cpu1.num_fp_insts                         2019                       # number of float instructions
-system.cpu1.num_int_register_reads           52989642                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes           9881584                       # number of times the integer registers were written
+system.cpu1.num_int_register_reads           53092313                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes           9899825                       # number of times the integer registers were written
 system.cpu1.num_fp_register_reads                1441                       # number of times the floating registers were read
 system.cpu1.num_fp_register_writes                580                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                      3676962                       # number of memory refs
-system.cpu1.num_load_insts                    2186992                       # Number of load instructions
-system.cpu1.num_store_insts                   1489970                       # Number of store instructions
-system.cpu1.num_idle_cycles              545339727.510646                       # Number of idle cycles
-system.cpu1.num_busy_cycles              36079420.489354                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.062054                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.937946                       # Percentage of idle cycles
-system.cpu1.Branches                          1445114                       # Number of branches fetched
+system.cpu1.num_mem_refs                      3684662                       # number of memory refs
+system.cpu1.num_load_insts                    2190856                       # Number of load instructions
+system.cpu1.num_store_insts                   1493806                       # Number of store instructions
+system.cpu1.num_idle_cycles              548865377.428164                       # Number of idle cycles
+system.cpu1.num_busy_cycles              35837787.571836                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.061292                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.938708                       # Percentage of idle cycles
+system.cpu1.Branches                          1448177                       # Number of branches fetched
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu2.branchPred.lookups                4780240                       # Number of BP lookups
-system.cpu2.branchPred.condPredicted          3898194                       # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect           223690                       # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups             3180058                       # Number of BTB lookups
-system.cpu2.branchPred.BTBHits                2524004                       # Number of BTB hits
+system.cpu2.branchPred.lookups                4782343                       # Number of BP lookups
+system.cpu2.branchPred.condPredicted          3901882                       # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect           223184                       # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups             3184465                       # Number of BTB lookups
+system.cpu2.branchPred.BTBHits                2528356                       # Number of BTB hits
 system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct            79.369747                       # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS                 414035                       # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect             21682                       # Number of incorrect RAS predictions.
+system.cpu2.branchPred.BTBHitPct            79.396571                       # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS                 413120                       # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect             21664                       # Number of incorrect RAS predictions.
 system.cpu2.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu2.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu2.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1807,25 +1640,25 @@ system.cpu2.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu2.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu2.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu2.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu2.dtb.read_hits                    10926394                       # DTB read hits
-system.cpu2.dtb.read_misses                     23081                       # DTB read misses
-system.cpu2.dtb.write_hits                    3349602                       # DTB write hits
-system.cpu2.dtb.write_misses                     6536                       # DTB write misses
+system.cpu2.dtb.read_hits                    10925413                       # DTB read hits
+system.cpu2.dtb.read_misses                     23157                       # DTB read misses
+system.cpu2.dtb.write_hits                    3347832                       # DTB write hits
+system.cpu2.dtb.write_misses                     6500                       # DTB write misses
 system.cpu2.dtb.flush_tlb                         552                       # Number of times complete TLB was flushed
 system.cpu2.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu2.dtb.flush_tlb_mva_asid                540                       # Number of times TLB was flushed by MVA & ASID
+system.cpu2.dtb.flush_tlb_mva_asid                542                       # Number of times TLB was flushed by MVA & ASID
 system.cpu2.dtb.flush_tlb_asid                     21                       # Number of times TLB was flushed by ASID
-system.cpu2.dtb.flush_entries                    2337                       # Number of entries that have been flushed from TLB
-system.cpu2.dtb.align_faults                      728                       # Number of TLB faults due to alignment restrictions
-system.cpu2.dtb.prefetch_faults                   164                       # Number of TLB faults due to prefetch
+system.cpu2.dtb.flush_entries                    2330                       # Number of entries that have been flushed from TLB
+system.cpu2.dtb.align_faults                      739                       # Number of TLB faults due to alignment restrictions
+system.cpu2.dtb.prefetch_faults                   153                       # Number of TLB faults due to prefetch
 system.cpu2.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu2.dtb.perms_faults                      452                       # Number of TLB faults due to permissions restrictions
-system.cpu2.dtb.read_accesses                10949475                       # DTB read accesses
-system.cpu2.dtb.write_accesses                3356138                       # DTB write accesses
+system.cpu2.dtb.perms_faults                      476                       # Number of TLB faults due to permissions restrictions
+system.cpu2.dtb.read_accesses                10948570                       # DTB read accesses
+system.cpu2.dtb.write_accesses                3354332                       # DTB write accesses
 system.cpu2.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu2.dtb.hits                         14275996                       # DTB hits
-system.cpu2.dtb.misses                          29617                       # DTB misses
-system.cpu2.dtb.accesses                     14305613                       # DTB accesses
+system.cpu2.dtb.hits                         14273245                       # DTB hits
+system.cpu2.dtb.misses                          29657                       # DTB misses
+system.cpu2.dtb.accesses                     14302902                       # DTB accesses
 system.cpu2.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu2.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu2.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1847,294 +1680,294 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu2.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu2.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu2.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu2.itb.inst_hits                     4052754                       # ITB inst hits
-system.cpu2.itb.inst_misses                      4681                       # ITB inst misses
+system.cpu2.itb.inst_hits                     4050371                       # ITB inst hits
+system.cpu2.itb.inst_misses                      4655                       # ITB inst misses
 system.cpu2.itb.read_hits                           0                       # DTB read hits
 system.cpu2.itb.read_misses                         0                       # DTB read misses
 system.cpu2.itb.write_hits                          0                       # DTB write hits
 system.cpu2.itb.write_misses                        0                       # DTB write misses
 system.cpu2.itb.flush_tlb                         552                       # Number of times complete TLB was flushed
 system.cpu2.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu2.itb.flush_tlb_mva_asid                540                       # Number of times TLB was flushed by MVA & ASID
+system.cpu2.itb.flush_tlb_mva_asid                542                       # Number of times TLB was flushed by MVA & ASID
 system.cpu2.itb.flush_tlb_asid                     21                       # Number of times TLB was flushed by ASID
-system.cpu2.itb.flush_entries                    1722                       # Number of entries that have been flushed from TLB
+system.cpu2.itb.flush_entries                    1717                       # Number of entries that have been flushed from TLB
 system.cpu2.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu2.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu2.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu2.itb.perms_faults                      963                       # Number of TLB faults due to permissions restrictions
+system.cpu2.itb.perms_faults                      991                       # Number of TLB faults due to permissions restrictions
 system.cpu2.itb.read_accesses                       0                       # DTB read accesses
 system.cpu2.itb.write_accesses                      0                       # DTB write accesses
-system.cpu2.itb.inst_accesses                 4057435                       # ITB inst accesses
-system.cpu2.itb.hits                          4052754                       # DTB hits
-system.cpu2.itb.misses                           4681                       # DTB misses
-system.cpu2.itb.accesses                      4057435                       # DTB accesses
-system.cpu2.numCycles                        88329548                       # number of cpu cycles simulated
+system.cpu2.itb.inst_accesses                 4055026                       # ITB inst accesses
+system.cpu2.itb.hits                          4050371                       # DTB hits
+system.cpu2.itb.misses                           4655                       # DTB misses
+system.cpu2.itb.accesses                      4055026                       # DTB accesses
+system.cpu2.numCycles                        88306923                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles           9368286                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts                      32480016                       # Number of instructions fetch has processed
-system.cpu2.fetch.Branches                    4780240                       # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches           2938039                       # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles                      6853051                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles                1759446                       # Number of cycles fetch has spent squashing
-system.cpu2.fetch.TlbCycles                     50956                       # Number of cycles fetch has spent waiting for tlb
-system.cpu2.fetch.BlockedCycles              19165610                       # Number of cycles fetch has spent blocked
-system.cpu2.fetch.MiscStallCycles                 248                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.PendingDrainCycles              867                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu2.fetch.PendingTrapStallCycles        33412                       # Number of stall cycles due to pending traps
-system.cpu2.fetch.PendingQuiesceStallCycles       724302                       # Number of stall cycles due to pending quiesce instructions
-system.cpu2.fetch.IcacheWaitRetryStallCycles          479                       # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines                  4051341                       # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes               290206                       # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.ItlbSquashes                   2075                       # Number of outstanding ITLB misses that were squashed
-system.cpu2.fetch.rateDist::samples          37405927                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean             1.043731                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev            2.431289                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.icacheStallCycles           9346989                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts                      32490356                       # Number of instructions fetch has processed
+system.cpu2.fetch.Branches                    4782343                       # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches           2941476                       # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles                      6854845                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles                1758076                       # Number of cycles fetch has spent squashing
+system.cpu2.fetch.TlbCycles                     51100                       # Number of cycles fetch has spent waiting for tlb
+system.cpu2.fetch.BlockedCycles              19188137                       # Number of cycles fetch has spent blocked
+system.cpu2.fetch.MiscStallCycles                 264                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.PendingDrainCycles              924                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu2.fetch.PendingTrapStallCycles        33833                       # Number of stall cycles due to pending traps
+system.cpu2.fetch.PendingQuiesceStallCycles       718254                       # Number of stall cycles due to pending quiesce instructions
+system.cpu2.fetch.IcacheWaitRetryStallCycles          435                       # Number of stall cycles due to full MSHR
+system.cpu2.fetch.CacheLines                  4048944                       # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes               289644                       # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.ItlbSquashes                   2020                       # Number of outstanding ITLB misses that were squashed
+system.cpu2.fetch.rateDist::samples          37402774                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean             1.043825                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev            2.431125                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0                30558019     81.69%     81.69% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1                  385772      1.03%     82.72% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2                  515915      1.38%     84.10% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3                  819609      2.19%     86.29% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4                  625256      1.67%     87.97% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5                  342326      0.92%     88.88% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6                 1044683      2.79%     91.67% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7                  230213      0.62%     92.29% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8                 2884134      7.71%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0                30553136     81.69%     81.69% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1                  385541      1.03%     82.72% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2                  516309      1.38%     84.10% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3                  819811      2.19%     86.29% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4                  629209      1.68%     87.97% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5                  341976      0.91%     88.89% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6                 1043472      2.79%     91.68% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7                  229749      0.61%     92.29% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8                 2883571      7.71%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total            37405927                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate                 0.054118                       # Number of branch fetches per cycle
-system.cpu2.fetch.rate                       0.367714                       # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles                 9993670                       # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles             19739606                       # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles                  6190224                       # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles               324742                       # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles               1156786                       # Number of cycles decode is squashing
-system.cpu2.decode.BranchResolved              609493                       # Number of times decode resolved a branch
-system.cpu2.decode.BranchMispred                53173                       # Number of times decode detected a branch misprediction
-system.cpu2.decode.DecodedInsts              36942390                       # Number of instructions handled by decode
-system.cpu2.decode.SquashedInsts               178785                       # Number of squashed instructions handled by decode
-system.cpu2.rename.SquashCycles               1156786                       # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles                10542033                       # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles                6802518                       # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles      11433975                       # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles                  5951508                       # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles              1518203                       # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts              34853467                       # Number of instructions processed by rename
-system.cpu2.rename.ROBFullEvents                  104                       # Number of times rename has blocked due to ROB full
-system.cpu2.rename.IQFullEvents                325261                       # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LSQFullEvents               883658                       # Number of times rename has blocked due to LSQ full
-system.cpu2.rename.FullRegisterEvents             140                       # Number of times there has been no free registers
-system.cpu2.rename.RenamedOperands           37388012                       # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups            160878048                       # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups       148313673                       # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups             3357                       # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps             26544776                       # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps                10843235                       # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts            285604                       # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts        261905                       # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts                  3322163                       # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads             6624625                       # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores            3901879                       # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads           530898                       # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores          772979                       # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded                  32179363                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded             501455                       # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued                 34749523                       # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued            55329                       # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined        7166724                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined     19100923                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved        145150                       # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples     37405927                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean        0.928984                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev       1.590317                       # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total            37402774                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate                 0.054156                       # Number of branch fetches per cycle
+system.cpu2.fetch.rate                       0.367925                       # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles                 9974482                       # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles             19754417                       # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles                  6192036                       # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles               324676                       # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles               1156258                       # Number of cycles decode is squashing
+system.cpu2.decode.BranchResolved              608942                       # Number of times decode resolved a branch
+system.cpu2.decode.BranchMispred                52938                       # Number of times decode detected a branch misprediction
+system.cpu2.decode.DecodedInsts              36945008                       # Number of instructions handled by decode
+system.cpu2.decode.SquashedInsts               178323                       # Number of squashed instructions handled by decode
+system.cpu2.rename.SquashCycles               1156258                       # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles                10522715                       # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles                6823267                       # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles      11427905                       # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles                  5953488                       # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles              1518249                       # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts              34855169                       # Number of instructions processed by rename
+system.cpu2.rename.ROBFullEvents                   93                       # Number of times rename has blocked due to ROB full
+system.cpu2.rename.IQFullEvents                324878                       # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LSQFullEvents               884563                       # Number of times rename has blocked due to LSQ full
+system.cpu2.rename.FullRegisterEvents             125                       # Number of times there has been no free registers
+system.cpu2.rename.RenamedOperands           37394312                       # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups            160859531                       # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups       148302897                       # Number of integer rename lookups
+system.cpu2.rename.fp_rename_lookups             3365                       # Number of floating rename lookups
+system.cpu2.rename.CommittedMaps             26531284                       # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps                10863027                       # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts            285247                       # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts        261616                       # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts                  3319534                       # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads             6621271                       # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores            3899723                       # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads           529692                       # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores          779693                       # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded                  32174765                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded             504636                       # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued                 34747602                       # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued            55361                       # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined        7180763                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined     19089893                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved        148627                       # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples     37402774                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean        0.929011                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev       1.590003                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0           24720555     66.09%     66.09% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1            3979487     10.64%     76.73% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2            2312001      6.18%     82.91% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3            1968335      5.26%     88.17% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4            2779247      7.43%     95.60% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5             968566      2.59%     98.19% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6             497905      1.33%     99.52% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7             144867      0.39%     99.91% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8              34964      0.09%    100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0           24715445     66.08%     66.08% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1            3980638     10.64%     76.72% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2            2310084      6.18%     82.90% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3            1974798      5.28%     88.18% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4            2777209      7.43%     95.60% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5             968528      2.59%     98.19% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6             496348      1.33%     99.52% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7             144954      0.39%     99.91% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8              34770      0.09%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total       37405927                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total       37402774                       # Number of insts issued each cycle
 system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu                  19427      1.28%      1.28% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult                     1      0.00%      1.28% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv                      0      0.00%      1.28% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd                    0      0.00%      1.28% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp                    0      0.00%      1.28% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt                    0      0.00%      1.28% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult                   0      0.00%      1.28% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv                    0      0.00%      1.28% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%      1.28% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd                     0      0.00%      1.28% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%      1.28% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu                     0      0.00%      1.28% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp                     0      0.00%      1.28% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt                     0      0.00%      1.28% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc                    0      0.00%      1.28% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult                    0      0.00%      1.28% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%      1.28% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift                   0      0.00%      1.28% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%      1.28% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%      1.28% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%      1.28% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%      1.28% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%      1.28% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%      1.28% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%      1.28% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%      1.28% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%      1.28% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%      1.28% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%      1.28% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead               1392100     91.45%     92.73% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite               110700      7.27%    100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu                  19778      1.30%      1.30% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult                     0      0.00%      1.30% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv                      0      0.00%      1.30% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd                    0      0.00%      1.30% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp                    0      0.00%      1.30% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt                    0      0.00%      1.30% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult                   0      0.00%      1.30% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv                    0      0.00%      1.30% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%      1.30% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd                     0      0.00%      1.30% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%      1.30% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu                     0      0.00%      1.30% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp                     0      0.00%      1.30% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt                     0      0.00%      1.30% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc                    0      0.00%      1.30% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult                    0      0.00%      1.30% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%      1.30% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift                   0      0.00%      1.30% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%      1.30% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%      1.30% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%      1.30% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%      1.30% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%      1.30% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%      1.30% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%      1.30% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%      1.30% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%      1.30% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%      1.30% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%      1.30% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead               1391818     91.56%     92.86% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite               108581      7.14%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu2.iq.FU_type_0::No_OpClass             8337      0.02%      0.02% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu             19784762     56.94%     56.96% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult               28044      0.08%     57.04% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     57.04% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     57.04% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     57.04% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     57.04% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     57.04% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     57.04% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     57.04% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     57.04% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     57.04% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     57.04% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     57.04% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     57.04% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc                  4      0.00%     57.04% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     57.04% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     57.04% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     57.04% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc              4      0.00%     57.04% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     57.04% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     57.04% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     57.04% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     57.04% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     57.04% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     57.04% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc           384      0.00%     57.04% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     57.04% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc            4      0.00%     57.04% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     57.04% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead            11409832     32.83%     89.88% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite            3518152     10.12%    100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::No_OpClass             8338      0.02%      0.02% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu             19786480     56.94%     56.97% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult               28071      0.08%     57.05% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     57.05% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     57.05% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     57.05% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     57.05% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     57.05% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     57.05% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     57.05% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     57.05% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     57.05% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     57.05% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     57.05% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     57.05% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc                  5      0.00%     57.05% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     57.05% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     57.05% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     57.05% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc              5      0.00%     57.05% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     57.05% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     57.05% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     57.05% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     57.05% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     57.05% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     57.05% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc           384      0.00%     57.05% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     57.05% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc            5      0.00%     57.05% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     57.05% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead            11408808     32.83%     89.88% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite            3515506     10.12%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total              34749523                       # Type of FU issued
-system.cpu2.iq.rate                          0.393408                       # Inst issue rate
-system.cpu2.iq.fu_busy_cnt                    1522228                       # FU busy when requested
-system.cpu2.iq.fu_busy_rate                  0.043806                       # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads         108504523                       # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes         39852721                       # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses     28051848                       # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads               7496                       # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes              3959                       # Number of floating instruction queue writes
-system.cpu2.iq.fp_inst_queue_wakeup_accesses         3344                       # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses              36259410                       # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses                   4004                       # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads          206643                       # Number of loads that had data forwarded from stores
+system.cpu2.iq.FU_type_0::total              34747602                       # Type of FU issued
+system.cpu2.iq.rate                          0.393487                       # Inst issue rate
+system.cpu2.iq.fu_busy_cnt                    1520177                       # FU busy when requested
+system.cpu2.iq.fu_busy_rate                  0.043749                       # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads         108495492                       # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes         39865371                       # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses     28048299                       # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.fp_inst_queue_reads               7541                       # Number of floating instruction queue reads
+system.cpu2.iq.fp_inst_queue_writes              3951                       # Number of floating instruction queue writes
+system.cpu2.iq.fp_inst_queue_wakeup_accesses         3361                       # Number of floating instruction queue wakeup accesses
+system.cpu2.iq.int_alu_accesses              36255412                       # Number of integer alu accesses
+system.cpu2.iq.fp_alu_accesses                   4029                       # Number of floating point alu accesses
+system.cpu2.iew.lsq.thread0.forwLoads          205816                       # Number of loads that had data forwarded from stores
 system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads      1533647                       # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses         2027                       # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation         9444                       # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores       562515                       # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedLoads      1533232                       # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses         1949                       # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation         9487                       # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores       562230                       # Number of stores squashed
 system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads      5286265                       # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked       344866                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu2.iew.lsq.thread0.rescheduledLoads      5287398                       # Number of loads that were rescheduled
+system.cpu2.iew.lsq.thread0.cacheBlocked       344554                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles               1156786                       # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles                5177746                       # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles                87629                       # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts           32763326                       # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts            61736                       # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts              6624625                       # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts             3901879                       # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts            359192                       # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents                 29253                       # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents                 2415                       # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents          9444                       # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect        107780                       # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect        89787                       # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts              197567                       # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts             33835206                       # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts             11139307                       # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts           914317                       # Number of squashed instructions skipped in execute
+system.cpu2.iew.iewSquashCycles               1156258                       # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles                5195373                       # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles                88422                       # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts           32761739                       # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts            61550                       # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts              6621271                       # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts             3899723                       # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts            362828                       # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents                 29785                       # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewLSQFullEvents                 2577                       # Number of times the LSQ has become full, causing a stall
+system.cpu2.iew.memOrderViolationEvents          9487                       # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect        107399                       # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect        89296                       # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts              196695                       # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts             33832847                       # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts             11137918                       # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts           914755                       # Number of squashed instructions skipped in execute
 system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu2.iew.exec_nop                        82508                       # number of nop insts executed
-system.cpu2.iew.exec_refs                    14623996                       # number of memory reference insts executed
-system.cpu2.iew.exec_branches                 3761047                       # Number of branches executed
-system.cpu2.iew.exec_stores                   3484689                       # Number of stores executed
-system.cpu2.iew.exec_rate                    0.383056                       # Inst execution rate
-system.cpu2.iew.wb_sent                      33433924                       # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count                     28055192                       # cumulative count of insts written-back
-system.cpu2.iew.wb_producers                 16098734                       # num instructions producing a value
-system.cpu2.iew.wb_consumers                 29085804                       # num instructions consuming a value
+system.cpu2.iew.exec_nop                        82338                       # number of nop insts executed
+system.cpu2.iew.exec_refs                    14620271                       # number of memory reference insts executed
+system.cpu2.iew.exec_branches                 3761250                       # Number of branches executed
+system.cpu2.iew.exec_stores                   3482353                       # Number of stores executed
+system.cpu2.iew.exec_rate                    0.383128                       # Inst execution rate
+system.cpu2.iew.wb_sent                      33431998                       # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count                     28051660                       # cumulative count of insts written-back
+system.cpu2.iew.wb_producers                 16098716                       # num instructions producing a value
+system.cpu2.iew.wb_consumers                 29087027                       # num instructions consuming a value
 system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate                      0.317620                       # insts written-back per cycle
-system.cpu2.iew.wb_fanout                    0.553491                       # average fanout of values written-back
+system.cpu2.iew.wb_rate                      0.317661                       # insts written-back per cycle
+system.cpu2.iew.wb_fanout                    0.553467                       # average fanout of values written-back
 system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts        7134883                       # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls         356305                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts           171320                       # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples     36248935                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean     0.700393                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev     1.738300                       # Number of insts commited each cycle
+system.cpu2.commit.commitSquashedInsts        7131660                       # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls         356009                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts           171002                       # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples     36246314                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean     0.700075                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev     1.737192                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0     27340525     75.42%     75.42% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1      4430140     12.22%     87.65% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2      1255420      3.46%     91.11% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3       637620      1.76%     92.87% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4       510981      1.41%     94.28% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5       317875      0.88%     95.15% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6       419132      1.16%     96.31% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7       311355      0.86%     97.17% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8      1025887      2.83%    100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0     27334959     75.41%     75.41% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1      4433375     12.23%     87.65% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2      1255912      3.46%     91.11% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3       639801      1.77%     92.88% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4       511761      1.41%     94.29% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5       317445      0.88%     95.16% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6       418775      1.16%     96.32% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7       310656      0.86%     97.18% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8      1023630      2.82%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total     36248935                       # Number of insts commited each cycle
-system.cpu2.commit.committedInsts            20549284                       # Number of instructions committed
-system.cpu2.commit.committedOps              25388512                       # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total     36246314                       # Number of insts commited each cycle
+system.cpu2.commit.committedInsts            20540563                       # Number of instructions committed
+system.cpu2.commit.committedOps              25375153                       # Number of ops (including micro ops) committed
 system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu2.commit.refs                       8430342                       # Number of memory references committed
-system.cpu2.commit.loads                      5090978                       # Number of loads committed
-system.cpu2.commit.membars                      94231                       # Number of memory barriers committed
-system.cpu2.commit.branches                   3241086                       # Number of branches committed
+system.cpu2.commit.refs                       8425532                       # Number of memory references committed
+system.cpu2.commit.loads                      5088039                       # Number of loads committed
+system.cpu2.commit.membars                      94081                       # Number of memory barriers committed
+system.cpu2.commit.branches                   3238597                       # Number of branches committed
 system.cpu2.commit.fp_insts                      3299                       # Number of committed floating point instructions.
-system.cpu2.commit.int_insts                 22644563                       # Number of committed integer instructions.
-system.cpu2.commit.function_calls              295800                       # Number of function calls committed.
-system.cpu2.commit.bw_lim_events              1025887                       # number cycles where commit BW limit reached
+system.cpu2.commit.int_insts                 22633154                       # Number of committed integer instructions.
+system.cpu2.commit.function_calls              295425                       # Number of function calls committed.
+system.cpu2.commit.bw_lim_events              1023630                       # number cycles where commit BW limit reached
 system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu2.rob.rob_reads                    67225559                       # The number of ROB reads
-system.cpu2.rob.rob_writes                   66247729                       # The number of ROB writes
-system.cpu2.timesIdled                         359329                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles                       50923621                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles                  3554004914                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts                   20493925                       # Number of Instructions Simulated
-system.cpu2.committedOps                     25333153                       # Number of Ops (including micro ops) Simulated
-system.cpu2.committedInsts_total             20493925                       # Number of Instructions Simulated
-system.cpu2.cpi                              4.310036                       # CPI: Cycles Per Instruction
-system.cpu2.cpi_total                        4.310036                       # CPI: Total CPI of All Threads
-system.cpu2.ipc                              0.232017                       # IPC: Instructions Per Cycle
-system.cpu2.ipc_total                        0.232017                       # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads               157011420                       # number of integer regfile reads
-system.cpu2.int_regfile_writes               29864331                       # number of integer regfile writes
-system.cpu2.fp_regfile_reads                    46835                       # number of floating regfile reads
-system.cpu2.fp_regfile_writes                   45178                       # number of floating regfile writes
-system.cpu2.misc_regfile_reads               66864323                       # number of misc regfile reads
-system.cpu2.misc_regfile_writes                296992                       # number of misc regfile writes
+system.cpu2.rob.rob_reads                    67208837                       # The number of ROB reads
+system.cpu2.rob.rob_writes                   66213984                       # The number of ROB writes
+system.cpu2.timesIdled                         359252                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles                       50904149                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles                  3546216081                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts                   20485207                       # Number of Instructions Simulated
+system.cpu2.committedOps                     25319797                       # Number of Ops (including micro ops) Simulated
+system.cpu2.committedInsts_total             20485207                       # Number of Instructions Simulated
+system.cpu2.cpi                              4.310765                       # CPI: Cycles Per Instruction
+system.cpu2.cpi_total                        4.310765                       # CPI: Total CPI of All Threads
+system.cpu2.ipc                              0.231977                       # IPC: Instructions Per Cycle
+system.cpu2.ipc_total                        0.231977                       # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads               156999830                       # number of integer regfile reads
+system.cpu2.int_regfile_writes               29869338                       # number of integer regfile writes
+system.cpu2.fp_regfile_reads                    46882                       # number of floating regfile reads
+system.cpu2.fp_regfile_writes                   45194                       # number of floating regfile writes
+system.cpu2.misc_regfile_reads               67020139                       # number of misc regfile reads
+system.cpu2.misc_regfile_writes                296788                       # number of misc regfile writes
 system.iocache.tags.replacements                    0                       # number of replacements
 system.iocache.tags.tagsinuse                       0                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
@@ -2151,10 +1984,10 @@ system.iocache.avg_blocked_cycles::no_mshrs          nan                       #
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1347826044250                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1347826044250                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1347826044250                       # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1347826044250                       # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1539425711000                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1539425711000                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1539425711000                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1539425711000                       # number of overall MSHR uncacheable cycles
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
index 1944dbbecdeb905501e761239e3f7b96ede7aa33..ef9bf74a4ec985b5853ea13239539170cabd7cf9 100644 (file)
@@ -1,16 +1,16 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.550456                       # Number of seconds simulated
-sim_ticks                                2550455693500                       # Number of ticks simulated
-final_tick                               2550455693500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.550648                       # Number of seconds simulated
+sim_ticks                                2550647964000                       # Number of ticks simulated
+final_tick                               2550647964000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  59744                       # Simulator instruction rate (inst/s)
-host_op_rate                                    76873                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2526372396                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 427472                       # Number of bytes of host memory used
-host_seconds                                  1009.53                       # Real time elapsed on the host
-sim_insts                                    60313472                       # Number of instructions simulated
-sim_ops                                      77606209                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  57676                       # Simulator instruction rate (inst/s)
+host_op_rate                                    74213                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2439007396                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 470664                       # Number of bytes of host memory used
+host_seconds                                  1045.77                       # Real time elapsed on the host
+sim_insts                                    60315890                       # Number of instructions simulated
+sim_ops                                      77609880                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.realview.nvmem.bytes_read::cpu0.inst           64                       # Number of bytes read from this memory
@@ -26,142 +26,142 @@ system.realview.nvmem.bw_inst_read::total           25                       # I
 system.realview.nvmem.bw_total::cpu0.inst           25                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total              25                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bytes_read::realview.clcd    121110528                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker         2176                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker         2048                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           504320                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          5079000                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker          832                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           295488                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          4015064                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            131007536                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       504320                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       295488                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          799808                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      3786368                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data       1520720                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data       1495380                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6802468                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.inst           483008                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          5043284                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker          640                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           315584                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          4051356                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            131006576                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       483008                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       315584                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          798592                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      3785856                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data       1521376                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data       1494724                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           6801956                       # Number of bytes written to this memory
 system.physmem.num_reads::realview.clcd      15138816                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker           34                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker           32                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst              7880                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             79395                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker           13                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              4617                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             62741                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total              15293498                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           59162                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data           380180                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data           373845                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               813187                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd        47485839                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker           853                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::cpu0.inst              7547                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             78836                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker           10                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              4931                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             63309                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total              15293483                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           59154                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data           380344                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data           373681                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               813179                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd        47482259                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker           803                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker            50                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              197737                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             1991409                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker           326                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst              115857                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             1574254                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                51366325                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         197737                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst         115857                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             313594                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1484585                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data             596254                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data             586319                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2667158                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1484585                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd       47485839                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker          853                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              189367                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             1977256                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker           251                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst              123727                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             1588363                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                51362077                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         189367                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst         123727                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             313094                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1484272                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data             596466                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data             586017                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2666756                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1484272                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd       47482259                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker          803                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           50                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             197737                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            2587663                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker          326                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst             115857                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            2160572                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               54033483                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                      15293498                       # Number of read requests accepted
-system.physmem.writeReqs                       813187                       # Number of write requests accepted
-system.physmem.readBursts                    15293498                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     813187                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                978241024                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                    542848                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   6911808                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 131007536                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                6802468                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                     8482                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                  705190                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           4696                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              955869                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              955539                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              954667                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              954789                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              955759                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              955951                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              954859                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              954668                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              956272                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              955769                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             954516                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             954114                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             956222                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             955973                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             955087                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             954962                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                6687                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                6466                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                6605                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                6628                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                6579                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                6834                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6823                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                6763                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7134                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                6882                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               6543                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6191                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7147                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               6760                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7044                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               6911                       # Per bank write bursts
+system.physmem.bw_total::cpu0.inst             189367                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            2573722                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker          251                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst             123727                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            2174381                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               54028833                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                      15293483                       # Number of read requests accepted
+system.physmem.writeReqs                       813179                       # Number of write requests accepted
+system.physmem.readBursts                    15293483                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     813179                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                976671488                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                   2111424                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   6834624                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 131006576                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                6801956                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                    32991                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                  706366                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs           4694                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0              955809                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              953120                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              953063                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              953290                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              955524                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              952811                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              952747                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              952554                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              956154                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              953015                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             952848                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             952579                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             956184                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             953741                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             953594                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             953459                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                6616                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                6407                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                6542                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                6564                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                6491                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                6761                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6753                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                6706                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7029                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                6806                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               6476                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6118                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7056                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               6677                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               6959                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               6830                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2550454486000                       # Total gap between requests
+system.physmem.totGap                    2550646795500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                      44                       # Read request sizes (log2)
 system.physmem.readPktSize::3                15138816                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  154638                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  154623                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                 754025                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  59162                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1173632                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                   1113468                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                   1067801                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                   3688063                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                   2661485                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                   2656312                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                   2669345                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                     52900                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                     59933                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                     20414                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                    20379                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                    20336                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                    20280                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                    20242                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                    20201                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                    20171                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                       38                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                        7                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  59154                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1055042                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    994364                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                    947765                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                    947544                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                    945397                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                    945218                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                   2783572                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                   2783267                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                   3699218                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                     24042                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                    23218                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                    23233                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                    22770                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                    22263                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                    21886                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                    21619                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                       50                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                       16                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::18                        4                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::19                        4                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
@@ -173,717 +173,457 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                      4933                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                      5661                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                      4993                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                      5216                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                      5378                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                      4912                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                      4910                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                      4924                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                      4835                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                      4824                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                     4802                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                     4788                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                     4768                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                     4751                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                     4744                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     4738                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     4712                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4729                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4737                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     4717                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     4678                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5055                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                      126                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                       57                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        86865                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean    11341.188281                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean    1014.168764                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev   16824.493217                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64-71          23628     27.20%     27.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-135        14156     16.30%     43.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192-199         2700      3.11%     46.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-263         2166      2.49%     49.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320-327         1318      1.52%     50.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-391         1170      1.35%     51.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448-455          896      1.03%     52.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-519          913      1.05%     54.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576-583          566      0.65%     54.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-647          606      0.70%     55.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704-711          521      0.60%     55.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-775          631      0.73%     56.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832-839          271      0.31%     57.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-903          267      0.31%     57.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960-967          154      0.18%     57.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1031          590      0.68%     58.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088-1095          110      0.13%     58.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152-1159          147      0.17%     58.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216-1223           73      0.08%     58.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280-1287          151      0.17%     58.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344-1351           55      0.06%     58.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408-1415          532      0.61%     59.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472-1479           32      0.04%     59.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536-1543          226      0.26%     59.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600-1607           18      0.02%     59.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664-1671          114      0.13%     59.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1728-1735           25      0.03%     59.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1792-1799          112      0.13%     60.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856-1863           26      0.03%     60.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1920-1927           51      0.06%     60.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984-1991           19      0.02%     60.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2048-2055          424      0.49%     60.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112-2119           10      0.01%     60.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2176-2183           29      0.03%     60.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2240-2247           12      0.01%     60.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2304-2311           47      0.05%     60.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2368-2375           15      0.02%     60.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2432-2439           23      0.03%     60.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2496-2503           12      0.01%     60.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2560-2567          153      0.18%     60.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2624-2631           13      0.01%     60.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2688-2695           25      0.03%     61.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2752-2759            8      0.01%     61.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2816-2823           30      0.03%     61.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2880-2887           14      0.02%     61.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2944-2951           22      0.03%     61.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3008-3015            8      0.01%     61.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3072-3079          344      0.40%     61.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3136-3143            8      0.01%     61.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3200-3207           12      0.01%     61.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3264-3271            9      0.01%     61.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3328-3335          150      0.17%     61.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3392-3399           12      0.01%     61.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3456-3463            8      0.01%     61.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3520-3527           14      0.02%     61.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3584-3591          136      0.16%     61.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3648-3655           11      0.01%     61.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3712-3719           13      0.01%     61.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3776-3783           10      0.01%     61.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3840-3847           83      0.10%     62.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3904-3911            9      0.01%     62.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3968-3975           12      0.01%     62.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4032-4039           10      0.01%     62.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4096-4103          470      0.54%     62.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4160-4167            7      0.01%     62.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4224-4231           13      0.01%     62.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4288-4295            8      0.01%     62.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4352-4359           83      0.10%     62.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4416-4423           13      0.01%     62.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4480-4487           10      0.01%     62.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4544-4551           11      0.01%     62.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4608-4615           20      0.02%     62.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4672-4679           11      0.01%     62.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4736-4743            7      0.01%     62.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4800-4807            8      0.01%     62.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4864-4871          151      0.17%     63.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4928-4935            7      0.01%     63.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4992-4999           13      0.01%     63.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5056-5063           10      0.01%     63.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5120-5127          397      0.46%     63.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5184-5191            3      0.00%     63.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5248-5255           13      0.01%     63.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5312-5319            7      0.01%     63.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5376-5383           18      0.02%     63.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5440-5447           13      0.01%     63.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5504-5511            9      0.01%     63.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5568-5575           10      0.01%     63.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5632-5639           76      0.09%     63.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5696-5703            6      0.01%     63.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5760-5767           11      0.01%     63.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5824-5831            5      0.01%     63.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5888-5895          208      0.24%     63.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5952-5959            5      0.01%     63.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6016-6023           13      0.01%     63.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6080-6087            7      0.01%     63.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6144-6151          368      0.42%     64.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6208-6215            6      0.01%     64.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6272-6279            3      0.00%     64.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6336-6343            4      0.00%     64.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6400-6407           73      0.08%     64.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6464-6471            2      0.00%     64.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6528-6535            7      0.01%     64.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6592-6599            5      0.01%     64.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6656-6663          137      0.16%     64.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6720-6727           10      0.01%     64.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6784-6791           24      0.03%     64.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6848-6855            2      0.00%     64.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6912-6919           60      0.07%     64.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6976-6983            5      0.01%     64.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7040-7047            5      0.01%     64.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7104-7111            7      0.01%     64.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7168-7175          270      0.31%     65.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7232-7239            5      0.01%     65.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7296-7303           10      0.01%     65.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7360-7367            9      0.01%     65.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7424-7431          215      0.25%     65.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7488-7495            8      0.01%     65.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7552-7559           21      0.02%     65.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7616-7623            7      0.01%     65.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7680-7687            8      0.01%     65.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7744-7751            2      0.00%     65.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7808-7815            2      0.00%     65.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7936-7943           69      0.08%     65.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8000-8007            4      0.00%     65.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8064-8071            6      0.01%     65.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8192-8199          602      0.69%     66.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8384-8391            1      0.00%     66.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8448-8455           67      0.08%     66.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8640-8647            1      0.00%     66.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8704-8711            2      0.00%     66.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8960-8967          203      0.23%     66.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9216-9223          262      0.30%     66.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9280-9287            1      0.00%     66.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9472-9479           56      0.06%     66.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9728-9735          129      0.15%     67.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9792-9799            1      0.00%     67.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9984-9991           65      0.07%     67.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10048-10055            1      0.00%     67.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10240-10247          354      0.41%     67.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10368-10375            1      0.00%     67.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10496-10503          132      0.15%     67.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10752-10759           66      0.08%     67.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11008-11015            2      0.00%     67.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11264-11271          377      0.43%     68.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11520-11527          143      0.16%     68.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11776-11783            1      0.00%     68.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12032-12039           65      0.07%     68.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12288-12295          444      0.51%     68.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12544-12551           65      0.07%     69.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12672-12679            1      0.00%     69.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12800-12807          120      0.14%     69.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13056-13063          129      0.15%     69.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13312-13319          321      0.37%     69.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13568-13575            4      0.00%     69.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13696-13703            1      0.00%     69.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13824-13831          137      0.16%     69.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13952-13959            1      0.00%     69.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14080-14087            5      0.01%     69.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14144-14151            1      0.00%     69.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14208-14215            1      0.00%     69.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14336-14343          386      0.44%     70.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14592-14599           64      0.07%     70.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14848-14855           71      0.08%     70.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15104-15111           56      0.06%     70.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15232-15239            1      0.00%     70.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15360-15367          386      0.44%     70.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15616-15623          121      0.14%     71.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15680-15687            1      0.00%     71.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15872-15879            5      0.01%     71.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16128-16135          125      0.14%     71.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16384-16391          641      0.74%     72.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16448-16455            1      0.00%     72.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16512-16519            1      0.00%     72.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16640-16647          125      0.14%     72.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16832-16839            1      0.00%     72.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16896-16903            7      0.01%     72.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17152-17159          120      0.14%     72.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17216-17223            1      0.00%     72.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17408-17415          386      0.44%     72.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17472-17479            1      0.00%     72.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17664-17671           54      0.06%     72.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17728-17735            2      0.00%     72.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17856-17863            1      0.00%     72.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17920-17927           71      0.08%     72.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17984-17991            1      0.00%     72.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18112-18119            1      0.00%     72.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18176-18183           65      0.07%     72.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18368-18375            1      0.00%     72.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18432-18439          384      0.44%     73.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18688-18695            5      0.01%     73.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18944-18951          132      0.15%     73.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19200-19207            6      0.01%     73.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19328-19335            1      0.00%     73.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19456-19463          322      0.37%     73.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19712-19719          129      0.15%     74.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19968-19975          120      0.14%     74.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20224-20231           65      0.07%     74.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20480-20487          442      0.51%     74.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20672-20679            1      0.00%     74.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20736-20743           64      0.07%     74.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20992-20999            1      0.00%     74.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21120-21127            1      0.00%     74.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21248-21255          144      0.17%     75.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21504-21511          377      0.43%     75.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22016-22023           65      0.07%     75.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22272-22279          131      0.15%     75.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22528-22535          354      0.41%     76.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22656-22663            1      0.00%     76.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22784-22791           66      0.08%     76.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22912-22919            1      0.00%     76.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23040-23047          128      0.15%     76.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23296-23303           55      0.06%     76.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23552-23559          261      0.30%     76.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23616-23623            1      0.00%     76.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23808-23815          203      0.23%     76.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24064-24071            2      0.00%     76.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24256-24263            1      0.00%     76.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24320-24327           67      0.08%     77.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24512-24519            1      0.00%     77.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24576-24583          495      0.57%     77.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24832-24839           66      0.08%     77.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25088-25095            2      0.00%     77.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25344-25351          204      0.23%     77.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25600-25607          262      0.30%     78.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25856-25863           56      0.06%     78.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26112-26119          129      0.15%     78.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26368-26375           67      0.08%     78.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26432-26439            1      0.00%     78.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26560-26567            1      0.00%     78.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26624-26631          355      0.41%     78.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26752-26759            1      0.00%     78.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26880-26887          131      0.15%     79.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26944-26951            1      0.00%     79.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27072-27079            1      0.00%     79.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27136-27143           64      0.07%     79.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27328-27335            2      0.00%     79.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27392-27399            3      0.00%     79.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27520-27527            1      0.00%     79.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27648-27655          377      0.43%     79.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27840-27847            1      0.00%     79.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27904-27911          143      0.16%     79.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28416-28423           65      0.07%     79.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28672-28679          441      0.51%     80.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28928-28935           65      0.07%     80.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29120-29127            1      0.00%     80.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29184-29191          119      0.14%     80.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29312-29319            1      0.00%     80.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29440-29447          128      0.15%     80.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29568-29575            1      0.00%     80.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29696-29703          321      0.37%     81.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29952-29959            6      0.01%     81.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30208-30215          134      0.15%     81.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30464-30471            4      0.00%     81.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30720-30727          385      0.44%     81.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30976-30983           66      0.08%     81.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31232-31239           71      0.08%     81.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31296-31303            2      0.00%     81.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31488-31495           54      0.06%     81.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31744-31751          385      0.44%     82.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32000-32007          120      0.14%     82.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32256-32263            4      0.00%     82.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32512-32519          124      0.14%     82.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32768-32775          640      0.74%     83.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32896-32903            1      0.00%     83.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33024-33031          124      0.14%     83.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33280-33287            4      0.00%     83.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33536-33543          121      0.14%     83.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33664-33671            1      0.00%     83.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33728-33735            1      0.00%     83.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33792-33799          386      0.44%     84.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34048-34055           54      0.06%     84.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34112-34119            1      0.00%     84.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34304-34311           71      0.08%     84.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34368-34375            1      0.00%     84.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34560-34567           66      0.08%     84.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34816-34823          384      0.44%     84.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35008-35015            1      0.00%     84.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35072-35079            4      0.00%     84.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35328-35335          134      0.15%     84.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35584-35591            5      0.01%     84.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35776-35783            1      0.00%     84.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35840-35847          321      0.37%     85.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36096-36103          128      0.15%     85.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36224-36231            2      0.00%     85.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36352-36359          120      0.14%     85.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36608-36615           65      0.07%     85.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36864-36871          441      0.51%     86.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37120-37127           64      0.07%     86.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37376-37383            1      0.00%     86.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37632-37639          143      0.16%     86.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37760-37767            1      0.00%     86.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37824-37831            1      0.00%     86.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37888-37895          377      0.43%     86.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38144-38151            1      0.00%     86.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38208-38215            1      0.00%     86.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38400-38407           64      0.07%     86.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38464-38471            1      0.00%     86.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38656-38663          130      0.15%     87.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38912-38919          355      0.41%     87.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39168-39175           66      0.08%     87.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39424-39431          128      0.15%     87.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39616-39623            1      0.00%     87.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39680-39687           55      0.06%     87.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39936-39943          261      0.30%     88.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40000-40007            1      0.00%     88.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40192-40199          203      0.23%     88.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40448-40455            1      0.00%     88.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40640-40647            1      0.00%     88.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40704-40711           66      0.08%     88.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40960-40967          496      0.57%     88.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41216-41223           67      0.08%     89.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41280-41287            1      0.00%     89.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41472-41479            2      0.00%     89.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41728-41735          203      0.23%     89.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41920-41927            1      0.00%     89.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41984-41991          260      0.30%     89.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42240-42247           55      0.06%     89.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42304-42311            1      0.00%     89.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42496-42503          128      0.15%     89.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42752-42759           67      0.08%     89.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42880-42887            1      0.00%     89.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43008-43015          353      0.41%     90.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43264-43271          131      0.15%     90.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43520-43527           65      0.07%     90.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43840-43847            1      0.00%     90.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44032-44039          379      0.44%     90.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44288-44295          143      0.16%     91.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44352-44359            1      0.00%     91.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44416-44423            2      0.00%     91.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44800-44807           67      0.08%     91.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44864-44871            1      0.00%     91.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45056-45063          443      0.51%     91.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45312-45319           67      0.08%     91.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45440-45447            1      0.00%     91.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45568-45575          122      0.14%     91.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45632-45639            1      0.00%     91.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45696-45703            1      0.00%     91.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45760-45767            1      0.00%     91.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45824-45831          130      0.15%     92.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46016-46023            1      0.00%     92.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46080-46087          322      0.37%     92.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46336-46343            4      0.00%     92.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46592-46599          131      0.15%     92.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46848-46855            5      0.01%     92.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46976-46983            1      0.00%     92.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47104-47111          384      0.44%     93.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47360-47367           64      0.07%     93.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47552-47559            1      0.00%     93.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47616-47623           72      0.08%     93.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47808-47815            1      0.00%     93.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47872-47879           54      0.06%     93.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48128-48135          385      0.44%     93.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48384-48391          121      0.14%     93.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48576-48583            1      0.00%     93.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48640-48647            5      0.01%     93.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48832-48839            1      0.00%     93.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48896-48903          123      0.14%     93.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::49024-49031            2      0.00%     93.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::49088-49095            1      0.00%     93.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::49152-49159         5211      6.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::49536-49543            1      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::49856-49863            1      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::50112-50119            1      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::50624-50631            1      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::50688-50695            1      0.00%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::51008-51015            1      0.00%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::51456-51463            1      0.00%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::51648-51655            1      0.00%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::51712-51719            1      0.00%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          86865                       # Bytes accessed per row activation
-system.physmem.totQLat                   369784547000                       # Total ticks spent queuing
-system.physmem.totMemAccLat              463560559500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                  76425080000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                 17350932500                       # Total ticks spent accessing banks
-system.physmem.avgQLat                       24192.62                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                     1135.16                       # Average bank access latency per DRAM burst
+system.physmem.wrQLenPdf::0                       297                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                       290                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                       288                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                       285                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                       284                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                       277                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                       277                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                       276                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                       273                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                       269                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                      267                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                      264                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                      262                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                      261                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                      261                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     2143                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2163                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     2390                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     3959                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     4958                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     5019                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     5011                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     5118                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     5111                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     4981                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     5456                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     5185                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     5074                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     5855                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     5373                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     4897                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     4875                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     4842                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     2215                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      991                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      982                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                     1034                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                     1009                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      915                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      954                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      918                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      909                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      899                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      867                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      895                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      858                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      852                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      852                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      853                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      851                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      847                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      846                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      844                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      863                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       13                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       965273                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean     1013.486813                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     999.850047                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev      92.541667                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127           4202      0.44%      0.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         3517      0.36%      0.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         1855      0.19%      0.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         1291      0.13%      1.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639          949      0.10%      1.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          717      0.07%      1.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          589      0.06%      1.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          765      0.08%      1.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151       951388     98.56%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         965273                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5001                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean      3051.486103                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev    52637.524815                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-65535          4974     99.46%     99.46% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::65536-131071            1      0.02%     99.48% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::131072-196607            8      0.16%     99.64% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::196608-262143            6      0.12%     99.76% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::393216-458751            1      0.02%     99.78% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::589824-655359            2      0.04%     99.82% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::983040-1.04858e+06            1      0.02%     99.84% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1.17965e+06-1.24518e+06            7      0.14%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1.37626e+06-1.44179e+06            1      0.02%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            5001                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5001                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        21.353929                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       19.695200                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        9.701170                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::1                   8      0.16%      0.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::2                   2      0.04%      0.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::3                   3      0.06%      0.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4                   1      0.02%      0.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::5                   8      0.16%      0.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::6                   1      0.02%      0.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::7                   1      0.02%      0.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8                   3      0.06%      0.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::9                   5      0.10%      0.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::10                  2      0.04%      0.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::11                  5      0.10%      0.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12                  2      0.04%      0.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::13                  1      0.02%      0.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::14                  1      0.02%      0.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::15                 10      0.20%      1.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               2816     56.31%     57.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 26      0.52%     57.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                135      2.70%     60.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                879     17.58%     78.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                 49      0.98%     79.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 23      0.46%     79.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 15      0.30%     79.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 25      0.50%     80.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                 14      0.28%     80.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                 18      0.36%     81.04% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                  7      0.14%     81.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27                 15      0.30%     81.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28                 16      0.32%     81.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29                 18      0.36%     82.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30                 15      0.30%     82.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::31                  8      0.16%     82.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32                 16      0.32%     82.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::33                 10      0.20%     83.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::37                  1      0.02%     83.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::39                  1      0.02%     83.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40                  3      0.06%     83.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::41                243      4.86%     88.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::42                480      9.60%     97.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::43                 27      0.54%     98.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44                 20      0.40%     98.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::45                 27      0.54%     99.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::46                 21      0.42%     99.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::47                 16      0.32%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48                  2      0.04%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::49                  1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::50                  1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5001                       # Writes before turning the bus around for reads
+system.physmem.totQLat                   577566851750                       # Total ticks spent queuing
+system.physmem.totMemAccLat              682115428000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                  76302460000                       # Total ticks spent in databus transfers
+system.physmem.totBankLat                 28246116250                       # Total ticks spent accessing banks
+system.physmem.avgQLat                       37847.20                       # Average queueing delay per DRAM burst
+system.physmem.avgBankLat                     1850.93                       # Average bank access latency per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  30327.78                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         383.56                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           2.71                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       51.37                       # Average system read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  44698.13                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         382.91                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           2.68                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       51.36                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        2.67                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           3.02                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       3.00                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           3.01                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       2.99                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         0.18                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                         1.05                       # Average write queue length when enqueuing
-system.physmem.readRowHits                   15213014                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     93134                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   99.53                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  86.24                       # Row buffer hit rate for writes
-system.physmem.avgGap                       158347.57                       # Average gap between requests
-system.physmem.pageHitRate                      99.44                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               2.65                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                     54973753                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq            16346163                       # Transaction distribution
-system.membus.trans_dist::ReadResp           16346166                       # Transaction distribution
+system.physmem.avgRdQLen                         6.73                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        15.38                       # Average write queue length when enqueuing
+system.physmem.readRowHits                   14274135                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     91331                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   93.54                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  85.51                       # Row buffer hit rate for writes
+system.physmem.avgGap                       158359.74                       # Average gap between requests
+system.physmem.pageHitRate                      93.48                       # Row buffer hit rate, read and write combined
+system.physmem.prechargeAllPercent               4.60                       # Percentage of time for which DRAM has all the banks in precharge state
+system.membus.throughput                     54969038                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq            16346130                       # Transaction distribution
+system.membus.trans_dist::ReadResp           16346133                       # Transaction distribution
 system.membus.trans_dist::WriteReq             763365                       # Transaction distribution
 system.membus.trans_dist::WriteResp            763365                       # Transaction distribution
-system.membus.trans_dist::Writeback             59162                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4696                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            4696                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            131412                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           131412                       # Transaction distribution
+system.membus.trans_dist::Writeback             59154                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4693                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq              1                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            4694                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            131434                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           131434                       # Transaction distribution
 system.membus.trans_dist::LoadLockedReq             3                       # Transaction distribution
 system.membus.trans_dist::StoreCondReq              3                       # Transaction distribution
 system.membus.trans_dist::StoreCondResp             3                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      2383052                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      2383060                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port            2                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         3790                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio            2                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1885968                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      4272814                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1885926                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      4272780                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     30277632                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total     30277632                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total               34550446                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave      2390470                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count::total               34550412                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave      2390486                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port           64                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio         7580                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio            4                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     16699476                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::total     19097594                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     16698004                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::total     19096138                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port    121110528                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.iocache.mem_side::total    121110528                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total           140208122                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus              140208122                       # Total data (bytes)
+system.membus.tot_pkt_size::total           140206666                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus              140206666                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy          1487391000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy          1487459000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy                1000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             3584500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             3645000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer4.occupancy                1500                       # Layer occupancy (ticks)
 system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer6.occupancy         17566049500                       # Layer occupancy (ticks)
+system.membus.reqLayer6.occupancy         17565357500                       # Layer occupancy (ticks)
 system.membus.reqLayer6.utilization               0.7                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         4736056592                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         4737629056                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
-system.membus.respLayer2.occupancy        34187486731                       # Layer occupancy (ticks)
-system.membus.respLayer2.utilization              1.3                       # Layer utilization (%)
+system.membus.respLayer2.occupancy        37816335199                       # Layer occupancy (ticks)
+system.membus.respLayer2.utilization              1.5                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.l2c.tags.replacements                    64408                       # number of replacements
-system.l2c.tags.tagsinuse                51449.796153                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    1905827                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   129798                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    14.683023                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle             2540137710500                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   36969.006628                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker    22.725284                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000371                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     4879.693838                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     3326.753767                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker    11.863300                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     3332.963946                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     2906.789020                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.564102                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000347                       # Average percentage of cache occupancy
+system.l2c.tags.replacements                    64394                       # number of replacements
+system.l2c.tags.tagsinuse                51423.269942                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    1904392                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   129782                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    14.673776                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle             2513283956500                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks   36971.606132                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker    22.825180                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000372                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     4577.267389                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     3052.603978                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker     7.951997                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     3614.635006                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     3176.379887                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.564142                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000348                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.074458                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.050762                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000181                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.050857                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.044354                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.785062                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1023           22                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        65368                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
+system.l2c.tags.occ_percent::cpu0.inst       0.069844                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.046579                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000121                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.055155                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.048468                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.784657                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1023           21                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        65367                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1023::4           21                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1024::0           37                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1024::1          342                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         3071                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         6835                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        55083                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1023     0.000336                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.997437                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 18939251                       # Number of tag accesses
-system.l2c.tags.data_accesses                18939251                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker        33125                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker         6695                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst             507433                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             188763                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker        31491                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker         7375                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             463939                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data             198427                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1437248                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          607832                       # number of Writeback hits
-system.l2c.Writeback_hits::total               607832                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data              21                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data              20                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                  41                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data             6                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data             4                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total                10                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            60764                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            52147                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               112911                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker         33125                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker          6695                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              507433                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              249527                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker         31491                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          7375                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              463939                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              250574                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1550159                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker        33125                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker         6695                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             507433                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             249527                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker        31491                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         7375                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             463939                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             250574                       # number of overall hits
-system.l2c.overall_hits::total                1550159                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.dtb.walker           34                       # number of ReadReq misses
+system.l2c.tags.age_task_id_blocks_1024::2         3070                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         6838                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        55080                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1023     0.000320                       # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024     0.997421                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 18929537                       # Number of tag accesses
+system.l2c.tags.data_accesses                18929537                       # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.dtb.walker        32378                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker         6463                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.inst             508619                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data             187861                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker        31368                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker         7240                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst             462078                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data             199585                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1435592                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          608227                       # number of Writeback hits
+system.l2c.Writeback_hits::total               608227                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data              20                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data              19                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                  39                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data             5                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data             6                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total                11                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data            60126                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            52843                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               112969                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.dtb.walker         32378                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker          6463                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst              508619                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              247987                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker         31368                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker          7240                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              462078                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              252428                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 1548561                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker        32378                       # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker         6463                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst             508619                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             247987                       # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker        31368                       # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker         7240                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             462078                       # number of overall hits
+system.l2c.overall_hits::cpu1.data             252428                       # number of overall hits
+system.l2c.overall_hits::total                1548561                       # number of overall hits
+system.l2c.ReadReq_misses::cpu0.dtb.walker           32                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu0.itb.walker            2                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst             7770                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data             6307                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.dtb.walker           13                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst             4624                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data             4437                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                23187                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data          1611                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data          1300                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              2911                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          73970                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          59227                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             133197                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.dtb.walker           34                       # number of demand (read+write) misses
+system.l2c.ReadReq_misses::cpu0.inst             7439                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data             6013                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.dtb.walker           10                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst             4938                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data             4716                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                23150                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data          1629                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data          1286                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              2915                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data            1                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total               1                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data          73716                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data          59496                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             133212                       # number of ReadExReq misses
+system.l2c.demand_misses::cpu0.dtb.walker           32                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst              7770                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data             80277                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker           13                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              4624                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data             63664                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                156384                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker           34                       # number of overall misses
+system.l2c.demand_misses::cpu0.inst              7439                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data             79729                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.dtb.walker           10                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst              4938                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data             64212                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                156362                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.dtb.walker           32                       # number of overall misses
 system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst             7770                       # number of overall misses
-system.l2c.overall_misses::cpu0.data            80277                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker           13                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             4624                       # number of overall misses
-system.l2c.overall_misses::cpu1.data            63664                       # number of overall misses
-system.l2c.overall_misses::total               156384                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.dtb.walker      2634500                       # number of ReadReq miss cycles
+system.l2c.overall_misses::cpu0.inst             7439                       # number of overall misses
+system.l2c.overall_misses::cpu0.data            79729                       # number of overall misses
+system.l2c.overall_misses::cpu1.dtb.walker           10                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst             4938                       # number of overall misses
+system.l2c.overall_misses::cpu1.data            64212                       # number of overall misses
+system.l2c.overall_misses::total               156362                       # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu0.dtb.walker      2459000                       # number of ReadReq miss cycles
 system.l2c.ReadReq_miss_latency::cpu0.itb.walker       158000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.inst    564954250                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data    469111750                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.dtb.walker      1020750                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst    346930750                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data    344094500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total     1728904500                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0.data       163993                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data       349985                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total       513978                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data   5540139123                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data   4380452342                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   9920591465                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker      2634500                       # number of demand (read+write) miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.inst    535184750                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.data    452595249                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.dtb.walker       747500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst    359066750                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data    362580750                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total     1712791999                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu0.data       209991                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data       255489                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total       465480                       # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data   5481304360                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data   4400908112                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   9882212472                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu0.dtb.walker      2459000                       # number of demand (read+write) miss cycles
 system.l2c.demand_miss_latency::cpu0.itb.walker       158000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst    564954250                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data   6009250873                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker      1020750                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst    346930750                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data   4724546842                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total     11649495965                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker      2634500                       # number of overall miss cycles
+system.l2c.demand_miss_latency::cpu0.inst    535184750                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data   5933899609                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.dtb.walker       747500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst    359066750                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data   4763488862                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total     11595004471                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.dtb.walker      2459000                       # number of overall miss cycles
 system.l2c.overall_miss_latency::cpu0.itb.walker       158000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst    564954250                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data   6009250873                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker      1020750                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst    346930750                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data   4724546842                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    11649495965                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.dtb.walker        33159                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker         6697                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst         515203                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data         195070                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker        31504                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker         7375                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst         468563                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data         202864                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            1460435                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       607832                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           607832                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data         1632                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data         1320                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            2952                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.overall_miss_latency::cpu0.inst    535184750                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data   5933899609                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.dtb.walker       747500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst    359066750                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data   4763488862                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total    11595004471                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.dtb.walker        32410                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker         6465                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.inst         516058                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data         193874                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker        31378                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker         7240                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst         467016                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data         204301                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            1458742                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       608227                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           608227                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data         1649                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data         1305                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            2954                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.SCUpgradeReq_accesses::cpu0.data            6                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data            4                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total            10                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       134734                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data       111374                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           246108                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker        33159                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker         6697                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst          515203                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data          329804                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker        31504                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker         7375                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          468563                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          314238                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             1706543                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker        33159                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker         6697                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         515203                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data         329804                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker        31504                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker         7375                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         468563                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         314238                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            1706543                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.001025                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000299                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.015081                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.032332                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000413                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.009868                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.021872                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.015877                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.987132                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.984848                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.986111                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.549008                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.531785                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.541214                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.001025                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.000299                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.015081                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.243408                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000413                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.009868                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.202598                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.091638                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.001025                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.000299                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.015081                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.243408                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000413                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.009868                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.202598                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.091638                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 77485.294118                       # average ReadReq miss latency
+system.l2c.SCUpgradeReq_accesses::cpu1.data            6                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total            12                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       133842                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data       112339                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           246181                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker        32410                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker         6465                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst          516058                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data          327716                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker        31378                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker         7240                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          467016                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data          316640                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             1704923                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker        32410                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker         6465                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         516058                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data         327716                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker        31378                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker         7240                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         467016                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data         316640                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            1704923                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000987                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000309                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.014415                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.031015                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000319                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst      0.010574                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data      0.023084                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.015870                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.987871                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.985441                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.986798                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.166667                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.083333                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.550769                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.529611                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.541114                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000987                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.000309                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.014415                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.243287                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000319                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.010574                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.202792                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.091712                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000987                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.000309                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.014415                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.243287                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000319                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.010574                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.202792                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.091712                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 76843.750000                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        79000                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 72709.684685                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 74379.538608                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 78519.230769                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75028.276384                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 77551.160694                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 74563.526976                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   101.795779                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   269.219231                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total   176.564067                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 74897.108598                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 73960.395462                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 74480.592393                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 77485.294118                       # average overall miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.inst 71943.103912                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.data 75269.457675                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        74750                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72715.016201                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 76883.110687                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 73986.695421                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   128.907919                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   198.669518                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total   159.684391                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 74357.050844                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 73969.814979                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 74184.101072                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 76843.750000                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu0.itb.walker        79000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 72709.684685                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 74856.445470                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 78519.230769                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 75028.276384                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 74210.650320                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 74492.889074                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 77485.294118                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 71943.103912                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 74425.862722                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        74750                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 72715.016201                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 74183.779698                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 74154.874400                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 76843.750000                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu0.itb.walker        79000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 72709.684685                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 74856.445470                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 78519.230769                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 75028.276384                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 74210.650320                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 74492.889074                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 71943.103912                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 74425.862722                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        74750                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 72715.016201                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 74183.779698                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 74154.874400                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -892,158 +632,166 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               59162                       # number of writebacks
-system.l2c.writebacks::total                    59162                       # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu0.inst             8                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu0.data            43                       # number of ReadReq MSHR hits
+system.l2c.writebacks::writebacks               59154                       # number of writebacks
+system.l2c.writebacks::total                    59154                       # number of writebacks
+system.l2c.ReadReq_mshr_hits::cpu0.inst             9                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu0.data            40                       # number of ReadReq MSHR hits
 system.l2c.ReadReq_mshr_hits::cpu1.inst             7                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.data            21                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total                79                       # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.inst              8                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.data             43                       # number of demand (read+write) MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu1.data            22                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::total                78                       # number of ReadReq MSHR hits
+system.l2c.demand_mshr_hits::cpu0.inst              9                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu0.data             40                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_hits::cpu1.inst              7                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.data             21                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                 79                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.inst             8                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu0.data            43                       # number of overall MSHR hits
+system.l2c.demand_mshr_hits::cpu1.data             22                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                 78                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu0.inst             9                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu0.data            40                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::cpu1.inst             7                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.data            21                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                79                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker           34                       # number of ReadReq MSHR misses
+system.l2c.overall_mshr_hits::cpu1.data            22                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total                78                       # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker           32                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            2                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.inst         7762                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.data         6264                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker           13                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst         4617                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data         4416                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total           23108                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data         1611                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data         1300                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total         2911                       # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data        73970                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data        59227                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        133197                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.dtb.walker           34                       # number of demand (read+write) MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.inst         7430                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.data         5973                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker           10                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.inst         4931                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.data         4694                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total           23072                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data         1629                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data         1286                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total         2915                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data            1                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total            1                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data        73716                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data        59496                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        133212                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.dtb.walker           32                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu0.itb.walker            2                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst         7762                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data        80234                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker           13                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst         4617                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data        63643                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           156305                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.dtb.walker           34                       # number of overall MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst         7430                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data        79689                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.dtb.walker           10                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst         4931                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data        64190                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           156284                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.dtb.walker           32                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu0.itb.walker            2                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst         7762                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data        80234                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.dtb.walker           13                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst         4617                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data        63643                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          156305                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker      2209500                       # number of ReadReq MSHR miss cycles
+system.l2c.overall_mshr_misses::cpu0.inst         7430                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data        79689                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.dtb.walker           10                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst         4931                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data        64190                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          156284                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker      2062500                       # number of ReadReq MSHR miss cycles
 system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker       133500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    466747500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.data    387626500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker       860750                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    288513000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data    287574500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total   1433665250                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     16111611                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     13003299                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total     29114910                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   4617307377                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   3642005658                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   8259313035                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      2209500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    441209000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.data    375003749                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker       625000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    296681500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data    302775000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total   1418490249                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     16291629                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     12864285                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total     29155914                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data        10001                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total        10001                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   4563686640                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   3660844388                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   8224531028                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      2062500                       # number of demand (read+write) MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       133500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst    466747500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data   5004933877                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       860750                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst    288513000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data   3929580158                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total   9692978285                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      2209500                       # number of overall MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst    441209000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data   4938690389                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       625000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst    296681500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data   3963619388                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   9643021277                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      2062500                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       133500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst    466747500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data   5004933877                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       860750                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst    288513000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data   3929580158                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total   9692978285                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst      6162749                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data  83808220000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  83134870250                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 166949252999                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   8942555713                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   8433790000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total  17376345713                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.LoadLockedReq_mshr_uncacheable_latency::cpu1.data       102500                       # number of LoadLockedReq MSHR uncacheable cycles
-system.l2c.LoadLockedReq_mshr_uncacheable_latency::total       102500                       # number of LoadLockedReq MSHR uncacheable cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst    441209000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data   4938690389                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       625000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst    296681500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data   3963619388                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   9643021277                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst      6566249                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data  83827031250                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  83117321750                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 166950919249                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   8951884751                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   8422103999                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total  17373988750                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.LoadLockedReq_mshr_uncacheable_latency::cpu1.data       116250                       # number of LoadLockedReq MSHR uncacheable cycles
+system.l2c.LoadLockedReq_mshr_uncacheable_latency::total       116250                       # number of LoadLockedReq MSHR uncacheable cycles
 system.l2c.StoreCondReq_mshr_uncacheable_latency::cpu1.data        60000                       # number of StoreCondReq MSHR uncacheable cycles
 system.l2c.StoreCondReq_mshr_uncacheable_latency::total        60000                       # number of StoreCondReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.inst      6162749                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data  92750775713                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data  91568660250                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 184325598712                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.001025                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000299                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.015066                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.032112                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000413                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.009854                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.021768                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.015823                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.987132                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.984848                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.986111                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.549008                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.531785                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.541214                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.001025                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000299                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.015066                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.243278                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000413                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.009854                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.202531                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.091592                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.001025                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000299                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.015066                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.243278                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000413                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.009854                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.202531                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.091592                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 64985.294118                       # average ReadReq mshr miss latency
+system.l2c.overall_mshr_uncacheable_latency::cpu0.inst      6566249                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data  92778916001                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data  91539425749                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 184324907999                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000987                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000309                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.014398                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.030809                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000319                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.010559                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.022976                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.015816                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.987871                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.985441                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.986798                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.166667                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.083333                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.550769                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.529611                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.541114                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000987                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000309                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.014398                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.243165                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000319                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.010559                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.202722                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.091666                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000987                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000309                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.014398                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.243165                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000319                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.010559                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.202722                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.091666                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 64453.125000                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        66750                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60132.375676                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61881.625160                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 66211.538462                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62489.278752                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65121.037138                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 62041.944348                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59382.099596                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 62783.149004                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        62500                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60166.599067                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64502.556455                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 61481.026742                       # average ReadReq mshr miss latency
 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data        10001                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10002.537692                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.686706                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 62421.351588                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61492.320361                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 62008.251199                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 64985.294118                       # average overall mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10003.332037                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10002.028816                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        10001                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        10001                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 61909.037929                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61530.932970                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 61740.166261                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 64453.125000                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        66750                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60132.375676                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 62379.214261                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 66211.538462                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62489.278752                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61744.106312                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 62013.232366                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 64985.294118                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59382.099596                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61974.555949                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        62500                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60166.599067                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61748.237856                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 61701.909837                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 64453.125000                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        66750                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60132.375676                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 62379.214261                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 66211.538462                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62489.278752                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61744.106312                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 62013.232366                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59382.099596                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61974.555949                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        62500                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60166.599067                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61748.237856                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 61701.909837                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
@@ -1066,49 +814,49 @@ system.cf0.dma_read_txs                             0                       # Nu
 system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
-system.toL2Bus.throughput                    58427801                       # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq            2677013                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2677015                       # Transaction distribution
+system.toL2Bus.throughput                    58424320                       # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq            2676714                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2676716                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteReq            763365                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteResp           763365                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           607832                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq            2952                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq            10                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp           2962                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           246108                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          246108                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           608227                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq            2954                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq            12                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp           2966                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           246181                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          246181                       # Transaction distribution
 system.toL2Bus.trans_dist::LoadLockedReq            3                       # Transaction distribution
 system.toL2Bus.trans_dist::StoreCondReq             3                       # Transaction distribution
 system.toL2Bus.trans_dist::StoreCondResp            3                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1968942                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      5796822                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        37990                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       150646                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               7954400                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     62968576                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     85534266                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        56288                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       258652                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size::total          148817782                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus             148817782                       # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus          199736                       # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy         4962135725                       # Layer occupancy (ticks)
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1967568                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      5797861                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        37552                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       149979                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               7952960                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     62924224                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     85579658                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        54820                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side       255152                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size::total          148813854                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus             148813854                       # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus          206020                       # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy         4963822946                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        4435783766                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        4432706696                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.2                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        4484209498                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        4484503287                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.2                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy          23967895                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy          23902881                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy          86426354                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy          86618127                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
-system.iobus.throughput                      48423111                       # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq             16322165                       # Transaction distribution
-system.iobus.trans_dist::ReadResp            16322165                       # Transaction distribution
+system.iobus.throughput                      48419467                       # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq             16322169                       # Transaction distribution
+system.iobus.trans_dist::ReadResp            16322169                       # Transaction distribution
 system.iobus.trans_dist::WriteReq                8177                       # Transaction distribution
 system.iobus.trans_dist::WriteResp               8177                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        30038                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         7932                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         7940                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio          522                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio         1030                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio           36                       # Packet count per connected master and slave (bytes)
@@ -1130,12 +878,12 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total      2383052                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total      2383060                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side     30277632                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.clcd.dma::total     30277632                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                32660684                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                32660692                       # Packet count per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio        39333                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio        15864                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio        15880                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio         1044                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio         2060                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio           72                       # Cumulative packet size per connected master and slave (bytes)
@@ -1157,14 +905,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total      2390470                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::total      2390486                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side    121110528                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.realview.clcd.dma::total    121110528                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total            123500998                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus               123500998                       # Total data (bytes)
+system.iobus.tot_pkt_size::total            123501014                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus               123501014                       # Total data (bytes)
 system.iobus.reqLayer0.occupancy             21111000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy              3971000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy              3975000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer2.occupancy               522000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
@@ -1210,19 +958,19 @@ system.iobus.reqLayer23.occupancy                8000                       # La
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer25.occupancy         15138816000                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.6                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy          2374875000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy          2374883000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.1                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy         41493951269                       # Layer occupancy (ticks)
-system.iobus.respLayer1.utilization               1.6                       # Layer utilization (%)
-system.cpu0.branchPred.lookups                7524637                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted          6008547                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect           377377                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups             4829480                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits                3929632                       # Number of BTB hits
+system.iobus.respLayer1.occupancy         37825687801                       # Layer occupancy (ticks)
+system.iobus.respLayer1.utilization               1.5                       # Layer utilization (%)
+system.cpu0.branchPred.lookups                7508483                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted          5992866                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect           375676                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups             4822577                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits                3918936                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            81.367601                       # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS                 723615                       # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect             39097                       # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct            81.262279                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS                 722501                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect             39246                       # Number of incorrect RAS predictions.
 system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1246,25 +994,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                    25732063                       # DTB read hits
-system.cpu0.dtb.read_misses                     40060                       # DTB read misses
-system.cpu0.dtb.write_hits                    6173955                       # DTB write hits
-system.cpu0.dtb.write_misses                    10391                       # DTB write misses
+system.cpu0.dtb.read_hits                    25709068                       # DTB read hits
+system.cpu0.dtb.read_misses                     39624                       # DTB read misses
+system.cpu0.dtb.write_hits                    6152335                       # DTB write hits
+system.cpu0.dtb.write_misses                    10221                       # DTB write misses
 system.cpu0.dtb.flush_tlb                         514                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid                769                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                     32                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    5654                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                     1384                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                   265                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_tlb_mva_asid                760                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid                     31                       # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries                    5608                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                     1406                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                   264                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      665                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                25772123                       # DTB read accesses
-system.cpu0.dtb.write_accesses                6184346                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      646                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                25748692                       # DTB read accesses
+system.cpu0.dtb.write_accesses                6162556                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         31906018                       # DTB hits
-system.cpu0.dtb.misses                          50451                       # DTB misses
-system.cpu0.dtb.accesses                     31956469                       # DTB accesses
+system.cpu0.dtb.hits                         31861403                       # DTB hits
+system.cpu0.dtb.misses                          49845                       # DTB misses
+system.cpu0.dtb.accesses                     31911248                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1286,664 +1034,664 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.inst_hits                     5897367                       # ITB inst hits
-system.cpu0.itb.inst_misses                      7084                       # ITB inst misses
+system.cpu0.itb.inst_hits                     5876098                       # ITB inst hits
+system.cpu0.itb.inst_misses                      7014                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
 system.cpu0.itb.flush_tlb                         514                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid                769                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                     32                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    2660                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid                760                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid                     31                       # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries                    2644                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                     1482                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                     1469                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                 5904451                       # ITB inst accesses
-system.cpu0.itb.hits                          5897367                       # DTB hits
-system.cpu0.itb.misses                           7084                       # DTB misses
-system.cpu0.itb.accesses                      5904451                       # DTB accesses
-system.cpu0.numCycles                       242280954                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                 5883112                       # ITB inst accesses
+system.cpu0.itb.hits                          5876098                       # DTB hits
+system.cpu0.itb.misses                           7014                       # DTB misses
+system.cpu0.itb.accesses                      5883112                       # DTB accesses
+system.cpu0.numCycles                       242192321                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles          15560897                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                      45618983                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                    7524637                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches           4653247                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                     10311307                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles                2438027                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles                     82681                       # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.BlockedCycles              50295736                       # Number of cycles fetch has spent blocked
-system.cpu0.fetch.MiscStallCycles                1713                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingDrainCycles             2004                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu0.fetch.PendingTrapStallCycles        47904                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles      1479659                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles          328                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                  5895435                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes               368728                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes                   2960                       # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples          79463748                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             0.723138                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            2.071375                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles          15567613                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                      45445847                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                    7508483                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches           4641437                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                     10272972                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles                2435180                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles                     81106                       # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.BlockedCycles              50250706                       # Number of cycles fetch has spent blocked
+system.cpu0.fetch.MiscStallCycles                1544                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingDrainCycles             1986                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu0.fetch.PendingTrapStallCycles        48114                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles      1489776                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles          378                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                  5874191                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes               367063                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes                   2900                       # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples          79394723                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             0.721041                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            2.068559                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0                69159455     87.03%     87.03% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                  678650      0.85%     87.89% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                  874708      1.10%     88.99% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                 1176149      1.48%     90.47% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4                 1117399      1.41%     91.87% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5                  558232      0.70%     92.58% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6                 1283192      1.61%     94.19% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7                  380865      0.48%     94.67% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8                 4235098      5.33%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0                69128739     87.07%     87.07% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                  676261      0.85%     87.92% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                  870795      1.10%     89.02% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                 1169302      1.47%     90.49% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4                 1115285      1.40%     91.90% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5                  553948      0.70%     92.59% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6                 1287197      1.62%     94.21% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7                  378519      0.48%     94.69% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8                 4214677      5.31%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total            79463748                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.031057                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.188290                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles                16659746                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles             51317609                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                  9233971                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles               657554                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles               1592691                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved             1005769                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred                91409                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts              54704033                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts               304298                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles               1592691                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles                17554490                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles               20340792                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles      27693159                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                  8932278                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles              3348216                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts              52126479                       # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents                  377                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents                497478                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LSQFullEvents              2175969                       # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.FullRegisterEvents             155                       # Number of times there has been no free registers
-system.cpu0.rename.RenamedOperands           53794326                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups            241736924                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups       220533984                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups             5031                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps             39400219                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                14394106                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts            593139                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts        541531                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                  6973197                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads            10037020                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores            7000202                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads          1050357                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores         1288163                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                  48430994                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded            1028168                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                 62176930                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued            89712                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined        9957065                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined     24599714                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved        276838                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples     79463748                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.782457                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.501316                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total            79394723                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.031002                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.187644                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles                16658432                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles             51288095                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                  9197431                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles               656874                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles               1591763                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved             1006093                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred                91406                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts              54494283                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts               303520                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles               1591763                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles                17551658                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles               20345183                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles      27653568                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                  8896202                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles              3354292                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts              51932303                       # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents                  196                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents                500448                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LSQFullEvents              2179621                       # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.FullRegisterEvents             261                       # Number of times there has been no free registers
+system.cpu0.rename.RenamedOperands           53595851                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups            240832893                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups       219678051                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups             5082                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps             39195467                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                14400384                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts            591696                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts        540219                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                  6961736                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads            10014185                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores            6974197                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads          1050889                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores         1353332                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                  48232956                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded            1025841                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                 61971057                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued            88766                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined        9957722                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined     24611703                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved        275811                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples     79394723                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.780544                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.499047                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0           56925517     71.64%     71.64% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1            7350450      9.25%     80.89% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2            3522799      4.43%     85.32% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3            2913274      3.67%     88.99% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4            6168473      7.76%     96.75% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5            1495817      1.88%     98.63% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6             789992      0.99%     99.63% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7             231277      0.29%     99.92% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8              66149      0.08%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0           56910995     71.68%     71.68% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1            7345017      9.25%     80.93% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2            3503110      4.41%     85.34% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3            2918035      3.68%     89.02% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4            6157997      7.76%     96.78% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5            1482939      1.87%     98.64% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6             783446      0.99%     99.63% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7             227116      0.29%     99.92% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8              66068      0.08%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total       79463748                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total       79394723                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu                  30568      0.69%      0.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                     2      0.00%      0.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                      0      0.00%      0.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%      0.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%      0.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%      0.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%      0.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%      0.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%      0.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%      0.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%      0.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%      0.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%      0.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%      0.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%      0.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%      0.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%      0.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%      0.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%      0.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%      0.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%      0.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%      0.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%      0.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%      0.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%      0.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%      0.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%      0.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%      0.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%      0.69% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead               4194749     94.30%     94.98% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite               223174      5.02%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu                  29670      0.67%      0.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                     1      0.00%      0.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                      0      0.00%      0.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%      0.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%      0.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%      0.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%      0.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%      0.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%      0.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%      0.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%      0.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%      0.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%      0.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%      0.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%      0.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%      0.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%      0.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%      0.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%      0.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%      0.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%      0.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%      0.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%      0.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%      0.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%      0.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%      0.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%      0.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%      0.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%      0.67% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead               4193006     94.32%     94.99% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite               222912      5.01%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass            15922      0.03%      0.03% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu             29222200     47.00%     47.02% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult               47810      0.08%     47.10% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     47.10% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     47.10% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     47.10% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     47.10% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     47.10% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     47.10% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     47.10% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     47.10% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     47.10% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     47.10% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     47.10% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     47.10% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                  7      0.00%     47.10% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     47.10% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     47.10% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     47.10% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              5      0.00%     47.10% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     47.10% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     47.10% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     47.10% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     47.10% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     47.10% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     47.10% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc          1242      0.00%     47.10% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     47.10% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc            6      0.00%     47.10% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     47.10% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead            26409099     42.47%     89.58% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite            6480639     10.42%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass            15869      0.03%      0.03% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu             29065604     46.90%     46.93% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult               46869      0.08%     47.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     47.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     47.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     47.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     47.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     47.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     47.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     47.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     47.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     47.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     47.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     47.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     47.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                 10      0.00%     47.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     47.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     47.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     47.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              7      0.00%     47.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     47.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     47.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     47.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     47.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     47.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     47.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc          1239      0.00%     47.01% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     47.01% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc           10      0.00%     47.01% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     47.01% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead            26385475     42.58%     89.58% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite            6455974     10.42%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total              62176930                       # Type of FU issued
-system.cpu0.iq.rate                          0.256632                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                    4448493                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.071546                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads         208394864                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes         59425365                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses     43388237                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads              11204                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes              6101                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses         5139                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses              66603600                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                   5901                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads          313863                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total              61971057                       # Type of FU issued
+system.cpu0.iq.rate                          0.255875                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                    4445589                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.071737                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads         207909567                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes         59225484                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses     43186225                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads              11292                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes              6130                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses         5133                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses              66394829                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                   5948                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads          311727                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads      2132926                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses         3897                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation        15826                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores       851086                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads      2130667                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses         3740                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation        15655                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores       850179                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads     17067174                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked       347980                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads     17067257                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked       348827                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles               1592691                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles               15703960                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles               239689                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts           49567887                       # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts           107700                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts             10037020                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts             7000202                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts            730031                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                 54998                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents                 4795                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents         15826                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect        184371                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect       145167                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts              329538                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts             61108768                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts             26079506                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts          1068162                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles               1591763                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles               15715155                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles               239745                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts           49373573                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts           105603                       # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts             10014185                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts             6974197                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts            727713                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                 55741                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents                 4727                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents         15655                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect        183161                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect       144870                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts              328031                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts             60906320                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts             26058550                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts          1064737                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                       108725                       # number of nop insts executed
-system.cpu0.iew.exec_refs                    32501673                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches                 5985971                       # Number of branches executed
-system.cpu0.iew.exec_stores                   6422167                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.252223                       # Inst execution rate
-system.cpu0.iew.wb_sent                      60615706                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                     43393376                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                 23422073                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                 43067972                       # num instructions consuming a value
+system.cpu0.iew.exec_nop                       114776                       # number of nop insts executed
+system.cpu0.iew.exec_refs                    32455686                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches                 5967734                       # Number of branches executed
+system.cpu0.iew.exec_stores                   6397136                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.251479                       # Inst execution rate
+system.cpu0.iew.wb_sent                      60414213                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                     43191358                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                 23287316                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                 42834885                       # num instructions consuming a value
 system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate                      0.179104                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.543840                       # average fanout of values written-back
+system.cpu0.iew.wb_rate                      0.178335                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.543653                       # average fanout of values written-back
 system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts        9785974                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls         751330                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts           287324                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples     77871057                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.504327                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.472133                       # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts        9785836                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls         750030                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts           285660                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples     77802960                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.502286                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.465598                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0     63445664     81.48%     81.48% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1      7408180      9.51%     90.99% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2      1965702      2.52%     93.51% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3      1101219      1.41%     94.93% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4       850042      1.09%     96.02% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5       579839      0.74%     96.76% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6       741280      0.95%     97.72% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7       350840      0.45%     98.17% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8      1428291      1.83%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0     63388396     81.47%     81.47% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1      7400911      9.51%     90.99% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2      1988257      2.56%     93.54% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3      1098992      1.41%     94.95% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4       865715      1.11%     96.07% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5       575312      0.74%     96.81% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6       733525      0.94%     97.75% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7       350428      0.45%     98.20% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8      1401424      1.80%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total     77871057                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts            30068673                       # Number of instructions committed
-system.cpu0.commit.committedOps              39272492                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total     77802960                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts            29900744                       # Number of instructions committed
+system.cpu0.commit.committedOps              39079359                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                      14053210                       # Number of memory references committed
-system.cpu0.commit.loads                      7904094                       # Number of loads committed
-system.cpu0.commit.membars                     209520                       # Number of memory barriers committed
-system.cpu0.commit.branches                   5180571                       # Number of branches committed
-system.cpu0.commit.fp_insts                      5103                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                 34976585                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls              508087                       # Number of function calls committed.
-system.cpu0.commit.bw_lim_events              1428291                       # number cycles where commit BW limit reached
+system.cpu0.commit.refs                      14007536                       # Number of memory references committed
+system.cpu0.commit.loads                      7883518                       # Number of loads committed
+system.cpu0.commit.membars                     209346                       # Number of memory barriers committed
+system.cpu0.commit.branches                   5162239                       # Number of branches committed
+system.cpu0.commit.fp_insts                      5086                       # Number of committed floating point instructions.
+system.cpu0.commit.int_insts                 34792812                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls              507721                       # Number of function calls committed.
+system.cpu0.commit.bw_lim_events              1401424                       # number cycles where commit BW limit reached
 system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads                   124525442                       # The number of ROB reads
-system.cpu0.rob.rob_writes                   99752707                       # The number of ROB writes
-system.cpu0.timesIdled                         907289                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                      162817206                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                  2250738250                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                   29995072                       # Number of Instructions Simulated
-system.cpu0.committedOps                     39198891                       # Number of Ops (including micro ops) Simulated
-system.cpu0.committedInsts_total             29995072                       # Number of Instructions Simulated
-system.cpu0.cpi                              8.077359                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        8.077359                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.123803                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.123803                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads               277602258                       # number of integer regfile reads
-system.cpu0.int_regfile_writes               44085175                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                    44877                       # number of floating regfile reads
-system.cpu0.fp_regfile_writes                   42488                       # number of floating regfile writes
-system.cpu0.misc_regfile_reads              138395505                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes                582325                       # number of misc regfile writes
-system.cpu0.icache.tags.replacements           984398                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          511.534546                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           10515921                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           984910                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            10.677037                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle       7008829000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   316.868268                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst   194.666278                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.618883                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.380208                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.999091                       # Average percentage of cache occupancy
+system.cpu0.rob.rob_reads                   124291086                       # The number of ROB reads
+system.cpu0.rob.rob_writes                   99365166                       # The number of ROB writes
+system.cpu0.timesIdled                         908697                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                      162797598                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                  2248209209                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                   29823122                       # Number of Instructions Simulated
+system.cpu0.committedOps                     39001737                       # Number of Ops (including micro ops) Simulated
+system.cpu0.committedInsts_total             29823122                       # Number of Instructions Simulated
+system.cpu0.cpi                              8.120958                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        8.120958                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.123138                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.123138                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads               276680521                       # number of integer regfile reads
+system.cpu0.int_regfile_writes               43875243                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                    44965                       # number of floating regfile reads
+system.cpu0.fp_regfile_writes                   42348                       # number of floating regfile writes
+system.cpu0.misc_regfile_reads              137565982                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes                581037                       # number of misc regfile writes
+system.cpu0.icache.tags.replacements           983714                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.569506                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           10510100                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           984226                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            10.678543                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle       7060452000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   317.023627                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst   194.545879                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.619187                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.379972                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.999159                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0          133                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          218                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          161                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0          143                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          206                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          163                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         12566693                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        12566693                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst      5337223                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst      5178698                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       10515921                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst      5337223                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst      5178698                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        10515921                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst      5337223                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst      5178698                       # number of overall hits
-system.cpu0.icache.overall_hits::total       10515921                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       558087                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst       507747                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total      1065834                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       558087                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst       507747                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total       1065834                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       558087                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst       507747                       # number of overall misses
-system.cpu0.icache.overall_misses::total      1065834                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   7713442509                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   6842687514                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  14556130023                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst   7713442509                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst   6842687514                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  14556130023                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst   7713442509                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst   6842687514                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  14556130023                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst      5895310                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst      5686445                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     11581755                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst      5895310                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst      5686445                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     11581755                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst      5895310                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst      5686445                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     11581755                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.094666                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.089291                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.092027                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.094666                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.089291                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.092027                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.094666                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.089291                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.092027                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13821.218751                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13476.569067                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 13657.032918                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13821.218751                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13476.569067                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 13657.032918                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13821.218751                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13476.569067                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 13657.032918                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs         7516                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses         12559701                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        12559701                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst      5314791                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst      5195309                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       10510100                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst      5314791                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst      5195309                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        10510100                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst      5314791                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst      5195309                       # number of overall hits
+system.cpu0.icache.overall_hits::total       10510100                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       559278                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst       506065                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      1065343                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       559278                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst       506065                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       1065343                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       559278                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst       506065                       # number of overall misses
+system.cpu0.icache.overall_misses::total      1065343                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   7693667190                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   6830219775                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  14523886965                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst   7693667190                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst   6830219775                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  14523886965                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst   7693667190                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst   6830219775                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  14523886965                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst      5874069                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst      5701374                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     11575443                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst      5874069                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst      5701374                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     11575443                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst      5874069                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst      5701374                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     11575443                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.095211                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.088762                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.092035                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.095211                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.088762                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.092035                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.095211                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.088762                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.092035                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13756.427376                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13496.724284                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 13633.061807                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13756.427376                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13496.724284                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 13633.061807                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13756.427376                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13496.724284                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 13633.061807                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs         6850                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              400                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              406                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    18.790000                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    16.871921                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        42303                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst        38592                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        80895                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst        42303                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu1.inst        38592                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        80895                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst        42303                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu1.inst        38592                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        80895                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       515784                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       469155                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       984939                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       515784                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst       469155                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       984939                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       515784                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst       469155                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       984939                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   6271733613                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   5566076348                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  11837809961                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   6271733613                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   5566076348                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  11837809961                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   6271733613                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   5566076348                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  11837809961                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst      8638250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total      8638250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst      8638250                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total      8638250                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.087491                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.082504                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.085042                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.087491                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.082504                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.085042                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.087491                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.082504                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.085042                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12159.612576                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11864.045674                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12018.825492                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12159.612576                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11864.045674                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12018.825492                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12159.612576                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11864.045674                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12018.825492                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        42606                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst        38478                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        81084                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst        42606                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu1.inst        38478                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        81084                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst        42606                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu1.inst        38478                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        81084                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       516672                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       467587                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       984259                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       516672                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst       467587                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       984259                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       516672                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst       467587                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       984259                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   6254333936                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   5558733090                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  11813067026                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   6254333936                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   5558733090                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  11813067026                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   6254333936                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   5558733090                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  11813067026                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst      9017250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total      9017250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst      9017250                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total      9017250                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.087958                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.082013                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.085030                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.087958                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.082013                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.085030                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.087958                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.082013                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.085030                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12105.037502                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11888.125825                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12001.990356                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12105.037502                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11888.125825                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12001.990356                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12105.037502                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11888.125825                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12001.990356                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements           643530                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.993287                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           21531295                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           644042                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            33.431508                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle         43200250                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   257.568714                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data   254.424573                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.503064                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.496923                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.replacements           643844                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.993221                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           21529454                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           644356                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            33.412359                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle         43687250                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   256.274589                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data   255.718633                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.500536                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.499450                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999987                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::0          190                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          303                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           19                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          304                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           18                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses        101651746                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses       101651746                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data      7028815                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data      6747590                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       13776405                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      3755876                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data      3505333                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       7261209                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       116971                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       125973                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       242944                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       119744                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data       127881                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       247625                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     10784691                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data     10252923                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        21037614                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     10784691                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data     10252923                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       21037614                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       339393                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data       409028                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       748421                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1648570                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data      1313214                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      2961784                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         7529                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         5999                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        13528                       # number of LoadLockedReq misses
+system.cpu0.dcache.tags.tag_accesses        101648096                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses       101648096                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data      7014056                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data      6760706                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       13774762                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      3747600                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data      3513292                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       7260892                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       116614                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       126440                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       243054                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       119391                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data       128245                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       247636                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     10761656                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data     10273998                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        21035654                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     10761656                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data     10273998                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       21035654                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       333491                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data       414863                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       748354                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      1635288                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data      1327358                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      2962646                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         7514                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         6065                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        13579                       # number of LoadLockedReq misses
 system.cpu0.dcache.StoreCondReq_misses::cpu0.data            6                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu1.data            4                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total           10                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      1987963                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data      1722242                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       3710205                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      1987963                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data      1722242                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      3710205                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   5452544877                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   5973510192                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  11426055069                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  85021863209                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data  64469772613                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 149491635822                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    108104498                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     79946495                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    188050993                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data        78000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data        52000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total       130000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  90474408086                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data  70443282805                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 160917690891                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  90474408086                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data  70443282805                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 160917690891                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      7368208                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data      7156618                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     14524826                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      5404446                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data      4818547                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     10222993                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       124500                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       131972                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       256472                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       119750                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       127885                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       247635                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     12772654                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data     11975165                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     24747819                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     12772654                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data     11975165                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     24747819                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.046062                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.057154                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.051527                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.305040                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.272533                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.289718                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.060474                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.045457                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.052746                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_misses::cpu1.data            6                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total           12                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      1968779                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data      1742221                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       3711000                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      1968779                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data      1742221                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      3711000                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   5348440293                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   6102853229                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  11451293522                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  83999211786                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data  64837852526                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 148837064312                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    107360498                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     81153996                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    188514494                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data        90501                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data        78000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total       168501                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  89347652079                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data  70940705755                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 160288357834                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  89347652079                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data  70940705755                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 160288357834                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      7347547                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data      7175569                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     14523116                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      5382888                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data      4840650                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     10223538                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       124128                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       132505                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       256633                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       119397                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       128251                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       247648                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     12730435                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data     12016219                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     24746654                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     12730435                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data     12016219                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     24746654                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.045388                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.057816                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.051528                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.303794                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.274211                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.289787                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.060534                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.045772                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.052912                       # miss rate for LoadLockedReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.000050                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000031                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000040                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.155642                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.143818                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.149920                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.155642                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.143818                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.149920                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16065.578480                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14604.159598                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 15266.881968                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 51573.098630                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 49093.120095                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 50473.510500                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14358.413866                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13326.636939                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13900.871747                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data        13000                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data     0.000047                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.000048                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.154651                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.144989                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.149960                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.154651                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.144989                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.149960                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16037.735030                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14710.526677                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 15301.974095                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 51366.616636                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 48847.298563                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 50237.883403                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14288.062018                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13380.708326                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13882.796524                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 15083.500000                       # average StoreCondReq miss latency
 system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data        13000                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total        13000                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 45511.112675                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 40902.081592                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 43371.644125                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 45511.112675                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 40902.081592                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 43371.644125                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs        36158                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets        27990                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs             3441                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets            289                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    10.507992                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets    96.851211                       # average number of cycles each access was blocked
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14041.750000                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 45382.265901                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 40718.545899                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 43192.766864                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 45382.265901                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 40718.545899                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 43192.766864                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs        37128                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets        22269                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs             3473                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets            273                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    10.690469                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets    81.571429                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       607832                       # number of writebacks
-system.cpu0.dcache.writebacks::total           607832                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       151038                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data       211492                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       362530                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1512262                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      1200569                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      2712831                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data          756                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data          622                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total         1378                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      1663300                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data      1412061                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      3075361                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      1663300                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data      1412061                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      3075361                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       188355                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       197536                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       385891                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       136308                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       112645                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       248953                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6773                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         5377                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total        12150                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.writebacks::writebacks       608227                       # number of writebacks
+system.cpu0.dcache.writebacks::total           608227                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       146313                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data       215949                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       362262                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1499850                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data      1213774                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      2713624                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data          765                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data          618                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total         1383                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      1646163                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data      1429723                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      3075886                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      1646163                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data      1429723                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      3075886                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       187178                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       198914                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       386092                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       135438                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       113584                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       249022                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6749                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         5447                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total        12196                       # number of LoadLockedReq MSHR misses
 system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data            6                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data            4                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total           10                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       324663                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data       310181                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       634844                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       324663                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data       310181                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       634844                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2624519460                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2624606109                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   5249125569                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   6430877605                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   5124459707                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  11555337312                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     85490752                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     61868005                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    147358757                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data        66000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data        44000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       110000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   9055397065                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   7749065816                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  16804462881                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   9055397065                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   7749065816                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  16804462881                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  91527132501                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  90809770250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182336902751                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data  13691854278                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  13083150967                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total  26775005245                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data       141500                       # number of LoadLockedReq MSHR uncacheable cycles
-system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total       141500                       # number of LoadLockedReq MSHR uncacheable cycles
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data            6                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total           12                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       322616                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data       312498                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       635114                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       322616                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data       312498                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       635114                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2596085748                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2657791594                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   5253877342                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   6365986816                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   5155346718                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  11521333534                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     84972752                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     62985504                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    147958256                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data        78499                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data        66000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total       144499                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   8962072564                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   7813138312                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  16775210876                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   8962072564                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   7813138312                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  16775210876                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  91546998750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  90791256750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182338255500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data  13710487847                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  13068639684                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total  26779127531                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data       155750                       # number of LoadLockedReq MSHR uncacheable cycles
+system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total       155750                       # number of LoadLockedReq MSHR uncacheable cycles
 system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data        96000                       # number of StoreCondReq MSHR uncacheable cycles
 system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total        96000                       # number of StoreCondReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 105218986779                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103892921217                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209111907996                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.025563                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.027602                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.026568                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.025221                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.023377                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.024352                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.054402                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.040743                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.047374                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 105257486597                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103859896434                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209117383031                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.025475                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.027721                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.026585                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.025161                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.023465                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.024358                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.054371                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.041108                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.047523                       # mshr miss rate for LoadLockedReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.000050                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000031                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000040                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.025419                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.025902                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.025653                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.025419                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.025902                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.025653                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13933.898543                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13286.722972                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13602.612056                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47179.018143                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 45492.118665                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46415.738360                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12622.287317                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11506.045192                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12128.292757                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data        11000                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.000047                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.000048                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.025342                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.026006                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.025665                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.025342                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.026006                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.025665                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13869.609399                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13361.510975                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13607.837878                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47002.959406                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 45387.965893                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46266.328011                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12590.421099                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11563.338351                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12131.703509                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 13083.166667                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data        11000                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total        11000                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27891.681728                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24982.400005                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26470.223994                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 27891.681728                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24982.400005                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26470.223994                       # average overall mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 12041.583333                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27779.380328                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25002.202612                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26412.913077                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 27779.380328                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25002.202612                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26412.913077                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -1958,15 +1706,15 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups                7303181                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted          5881126                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect           346154                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups             4653929                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits                3750959                       # Number of BTB hits
+system.cpu1.branchPred.lookups                7323132                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted          5902490                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect           346200                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups             4511574                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits                3765481                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            80.597684                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS                 679679                       # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect             34597                       # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct            83.462690                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS                 676459                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect             34463                       # Number of incorrect RAS predictions.
 system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1990,25 +1738,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    25488049                       # DTB read hits
-system.cpu1.dtb.read_misses                     36227                       # DTB read misses
-system.cpu1.dtb.write_hits                    5538132                       # DTB write hits
-system.cpu1.dtb.write_misses                     8320                       # DTB write misses
-system.cpu1.dtb.flush_tlb                         512                       # Number of times complete TLB was flushed
+system.cpu1.dtb.read_hits                    25506602                       # DTB read hits
+system.cpu1.dtb.read_misses                     36488                       # DTB read misses
+system.cpu1.dtb.write_hits                    5558527                       # DTB write hits
+system.cpu1.dtb.write_misses                     8439                       # DTB write misses
+system.cpu1.dtb.flush_tlb                         510                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid                670                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                     31                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    5495                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                     1338                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   228                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_tlb_mva_asid                679                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid                     32                       # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries                    5463                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                     2276                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults                   232                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                      677                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                25524276                       # DTB read accesses
-system.cpu1.dtb.write_accesses                5546452                       # DTB write accesses
+system.cpu1.dtb.perms_faults                      679                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                25543090                       # DTB read accesses
+system.cpu1.dtb.write_accesses                5566966                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         31026181                       # DTB hits
-system.cpu1.dtb.misses                          44547                       # DTB misses
-system.cpu1.dtb.accesses                     31070728                       # DTB accesses
+system.cpu1.dtb.hits                         31065129                       # DTB hits
+system.cpu1.dtb.misses                          44927                       # DTB misses
+system.cpu1.dtb.accesses                     31110056                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -2030,294 +1778,294 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.inst_hits                     5688452                       # ITB inst hits
-system.cpu1.itb.inst_misses                      7006                       # ITB inst misses
+system.cpu1.itb.inst_hits                     5703436                       # ITB inst hits
+system.cpu1.itb.inst_misses                      7020                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.flush_tlb                         512                       # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb                         510                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid                670                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                     31                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                    2704                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid                679                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid                     32                       # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries                    2688                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                     1448                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                     1487                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                 5695458                       # ITB inst accesses
-system.cpu1.itb.hits                          5688452                       # DTB hits
-system.cpu1.itb.misses                           7006                       # DTB misses
-system.cpu1.itb.accesses                      5695458                       # DTB accesses
-system.cpu1.numCycles                       236990378                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                 5710456                       # ITB inst accesses
+system.cpu1.itb.hits                          5703436                       # DTB hits
+system.cpu1.itb.misses                           7020                       # DTB misses
+system.cpu1.itb.accesses                      5710456                       # DTB accesses
+system.cpu1.numCycles                       237056909                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles          14445279                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                      45031495                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                    7303181                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches           4430638                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                      9912685                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles                2288075                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles                     85272                       # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.BlockedCycles              49385810                       # Number of cycles fetch has spent blocked
-system.cpu1.fetch.MiscStallCycles                1038                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingDrainCycles             1883                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu1.fetch.PendingTrapStallCycles        43903                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles      1235955                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles          192                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                  5686448                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes               352687                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes                   3068                       # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples          76688585                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             0.724367                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            2.076407                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles          14419718                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                      45234990                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                    7323132                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches           4441940                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                      9947853                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles                2287798                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles                     84999                       # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.BlockedCycles              49482147                       # Number of cycles fetch has spent blocked
+system.cpu1.fetch.MiscStallCycles                1272                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingDrainCycles             1896                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu1.fetch.PendingTrapStallCycles        44871                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles      1235484                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles          189                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                  5701379                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes               352457                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes                   3064                       # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples          76794959                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             0.726229                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            2.078871                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0                66784675     87.09%     87.09% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                  633491      0.83%     87.91% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                  843387      1.10%     89.01% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                 1127901      1.47%     90.48% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4                  993338      1.30%     91.78% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5                  549443      0.72%     92.49% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6                 1277588      1.67%     94.16% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7                  369483      0.48%     94.64% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8                 4109279      5.36%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0                66855647     87.06%     87.06% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                  632615      0.82%     87.88% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                  843009      1.10%     88.98% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                 1133482      1.48%     90.45% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4                 1002056      1.30%     91.76% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5                  554704      0.72%     92.48% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6                 1272745      1.66%     94.14% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7                  372184      0.48%     94.62% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8                 4128517      5.38%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total            76688585                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.030816                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       0.190014                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                15549027                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles             50133952                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                  8864377                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles               645129                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles               1493916                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved              964413                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred                85194                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts              52934695                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts               283965                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles               1493916                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles                16391230                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles               19303163                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles      27652687                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                  8622958                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles              3222506                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts              50466149                       # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents                  174                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents                593171                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LSQFullEvents              1994496                       # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.FullRegisterEvents             690                       # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands           52886950                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups            233487672                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups       213429055                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups             5328                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps             39332432                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                13554518                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts            579559                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts        536966                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                  6477487                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads             9753455                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores            6333018                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads           895982                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores         1122035                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                  46958561                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded             957421                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                 60864798                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued            86364                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined        9232524                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined     23424717                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved        226140                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples     76688585                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.793662                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.504660                       # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total            76794959                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.030892                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       0.190819                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles                15530724                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles             50222847                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                  8895356                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles               650267                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles               1493551                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved              963840                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred                85500                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts              53154493                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts               286161                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles               1493551                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles                16374919                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles               19306160                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles      27715779                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                  8656578                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles              3245827                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts              50687701                       # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents                  339                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents                605911                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LSQFullEvents              2002092                       # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.FullRegisterEvents             648                       # Number of times there has been no free registers
+system.cpu1.rename.RenamedOperands           53113804                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups            234485879                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups       214384735                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups             5365                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps             39540919                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                13572884                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts            579809                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts        536931                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                  6499660                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads             9772559                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores            6360216                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads           888468                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores         1099515                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                  47171321                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded             962588                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                 61070577                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued            91971                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined        9248404                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined     23463374                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved        229936                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples     76794959                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.795242                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.505673                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0           54509370     71.08%     71.08% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1            7300848      9.52%     80.60% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2            3460717      4.51%     85.11% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3            2863086      3.73%     88.85% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4            6124123      7.99%     96.83% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5            1373475      1.79%     98.62% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6             772006      1.01%     99.63% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7             222325      0.29%     99.92% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8              62635      0.08%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0           54534134     71.01%     71.01% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1            7328500      9.54%     80.56% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2            3483988      4.54%     85.09% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3            2874889      3.74%     88.84% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4            6131286      7.98%     96.82% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5            1377966      1.79%     98.61% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6             776904      1.01%     99.63% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7             225300      0.29%     99.92% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8              61992      0.08%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total       76688585                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total       76794959                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                  28981      0.66%      0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                     4      0.00%      0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                      0      0.00%      0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%      0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%      0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%      0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      0.66% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead               4176523     94.96%     95.62% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite               192832      4.38%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                  29712      0.67%      0.67% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                     3      0.00%      0.67% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                      0      0.00%      0.67% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      0.67% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      0.67% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      0.67% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%      0.67% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      0.67% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      0.67% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      0.67% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      0.67% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      0.67% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      0.67% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      0.67% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      0.67% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%      0.67% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      0.67% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%      0.67% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      0.67% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      0.67% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      0.67% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      0.67% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      0.67% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      0.67% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      0.67% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      0.67% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      0.67% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      0.67% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      0.67% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead               4180230     94.88%     95.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite               195658      4.44%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass            12596      0.02%      0.02% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu             28808168     47.33%     47.35% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult               45770      0.08%     47.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     47.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     47.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     47.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     47.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     47.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     47.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     47.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     47.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     47.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     47.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     47.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     47.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                 12      0.00%     47.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     47.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     47.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     47.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              9      0.00%     47.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     47.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     47.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     47.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     47.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     47.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     47.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc           867      0.00%     47.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     47.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            9      0.00%     47.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     47.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead            26145062     42.96%     90.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite            5852305      9.62%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass            12649      0.02%      0.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu             28971083     47.44%     47.46% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult               46630      0.08%     47.54% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     47.54% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     47.54% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     47.54% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     47.54% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     47.54% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     47.54% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     47.54% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     47.54% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     47.54% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     47.54% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     47.54% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     47.54% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                 12      0.00%     47.54% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     47.54% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     47.54% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     47.54% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              7      0.00%     47.54% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     47.54% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     47.54% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     47.54% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     47.54% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     47.54% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     47.54% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc           875      0.00%     47.54% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     47.54% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            7      0.00%     47.54% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     47.54% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead            26162080     42.84%     90.38% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite            5877234      9.62%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total              60864798                       # Type of FU issued
-system.cpu1.iq.rate                          0.256824                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                    4398340                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.072264                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads         202935847                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes         57156855                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses     42177968                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads              11410                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes              6319                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses         5146                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses              65244557                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                   5985                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads          312441                       # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total              61070577                       # Type of FU issued
+system.cpu1.iq.rate                          0.257620                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                    4405603                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.072140                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads         203466895                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes         57390461                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses     42382296                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads              11528                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes              6422                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses         5160                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses              65457468                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                   6063                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads          311906                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads      2001655                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses         2943                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation        15220                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores       749307                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads      1999074                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses         3048                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation        15122                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores       750838                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads     17042804                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked       332523                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads     17042744                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked       332080                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles               1493916                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles               14868856                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles               223350                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts           48029034                       # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts            96518                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts              9753455                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts             6333018                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts            681732                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                 49156                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents                 5134                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents         15220                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect        168778                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect       134493                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts              303271                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts             59837987                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts             25827716                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts          1026811                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles               1493551                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles               14864582                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles               222698                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts           48241525                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts            96453                       # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts              9772559                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts             6360216                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts            687199                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                 48610                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents                 4313                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents         15122                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect        168053                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect       134565                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts              302618                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts             60042253                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts             25845364                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts          1028324                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                       113052                       # number of nop insts executed
-system.cpu1.iew.exec_refs                    31629861                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches                 5852394                       # Number of branches executed
-system.cpu1.iew.exec_stores                   5802145                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.252491                       # Inst execution rate
-system.cpu1.iew.wb_sent                      59370669                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                     42183114                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                 23501476                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                 42733790                       # num instructions consuming a value
+system.cpu1.iew.exec_nop                       107616                       # number of nop insts executed
+system.cpu1.iew.exec_refs                    31671376                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches                 5872062                       # Number of branches executed
+system.cpu1.iew.exec_stores                   5826012                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.253282                       # Inst execution rate
+system.cpu1.iew.wb_sent                      59578158                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                     42387456                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                 23643387                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                 43005248                       # num instructions consuming a value
 system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate                      0.177995                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.549951                       # average fanout of values written-back
+system.cpu1.iew.wb_rate                      0.178807                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.549779                       # average fanout of values written-back
 system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts        9169088                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls         731281                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts           262316                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples     75194669                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.511793                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.483255                       # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts        9166908                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls         732652                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts           262014                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples     75301408                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.513681                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.486972                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0     60941986     81.05%     81.05% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1      7448338      9.91%     90.95% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2      1921902      2.56%     93.51% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3      1064941      1.42%     94.92% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4       820613      1.09%     96.01% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5       497482      0.66%     96.68% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6       699016      0.93%     97.61% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7       369953      0.49%     98.10% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8      1430438      1.90%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0     60995111     81.00%     81.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1      7470337      9.92%     90.92% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2      1928698      2.56%     93.48% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3      1074141      1.43%     94.91% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4       820415      1.09%     96.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5       494186      0.66%     96.66% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6       699344      0.93%     97.58% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7       371316      0.49%     98.08% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8      1447860      1.92%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total     75194669                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts            30395180                       # Number of instructions committed
-system.cpu1.commit.committedOps              38484098                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total     75301408                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts            30565527                       # Number of instructions committed
+system.cpu1.commit.committedOps              38680902                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                      13335511                       # Number of memory references committed
-system.cpu1.commit.loads                      7751800                       # Number of loads committed
-system.cpu1.commit.membars                     194141                       # Number of memory barriers committed
-system.cpu1.commit.branches                   5126394                       # Number of branches committed
-system.cpu1.commit.fp_insts                      5109                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                 34219487                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls              483277                       # Number of function calls committed.
-system.cpu1.commit.bw_lim_events              1430438                       # number cycles where commit BW limit reached
+system.cpu1.commit.refs                      13382863                       # Number of memory references committed
+system.cpu1.commit.loads                      7773485                       # Number of loads committed
+system.cpu1.commit.membars                     194338                       # Number of memory barriers committed
+system.cpu1.commit.branches                   5145142                       # Number of branches committed
+system.cpu1.commit.fp_insts                      5126                       # Number of committed floating point instructions.
+system.cpu1.commit.int_insts                 34406663                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls              483721                       # Number of function calls committed.
+system.cpu1.commit.bw_lim_events              1447860                       # number cycles where commit BW limit reached
 system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads                   120543738                       # The number of ROB reads
-system.cpu1.rob.rob_writes                   96843723                       # The number of ROB writes
-system.cpu1.timesIdled                         866392                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                      160301793                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                  2319061347                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                   30318400                       # Number of Instructions Simulated
-system.cpu1.committedOps                     38407318                       # Number of Ops (including micro ops) Simulated
-system.cpu1.committedInsts_total             30318400                       # Number of Instructions Simulated
-system.cpu1.cpi                              7.816718                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        7.816718                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.127931                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.127931                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads               271568545                       # number of integer regfile reads
-system.cpu1.int_regfile_writes               43555908                       # number of integer regfile writes
-system.cpu1.fp_regfile_reads                    45194                       # number of floating regfile reads
-system.cpu1.fp_regfile_writes                   42320                       # number of floating regfile writes
-system.cpu1.misc_regfile_reads              132647791                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes                591619                       # number of misc regfile writes
+system.cpu1.rob.rob_reads                   120827478                       # The number of ROB reads
+system.cpu1.rob.rob_writes                   97232532                       # The number of ROB writes
+system.cpu1.timesIdled                         865086                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                      160261950                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                  2316983227                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                   30492768                       # Number of Instructions Simulated
+system.cpu1.committedOps                     38608143                       # Number of Ops (including micro ops) Simulated
+system.cpu1.committedInsts_total             30492768                       # Number of Instructions Simulated
+system.cpu1.cpi                              7.774201                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        7.774201                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.128631                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.128631                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads               272500909                       # number of integer regfile reads
+system.cpu1.int_regfile_writes               43779735                       # number of integer regfile writes
+system.cpu1.fp_regfile_reads                    45015                       # number of floating regfile reads
+system.cpu1.fp_regfile_writes                   42294                       # number of floating regfile writes
+system.cpu1.misc_regfile_reads              133085319                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes                592959                       # number of misc regfile writes
 system.iocache.tags.replacements                    0                       # number of replacements
 system.iocache.tags.tagsinuse                       0                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
@@ -2334,17 +2082,17 @@ system.iocache.avg_blocked_cycles::no_mshrs          nan                       #
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1518507680269                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1518507680269                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1518507680269                       # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1518507680269                       # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736889440801                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1736889440801                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736889440801                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1736889440801                       # number of overall MSHR uncacheable cycles
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   83057                       # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce                   83061                       # number of quiesce instructions executed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
 
index 31d2c17792db97c7beea60697e68336124de04bd..0948685761dc1011949284a6215f4f60e5e61672 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.629750                       # Number of seconds simulated
-sim_ticks                                2629749511500                       # Number of ticks simulated
-final_tick                               2629749511500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.629695                       # Number of seconds simulated
+sim_ticks                                2629694709500                       # Number of ticks simulated
+final_tick                               2629694709500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 406352                       # Simulator instruction rate (inst/s)
-host_op_rate                                   517075                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            17746353667                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 422316                       # Number of bytes of host memory used
-host_seconds                                   148.19                       # Real time elapsed on the host
-sim_insts                                    60215342                       # Number of instructions simulated
-sim_ops                                      76622873                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 422902                       # Simulator instruction rate (inst/s)
+host_op_rate                                   538135                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            18468797106                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 466428                       # Number of bytes of host memory used
+host_seconds                                   142.39                       # Real time elapsed on the host
+sim_insts                                    60215255                       # Number of instructions simulated
+sim_ops                                      76622777                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::realview.clcd    124256256                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           298760                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          4637400                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           291720                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          4684888                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.dtb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           405700                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          4423316                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            134021624                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       298760                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       405700                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          704460                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      3690048                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data       1524460                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data       1491820                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6706328                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu1.inst           412356                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          4375828                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            134021240                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       291720                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       412356                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          704076                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      3689664                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data       1522876                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data       1493404                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           6705944                       # Number of bytes written to this memory
 system.physmem.num_reads::realview.clcd      15532032                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             10880                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             72495                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             10770                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             73237                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.dtb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              6355                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             69149                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total              15690914                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           57657                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data           381115                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data           372955                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               811727                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd        47250225                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::cpu1.inst              6459                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             68407                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total              15690908                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           57651                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data           380719                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data           373351                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               811721                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd        47251210                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker            49                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              113608                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             1763438                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              110933                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             1781533                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu1.dtb.walker            24                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst              154273                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             1682029                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                50963646                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         113608                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst         154273                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             267881                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1403194                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data             579698                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data             567286                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2550177                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1403194                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd       47250225                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst              156808                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             1664006                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                50964562                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         110933                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst         156808                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             267741                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1403077                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data             579108                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data             567900                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2550085                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1403077                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd       47251210                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           49                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             113608                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            2343136                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             110933                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            2360641                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu1.dtb.walker           24                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst             154273                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            2249315                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               53513824                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                      15690914                       # Number of read requests accepted
-system.physmem.writeReqs                       811727                       # Number of write requests accepted
-system.physmem.readBursts                    15690914                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     811727                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM               1004216640                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      1856                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   6837504                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 134021624                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                6706328                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                       29                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                  704891                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           4516                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              980392                       # Per bank write bursts
+system.physmem.bw_total::cpu1.inst             156808                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            2231906                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               53514647                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                      15690908                       # Number of read requests accepted
+system.physmem.writeReqs                       811721                       # Number of write requests accepted
+system.physmem.readBursts                    15690908                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     811721                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM               1004216192                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      1920                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   6737024                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 134021240                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                6705944                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                       30                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                  706455                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs           4517                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0              980391                       # Per bank write bursts
 system.physmem.perBankRdBursts::1              980206                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              980222                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              980218                       # Per bank write bursts
 system.physmem.perBankRdBursts::3              980431                       # Per bank write bursts
 system.physmem.perBankRdBursts::4              986950                       # Per bank write bursts
 system.physmem.perBankRdBursts::5              980708                       # Per bank write bursts
 system.physmem.perBankRdBursts::6              980610                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              980424                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              980421                       # Per bank write bursts
 system.physmem.perBankRdBursts::8              980615                       # Per bank write bursts
 system.physmem.perBankRdBursts::9              980431                       # Per bank write bursts
 system.physmem.perBankRdBursts::10             979815                       # Per bank write bursts
 system.physmem.perBankRdBursts::11             979558                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             980153                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             980154                       # Per bank write bursts
 system.physmem.perBankRdBursts::13             980093                       # Per bank write bursts
 system.physmem.perBankRdBursts::14             980167                       # Per bank write bursts
 system.physmem.perBankRdBursts::15             980110                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                6736                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                6598                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                6606                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                6671                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                6749                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7050                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                7030                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                6882                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                6998                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                6828                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               6323                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6124                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               6612                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               6392                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               6620                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               6617                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                6645                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                6506                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                6513                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                6561                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                6643                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                6949                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6933                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                6786                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                6904                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                6725                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               6221                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6029                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               6513                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               6297                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               6516                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               6525                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2629745080000                       # Total gap between requests
+system.physmem.totGap                    2629690290000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                    6718                       # Read request sizes (log2)
 system.physmem.readPktSize::3                15532032                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  152164                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  152158                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                 754070                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  57657                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1279103                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                   1122938                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                   1123139                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                   3790711                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                   2702315                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                   2701600                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                   2718927                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                     52097                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                     57127                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                     20508                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                    20484                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                    20457                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                    20388                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                    20359                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                    20349                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                    20334                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                       49                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  57651                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1128915                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    971082                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                    971066                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                    973046                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                    971647                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                    972454                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                   2865167                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                   2865325                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                   3808659                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                     25323                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                    23577                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                    23920                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                    23318                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                    22983                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                    22230                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                    22150                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                       16                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
@@ -157,372 +157,172 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                      5035                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                      5010                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                      4993                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                      4972                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                      4958                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                      4943                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                      4934                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                      4919                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                      4897                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                      4876                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                     4859                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                     4845                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                     4830                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                     4818                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                     4803                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     4787                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     4764                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4748                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4733                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     4718                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     4704                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     4690                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        90358                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean    11189.419509                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean    1031.170467                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev   16748.902235                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64-71          23468     25.97%     25.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-135        14751     16.33%     42.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192-199         2914      3.22%     45.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-263         2094      2.32%     47.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320-327         1353      1.50%     49.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-391         1190      1.32%     50.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448-455          937      1.04%     51.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-519         1064      1.18%     52.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576-583          629      0.70%     53.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-647          518      0.57%     54.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704-711          534      0.59%     54.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-775          581      0.64%     55.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832-839          314      0.35%     55.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-903          296      0.33%     56.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960-967          233      0.26%     56.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1031          596      0.66%     56.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088-1095          187      0.21%     57.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152-1159          143      0.16%     57.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216-1223          114      0.13%     57.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280-1287          279      0.31%     57.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344-1351          129      0.14%     57.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408-1415         2228      2.47%     60.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472-1479          121      0.13%     60.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536-1543          211      0.23%     60.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600-1607           45      0.05%     60.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664-1671           43      0.05%     60.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1728-1735           36      0.04%     60.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1792-1799          110      0.12%     61.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856-1863           48      0.05%     61.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1920-1927           23      0.03%     61.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984-1991           25      0.03%     61.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2048-2055          356      0.39%     61.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112-2119           15      0.02%     61.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2176-2183           22      0.02%     61.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2240-2247           30      0.03%     61.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2304-2311           81      0.09%     61.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2368-2375           12      0.01%     61.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2432-2439           26      0.03%     61.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2496-2503           20      0.02%     61.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2560-2567           86      0.10%     61.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2624-2631           19      0.02%     61.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2688-2695           10      0.01%     61.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2752-2759           26      0.03%     61.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2816-2823           61      0.07%     61.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2880-2887            6      0.01%     61.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2944-2951           22      0.02%     61.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3008-3015           13      0.01%     62.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3072-3079          332      0.37%     62.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3136-3143           20      0.02%     62.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3200-3207           10      0.01%     62.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3264-3271            9      0.01%     62.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3328-3335          157      0.17%     62.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3392-3399            5      0.01%     62.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3456-3463           12      0.01%     62.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3520-3527           18      0.02%     62.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3584-3591          140      0.15%     62.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3648-3655           11      0.01%     62.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3712-3719           18      0.02%     62.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3776-3783           30      0.03%     62.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3840-3847          133      0.15%     62.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3904-3911           19      0.02%     63.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3968-3975            8      0.01%     63.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4032-4039            8      0.01%     63.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4096-4103          364      0.40%     63.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4160-4167            3      0.00%     63.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4224-4231            3      0.00%     63.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4288-4295           18      0.02%     63.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4352-4359           73      0.08%     63.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4416-4423            2      0.00%     63.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4480-4487           14      0.02%     63.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4544-4551            3      0.00%     63.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4608-4615           77      0.09%     63.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4672-4679           17      0.02%     63.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4736-4743            5      0.01%     63.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4800-4807            3      0.00%     63.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4864-4871           26      0.03%     63.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4928-4935            5      0.01%     63.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4992-4999            8      0.01%     63.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5056-5063           15      0.02%     63.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5120-5127          270      0.30%     64.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5184-5191            5      0.01%     64.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5248-5255           15      0.02%     64.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5312-5319            3      0.00%     64.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5376-5383           73      0.08%     64.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5440-5447          165      0.18%     64.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5504-5511           59      0.07%     64.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5568-5575            1      0.00%     64.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5632-5639          245      0.27%     64.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5696-5703            1      0.00%     64.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5888-5895          129      0.14%     64.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5952-5959            1      0.00%     64.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6144-6151          396      0.44%     65.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6400-6407          186      0.21%     65.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6528-6535            2      0.00%     65.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6592-6599            1      0.00%     65.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6656-6663           68      0.08%     65.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6784-6791            1      0.00%     65.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6912-6919            2      0.00%     65.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7168-7175          266      0.29%     65.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7424-7431           68      0.08%     65.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7680-7687          129      0.14%     66.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7936-7943           66      0.07%     66.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8192-8199          514      0.57%     66.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8448-8455           66      0.07%     66.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8704-8711          130      0.14%     66.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8960-8967           68      0.08%     66.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9216-9223          264      0.29%     67.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9472-9479            2      0.00%     67.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9728-9735           69      0.08%     67.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9984-9991          190      0.21%     67.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10048-10055            1      0.00%     67.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10240-10247          395      0.44%     67.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10496-10503          130      0.14%     68.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10752-10759          245      0.27%     68.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11008-11015           65      0.07%     68.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11264-11271          270      0.30%     68.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11520-11527            6      0.01%     68.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11584-11591            1      0.00%     68.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11776-11783           73      0.08%     68.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11840-11847            1      0.00%     68.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12032-12039           68      0.08%     68.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12288-12295          342      0.38%     69.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12480-12487            2      0.00%     69.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12544-12551          127      0.14%     69.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12672-12679            1      0.00%     69.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12800-12807          128      0.14%     69.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12992-12999            1      0.00%     69.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13056-13063          133      0.15%     69.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13312-13319          321      0.36%     70.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13568-13575           57      0.06%     70.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13824-13831           77      0.09%     70.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14080-14087           70      0.08%     70.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14336-14343          324      0.36%     70.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14400-14407            1      0.00%     70.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14592-14599           72      0.08%     70.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14848-14855          127      0.14%     70.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15104-15111          141      0.16%     71.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15360-15367          387      0.43%     71.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15616-15623           73      0.08%     71.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15872-15879            1      0.00%     71.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16128-16135           65      0.07%     71.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16384-16391          651      0.72%     72.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16640-16647           66      0.07%     72.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16896-16903            2      0.00%     72.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16960-16967            1      0.00%     72.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17024-17031            1      0.00%     72.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17152-17159           72      0.08%     72.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17408-17415          389      0.43%     72.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17664-17671          142      0.16%     73.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17920-17927          126      0.14%     73.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18176-18183           70      0.08%     73.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18240-18247            1      0.00%     73.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18432-18439          321      0.36%     73.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18496-18503            1      0.00%     73.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18624-18631            1      0.00%     73.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18688-18695           69      0.08%     73.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18944-18951           77      0.09%     73.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19072-19079            1      0.00%     73.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19200-19207           59      0.07%     73.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19456-19463          322      0.36%     74.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19648-19655            1      0.00%     74.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19712-19719          131      0.14%     74.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19968-19975          131      0.14%     74.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20224-20231          129      0.14%     74.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20480-20487          344      0.38%     75.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20736-20743           69      0.08%     75.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20992-20999           72      0.08%     75.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21248-21255            6      0.01%     75.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21440-21447            1      0.00%     75.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21504-21511          266      0.29%     75.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21760-21767           64      0.07%     75.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22016-22023          246      0.27%     75.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22272-22279          133      0.15%     76.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22528-22535          396      0.44%     76.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22784-22791          186      0.21%     76.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23040-23047           68      0.08%     76.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23424-23431            1      0.00%     76.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23552-23559          265      0.29%     77.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23808-23815           68      0.08%     77.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24064-24071          130      0.14%     77.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24320-24327           65      0.07%     77.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24384-24391            1      0.00%     77.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24576-24583          512      0.57%     77.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24832-24839           66      0.07%     77.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25088-25095          129      0.14%     78.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25344-25351           67      0.07%     78.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25472-25479            1      0.00%     78.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25600-25607          264      0.29%     78.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25792-25799            1      0.00%     78.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26112-26119           69      0.08%     78.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26368-26375          185      0.20%     78.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26624-26631          394      0.44%     79.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26816-26823            1      0.00%     79.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26880-26887          130      0.14%     79.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26944-26951            1      0.00%     79.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27136-27143          246      0.27%     79.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27392-27399           65      0.07%     79.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27648-27655          267      0.30%     80.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27840-27847            2      0.00%     80.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27904-27911            4      0.00%     80.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28160-28167           73      0.08%     80.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28416-28423           69      0.08%     80.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28544-28551            1      0.00%     80.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28608-28615            1      0.00%     80.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28672-28679          339      0.38%     80.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28928-28935          128      0.14%     80.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29184-29191          130      0.14%     80.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29440-29447          133      0.15%     80.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29504-29511            1      0.00%     80.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29696-29703          322      0.36%     81.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29760-29767            1      0.00%     81.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29888-29895            1      0.00%     81.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29952-29959           57      0.06%     81.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30208-30215           76      0.08%     81.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30272-30279            2      0.00%     81.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30464-30471           68      0.08%     81.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30720-30727          322      0.36%     81.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30976-30983           72      0.08%     82.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31232-31239          126      0.14%     82.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31488-31495          141      0.16%     82.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31616-31623            1      0.00%     82.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31744-31751          387      0.43%     82.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32000-32007           71      0.08%     82.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32192-32199            1      0.00%     82.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32256-32263            1      0.00%     82.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32512-32519           66      0.07%     82.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32768-32775          652      0.72%     83.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33024-33031           71      0.08%     83.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33280-33287            3      0.00%     83.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33344-33351            1      0.00%     83.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33536-33543           71      0.08%     83.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33792-33799          386      0.43%     84.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34048-34055          141      0.16%     84.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34304-34311          126      0.14%     84.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34560-34567           72      0.08%     84.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34816-34823          320      0.35%     84.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35072-35079           68      0.08%     84.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35328-35335           76      0.08%     85.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35584-35591           57      0.06%     85.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35648-35655            1      0.00%     85.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35840-35847          321      0.36%     85.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36096-36103          132      0.15%     85.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36352-36359          129      0.14%     85.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36608-36615          128      0.14%     85.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36864-36871          338      0.37%     86.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37120-37127           69      0.08%     86.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37376-37383           72      0.08%     86.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37632-37639            4      0.00%     86.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37696-37703            2      0.00%     86.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37888-37895          269      0.30%     86.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38144-38151           65      0.07%     86.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38400-38407          246      0.27%     87.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38592-38599            1      0.00%     87.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38656-38663          129      0.14%     87.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38912-38919          394      0.44%     87.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39168-39175          185      0.20%     87.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39424-39431           67      0.07%     87.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39744-39751            1      0.00%     87.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39936-39943          264      0.29%     88.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40064-40071            1      0.00%     88.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40192-40199           67      0.07%     88.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40448-40455          129      0.14%     88.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40704-40711           65      0.07%     88.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40960-40967          512      0.57%     89.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41152-41159            1      0.00%     89.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41216-41223           65      0.07%     89.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41472-41479          129      0.14%     89.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41728-41735           68      0.08%     89.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41984-41991          264      0.29%     89.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42112-42119            1      0.00%     89.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42496-42503           68      0.08%     89.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42752-42759          186      0.21%     89.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43008-43015          395      0.44%     90.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43264-43271          132      0.15%     90.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43520-43527          246      0.27%     90.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43776-43783           64      0.07%     90.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44032-44039          266      0.29%     91.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44096-44103            1      0.00%     91.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44288-44295            6      0.01%     91.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44544-44551           71      0.08%     91.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44800-44807           69      0.08%     91.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45056-45063          340      0.38%     91.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45312-45319          129      0.14%     91.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45568-45575          130      0.14%     92.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45824-45831          131      0.14%     92.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46080-46087          320      0.35%     92.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46336-46343           58      0.06%     92.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46464-46471            1      0.00%     92.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46592-46599           74      0.08%     92.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46848-46855           70      0.08%     92.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47104-47111          320      0.35%     93.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47296-47303            1      0.00%     93.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47360-47367           72      0.08%     93.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47616-47623          128      0.14%     93.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47872-47879          142      0.16%     93.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48128-48135          388      0.43%     93.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48192-48199            1      0.00%     93.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48384-48391           73      0.08%     93.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48640-48647            2      0.00%     93.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48896-48903           66      0.07%     94.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48960-48967            1      0.00%     94.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::49024-49031            2      0.00%     94.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::49088-49095            2      0.00%     94.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::49152-49159         5356      5.93%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          90358                       # Bytes accessed per row activation
-system.physmem.totQLat                   377355345750                       # Total ticks spent queuing
-system.physmem.totMemAccLat              474591583250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                  78454425000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                 18781812500                       # Total ticks spent accessing banks
-system.physmem.avgQLat                       24049.33                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                     1196.99                       # Average bank access latency per DRAM burst
+system.physmem.wrQLenPdf::0                       362                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                       357                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                       351                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                       346                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                       344                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                       342                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                       339                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                       333                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                       330                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                       328                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                      324                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                      322                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                      320                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                      316                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                      312                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     2639                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2695                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     3184                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     4442                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     4405                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     4394                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     4384                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     4400                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     4387                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     4357                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     5258                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     4449                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     4419                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     5254                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     4320                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     4318                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     4276                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     4193                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     1201                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                     1180                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                     1181                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                     1179                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                     1168                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                     1167                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                     1166                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                     1165                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                     1166                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                     1164                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                     1164                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                     1164                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                     1164                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                     1164                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                     1163                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                     1163                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                     1157                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                     1152                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                     1147                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                     1146                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                     1145                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       990183                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean     1014.719065                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean    1002.794597                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev      86.877825                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127           3622      0.37%      0.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         3291      0.33%      0.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         1715      0.17%      0.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         1178      0.12%      0.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639          920      0.09%      1.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          703      0.07%      1.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          532      0.05%      1.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          420      0.04%      1.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151       977802     98.75%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         990183                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          4537                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean      3458.425832                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev    54557.622307                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-65535          4511     99.43%     99.43% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::131072-196607            8      0.18%     99.60% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::196608-262143            4      0.09%     99.69% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::393216-458751            2      0.04%     99.74% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::589824-655359            3      0.07%     99.80% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::786432-851967            1      0.02%     99.82% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::983040-1.04858e+06            1      0.02%     99.85% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1.17965e+06-1.24518e+06            6      0.13%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1.37626e+06-1.44179e+06            1      0.02%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            4537                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          4537                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        23.201675                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       21.361663                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        9.873768                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::1                   5      0.11%      0.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::2                   7      0.15%      0.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::3                   5      0.11%      0.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4                   2      0.04%      0.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::5                   2      0.04%      0.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::6                   4      0.09%      0.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::7                   6      0.13%      0.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8                   3      0.07%      0.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::9                   3      0.07%      0.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::10                  3      0.07%      0.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::11                  3      0.07%      0.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12                  2      0.04%      0.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::13                  4      0.09%      1.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::14                  7      0.15%      1.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::15                 17      0.37%      1.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               1491     32.86%     34.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                339      7.47%     41.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                208      4.58%     46.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19               1050     23.14%     69.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                 16      0.35%     70.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 12      0.26%     70.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 20      0.44%     70.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 24      0.53%     71.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                 18      0.40%     71.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                 14      0.31%     71.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                 18      0.40%     72.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27                 18      0.40%     72.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28                 19      0.42%     73.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29                 13      0.29%     73.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30                 11      0.24%     73.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::31                 12      0.26%     73.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32                 11      0.24%     74.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::33                  3      0.07%     74.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::35                  2      0.04%     74.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36                  1      0.02%     74.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::39               1015     22.37%     96.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40                 76      1.68%     98.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::41                 13      0.29%     98.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::42                 42      0.93%     99.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::47                  1      0.02%     99.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::49                  5      0.11%     99.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::50                  5      0.11%     99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::51                  5      0.11%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52                  1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::53                  1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            4537                       # Writes before turning the bus around for reads
+system.physmem.totQLat                   592300556750                       # Total ticks spent queuing
+system.physmem.totMemAccLat              700300341750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                  78454390000                       # Total ticks spent in databus transfers
+system.physmem.totBankLat                 29545395000                       # Total ticks spent accessing banks
+system.physmem.avgQLat                       37748.08                       # Average queueing delay per DRAM burst
+system.physmem.avgBankLat                     1882.97                       # Average bank access latency per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  30246.32                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         381.87                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           2.60                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  44631.05                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         381.88                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           2.56                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                       50.96                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        2.55                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           3.00                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       2.98                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         0.18                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                         1.22                       # Average write queue length when enqueuing
-system.physmem.readRowHits                   15616397                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     90966                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   99.53                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  85.15                       # Row buffer hit rate for writes
-system.physmem.avgGap                       159352.98                       # Average gap between requests
-system.physmem.pageHitRate                      99.43                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               2.38                       # Percentage of time for which DRAM has all the banks in precharge state
+system.physmem.avgRdQLen                         7.04                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        14.89                       # Average write queue length when enqueuing
+system.physmem.readRowHits                   14676487                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     89750                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   93.54                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  85.26                       # Row buffer hit rate for writes
+system.physmem.avgGap                       159349.78                       # Average gap between requests
+system.physmem.pageHitRate                      93.48                       # Row buffer hit rate, read and write combined
+system.physmem.prechargeAllPercent               4.16                       # Percentage of time for which DRAM has all the banks in precharge state
 system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
@@ -535,259 +335,259 @@ system.realview.nvmem.bw_inst_read::cpu0.inst            8
 system.realview.nvmem.bw_inst_read::total            8                       # Instruction read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu0.inst            8                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total               8                       # Total bandwidth to/from this memory (bytes/s)
-system.membus.throughput                     54425810                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq            16743683                       # Transaction distribution
-system.membus.trans_dist::ReadResp           16743683                       # Transaction distribution
+system.membus.throughput                     54426652                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq            16743677                       # Transaction distribution
+system.membus.trans_dist::ReadResp           16743677                       # Transaction distribution
 system.membus.trans_dist::WriteReq             763441                       # Transaction distribution
 system.membus.trans_dist::WriteResp            763441                       # Transaction distribution
-system.membus.trans_dist::Writeback             57657                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4516                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            4516                       # Transaction distribution
+system.membus.trans_dist::Writeback             57651                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4517                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            4517                       # Transaction distribution
 system.membus.trans_dist::ReadExReq            131342                       # Transaction distribution
 system.membus.trans_dist::ReadExResp           131342                       # Transaction distribution
 system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      2383092                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           10                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio         3860                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio            2                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1892593                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      4279557                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1892577                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      4279541                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     31064064                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total     31064064                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total               35343621                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total               35343605                       # Packet count per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave      2390550                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port           20                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio         7720                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio            4                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     16471696                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::total     18869990                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     16470928                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::total     18869222                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port    124256256                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.iocache.mem_side::total    124256256                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total           143126246                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus              143126246                       # Total data (bytes)
+system.membus.tot_pkt_size::total           143125478                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus              143125478                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy          1225748500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy          1225762000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy                5000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             3758000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             3755500                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer4.occupancy                1000                       # Layer occupancy (ticks)
 system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer6.occupancy         18171669500                       # Layer occupancy (ticks)
+system.membus.reqLayer6.occupancy         18171181500                       # Layer occupancy (ticks)
 system.membus.reqLayer6.utilization               0.7                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         4990674222                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         4987933108                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
-system.membus.respLayer2.occupancy        35076241500                       # Layer occupancy (ticks)
-system.membus.respLayer2.utilization              1.3                       # Layer utilization (%)
+system.membus.respLayer2.occupancy        38819144750                       # Layer occupancy (ticks)
+system.membus.respLayer2.utilization              1.5                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.l2c.tags.replacements                    62047                       # number of replacements
-system.l2c.tags.tagsinuse                51602.841569                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    1699505                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   127430                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    13.336773                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle             2574813583500                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   38208.002352                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000703                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     2774.091625                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     3066.452073                       # Average occupied blocks per requestor
+system.l2c.tags.replacements                    62041                       # number of replacements
+system.l2c.tags.tagsinuse                51600.507824                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    1699332                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   127423                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    13.336148                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle             2574803290500                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks   38204.625202                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker     0.000702                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     2677.995545                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     3048.557344                       # Average occupied blocks per requestor
 system.l2c.tags.occ_blocks::cpu1.dtb.walker     0.000187                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     4246.643785                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     3307.650843                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.583008                       # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::cpu1.inst     4342.999627                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     3326.329216                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.582956                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.042329                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.046790                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.040863                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.046517                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000000                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.064799                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.050471                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.787397                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024        65383                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           27                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1           25                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         2131                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         6484                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        56716                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024     0.997665                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 17278266                       # Number of tag accesses
-system.l2c.tags.data_accesses                17278266                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker         9823                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker         3607                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst             411412                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             183126                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker        10084                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker         3595                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             433138                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data             187347                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1242132                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          596464                       # number of Writeback hits
-system.l2c.Writeback_hits::total               596464                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data              13                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data              13                       # number of UpgradeReq hits
+system.l2c.tags.occ_percent::cpu1.inst       0.066269                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.050756                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.787361                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1024        65382                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           26                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1           26                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         2132                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         6447                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        56751                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1024     0.997650                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 17277037                       # Number of tag accesses
+system.l2c.tags.data_accesses                17277037                       # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.dtb.walker         9996                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker         3617                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.inst             411271                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data             183421                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker         9883                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker         3502                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst             433200                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data             187065                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1241955                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          596489                       # number of Writeback hits
+system.l2c.Writeback_hits::total               596489                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data              14                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data              12                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::total                  26                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            57116                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            57419                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               114535                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker          9823                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker          3607                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              411412                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              240242                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker         10084                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          3595                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              433138                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              244766                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1356667                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker         9823                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker         3607                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             411412                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             240242                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker        10084                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         3595                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             433138                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             244766                       # number of overall hits
-system.l2c.overall_hits::total                1356667                       # number of overall hits
+system.l2c.ReadExReq_hits::cpu0.data            55903                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            58636                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               114539                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.dtb.walker          9996                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker          3617                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst              411271                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              239324                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker          9883                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker          3502                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              433200                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              245701                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 1356494                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker         9996                       # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker         3617                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst             411271                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             239324                       # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker         9883                       # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker         3502                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             433200                       # number of overall hits
+system.l2c.overall_hits::cpu1.data             245701                       # number of overall hits
+system.l2c.overall_hits::total                1356494                       # number of overall hits
 system.l2c.ReadReq_misses::cpu0.itb.walker            2                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst             4254                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data             5302                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.inst             4144                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data             5204                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu1.dtb.walker            1                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst             6338                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data             4925                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                20822                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data          1344                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data          1536                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              2880                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          67932                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          65046                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             132978                       # number of ReadExReq misses
+system.l2c.ReadReq_misses::cpu1.inst             6442                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data             5023                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                20816                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data          1406                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data          1477                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              2883                       # number of UpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data          68791                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data          64185                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             132976                       # number of ReadExReq misses
 system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst              4254                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data             73234                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst              4144                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data             73995                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu1.dtb.walker            1                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              6338                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data             69971                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                153800                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst              6442                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data             69208                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                153792                       # number of demand (read+write) misses
 system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst             4254                       # number of overall misses
-system.l2c.overall_misses::cpu0.data            73234                       # number of overall misses
+system.l2c.overall_misses::cpu0.inst             4144                       # number of overall misses
+system.l2c.overall_misses::cpu0.data            73995                       # number of overall misses
 system.l2c.overall_misses::cpu1.dtb.walker            1                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             6338                       # number of overall misses
-system.l2c.overall_misses::cpu1.data            69971                       # number of overall misses
-system.l2c.overall_misses::total               153800                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst             6442                       # number of overall misses
+system.l2c.overall_misses::cpu1.data            69208                       # number of overall misses
+system.l2c.overall_misses::total               153792                       # number of overall misses
 system.l2c.ReadReq_miss_latency::cpu0.itb.walker       149500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.inst    304771500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data    393396750                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.inst    292011000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.data    389009500                       # number of ReadReq miss cycles
 system.l2c.ReadReq_miss_latency::cpu1.dtb.walker        89250                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst    451834250                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data    374309250                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total     1524550500                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0.data       232990                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data       231990                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total       464980                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data   4846991473                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data   4619004891                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   9465996364                       # number of ReadExReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst    455480250                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data    379549000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total     1516288500                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu0.data       256489                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data       208991                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total       465480                       # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data   4825847704                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data   4517645162                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   9343492866                       # number of ReadExReq miss cycles
 system.l2c.demand_miss_latency::cpu0.itb.walker       149500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst    304771500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data   5240388223                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.inst    292011000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data   5214857204                       # number of demand (read+write) miss cycles
 system.l2c.demand_miss_latency::cpu1.dtb.walker        89250                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst    451834250                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data   4993314141                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total     10990546864                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst    455480250                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data   4897194162                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total     10859781366                       # number of demand (read+write) miss cycles
 system.l2c.overall_miss_latency::cpu0.itb.walker       149500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst    304771500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data   5240388223                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.inst    292011000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data   5214857204                       # number of overall miss cycles
 system.l2c.overall_miss_latency::cpu1.dtb.walker        89250                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst    451834250                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data   4993314141                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    10990546864                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.dtb.walker         9823                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker         3609                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst         415666                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data         188428                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker        10085                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker         3595                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst         439476                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data         192272                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            1262954                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       596464                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           596464                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data         1357                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data         1549                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            2906                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       125048                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data       122465                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           247513                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker         9823                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker         3609                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst          415666                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data          313476                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker        10085                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker         3595                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          439476                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          314737                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             1510467                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker         9823                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker         3609                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         415666                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data         313476                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker        10085                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker         3595                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         439476                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         314737                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            1510467                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000554                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.010234                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.028138                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000099                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.014422                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.025615                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.016487                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.990420                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.991607                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.991053                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.543247                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.531140                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.537257                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.000554                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.010234                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.233619                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000099                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.014422                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.222316                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.101823                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.000554                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.010234                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.233619                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000099                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.014422                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.222316                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.101823                       # miss rate for overall accesses
+system.l2c.overall_miss_latency::cpu1.inst    455480250                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data   4897194162                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total    10859781366                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.dtb.walker         9996                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker         3619                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.inst         415415                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data         188625                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker         9884                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker         3502                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst         439642                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data         192088                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            1262771                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       596489                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           596489                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data         1420                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data         1489                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            2909                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       124694                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data       122821                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           247515                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker         9996                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker         3619                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst          415415                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data          313319                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker         9884                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker         3502                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          439642                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data          314909                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             1510286                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker         9996                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker         3619                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         415415                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data         313319                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker         9884                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker         3502                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         439642                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data         314909                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            1510286                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000553                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.009976                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.027589                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000101                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst      0.014653                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data      0.026149                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.016484                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.990141                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.991941                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.991062                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.551679                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.522590                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.537244                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.000553                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.009976                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.236165                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000101                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.014653                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.219771                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.101830                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.000553                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.009976                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.236165                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000101                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.014653                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.219771                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.101830                       # miss rate for overall accesses
 system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        74750                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 71643.511989                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 74197.802716                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.inst 70465.974903                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.data 74752.017679                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        89250                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 71289.720732                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 76001.878173                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 73218.254731                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   173.355655                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   151.035156                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total   161.451389                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 71350.637005                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 71011.359515                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 71184.679902                       # average ReadExReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 70704.788885                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 75562.213816                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 72842.452921                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   182.424609                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data   141.496953                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total   161.456816                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 70152.312134                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 70384.749739                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 70264.505369                       # average ReadExReq miss latency
 system.l2c.demand_avg_miss_latency::cpu0.itb.walker        74750                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 71643.511989                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 71556.766297                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 70465.974903                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 70475.805176                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        89250                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 71289.720732                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 71362.623673                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 71459.992614                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 70704.788885                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 70760.521356                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 70613.434808                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu0.itb.walker        74750                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 71643.511989                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 71556.766297                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 70465.974903                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 70475.805176                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        89250                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 71289.720732                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 71362.623673                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 71459.992614                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 70704.788885                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 70760.521356                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 70613.434808                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -796,129 +596,129 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               57657                       # number of writebacks
-system.l2c.writebacks::total                    57657                       # number of writebacks
+system.l2c.writebacks::writebacks               57651                       # number of writebacks
+system.l2c.writebacks::total                    57651                       # number of writebacks
 system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            2                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.inst         4254                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.data         5302                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.inst         4144                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.data         5204                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker            1                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst         6338                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data         4925                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total           20822                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data         1344                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data         1536                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total         2880                       # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data        67932                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data        65046                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        132978                       # number of ReadExReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.inst         6442                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.data         5023                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total           20816                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data         1406                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data         1477                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total         2883                       # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data        68791                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data        64185                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        132976                       # number of ReadExReq MSHR misses
 system.l2c.demand_mshr_misses::cpu0.itb.walker            2                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst         4254                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data        73234                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst         4144                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data        73995                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu1.dtb.walker            1                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst         6338                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data        69971                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           153800                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst         6442                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data        69208                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           153792                       # number of demand (read+write) MSHR misses
 system.l2c.overall_mshr_misses::cpu0.itb.walker            2                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst         4254                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data        73234                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst         4144                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data        73995                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu1.dtb.walker            1                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst         6338                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data        69971                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          153800                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst         6442                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data        69208                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          153792                       # number of overall MSHR misses
 system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker       125000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    250900000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.data    327379750                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    239540000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.data    324214500                       # number of ReadReq MSHR miss cycles
 system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker        76250                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    371456750                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data    312895750                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total   1262833500                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     13441344                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     15361536                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total     28802880                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   3976712027                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   3785150609                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   7761862636                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    373802250                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data    316907500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total   1254665500                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     14061406                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     14772477                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total     28833883                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   3946484796                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   3696331838                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   7642816634                       # number of ReadExReq MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       125000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst    250900000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data   4304091777                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst    239540000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data   4270699296                       # number of demand (read+write) MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker        76250                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst    371456750                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data   4098046359                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total   9024696136                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst    373802250                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data   4013239338                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   8897482134                       # number of demand (read+write) MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       125000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst    250900000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data   4304091777                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst    239540000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data   4270699296                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker        76250                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst    371456750                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data   4098046359                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total   9024696136                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    344358750                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data  83703872750                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst       842500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  82981576250                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 167030650250                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   8433139011                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   8270681501                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total  16703820512                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    344358750                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data  92137011761                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.inst       842500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data  91252257751                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 183734470762                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000554                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.010234                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.028138                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000099                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.014422                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.025615                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.016487                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.990420                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.991607                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.991053                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.543247                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.531140                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.537257                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000554                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.010234                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.233619                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000099                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.014422                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.222316                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.101823                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000554                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.010234                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.233619                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000099                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.014422                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.222316                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.101823                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_latency::cpu1.inst    373802250                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data   4013239338                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   8897482134                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    351469750                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data  82683235750                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst       856250                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  84002858250                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 167038420000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   8408462374                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data   8295509001                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total  16703971375                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    351469750                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data  91091698124                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst       856250                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data  92298367251                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 183742391375                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000553                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.009976                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.027589                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000101                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.014653                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.026149                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.016484                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.990141                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.991941                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.991062                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.551679                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.522590                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.537244                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000553                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.009976                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.236165                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000101                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.014653                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.219771                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.101830                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000553                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.009976                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.236165                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000101                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.014653                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.219771                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.101830                       # mshr miss rate for overall accesses
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 58979.783733                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61746.463599                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 57804.054054                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 62301.018447                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        76250                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58607.881035                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63532.131980                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 60649.001057                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58025.807203                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63091.280111                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 60274.092045                       # average ReadReq mshr miss latency
 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data        10001                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data        10001                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total        10001                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 58539.598819                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58191.904329                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 58369.524553                       # average ReadExReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001.677048                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.346861                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 57369.202308                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 57588.717582                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 57475.158179                       # average ReadExReq mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 58979.783733                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58771.769629                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 57804.054054                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 57716.052382                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        76250                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58607.881035                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58567.783210                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 58678.128322                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58025.807203                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57988.084297                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 57853.998478                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 58979.783733                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58771.769629                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 57804.054054                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57716.052382                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        76250                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58607.881035                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58567.783210                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 58678.128322                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58025.807203                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57988.084297                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 57853.998478                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
@@ -939,39 +739,39 @@ system.cf0.dma_read_txs                             0                       # Nu
 system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
-system.toL2Bus.throughput                    52791444                       # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq            2472019                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2472019                       # Transaction distribution
+system.toL2Bus.throughput                    52790847                       # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq            2471761                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2471761                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteReq            763441                       # Transaction distribution
 system.toL2Bus.trans_dist::WriteResp           763441                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           596464                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq            2906                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp           2906                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           247513                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          247513                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1725197                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      5753946                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        20259                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        50584                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               7549986                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     54755680                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     83794182                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        28816                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        79632                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size::total          138658310                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus             138658310                       # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus          169964                       # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy         4808748000                       # Layer occupancy (ticks)
+system.toL2Bus.trans_dist::Writeback           596489                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq            2909                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp           2909                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           247515                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          247515                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1725013                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      5754007                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side        20046                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        50514                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               7549580                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     54750240                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     83796742                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side        28484                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        79520                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size::total          138654986                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus             138654986                       # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus          168824                       # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy         4808734000                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        3865724000                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        3865148750                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        4421241528                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        4420266392                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.2                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy          13055000                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy          12925000                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy          30676250                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy          30634250                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
-system.iobus.throughput                      48159266                       # Throughput (bytes/s)
+system.iobus.throughput                      48160270                       # Throughput (bytes/s)
 system.iobus.trans_dist::ReadReq             16715394                       # Transaction distribution
 system.iobus.trans_dist::ReadResp            16715394                       # Transaction distribution
 system.iobus.trans_dist::WriteReq                8184                       # Transaction distribution
@@ -1081,8 +881,8 @@ system.iobus.reqLayer25.occupancy         15532032000                       # La
 system.iobus.reqLayer25.utilization               0.6                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy          2374908000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.1                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy         42583156500                       # Layer occupancy (ticks)
-system.iobus.respLayer1.utilization               1.6                       # Layer utilization (%)
+system.iobus.respLayer1.occupancy         38823243250                       # Layer occupancy (ticks)
+system.iobus.respLayer1.utilization               1.5                       # Layer utilization (%)
 system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1106,25 +906,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                     7421730                       # DTB read hits
-system.cpu0.dtb.read_misses                      6821                       # DTB read misses
-system.cpu0.dtb.write_hits                    5623030                       # DTB write hits
-system.cpu0.dtb.write_misses                     1843                       # DTB write misses
+system.cpu0.dtb.read_hits                     7344844                       # DTB read hits
+system.cpu0.dtb.read_misses                      6860                       # DTB read misses
+system.cpu0.dtb.write_hits                    5551128                       # DTB write hits
+system.cpu0.dtb.write_misses                     1832                       # DTB write misses
 system.cpu0.dtb.flush_tlb                        2493                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid                666                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_mva_asid                699                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                     31                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    6415                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_entries                    6351                       # Number of entries that have been flushed from TLB
 system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                   147                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults                   137                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      218                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                 7428551                       # DTB read accesses
-system.cpu0.dtb.write_accesses                5624873                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      220                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                 7351704                       # DTB read accesses
+system.cpu0.dtb.write_accesses                5552960                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         13044760                       # DTB hits
-system.cpu0.dtb.misses                           8664                       # DTB misses
-system.cpu0.dtb.accesses                     13053424                       # DTB accesses
+system.cpu0.dtb.hits                         12895972                       # DTB hits
+system.cpu0.dtb.misses                           8692                       # DTB misses
+system.cpu0.dtb.accesses                     12904664                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1146,125 +946,125 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.inst_hits                    30640130                       # ITB inst hits
-system.cpu0.itb.inst_misses                      3559                       # ITB inst misses
+system.cpu0.itb.inst_hits                    30211154                       # ITB inst hits
+system.cpu0.itb.inst_misses                      3603                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
 system.cpu0.itb.write_misses                        0                       # DTB write misses
 system.cpu0.itb.flush_tlb                        2493                       # Number of times complete TLB was flushed
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid                666                       # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_mva_asid                699                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.itb.flush_tlb_asid                     31                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    2782                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries                    2758                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                30643689                       # ITB inst accesses
-system.cpu0.itb.hits                         30640130                       # DTB hits
-system.cpu0.itb.misses                           3559                       # DTB misses
-system.cpu0.itb.accesses                     30643689                       # DTB accesses
-system.cpu0.numCycles                      2628262208                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                30214757                       # ITB inst accesses
+system.cpu0.itb.hits                         30211154                       # DTB hits
+system.cpu0.itb.misses                           3603                       # DTB misses
+system.cpu0.itb.accesses                     30214757                       # DTB accesses
+system.cpu0.numCycles                      2627736532                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   30017324                       # Number of instructions committed
-system.cpu0.committedOps                     38175915                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             34451316                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                  4807                       # Number of float alu accesses
-system.cpu0.num_func_calls                    1059150                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      3975405                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    34451316                       # number of integer instructions
-system.cpu0.num_fp_insts                         4807                       # number of float instructions
-system.cpu0.num_int_register_reads          199768149                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          37153826                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads                3633                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes               1176                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                     13618692                       # number of memory refs
-system.cpu0.num_load_insts                    7744625                       # Number of load instructions
-system.cpu0.num_store_insts                   5874067                       # Number of store instructions
-system.cpu0.num_idle_cycles              2288630899.609074                       # Number of idle cycles
-system.cpu0.num_busy_cycles              339631308.390926                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.129223                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.870777                       # Percentage of idle cycles
-system.cpu0.Branches                          5132509                       # Number of branches fetched
+system.cpu0.committedInsts                   29624937                       # Number of instructions committed
+system.cpu0.committedOps                     37728426                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses             34074958                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                  4583                       # Number of float alu accesses
+system.cpu0.num_func_calls                    1045164                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      3935196                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    34074958                       # number of integer instructions
+system.cpu0.num_fp_insts                         4583                       # number of float instructions
+system.cpu0.num_int_register_reads          197582111                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          36713164                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads                3288                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes               1298                       # number of times the floating registers were written
+system.cpu0.num_mem_refs                     13470170                       # number of memory refs
+system.cpu0.num_load_insts                    7667939                       # Number of load instructions
+system.cpu0.num_store_insts                   5802231                       # Number of store instructions
+system.cpu0.num_idle_cycles              2282002616.045546                       # Number of idle cycles
+system.cpu0.num_busy_cycles              345733915.954454                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.131571                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.868429                       # Percentage of idle cycles
+system.cpu0.Branches                          5074688                       # Number of branches fetched
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu0.kern.inst.quiesce                   83029                       # number of quiesce instructions executed
-system.cpu0.icache.tags.replacements           856246                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          510.851832                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           60652701                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           856758                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            70.793271                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      20193023250                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   218.639655                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst   292.212178                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.427031                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.570727                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.997757                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements           856147                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          510.849495                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           60652706                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           856659                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            70.801458                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      20216402250                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   158.742483                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst   352.107012                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.310044                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.687709                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.997753                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::0           44                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::1          195                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::2          266                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::3            7                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         62366219                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        62366219                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     30223720                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst     30428981                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       60652701                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     30223720                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst     30428981                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        60652701                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     30223720                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst     30428981                       # number of overall hits
-system.cpu0.icache.overall_hits::total       60652701                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       416410                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst       440349                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       856759                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       416410                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst       440349                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        856759                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       416410                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst       440349                       # number of overall misses
-system.cpu0.icache.overall_misses::total       856759                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   5686967000                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   6125458750                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  11812425750                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst   5686967000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst   6125458750                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  11812425750                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst   5686967000                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst   6125458750                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  11812425750                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     30640130                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst     30869330                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     61509460                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     30640130                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst     30869330                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     61509460                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     30640130                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst     30869330                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     61509460                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.013590                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.014265                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.013929                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.013590                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.014265                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.013929                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.013590                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.014265                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.013929                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13657.133594                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13910.463632                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 13787.337804                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13657.133594                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13910.463632                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 13787.337804                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13657.133594                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13910.463632                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 13787.337804                       # average overall miss latency
+system.cpu0.icache.tags.tag_accesses         62366026                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        62366026                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     29795008                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst     30857698                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       60652706                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     29795008                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst     30857698                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        60652706                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     29795008                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst     30857698                       # number of overall hits
+system.cpu0.icache.overall_hits::total       60652706                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       416146                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst       440514                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       856660                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       416146                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst       440514                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        856660                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       416146                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst       440514                       # number of overall misses
+system.cpu0.icache.overall_misses::total       856660                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   5672028500                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   6130116250                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  11802144750                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst   5672028500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst   6130116250                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  11802144750                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst   5672028500                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst   6130116250                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  11802144750                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     30211154                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst     31298212                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     61509366                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     30211154                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst     31298212                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     61509366                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     30211154                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst     31298212                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     61509366                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.013775                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.014075                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.013927                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.013775                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.014075                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.013927                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.013775                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.014075                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.013927                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13629.900323                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13915.826171                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 13776.929879                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13629.900323                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13915.826171                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 13776.929879                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13629.900323                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13915.826171                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 13776.929879                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1273,48 +1073,48 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       416410                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       440349                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       856759                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       416410                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst       440349                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       856759                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       416410                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst       440349                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       856759                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   4852567000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   5242306250                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  10094873250                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   4852567000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   5242306250                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  10094873250                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   4852567000                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   5242306250                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  10094873250                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    435943750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      1072500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    437016250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    435943750                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst      1072500                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total    437016250                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.013590                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.014265                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.013929                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.013590                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.014265                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.013929                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.013590                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.014265                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.013929                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11653.339257                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11904.889644                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11782.628779                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11653.339257                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11904.889644                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 11782.628779                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11653.339257                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11904.889644                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 11782.628779                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       416146                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       440514                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       856660                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       416146                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst       440514                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       856660                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       416146                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst       440514                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       856660                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   4838197500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   5246649750                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  10084847250                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   4838197500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   5246649750                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  10084847250                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   4838197500                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   5246649750                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  10084847250                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    442799750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      1085250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    443885000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    442799750                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst      1085250                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total    443885000                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.013775                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.014075                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.013927                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.013775                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.014075                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.013927                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.013775                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.014075                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.013927                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11626.202102                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11910.290592                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11772.286847                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11626.202102                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11910.290592                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 11772.286847                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11626.202102                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11910.290592                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 11772.286847                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -1322,120 +1122,120 @@ system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements           627701                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.877186                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           23661631                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           628213                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            37.664981                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle        664900250                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   184.960449                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data   326.916737                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.361251                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.638509                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.999760                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.replacements           627716                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.875867                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           23661613                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           628228                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            37.664053                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle        671680250                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   152.516115                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data   359.359751                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.297883                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.701875                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.999758                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0           73                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          330                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0           72                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          331                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::2          109                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         97787589                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        97787589                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data      6520468                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data      6679152                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       13199620                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      4990639                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data      4984500                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       9975139                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       118374                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       117820                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       236194                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       124360                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data       123412                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       247772                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     11511107                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data     11663652                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        23174759                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     11511107                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data     11663652                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       23174759                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       182444                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data       186677                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       369121                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       126405                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data       124014                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       250419                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         5984                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         5595                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        11579                       # number of LoadLockedReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       308849                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data       310691                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total        619540                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       308849                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data       310691                       # number of overall misses
-system.cpu0.dcache.overall_misses::total       619540                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   2722910750                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   2758252500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total   5481163250                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   5855218871                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   5625941645                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  11481160516                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data     80735500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     79463250                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    160198750                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data   8578129621                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data   8384194145                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  16962323766                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data   8578129621                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data   8384194145                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  16962323766                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      6702912                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data      6865829                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     13568741                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      5117044                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data      5108514                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total     10225558                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       124358                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       123415                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       247773                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       124360                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       123412                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       247772                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     11819956                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data     11974343                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     23794299                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     11819956                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data     11974343                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     23794299                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.027219                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.027189                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.027204                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.024703                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.024276                       # miss rate for WriteReq accesses
+system.cpu0.dcache.tags.tag_accesses         97787592                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        97787592                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data      6450546                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data      6749057                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       13199603                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      4919460                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data      5055668                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       9975128                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       118398                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data       117802                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       236200                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       124425                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data       123348                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       247773                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     11370006                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data     11804725                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        23174731                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     11370006                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data     11804725                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       23174731                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       182595                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data       186544                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       369139                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       126114                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data       124310                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       250424                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         6030                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data         5544                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        11574                       # number of LoadLockedReq misses
+system.cpu0.dcache.demand_misses::cpu0.data       308709                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data       310854                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total        619563                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data       308709                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data       310854                       # number of overall misses
+system.cpu0.dcache.overall_misses::total       619563                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   2721600000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   2760360750                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total   5481960750                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   5821979202                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   5534732315                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  11356711517                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data     81055000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data     79345250                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    160400250                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data   8543579202                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data   8295093065                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  16838672267                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data   8543579202                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data   8295093065                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  16838672267                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      6633141                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data      6935601                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     13568742                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      5045574                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data      5179978                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total     10225552                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       124428                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data       123346                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       247774                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       124425                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data       123348                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       247773                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     11678715                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data     12115579                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     23794294                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     11678715                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data     12115579                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     23794294                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.027528                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.026897                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.027205                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.024995                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.023998                       # miss rate for WriteReq accesses
 system.cpu0.dcache.WriteReq_miss_rate::total     0.024490                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.048119                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.045335                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.046732                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.026129                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.025946                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.026037                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.026129                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.025946                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.026037                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14924.638519                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14775.534747                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 14849.231688                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 46321.101784                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 45365.375240                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 45847.801149                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13491.895053                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14202.546917                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13835.283703                       # average LoadLockedReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 27774.509942                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 26985.635712                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 27378.900097                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 27774.509942                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 26985.635712                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 27378.900097                       # average overall miss latency
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.048462                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data     0.044947                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.046712                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.026433                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.025657                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.026038                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.026433                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.025657                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.026038                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14905.117884                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14797.370862                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 14850.668041                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 46164.416338                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 44523.628952                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 45349.932582                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13441.956882                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14311.913781                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13858.670295                       # average LoadLockedReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 27675.186671                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 26684.852262                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 27178.305139                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 27675.186671                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 26684.852262                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 27178.305139                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1444,77 +1244,77 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       596464                       # number of writebacks
-system.cpu0.dcache.writebacks::total           596464                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       182444                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       186677                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       369121                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       126405                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       124014                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       250419                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         5984                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         5595                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total        11579                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       308849                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data       310691                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       619540                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       308849                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data       310691                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       619540                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2356704250                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2383886500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   4740590750                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   5575941129                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   5352926355                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total  10928867484                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     68762500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     68225750                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    136988250                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   7932645379                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   7736812855                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  15669458234                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   7932645379                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   7736812855                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  15669458234                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  91432491750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  90647732000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182080223750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data  13248714489                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  12991485999                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total  26240200488                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 104681206239                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103639217999                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 208320424238                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.027219                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.027189                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.027204                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.024703                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.024276                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.writebacks::writebacks       596489                       # number of writebacks
+system.cpu0.dcache.writebacks::total           596489                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       182595                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       186544                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       369139                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       126114                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data       124310                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       250424                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6030                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data         5544                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total        11574                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       308709                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data       310854                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       619563                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       308709                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data       310854                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       619563                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2355168000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2386207250                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   4741375250                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   5543852798                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   5262622685                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total  10806475483                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     68990000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     68208750                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    137198750                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   7899020798                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   7648829935                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  15547850733                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   7899020798                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   7648829935                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  15547850733                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  90318421750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  91762441000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182080862750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data  13218125626                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  13022508499                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total  26240634125                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 103536547376                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 104784949499                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 208321496875                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.027528                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.026897                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.027205                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.024995                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.023998                       # mshr miss rate for WriteReq accesses
 system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.024490                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.048119                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.045335                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.046732                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.026129                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.025946                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.026037                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.026129                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.025946                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.026037                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12917.411644                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12770.113619                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12842.918040                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44111.713374                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 43163.887585                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43642.325399                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11491.059492                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12194.057194                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11830.749633                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25684.542864                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24901.953565                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25292.084827                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25684.542864                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24901.953565                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25292.084827                       # average overall mshr miss latency
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.048462                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.044947                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.046712                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.026433                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.025657                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.026038                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.026433                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.025657                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.026038                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12898.315945                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12791.659072                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12844.417008                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 43959.059248                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42334.668852                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43152.714927                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11441.127695                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12303.165584                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11854.047866                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25587.270854                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24605.859777                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25094.866435                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25587.270854                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24605.859777                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25094.866435                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -1548,25 +1348,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                     7578931                       # DTB read hits
-system.cpu1.dtb.read_misses                      7259                       # DTB read misses
-system.cpu1.dtb.write_hits                    5610002                       # DTB write hits
-system.cpu1.dtb.write_misses                     1852                       # DTB write misses
+system.cpu1.dtb.read_hits                     7655819                       # DTB read hits
+system.cpu1.dtb.read_misses                      7243                       # DTB read misses
+system.cpu1.dtb.write_hits                    5681899                       # DTB write hits
+system.cpu1.dtb.write_misses                     1828                       # DTB write misses
 system.cpu1.dtb.flush_tlb                        2493                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid                773                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_mva_asid                740                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                     32                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    6696                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries                    6711                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   139                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                   143                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                      234                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                 7586190                       # DTB read accesses
-system.cpu1.dtb.write_accesses                5611854                       # DTB write accesses
+system.cpu1.dtb.perms_faults                      232                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                 7663062                       # DTB read accesses
+system.cpu1.dtb.write_accesses                5683727                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         13188933                       # DTB hits
-system.cpu1.dtb.misses                           9111                       # DTB misses
-system.cpu1.dtb.accesses                     13198044                       # DTB accesses
+system.cpu1.dtb.hits                         13337718                       # DTB hits
+system.cpu1.dtb.misses                           9071                       # DTB misses
+system.cpu1.dtb.accesses                     13346789                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1588,50 +1388,50 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.inst_hits                    30869347                       # ITB inst hits
-system.cpu1.itb.inst_misses                      3806                       # ITB inst misses
+system.cpu1.itb.inst_hits                    31298229                       # ITB inst hits
+system.cpu1.itb.inst_misses                      3696                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
 system.cpu1.itb.write_misses                        0                       # DTB write misses
 system.cpu1.itb.flush_tlb                        2493                       # Number of times complete TLB was flushed
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid                773                       # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_mva_asid                740                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                     32                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                    2929                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                    2898                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                30873153                       # ITB inst accesses
-system.cpu1.itb.hits                         30869347                       # DTB hits
-system.cpu1.itb.misses                           3806                       # DTB misses
-system.cpu1.itb.accesses                     30873153                       # DTB accesses
-system.cpu1.numCycles                      2631236815                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                31301925                       # ITB inst accesses
+system.cpu1.itb.hits                         31298229                       # DTB hits
+system.cpu1.itb.misses                           3696                       # DTB misses
+system.cpu1.itb.accesses                     31301925                       # DTB accesses
+system.cpu1.numCycles                      2631652887                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   30198018                       # Number of instructions committed
-system.cpu1.committedOps                     38446958                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             34771949                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                  5462                       # Number of float alu accesses
-system.cpu1.num_func_calls                    1081332                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      3974549                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    34771949                       # number of integer instructions
-system.cpu1.num_fp_insts                         5462                       # number of float instructions
-system.cpu1.num_int_register_reads          201690852                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          37382680                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads                3860                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes               1604                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                     13782650                       # number of memory refs
-system.cpu1.num_load_insts                    7920272                       # Number of load instructions
-system.cpu1.num_store_insts                   5862378                       # Number of store instructions
-system.cpu1.num_idle_cycles              2292306354.384825                       # Number of idle cycles
-system.cpu1.num_busy_cycles              338930460.615175                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.128810                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.871190                       # Percentage of idle cycles
-system.cpu1.Branches                          5177848                       # Number of branches fetched
+system.cpu1.committedInsts                   30590318                       # Number of instructions committed
+system.cpu1.committedOps                     38894351                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             35148183                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                  5686                       # Number of float alu accesses
+system.cpu1.num_func_calls                    1095318                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      4014750                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    35148183                       # number of integer instructions
+system.cpu1.num_fp_insts                         5686                       # number of float instructions
+system.cpu1.num_int_register_reads          203876321                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          37823170                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads                4205                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes               1482                       # number of times the floating registers were written
+system.cpu1.num_mem_refs                     13931138                       # number of memory refs
+system.cpu1.num_load_insts                    7996929                       # Number of load instructions
+system.cpu1.num_store_insts                   5934209                       # Number of store instructions
+system.cpu1.num_idle_cycles              2293790821.520695                       # Number of idle cycles
+system.cpu1.num_busy_cycles              337862065.479305                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.128384                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.871616                       # Percentage of idle cycles
+system.cpu1.Branches                          5235663                       # Number of branches fetched
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
 system.iocache.tags.replacements                    0                       # number of replacements
@@ -1650,10 +1450,10 @@ system.iocache.avg_blocked_cycles::no_mshrs          nan                       #
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1557250761500                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1557250761500                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1557250761500                       # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1557250761500                       # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1783080197250                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1783080197250                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1783080197250                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1783080197250                       # number of overall MSHR uncacheable cycles
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
index 467207c9e90fb02e700dbdf47e03a5ab32cbcadc..6ae80aee81b33db22660cdcb67029661a4120876 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  5.133933                       # Number of seconds simulated
-sim_ticks                                5133933067000                       # Number of ticks simulated
-final_tick                               5133933067000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  5.137972                       # Number of seconds simulated
+sim_ticks                                5137971999000                       # Number of ticks simulated
+final_tick                               5137971999000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 186687                       # Simulator instruction rate (inst/s)
-host_op_rate                                   369023                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2350538489                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 736008                       # Number of bytes of host memory used
-host_seconds                                  2184.15                       # Real time elapsed on the host
-sim_insts                                   407751929                       # Number of instructions simulated
-sim_ops                                     806002693                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 151274                       # Simulator instruction rate (inst/s)
+host_op_rate                                   299020                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1905679647                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 770140                       # Number of bytes of host memory used
+host_seconds                                  2696.14                       # Real time elapsed on the host
+sim_insts                                   407854776                       # Number of instructions simulated
+sim_ops                                     806198141                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::pc.south_bridge.ide      2437184                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker         3904                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker          320                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           1029376                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          10746496                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             14217280                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      1029376                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1029376                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      9492672                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           9492672                       # Number of bytes written to this memory
-system.physmem.num_reads::pc.south_bridge.ide        38081                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker           61                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker            5                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              16084                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             167914                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                222145                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          148323                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               148323                       # Number of write requests responded to by this memory
-system.physmem.bw_read::pc.south_bridge.ide       474721                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker            760                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker             62                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               200504                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              2093229                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2769276                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          200504                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             200504                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1849006                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1849006                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1849006                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide       474721                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker           760                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker            62                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              200504                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             2093229                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4618282                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        222145                       # Number of read requests accepted
-system.physmem.writeReqs                       148323                       # Number of write requests accepted
-system.physmem.readBursts                      222145                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     148323                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 14211648                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      5632                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   9492416                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  14217280                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                9492672                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                       88                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::pc.south_bridge.ide      2477120                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker         3136                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker          256                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           1034624                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          10750336                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             14265472                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1034624                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1034624                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      9529024                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           9529024                       # Number of bytes written to this memory
+system.physmem.num_reads::pc.south_bridge.ide        38705                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker           49                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker            4                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              16166                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             167974                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                222898                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          148891                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               148891                       # Number of write requests responded to by this memory
+system.physmem.bw_read::pc.south_bridge.ide       482120                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker            610                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker             50                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               201368                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              2092331                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2776479                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          201368                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             201368                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1854627                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1854627                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1854627                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide       482120                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker           610                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker            50                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              201368                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             2092331                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                4631107                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        222898                       # Number of read requests accepted
+system.physmem.writeReqs                       148891                       # Number of write requests accepted
+system.physmem.readBursts                      222898                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     148891                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 14252672                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     12800                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   9527360                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  14265472                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                9529024                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      200                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           1715                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               14970                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               13960                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               14769                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               13764                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               13644                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               13392                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               13407                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               13589                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               13408                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               13258                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              13821                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              13878                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              14332                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              14527                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              13749                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              13589                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               10370                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                9405                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                9871                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                9165                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                9017                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                8953                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                8740                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                8992                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                8721                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                8568                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               9309                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               9216                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               9686                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               9800                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               9415                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               9091                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs           1701                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               14548                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               13887                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               14162                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               13520                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               14300                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               13581                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               13426                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               13413                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               13607                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               13662                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              13602                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              13631                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              14336                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              14588                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              14340                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              14095                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                9881                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                9301                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                9417                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                9104                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                9702                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                8858                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                8862                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                8906                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                8978                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                9056                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               9081                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               9102                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               9605                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               9854                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               9646                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               9512                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           8                       # Number of times write queue was full causing retry
-system.physmem.totGap                    5133933013500                       # Total gap between requests
+system.physmem.numWrRetry                           7                       # Number of times write queue was full causing retry
+system.physmem.totGap                    5137971883500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  222145                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  222898                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 148323                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    174666                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     21456                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      6950                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      2913                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      2112                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      2066                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      1506                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      1520                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      1430                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      1072                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      864                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      755                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      678                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      656                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      606                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      583                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      571                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                      555                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                      538                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                      523                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                       33                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21                        3                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        1                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 148891                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    173419                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     13832                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      4649                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      2839                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      2570                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      4077                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      3447                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      3320                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      2968                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                      1935                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                     1633                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                     1479                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                     1288                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                     1096                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                      836                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                      757                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                      725                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                      696                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                      691                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                      416                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                       25                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
@@ -141,369 +141,239 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                      6022                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                      6256                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                      6299                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                      6341                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                      6448                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                      6596                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                      6608                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                      6666                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                      6998                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                      7022                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                     7020                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                     7083                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                     7644                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                     7121                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                     7236                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     7399                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     7458                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     6317                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     6247                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6188                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6157                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     6233                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                      386                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                      282                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                       69                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                       52                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                       42                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                       36                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                       32                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                       23                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                       20                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                       22                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        68754                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      344.735608                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     150.882581                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev    1084.800437                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64-67          30893     44.93%     44.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-131        10573     15.38%     60.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192-195         6859      9.98%     70.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-259         4406      6.41%     76.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320-323         2663      3.87%     80.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-387         2166      3.15%     83.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448-451         1652      2.40%     86.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-515         1226      1.78%     87.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576-579         1018      1.48%     89.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-643          978      1.42%     90.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704-707          656      0.95%     91.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-771          637      0.93%     92.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832-835          446      0.65%     93.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-899          438      0.64%     93.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960-963          344      0.50%     94.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1027          542      0.79%     95.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088-1091          252      0.37%     95.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152-1155          218      0.32%     95.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216-1219          163      0.24%     96.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280-1283          136      0.20%     96.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344-1347          158      0.23%     96.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408-1411          420      0.61%     97.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472-1475          150      0.22%     97.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536-1539          127      0.18%     97.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600-1603          107      0.16%     97.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664-1667           87      0.13%     97.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1728-1731           59      0.09%     97.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1792-1795           64      0.09%     98.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856-1859           17      0.02%     98.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1920-1923           43      0.06%     98.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984-1987           19      0.03%     98.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2048-2051           31      0.05%     98.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112-2115           20      0.03%     98.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2176-2179           40      0.06%     98.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2240-2243           10      0.01%     98.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2304-2307           13      0.02%     98.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2368-2371           16      0.02%     98.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2432-2435           31      0.05%     98.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2496-2499           10      0.01%     98.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2560-2563            6      0.01%     98.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2624-2627           13      0.02%     98.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2688-2691           31      0.05%     98.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2752-2755           12      0.02%     98.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2816-2819            4      0.01%     98.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2880-2883            6      0.01%     98.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2944-2947           27      0.04%     98.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3008-3011            9      0.01%     98.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3072-3075           12      0.02%     98.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3136-3139            6      0.01%     98.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3200-3203           28      0.04%     98.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3264-3267            6      0.01%     98.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3328-3331            7      0.01%     98.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3392-3395            2      0.00%     98.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3456-3459           25      0.04%     98.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3520-3523            3      0.00%     98.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3584-3587            5      0.01%     98.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3648-3651            5      0.01%     98.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3712-3715           26      0.04%     98.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3776-3779           10      0.01%     98.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3840-3843            5      0.01%     98.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3904-3907            9      0.01%     98.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3968-3971           28      0.04%     98.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4032-4035            4      0.01%     98.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4096-4099           15      0.02%     98.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4160-4163            3      0.00%     98.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4224-4227           27      0.04%     98.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4288-4291            3      0.00%     98.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4352-4355            2      0.00%     98.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4416-4419            2      0.00%     98.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4480-4483           23      0.03%     98.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4544-4547            3      0.00%     98.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4608-4611            2      0.00%     98.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4672-4675            5      0.01%     98.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4736-4739           25      0.04%     99.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4800-4803            4      0.01%     99.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4864-4867            1      0.00%     99.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4992-4995           22      0.03%     99.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5056-5059            2      0.00%     99.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5120-5123            3      0.00%     99.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5184-5187            4      0.01%     99.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5248-5251           26      0.04%     99.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5376-5379            1      0.00%     99.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5440-5443            2      0.00%     99.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5504-5507           22      0.03%     99.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5568-5571            4      0.01%     99.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5696-5699            3      0.00%     99.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5760-5763           24      0.03%     99.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5824-5827            4      0.01%     99.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5888-5891            1      0.00%     99.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5952-5955            1      0.00%     99.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6016-6019           24      0.03%     99.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6080-6083            1      0.00%     99.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6144-6147            1      0.00%     99.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6208-6211            3      0.00%     99.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6272-6275           24      0.03%     99.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6336-6339            3      0.00%     99.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6400-6403            4      0.01%     99.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6464-6467            1      0.00%     99.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6528-6531           23      0.03%     99.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6592-6595            4      0.01%     99.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6656-6659           75      0.11%     99.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6720-6723            3      0.00%     99.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6784-6787            2      0.00%     99.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6848-6851            5      0.01%     99.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6912-6915            5      0.01%     99.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6976-6979            3      0.00%     99.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7040-7043            9      0.01%     99.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7104-7107            2      0.00%     99.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7168-7171           11      0.02%     99.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7232-7235            2      0.00%     99.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7360-7363            1      0.00%     99.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7488-7491            2      0.00%     99.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7552-7555            2      0.00%     99.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7616-7619            2      0.00%     99.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7680-7683            1      0.00%     99.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7744-7747            2      0.00%     99.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7808-7811            3      0.00%     99.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7872-7875            4      0.01%     99.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7936-7939            3      0.00%     99.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8000-8003            1      0.00%     99.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8064-8067            5      0.01%     99.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8128-8131            3      0.00%     99.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8192-8195           15      0.02%     99.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8320-8323            1      0.00%     99.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8384-8387            1      0.00%     99.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8448-8451            1      0.00%     99.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8512-8515            5      0.01%     99.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8640-8643            2      0.00%     99.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8704-8707            2      0.00%     99.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8768-8771            2      0.00%     99.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8832-8835            1      0.00%     99.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8896-8899            1      0.00%     99.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9024-9027            1      0.00%     99.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9152-9155            4      0.01%     99.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9216-9219            5      0.01%     99.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9344-9347            1      0.00%     99.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9472-9475            1      0.00%     99.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9536-9539            4      0.01%     99.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9600-9603            4      0.01%     99.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9664-9667            2      0.00%     99.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9792-9795            2      0.00%     99.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9856-9859            2      0.00%     99.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9920-9923            2      0.00%     99.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9984-9987            3      0.00%     99.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10112-10115            3      0.00%     99.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10304-10307            1      0.00%     99.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10432-10435            1      0.00%     99.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10496-10499            1      0.00%     99.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10560-10563            1      0.00%     99.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10624-10627            1      0.00%     99.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10880-10883            1      0.00%     99.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10944-10947            1      0.00%     99.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11072-11075            1      0.00%     99.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11136-11139            1      0.00%     99.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11200-11203            2      0.00%     99.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11264-11267            1      0.00%     99.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11328-11331            1      0.00%     99.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11392-11395            3      0.00%     99.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11520-11523            3      0.00%     99.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11712-11715            2      0.00%     99.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11904-11907            1      0.00%     99.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12160-12163            2      0.00%     99.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12224-12227            2      0.00%     99.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12416-12419            2      0.00%     99.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12608-12611            1      0.00%     99.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12672-12675            3      0.00%     99.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12736-12739            1      0.00%     99.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12928-12931            2      0.00%     99.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13056-13059            2      0.00%     99.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13184-13187            1      0.00%     99.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13248-13251            2      0.00%     99.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13312-13315            1      0.00%     99.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13632-13635            2      0.00%     99.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13696-13699            3      0.00%     99.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13824-13827            1      0.00%     99.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13888-13891            6      0.01%     99.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13952-13955            5      0.01%     99.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14016-14019            1      0.00%     99.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14080-14083            1      0.00%     99.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14208-14211            2      0.00%     99.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14272-14275            4      0.01%     99.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14400-14403            2      0.00%     99.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14464-14467            1      0.00%     99.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14528-14531            2      0.00%     99.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14592-14595            1      0.00%     99.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14656-14659            2      0.00%     99.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14720-14723            2      0.00%     99.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14784-14787            1      0.00%     99.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14848-14851            1      0.00%     99.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14912-14915           25      0.04%     99.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14976-14979            6      0.01%     99.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15040-15043            8      0.01%     99.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15104-15107            4      0.01%     99.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15168-15171            3      0.00%     99.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15232-15235            8      0.01%     99.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15296-15299            3      0.00%     99.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15360-15363           14      0.02%     99.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15424-15427            1      0.00%     99.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15488-15491            1      0.00%     99.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15552-15555            2      0.00%     99.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15616-15619            2      0.00%     99.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15680-15683            5      0.01%     99.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15744-15747            1      0.00%     99.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15808-15811            4      0.01%     99.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15872-15875            3      0.00%     99.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15936-15939            5      0.01%     99.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16000-16003            1      0.00%     99.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16064-16067            3      0.00%     99.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16128-16131            4      0.01%     99.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16192-16195            2      0.00%     99.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16256-16259           10      0.01%     99.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16320-16323            9      0.01%     99.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16384-16387           42      0.06%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          68754                       # Bytes accessed per row activation
-system.physmem.totQLat                     5103462500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                9310522500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   1110285000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                  3096775000                       # Total ticks spent accessing banks
-system.physmem.avgQLat                       22982.67                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    13945.86                       # Average bank access latency per DRAM burst
+system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     1621                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     1713                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     2212                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     6088                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     6446                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6550                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     6593                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     6786                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     6786                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     6856                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     8981                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     7771                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     7845                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     9165                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     8452                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     8559                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     8587                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     8595                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     2877                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                     2483                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                     2347                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                     2192                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                     2164                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                     2092                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                     1899                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                     1791                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                     1654                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                     1568                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                     1402                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                     1217                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                     1040                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      892                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      750                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      634                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      513                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      450                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      352                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      284                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      218                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      132                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       92                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       64                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       49                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       35                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       21                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       18                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       13                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       13                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       14                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        49868                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      381.994064                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     221.175651                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     374.202346                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          15813     31.71%     31.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        11064     22.19%     53.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5080     10.19%     64.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2824      5.66%     69.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         1980      3.97%     73.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1284      2.57%     76.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          922      1.85%     78.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          716      1.44%     79.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        10185     20.42%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          49868                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          8142                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        27.350037                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      531.765782                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           8141     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::47104-49151            1      0.01%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            8142                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          8142                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        18.283591                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.627324                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        6.611364                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-17            6056     74.38%     74.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18-19            1276     15.67%     90.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-21             101      1.24%     91.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22-23              41      0.50%     91.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-25              52      0.64%     92.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26-27              70      0.86%     93.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-29              65      0.80%     94.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30-31              71      0.87%     94.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-33              51      0.63%     95.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::34-35              44      0.54%     96.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-37              56      0.69%     96.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::38-39              33      0.41%     97.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-41              34      0.42%     97.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::42-43              29      0.36%     98.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-45              35      0.43%     98.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::46-47              23      0.28%     98.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-49              19      0.23%     98.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::50-51              12      0.15%     99.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-53              12      0.15%     99.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::54-55               9      0.11%     99.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-57               6      0.07%     99.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::58-59               7      0.09%     99.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-61               2      0.02%     99.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::62-63              13      0.16%     99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-65              13      0.16%     99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::66-67               1      0.01%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::70-71               1      0.01%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-73               4      0.05%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::74-75               3      0.04%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-77               2      0.02%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-81               1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            8142                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     5275412250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                9510468500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1113490000                       # Total ticks spent in databus transfers
+system.physmem.totBankLat                  3121566250                       # Total ticks spent accessing banks
+system.physmem.avgQLat                       23688.64                       # Average queueing delay per DRAM burst
+system.physmem.avgBankLat                    14017.04                       # Average bank access latency per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  41928.53                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  42705.68                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           2.77                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           1.85                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        2.77                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        2.78                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        1.85                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.04                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         0.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                         8.57                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     193293                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    108329                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   87.05                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  73.04                       # Row buffer hit rate for writes
-system.physmem.avgGap                     13857966.18                       # Average gap between requests
-system.physmem.pageHitRate                      81.44                       # Row buffer hit rate, read and write combined
+system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        24.02                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     186969                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    110725                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   83.96                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  74.37                       # Row buffer hit rate for writes
+system.physmem.avgGap                     13819590.91                       # Average gap between requests
+system.physmem.pageHitRate                      80.11                       # Row buffer hit rate, read and write combined
 system.physmem.prechargeAllPercent               0.14                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                      5095991                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq              662317                       # Transaction distribution
-system.membus.trans_dist::ReadResp             662311                       # Transaction distribution
-system.membus.trans_dist::WriteReq              13762                       # Transaction distribution
-system.membus.trans_dist::WriteResp             13762                       # Transaction distribution
-system.membus.trans_dist::Writeback            148323                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             2201                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            1734                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            179351                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           179346                       # Transaction distribution
-system.membus.trans_dist::MessageReq             1642                       # Transaction distribution
-system.membus.trans_dist::MessageResp            1642                       # Transaction distribution
-system.membus.trans_dist::BadAddressError            6                       # Transaction distribution
-system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave         3284                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.apicbridge.master::total         3284                       # Packet count per connected master and slave (bytes)
+system.membus.throughput                      5100645                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq              662331                       # Transaction distribution
+system.membus.trans_dist::ReadResp             662323                       # Transaction distribution
+system.membus.trans_dist::WriteReq              13764                       # Transaction distribution
+system.membus.trans_dist::WriteResp             13764                       # Transaction distribution
+system.membus.trans_dist::Writeback            148891                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             2168                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            1718                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            179464                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           179461                       # Transaction distribution
+system.membus.trans_dist::MessageReq             1643                       # Transaction distribution
+system.membus.trans_dist::MessageResp            1643                       # Transaction distribution
+system.membus.trans_dist::BadAddressError            8                       # Transaction distribution
+system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave         3286                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.apicbridge.master::total         3286                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       471038                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio       775072                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       474374                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio           12                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1720496                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       132379                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       132379                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1856159                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6568                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.apicbridge.master::total         6568                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio       775076                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       475146                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio           16                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1721276                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       133006                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       133006                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1857568                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6572                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.apicbridge.master::total         6572                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       241802                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      1550141                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     18286080                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     20078023                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      5423872                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::total      5423872                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            25508463                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus               25508463                       # Total data (bytes)
-system.membus.snoop_data_through_bus           654016                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy           250556000                       # Layer occupancy (ticks)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      1550149                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     18330624                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     20122575                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      5463872                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::total      5463872                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total            25593019                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               25593019                       # Total data (bytes)
+system.membus.snoop_data_through_bus           613952                       # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy           250521000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy           583258500                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy           583253500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             3284000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             3286000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer3.occupancy          1605908499                       # Layer occupancy (ticks)
+system.membus.reqLayer3.occupancy          1611616249                       # Layer occupancy (ticks)
 system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer4.occupancy                8000                       # Layer occupancy (ticks)
+system.membus.reqLayer4.occupancy               10500                       # Layer occupancy (ticks)
 system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer0.occupancy            1642000                       # Layer occupancy (ticks)
+system.membus.respLayer0.occupancy            1643000                       # Layer occupancy (ticks)
 system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         3150989153                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         3152435901                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.1                       # Layer utilization (%)
-system.membus.respLayer4.occupancy          429464748                       # Layer occupancy (ticks)
+system.membus.respLayer4.occupancy          429736248                       # Layer occupancy (ticks)
 system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
-system.iocache.tags.replacements                47576                       # number of replacements
-system.iocache.tags.tagsinuse                0.103980                       # Cycle average of tags in use
+system.iocache.tags.replacements                47579                       # number of replacements
+system.iocache.tags.tagsinuse                0.116331                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                47592                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs                47595                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         4992951939000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.103980                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::pc.south_bridge.ide     0.006499                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.006499                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         4992993838000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.116331                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::pc.south_bridge.ide     0.007271                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.007271                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               428679                       # Number of tag accesses
-system.iocache.tags.data_accesses              428679                       # Number of data accesses
-system.iocache.ReadReq_misses::pc.south_bridge.ide          911                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              911                       # number of ReadReq misses
+system.iocache.tags.tag_accesses               428697                       # Number of tag accesses
+system.iocache.tags.data_accesses              428697                       # Number of data accesses
+system.iocache.ReadReq_misses::pc.south_bridge.ide          913                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              913                       # number of ReadReq misses
 system.iocache.WriteReq_misses::pc.south_bridge.ide        46720                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total           46720                       # number of WriteReq misses
-system.iocache.demand_misses::pc.south_bridge.ide        47631                       # number of demand (read+write) misses
-system.iocache.demand_misses::total             47631                       # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide        47631                       # number of overall misses
-system.iocache.overall_misses::total            47631                       # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    151022435                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total    151022435                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::pc.south_bridge.ide  11480088301                       # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total  11480088301                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide  11631110736                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total  11631110736                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide  11631110736                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total  11631110736                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide          911                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            911                       # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::pc.south_bridge.ide        47633                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             47633                       # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide        47633                       # number of overall misses
+system.iocache.overall_misses::total            47633                       # number of overall misses
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    149265435                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total    149265435                       # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::pc.south_bridge.ide  11474717915                       # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total  11474717915                       # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide  11623983350                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total  11623983350                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide  11623983350                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total  11623983350                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::pc.south_bridge.ide          913                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            913                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::pc.south_bridge.ide        46720                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total         46720                       # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide        47631                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           47631                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide        47631                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          47631                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::pc.south_bridge.ide        47633                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           47633                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide        47633                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          47633                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteReq accesses
@@ -512,40 +382,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 165776.547750                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 165776.547750                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 245721.068086                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 245721.068086                       # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 244192.033256                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 244192.033256                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 244192.033256                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 244192.033256                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs        172788                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 163488.975904                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 163488.975904                       # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 245606.119756                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 245606.119756                       # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 244032.148930                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 244032.148930                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 244032.148930                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 244032.148930                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs        177888                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                10383                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                14382                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs    16.641433                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs    12.368794                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks           46667                       # number of writebacks
-system.iocache.writebacks::total                46667                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          911                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          911                       # number of ReadReq MSHR misses
+system.iocache.writebacks::writebacks           46668                       # number of writebacks
+system.iocache.writebacks::total                46668                       # number of writebacks
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          913                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          913                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total        46720                       # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide        47631                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total        47631                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide        47631                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total        47631                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide    103624935                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total    103624935                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide   9049102305                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total   9049102305                       # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide   9152727240                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   9152727240                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide   9152727240                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   9152727240                       # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::pc.south_bridge.ide        47633                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total        47633                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide        47633                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total        47633                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide    101762935                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total    101762935                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide   9043225919                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total   9043225919                       # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide   9144988854                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   9144988854                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide   9144988854                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   9144988854                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteReq accesses
@@ -554,14 +424,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 113748.556531                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 113748.556531                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 193687.977419                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 193687.977419                       # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 192159.040121                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 192159.040121                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 192159.040121                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 192159.040121                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 111459.950712                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 111459.950712                       # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 193562.198609                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 193562.198609                       # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 191988.513300                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 191988.513300                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 191988.513300                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 191988.513300                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
@@ -575,13 +445,13 @@ system.pc.south_bridge.ide.disks1.dma_read_txs            0
 system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
-system.iobus.throughput                        638147                       # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq               225559                       # Transaction distribution
-system.iobus.trans_dist::ReadResp              225559                       # Transaction distribution
+system.iobus.throughput                        637649                       # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq               225561                       # Transaction distribution
+system.iobus.trans_dist::ReadResp              225561                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               57591                       # Transaction distribution
 system.iobus.trans_dist::WriteResp              57591                       # Transaction distribution
-system.iobus.trans_dist::MessageReq              1642                       # Transaction distribution
-system.iobus.trans_dist::MessageResp             1642                       # Transaction distribution
+system.iobus.trans_dist::MessageReq              1643                       # Transaction distribution
+system.iobus.trans_dist::MessageResp             1643                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           44                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11134                       # Packet count per connected master and slave (bytes)
@@ -601,11 +471,11 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio
 system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio         2128                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       471038                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95262                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95262                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3284                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3284                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  569584                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95266                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95266                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3286                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3286                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  569590                       # Packet count per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6712                       # Cumulative packet size per connected master and slave (bytes)
@@ -625,13 +495,13 @@ system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio
 system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio         4256                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::total       241802                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027832                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total      3027832                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6568                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total         6568                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total              3276202                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus                 3276202                       # Total data (bytes)
-system.iobus.reqLayer0.occupancy              3916600                       # Layer occupancy (ticks)
+system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027848                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total      3027848                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6572                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total         6572                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::total              3276222                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus                 3276222                       # Total data (bytes)
+system.iobus.reqLayer0.occupancy              3918904                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                34000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
@@ -667,155 +537,155 @@ system.iobus.reqLayer16.occupancy                9000                       # La
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer18.occupancy           424364988                       # Layer occupancy (ticks)
+system.iobus.reqLayer18.occupancy           425268102                       # Layer occupancy (ticks)
 system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer19.occupancy             1064000                       # Layer occupancy (ticks)
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy           460167000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            53080252                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            53403752                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer2.occupancy             1642000                       # Layer occupancy (ticks)
+system.iobus.respLayer2.occupancy             1643000                       # Layer occupancy (ticks)
 system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                85602749                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          85602749                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            882967                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             79146839                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                77528417                       # Number of BTB hits
+system.cpu.branchPred.lookups                85606951                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          85606951                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            878900                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             79252981                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                77536604                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             97.955165                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1444593                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect             180696                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             97.834306                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1442152                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             179942                       # Number of incorrect RAS predictions.
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
-system.cpu.numCycles                        453810576                       # number of cpu cycles simulated
+system.cpu.numCycles                        453123649                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           25587128                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      422793434                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    85602749                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           78973010                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     162653475                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 3995125                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                     108453                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles               71359520                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                43835                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles         87857                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles          286                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                   8489508                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                384110                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                    2391                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          262908725                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              3.175877                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.411274                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           25513299                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      422793316                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    85606951                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           78978756                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     162666775                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 3977899                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                     109317                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles               70887668                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                43514                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles         89257                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles          186                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                   8479758                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                384207                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                    2414                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          262364646                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              3.182537                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.411732                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                100670178     38.29%     38.29% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  1530444      0.58%     38.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 71820335     27.32%     66.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                   896426      0.34%     66.53% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  1566584      0.60%     67.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  2396730      0.91%     68.04% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  1019321      0.39%     68.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1330214      0.51%     68.93% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 81678493     31.07%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                100112047     38.16%     38.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  1537808      0.59%     38.74% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 71834602     27.38%     66.12% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                   894624      0.34%     66.46% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  1560586      0.59%     67.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  2393199      0.91%     67.97% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  1018516      0.39%     68.36% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1331320      0.51%     68.87% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 81681944     31.13%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            262908725                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.188631                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.931652                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 29469022                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              68533895                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 158500921                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               3336716                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                3068171                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts              832628882                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                  1005                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                3068171                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 32166033                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                43333689                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       12473461                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 158788115                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              13079256                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              829706187                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                 21464                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                6056720                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               5143219                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands           991368832                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            1800529447                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1106981108                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups               114                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             963921381                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 27447449                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts             454679                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts         459073                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  29562257                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             16738170                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores             9831898                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1099509                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores           931888                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  824922108                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             1185282                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 820965230                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            150616                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        19266581                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     29327510                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         130776                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     262908725                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         3.122625                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.401229                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            262364646                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.188926                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.933064                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 29407134                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              68048451                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 158512522                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               3341909                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                3054630                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts              832669874                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                   887                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                3054630                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 32105381                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                42832622                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       12466754                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 158806940                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              13098319                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              829768905                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                 20738                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                6073581                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               5148249                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands           991466417                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1800660067                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1107048961                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups               106                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             964157062                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 27309353                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts             454429                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts         460129                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  29597584                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             16731616                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores             9822119                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1090956                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores           912656                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  824999655                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             1185445                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 821065367                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            147374                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        19153823                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     29264539                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         130709                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     262364646                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         3.129482                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.399412                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            76541753     29.11%     29.11% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            15760378      5.99%     35.11% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            10546081      4.01%     39.12% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             7369618      2.80%     41.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            75729447     28.80%     70.73% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             3748882      1.43%     72.15% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            72293205     27.50%     99.65% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              772480      0.29%     99.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              146881      0.06%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            75980319     28.96%     28.96% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            15750588      6.00%     34.96% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            10556494      4.02%     38.99% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             7365908      2.81%     41.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            75746368     28.87%     70.66% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             3736962      1.42%     72.09% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            72307682     27.56%     99.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              774907      0.30%     99.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              145418      0.06%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       262908725                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       262364646                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  349560     33.18%     33.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                    241      0.02%     33.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                    1967      0.19%     33.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     33.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     33.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     33.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     33.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     33.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     33.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     33.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     33.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     33.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     33.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     33.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     33.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     33.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     33.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     33.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     33.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     33.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     33.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     33.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     33.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     33.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     33.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     33.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     33.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     33.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     33.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                 548780     52.08%     85.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                153094     14.53%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  352804     33.38%     33.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                    241      0.02%     33.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                     895      0.08%     33.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     33.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     33.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     33.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     33.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     33.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     33.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     33.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     33.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     33.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     33.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     33.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     33.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     33.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     33.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     33.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     33.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     33.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     33.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     33.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     33.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     33.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     33.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     33.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     33.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     33.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     33.49% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 548620     51.91%     85.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                154313     14.60%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass            307236      0.04%      0.04% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             793474466     96.65%     96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               149866      0.02%     96.71% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                124488      0.02%     96.72% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass            307554      0.04%      0.04% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             793584898     96.65%     96.69% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               150109      0.02%     96.71% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                124066      0.02%     96.72% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     96.72% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     96.72% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     96.72% # Type of FU issued
@@ -842,297 +712,297 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     96.72% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     96.72% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.72% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     96.72% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             17682042      2.15%     98.88% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             9227132      1.12%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             17676623      2.15%     98.88% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             9222117      1.12%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              820965230                       # Type of FU issued
-system.cpu.iq.rate                           1.809048                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     1053642                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.001283                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         1906151693                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         845384400                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    817050943                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 198                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                210                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses           54                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              821711543                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                      93                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          1694469                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              821065367                       # Type of FU issued
+system.cpu.iq.rate                           1.812012                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     1056873                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.001287                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         1905808819                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         845349453                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    817155578                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 173                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                180                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses           48                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              821814606                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                      80                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1693534                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      2748093                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        19141                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        11819                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      1409863                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      2731831                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        17734                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        12108                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      1395931                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads      1931395                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked         11998                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads      1932011                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked         12232                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                3068171                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                31463417                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               2151711                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           826107390                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            248376                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              16738170                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts              9831898                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts             690155                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                1620159                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 12279                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          11819                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         498534                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       508074                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1006608                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             819554351                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              17378079                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           1410878                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                3054630                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                30960729                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               2157350                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           826185100                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            241589                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              16731616                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts              9822119                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts             690497                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                1620390                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 12858                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          12108                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         495281                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       506440                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              1001721                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             819661058                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              17373288                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1404308                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                     26421028                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 83090233                       # Number of branches executed
-system.cpu.iew.exec_stores                    9042949                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.805939                       # Inst execution rate
-system.cpu.iew.wb_sent                      819150966                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     817050997                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 638575855                       # num instructions producing a value
-system.cpu.iew.wb_consumers                1043882621                       # num instructions consuming a value
+system.cpu.iew.exec_refs                     26412112                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 83101028                       # Number of branches executed
+system.cpu.iew.exec_stores                    9038824                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.808913                       # Inst execution rate
+system.cpu.iew.wb_sent                      819257147                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     817155626                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 638657480                       # num instructions producing a value
+system.cpu.iew.wb_consumers                1044041746                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.800423                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.611731                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.803383                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.611716                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        19994665                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls         1054506                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            892807                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    259840554                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     3.101913                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.863847                       # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts        19877862                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         1054736                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            888910                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    259310016                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     3.109013                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.863250                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     88304488     33.98%     33.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     11858711      4.56%     38.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      3833949      1.48%     40.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     74748511     28.77%     68.79% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      2384583      0.92%     69.71% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1475819      0.57%     70.28% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       859128      0.33%     70.61% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     70844564     27.26%     97.87% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      5530801      2.13%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     87730314     33.83%     33.83% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     11862694      4.57%     38.41% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      3835821      1.48%     39.89% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     74768182     28.83%     68.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      2381229      0.92%     69.64% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1479438      0.57%     70.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       861979      0.33%     70.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     70857593     27.33%     97.87% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      5532766      2.13%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    259840554                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            407751929                       # Number of instructions committed
-system.cpu.commit.committedOps              806002693                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    259310016                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            407854776                       # Number of instructions committed
+system.cpu.commit.committedOps              806198141                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       22412111                       # Number of memory references committed
-system.cpu.commit.loads                      13990076                       # Number of loads committed
-system.cpu.commit.membars                      474663                       # Number of memory barriers committed
-system.cpu.commit.branches                   82157264                       # Number of branches committed
+system.cpu.commit.refs                       22425972                       # Number of memory references committed
+system.cpu.commit.loads                      13999784                       # Number of loads committed
+system.cpu.commit.membars                      474669                       # Number of memory barriers committed
+system.cpu.commit.branches                   82177261                       # Number of branches committed
 system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 734852381                       # Number of committed integer instructions.
-system.cpu.commit.function_calls              1155163                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events               5530801                       # number cycles where commit BW limit reached
+system.cpu.commit.int_insts                 735033306                       # Number of committed integer instructions.
+system.cpu.commit.function_calls              1155486                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events               5532766                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   1080228878                       # The number of ROB reads
-system.cpu.rob.rob_writes                  1655077473                       # The number of ROB writes
-system.cpu.timesIdled                         1260592                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                       190901851                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   9814061063                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                   407751929                       # Number of Instructions Simulated
-system.cpu.committedOps                     806002693                       # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total             407751929                       # Number of Instructions Simulated
-system.cpu.cpi                               1.112958                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.112958                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.898507                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.898507                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               1088763208                       # number of integer regfile reads
-system.cpu.int_regfile_writes               653821136                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                        54                       # number of floating regfile reads
-system.cpu.cc_regfile_reads                 415622850                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                321492626                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               264082516                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                 402300                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput                53661983                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq        3016761                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       3016231                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq         13762                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp        13762                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      1581663                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2241                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2241                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       334732                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       288041                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::BadAddressError            6                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1916491                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6123200                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        19443                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       154439                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           8213573                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     61324288                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    207594695                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       616960                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side      5463872                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      274999815                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus         274973191                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus       523840                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy     4039348922                       # Layer occupancy (ticks)
+system.cpu.rob.rob_reads                   1079774887                       # The number of ROB reads
+system.cpu.rob.rob_writes                  1655221365                       # The number of ROB writes
+system.cpu.timesIdled                         1257777                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                       190759003                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   9822826051                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                   407854776                       # Number of Instructions Simulated
+system.cpu.committedOps                     806198141                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total             407854776                       # Number of Instructions Simulated
+system.cpu.cpi                               1.110993                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.110993                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.900096                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.900096                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               1088904390                       # number of integer regfile reads
+system.cpu.int_regfile_writes               653903158                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                        48                       # number of floating regfile reads
+system.cpu.cc_regfile_reads                 415697548                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                321557341                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               264102486                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                 402568                       # number of misc regfile writes
+system.cpu.toL2Bus.throughput                53587278                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq        3014875                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       3014340                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq         13764                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp        13764                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      1579042                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2208                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2208                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       336648                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       289942                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::BadAddressError            8                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1911181                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6131826                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        18757                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       150026                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           8211790                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     61153920                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    207959183                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       582080                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side      5191488                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      274886671                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         274861071                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus       468864                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy     4035423910                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy       624000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy       600000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    1440815600                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    1436807344                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    3139539816                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    3142634309                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy      14707994                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy      14495745                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy     103656142                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy     103414152                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu.icache.tags.replacements            957724                       # number of replacements
-system.cpu.icache.tags.tagsinuse           509.254964                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs             7477774                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            958236                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              7.803687                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle      147611306250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   509.254964                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.994639                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.994639                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements            955079                       # number of replacements
+system.cpu.icache.tags.tagsinuse           509.954947                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs             7470392                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            955591                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs              7.817562                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle      147668859250                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   509.954947                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.996006                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.996006                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          101                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          215                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          196                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           95                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          242                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          175                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses           9447804                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses          9447804                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst      7477774                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total         7477774                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst       7477774                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total          7477774                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst      7477774                       # number of overall hits
-system.cpu.icache.overall_hits::total         7477774                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1011731                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1011731                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1011731                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1011731                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1011731                       # number of overall misses
-system.cpu.icache.overall_misses::total       1011731                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  14180716030                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  14180716030                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  14180716030                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  14180716030                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  14180716030                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  14180716030                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst      8489505                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total      8489505                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst      8489505                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total      8489505                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst      8489505                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total      8489505                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.119174                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.119174                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.119174                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.119174                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.119174                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.119174                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14016.290921                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 14016.290921                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 14016.290921                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 14016.290921                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 14016.290921                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 14016.290921                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         5333                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses           9435405                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses          9435405                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst      7470392                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total         7470392                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst       7470392                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total          7470392                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst      7470392                       # number of overall hits
+system.cpu.icache.overall_hits::total         7470392                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1009362                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1009362                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1009362                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1009362                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1009362                       # number of overall misses
+system.cpu.icache.overall_misses::total       1009362                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  14063763284                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  14063763284                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  14063763284                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  14063763284                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  14063763284                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  14063763284                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst      8479754                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total      8479754                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst      8479754                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total      8479754                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst      8479754                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total      8479754                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.119032                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.119032                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.119032                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.119032                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.119032                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.119032                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13933.319546                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13933.319546                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13933.319546                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13933.319546                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13933.319546                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13933.319546                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         4512                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               185                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               173                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    28.827027                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    26.080925                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        53432                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        53432                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        53432                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        53432                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        53432                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        53432                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       958299                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       958299                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       958299                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       958299                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       958299                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       958299                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  11693776143                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  11693776143                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  11693776143                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  11693776143                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  11693776143                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  11693776143                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.112880                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.112880                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.112880                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.112880                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.112880                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.112880                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12202.638365                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12202.638365                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12202.638365                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12202.638365                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12202.638365                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12202.638365                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        53711                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        53711                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        53711                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        53711                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        53711                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        53711                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       955651                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       955651                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       955651                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       955651                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       955651                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       955651                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  11613116903                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  11613116903                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  11613116903                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  11613116903                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  11613116903                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  11613116903                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.112698                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.112698                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.112698                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.112698                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.112698                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.112698                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12152.048083                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12152.048083                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12152.048083                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 12152.048083                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12152.048083                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 12152.048083                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.itb_walker_cache.tags.replacements         8926                       # number of replacements
-system.cpu.itb_walker_cache.tags.tagsinuse     6.004704                       # Cycle average of tags in use
-system.cpu.itb_walker_cache.tags.total_refs        20407                       # Total number of references to valid blocks.
-system.cpu.itb_walker_cache.tags.sampled_refs         8940                       # Sample count of references to valid blocks.
-system.cpu.itb_walker_cache.tags.avg_refs     2.282662                       # Average number of references to valid blocks.
-system.cpu.itb_walker_cache.tags.warmup_cycle 5105549292500                       # Cycle when the warmup percentage was hit.
-system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     6.004704                       # Average occupied blocks per requestor
-system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.375294                       # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.tags.occ_percent::total     0.375294                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.tags.replacements         8788                       # number of replacements
+system.cpu.itb_walker_cache.tags.tagsinuse     5.050842                       # Cycle average of tags in use
+system.cpu.itb_walker_cache.tags.total_refs        20362                       # Total number of references to valid blocks.
+system.cpu.itb_walker_cache.tags.sampled_refs         8802                       # Sample count of references to valid blocks.
+system.cpu.itb_walker_cache.tags.avg_refs     2.313338                       # Average number of references to valid blocks.
+system.cpu.itb_walker_cache.tags.warmup_cycle 5105053160000                       # Cycle when the warmup percentage was hit.
+system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     5.050842                       # Average occupied blocks per requestor
+system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.315678                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.tags.occ_percent::total     0.315678                       # Average percentage of cache occupancy
 system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024           14                       # Occupied blocks per task id
 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0            6                       # Occupied blocks per task id
 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1            2                       # Occupied blocks per task id
 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2            6                       # Occupied blocks per task id
 system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024     0.875000                       # Percentage of cache occupancy per task id
-system.cpu.itb_walker_cache.tags.tag_accesses        70243                       # Number of tag accesses
-system.cpu.itb_walker_cache.tags.data_accesses        70243                       # Number of data accesses
-system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        20415                       # number of ReadReq hits
-system.cpu.itb_walker_cache.ReadReq_hits::total        20415                       # number of ReadReq hits
+system.cpu.itb_walker_cache.tags.tag_accesses        69716                       # Number of tag accesses
+system.cpu.itb_walker_cache.tags.data_accesses        69716                       # Number of data accesses
+system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        20363                       # number of ReadReq hits
+system.cpu.itb_walker_cache.ReadReq_hits::total        20363                       # number of ReadReq hits
 system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            2                       # number of WriteReq hits
 system.cpu.itb_walker_cache.WriteReq_hits::total            2                       # number of WriteReq hits
-system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker        20417                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.demand_hits::total        20417                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker        20417                       # number of overall hits
-system.cpu.itb_walker_cache.overall_hits::total        20417                       # number of overall hits
-system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker         9803                       # number of ReadReq misses
-system.cpu.itb_walker_cache.ReadReq_misses::total         9803                       # number of ReadReq misses
-system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker         9803                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.demand_misses::total         9803                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker         9803                       # number of overall misses
-system.cpu.itb_walker_cache.overall_misses::total         9803                       # number of overall misses
-system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker    109186247                       # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.ReadReq_miss_latency::total    109186247                       # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker    109186247                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::total    109186247                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker    109186247                       # number of overall miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::total    109186247                       # number of overall miss cycles
-system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        30218                       # number of ReadReq accesses(hits+misses)
-system.cpu.itb_walker_cache.ReadReq_accesses::total        30218                       # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker        20365                       # number of demand (read+write) hits
+system.cpu.itb_walker_cache.demand_hits::total        20365                       # number of demand (read+write) hits
+system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker        20365                       # number of overall hits
+system.cpu.itb_walker_cache.overall_hits::total        20365                       # number of overall hits
+system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker         9662                       # number of ReadReq misses
+system.cpu.itb_walker_cache.ReadReq_misses::total         9662                       # number of ReadReq misses
+system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker         9662                       # number of demand (read+write) misses
+system.cpu.itb_walker_cache.demand_misses::total         9662                       # number of demand (read+write) misses
+system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker         9662                       # number of overall misses
+system.cpu.itb_walker_cache.overall_misses::total         9662                       # number of overall misses
+system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker    109674498                       # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.ReadReq_miss_latency::total    109674498                       # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker    109674498                       # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::total    109674498                       # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker    109674498                       # number of overall miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::total    109674498                       # number of overall miss cycles
+system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        30025                       # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.ReadReq_accesses::total        30025                       # number of ReadReq accesses(hits+misses)
 system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            2                       # number of WriteReq accesses(hits+misses)
 system.cpu.itb_walker_cache.WriteReq_accesses::total            2                       # number of WriteReq accesses(hits+misses)
-system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        30220                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.demand_accesses::total        30220                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        30220                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::total        30220                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.324409                       # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.324409                       # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.324388                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_miss_rate::total     0.324388                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.324388                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_miss_rate::total     0.324388                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11138.044170                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11138.044170                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11138.044170                       # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11138.044170                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11138.044170                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11138.044170                       # average overall miss latency
+system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        30027                       # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.demand_accesses::total        30027                       # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        30027                       # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::total        30027                       # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.321799                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.321799                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.321777                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_miss_rate::total     0.321777                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.321777                       # miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_miss_rate::total     0.321777                       # miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11351.117574                       # average ReadReq miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11351.117574                       # average ReadReq miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11351.117574                       # average overall miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11351.117574                       # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11351.117574                       # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11351.117574                       # average overall miss latency
 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -1141,85 +1011,85 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.itb_walker_cache.writebacks::writebacks         1993                       # number of writebacks
-system.cpu.itb_walker_cache.writebacks::total         1993                       # number of writebacks
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker         9803                       # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::total         9803                       # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker         9803                       # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::total         9803                       # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker         9803                       # number of overall MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::total         9803                       # number of overall MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker     89573259                       # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total     89573259                       # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker     89573259                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::total     89573259                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker     89573259                       # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::total     89573259                       # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.324409                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.324409                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.324388                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.324388                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.324388                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.324388                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  9137.331327                       # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total  9137.331327                       # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  9137.331327                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  9137.331327                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  9137.331327                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  9137.331327                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.writebacks::writebacks         1311                       # number of writebacks
+system.cpu.itb_walker_cache.writebacks::total         1311                       # number of writebacks
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker         9662                       # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::total         9662                       # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker         9662                       # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::total         9662                       # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker         9662                       # number of overall MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::total         9662                       # number of overall MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker     90345008                       # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total     90345008                       # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker     90345008                       # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::total     90345008                       # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker     90345008                       # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::total     90345008                       # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.321799                       # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.321799                       # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.321777                       # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.321777                       # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.321777                       # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.321777                       # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  9350.549369                       # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total  9350.549369                       # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  9350.549369                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  9350.549369                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  9350.549369                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  9350.549369                       # average overall mshr miss latency
 system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.dtb_walker_cache.tags.replacements        68011                       # number of replacements
-system.cpu.dtb_walker_cache.tags.tagsinuse    14.842846                       # Cycle average of tags in use
-system.cpu.dtb_walker_cache.tags.total_refs        91726                       # Total number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.sampled_refs        68027                       # Sample count of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.avg_refs     1.348376                       # Average number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.warmup_cycle 4994240386000                       # Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker    14.842846                       # Average occupied blocks per requestor
-system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.927678                       # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.tags.occ_percent::total     0.927678                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.tags.replacements        67950                       # number of replacements
+system.cpu.dtb_walker_cache.tags.tagsinuse    13.831671                       # Cycle average of tags in use
+system.cpu.dtb_walker_cache.tags.total_refs        92323                       # Total number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.sampled_refs        67966                       # Sample count of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.avg_refs     1.358370                       # Average number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.warmup_cycle 5101646178000                       # Cycle when the warmup percentage was hit.
+system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker    13.831671                       # Average occupied blocks per requestor
+system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.864479                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.tags.occ_percent::total     0.864479                       # Average percentage of cache occupancy
 system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024           16                       # Occupied blocks per task id
 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0            6                       # Occupied blocks per task id
 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            7                       # Occupied blocks per task id
 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2            3                       # Occupied blocks per task id
 system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dtb_walker_cache.tags.tag_accesses       390650                       # Number of tag accesses
-system.cpu.dtb_walker_cache.tags.data_accesses       390650                       # Number of data accesses
-system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker        91726                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.ReadReq_hits::total        91726                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker        91726                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::total        91726                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker        91726                       # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::total        91726                       # number of overall hits
-system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker        69066                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.ReadReq_misses::total        69066                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker        69066                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_misses::total        69066                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker        69066                       # number of overall misses
-system.cpu.dtb_walker_cache.overall_misses::total        69066                       # number of overall misses
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker    860977213                       # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::total    860977213                       # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker    860977213                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::total    860977213                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker    860977213                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::total    860977213                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker       160792                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.ReadReq_accesses::total       160792                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker       160792                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::total       160792                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       160792                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::total       160792                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.429536                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.429536                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.429536                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::total     0.429536                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.429536                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::total     0.429536                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12466.006617                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12466.006617                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12466.006617                       # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12466.006617                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12466.006617                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12466.006617                       # average overall miss latency
+system.cpu.dtb_walker_cache.tags.tag_accesses       391373                       # Number of tag accesses
+system.cpu.dtb_walker_cache.tags.data_accesses       391373                       # Number of data accesses
+system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker        92323                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.ReadReq_hits::total        92323                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker        92323                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.demand_hits::total        92323                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker        92323                       # number of overall hits
+system.cpu.dtb_walker_cache.overall_hits::total        92323                       # number of overall hits
+system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker        68909                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.ReadReq_misses::total        68909                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker        68909                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.demand_misses::total        68909                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker        68909                       # number of overall misses
+system.cpu.dtb_walker_cache.overall_misses::total        68909                       # number of overall misses
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker    862549215                       # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::total    862549215                       # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker    862549215                       # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::total    862549215                       # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker    862549215                       # number of overall miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::total    862549215                       # number of overall miss cycles
+system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker       161232                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.ReadReq_accesses::total       161232                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker       161232                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.demand_accesses::total       161232                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       161232                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::total       161232                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.427390                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.427390                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.427390                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::total     0.427390                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.427390                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::total     0.427390                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12517.221481                       # average ReadReq miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12517.221481                       # average ReadReq miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12517.221481                       # average overall miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12517.221481                       # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12517.221481                       # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12517.221481                       # average overall miss latency
 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -1228,153 +1098,153 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.dtb_walker_cache.writebacks::writebacks        21216                       # number of writebacks
-system.cpu.dtb_walker_cache.writebacks::total        21216                       # number of writebacks
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker        69066                       # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total        69066                       # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker        69066                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::total        69066                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker        69066                       # number of overall MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::total        69066                       # number of overall MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    722730929                       # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total    722730929                       # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker    722730929                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total    722730929                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker    722730929                       # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total    722730929                       # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.429536                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.429536                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.429536                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.429536                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.429536                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.429536                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10464.351910                       # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10464.351910                       # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10464.351910                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10464.351910                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10464.351910                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10464.351910                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.writebacks::writebacks        16529                       # number of writebacks
+system.cpu.dtb_walker_cache.writebacks::total        16529                       # number of writebacks
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker        68909                       # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total        68909                       # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker        68909                       # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::total        68909                       # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker        68909                       # number of overall MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::total        68909                       # number of overall MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    724629911                       # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total    724629911                       # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker    724629911                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total    724629911                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker    724629911                       # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total    724629911                       # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.427390                       # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.427390                       # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.427390                       # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.427390                       # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.427390                       # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.427390                       # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10515.751368                       # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10515.751368                       # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10515.751368                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10515.751368                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10515.751368                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10515.751368                       # average overall mshr miss latency
 system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements           1656829                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.997280                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            18997986                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1657341                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             11.462931                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle          39724250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.997280                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999995                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999995                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements           1659840                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.996448                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            18992605                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1660352                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             11.438903                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle          40084250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.996448                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999993                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999993                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          188                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          309                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           15                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          189                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          306                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           17                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          87846935                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         87846935                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     10898836                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        10898836                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      8096443                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        8096443                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      18995279                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         18995279                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     18995279                       # number of overall hits
-system.cpu.dcache.overall_hits::total        18995279                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      2236048                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       2236048                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       316058                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       316058                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      2552106                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2552106                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      2552106                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2552106                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  33041447208                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  33041447208                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  12234670517                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  12234670517                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  45276117725                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  45276117725                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  45276117725                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  45276117725                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     13134884                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     13134884                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      8412501                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      8412501                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     21547385                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     21547385                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     21547385                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     21547385                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.170237                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.170237                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037570                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.037570                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.118442                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.118442                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.118442                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.118442                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14776.716425                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14776.716425                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38710.206725                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 38710.206725                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 17740.688563                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 17740.688563                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 17740.688563                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 17740.688563                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs       395761                       # number of cycles access was blocked
+system.cpu.dcache.tags.tag_accesses          87845319                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         87845319                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     10889826                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        10889826                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      8100117                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        8100117                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      18989943                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         18989943                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     18989943                       # number of overall hits
+system.cpu.dcache.overall_hits::total        18989943                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      2239768                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       2239768                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       316527                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       316527                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      2556295                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2556295                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2556295                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2556295                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  32903838390                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  32903838390                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  11976667737                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  11976667737                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  44880506127                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  44880506127                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  44880506127                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  44880506127                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     13129594                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     13129594                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      8416644                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      8416644                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     21546238                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     21546238                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     21546238                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     21546238                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.170589                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.170589                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037607                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.037607                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.118642                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.118642                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.118642                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.118642                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14690.735107                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14690.735107                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37837.744448                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 37837.744448                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 17556.857142                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 17556.857142                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 17556.857142                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 17556.857142                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       388578                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs             42262                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs             42350                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.364465                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.175396                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      1558454                       # number of writebacks
-system.cpu.dcache.writebacks::total           1558454                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       866560                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       866560                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        25905                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        25905                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       892465                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       892465                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       892465                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       892465                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1369488                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1369488                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       290153                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       290153                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1659641                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1659641                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1659641                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1659641                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  17811534705                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  17811534705                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11340798474                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  11340798474                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  29152333179                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  29152333179                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  29152333179                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  29152333179                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  97363398000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  97363398000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2536146500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2536146500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  99899544500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  99899544500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.104263                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.104263                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.034491                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.034491                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.077023                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.077023                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.077023                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.077023                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13005.980852                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13005.980852                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39085.580621                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39085.580621                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17565.445285                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 17565.445285                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17565.445285                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 17565.445285                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks      1561202                       # number of writebacks
+system.cpu.dcache.writebacks::total           1561202                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       869210                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       869210                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        24502                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        24502                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       893712                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       893712                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       893712                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       893712                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1370558                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1370558                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       292025                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       292025                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1662583                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1662583                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1662583                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1662583                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  17741695710                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  17741695710                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11080104948                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  11080104948                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  28821800658                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  28821800658                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  28821800658                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  28821800658                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  97363380000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  97363380000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2536381000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2536381000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  99899761000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  99899761000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.104387                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.104387                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.034696                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.034696                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.077163                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.077163                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.077163                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.077163                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12944.870418                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12944.870418                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37942.316404                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37942.316404                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17335.555974                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 17335.555974                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17335.555974                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 17335.555974                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1382,150 +1252,150 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           111322                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        64824.350244                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            3788284                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           175285                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            21.612140                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           111989                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        64821.159717                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            3780351                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           176044                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            21.473899                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 50850.934653                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     9.783858                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.126014                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  3002.561725                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 10960.943994                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.775924                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000149                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000002                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.045815                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.167251                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.989141                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        63963                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           41                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          514                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3380                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5452                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54576                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.975998                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         34635418                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        34635418                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        64096                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         7642                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst       942107                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data      1332840                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        2346685                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      1581663                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      1581663                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data          320                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total          320                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       155094                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       155094                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker        64096                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker         7642                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst       942107                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      1487934                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2501779                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker        64096                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker         7642                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst       942107                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      1487934                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2501779                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           61                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            5                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.inst        16085                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data        35964                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        52115                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data         1454                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total         1454                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       132906                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       132906                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker           61                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.itb.walker            5                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst        16085                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       168870                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        185021                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker           61                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.itb.walker            5                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst        16085                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       168870                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       185021                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      5922249                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       375500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   1293203490                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data   2919351194                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total   4218852433                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     17719300                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total     17719300                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   9455061655                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   9455061655                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      5922249                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       375500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst   1293203490                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  12374412849                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  13673914088                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      5922249                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       375500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst   1293203490                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  12374412849                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  13673914088                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        64157                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         7647                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.inst       958192                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      1368804                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      2398800                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      1581663                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      1581663                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data         1774                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total         1774                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       288000                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       288000                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker        64157                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker         7647                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst       958192                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      1656804                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2686800                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker        64157                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker         7647                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst       958192                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      1656804                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2686800                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000951                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000654                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.016787                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.026274                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.021725                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.819617                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.819617                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.461479                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.461479                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000951                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000654                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016787                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.101925                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.068863                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000951                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000654                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016787                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.101925                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.068863                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 97086.049180                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        75100                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80398.103202                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 81174.262985                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 80952.747443                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12186.588721                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12186.588721                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71140.969219                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71140.969219                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 97086.049180                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        75100                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80398.103202                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73277.745301                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 73904.659947                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 97086.049180                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        75100                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80398.103202                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73277.745301                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 73904.659947                       # average overall miss latency
+system.cpu.l2cache.tags.occ_blocks::writebacks 50592.226872                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    10.121398                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.097025                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2916.382816                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 11302.331606                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.771976                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000154                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000001                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.044500                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.172460                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.989092                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        64055                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           53                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          517                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3496                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6269                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        53720                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.977402                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         34623360                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        34623360                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        64539                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         7780                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.inst       939362                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data      1333943                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        2345624                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      1579042                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      1579042                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data          315                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total          315                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       156902                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       156902                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker        64539                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.itb.walker         7780                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst       939362                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      1490845                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2502526                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.dtb.walker        64539                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.itb.walker         7780                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst       939362                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      1490845                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2502526                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker           49                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            4                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.inst        16168                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data        35908                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        52129                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data         1443                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total         1443                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       133016                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       133016                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.dtb.walker           49                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.itb.walker            4                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst        16168                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       168924                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        185145                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.dtb.walker           49                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.itb.walker            4                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.inst        16168                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       168924                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       185145                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker      4159750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       369250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   1243133741                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data   2836550442                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   4084213183                       # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     17687795                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total     17687795                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   9175416141                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   9175416141                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker      4159750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       369250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst   1243133741                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  12011966583                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  13259629324                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker      4159750                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       369250                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst   1243133741                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  12011966583                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  13259629324                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        64588                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         7784                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.inst       955530                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      1369851                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      2397753                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      1579042                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      1579042                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data         1758                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total         1758                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       289918                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       289918                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker        64588                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.itb.walker         7784                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst       955530                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      1659769                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2687671                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker        64588                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.itb.walker         7784                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst       955530                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      1659769                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2687671                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000759                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000514                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.016920                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.026213                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.021741                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.820819                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.820819                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.458806                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.458806                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000759                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000514                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016920                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.101776                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.068887                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000759                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000514                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016920                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.101776                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.068887                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 84892.857143                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 92312.500000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76888.529255                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78994.943801                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 78348.197414                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12257.654193                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12257.654193                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68979.792965                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68979.792965                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 84892.857143                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 92312.500000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76888.529255                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71108.703222                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 71617.539356                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 84892.857143                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 92312.500000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76888.529255                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71108.703222                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 71617.539356                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1534,99 +1404,99 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       101656                       # number of writebacks
-system.cpu.l2cache.writebacks::total           101656                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            1                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data            1                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total            2                       # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data            1                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total            2                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data            1                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total            2                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           61                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            5                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        16084                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        35963                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        52113                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         1454                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total         1454                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       132906                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       132906                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           61                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            5                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        16084                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       168869                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       185019                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           61                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            5                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        16084                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       168869                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       185019                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      5166251                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       312500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   1091253760                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   2471371556                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   3568104067                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     15558435                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     15558435                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7786682845                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7786682845                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      5166251                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       312500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1091253760                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  10258054401                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  11354786912                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      5166251                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       312500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1091253760                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  10258054401                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  11354786912                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  89250274500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  89250274500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2370476500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2370476500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  91620751000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  91620751000                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000951                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000654                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.016786                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.026273                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.021725                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.819617                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.819617                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.461479                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.461479                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000951                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000654                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016786                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.101925                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.068862                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000951                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000654                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016786                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.101925                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.068862                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 84692.639344                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        62500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67847.162397                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68719.838612                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68468.598373                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10700.436726                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10700.436726                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58587.895543                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58587.895543                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 84692.639344                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        62500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67847.162397                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60745.633604                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61370.923592                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 84692.639344                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        62500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67847.162397                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60745.633604                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61370.923592                       # average overall mshr miss latency
+system.cpu.l2cache.writebacks::writebacks       102223                       # number of writebacks
+system.cpu.l2cache.writebacks::total           102223                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            2                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data            2                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total            4                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst            2                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data            2                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total            4                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst            2                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data            2                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total            4                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker           49                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            4                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        16166                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        35906                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        52125                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         1443                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total         1443                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       133016                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       133016                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker           49                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            4                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        16166                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       168922                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       185141                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker           49                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            4                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        16166                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       168922                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       185141                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      3552250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       319250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   1040184259                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   2389977554                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   3434033313                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     15330925                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     15330925                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7506177359                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7506177359                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      3552250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       319250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1040184259                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   9896154913                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  10940210672                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      3552250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       319250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1040184259                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   9896154913                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  10940210672                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  89250256000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  89250256000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2370696500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2370696500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  91620952500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total  91620952500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000759                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000514                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.016918                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.026212                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.021739                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.820819                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.820819                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.458806                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.458806                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000759                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000514                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016918                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.101774                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.068885                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000759                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000514                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016918                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.101774                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.068885                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 72494.897959                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 79812.500000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64343.947730                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66562.066340                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 65880.735022                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10624.341649                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10624.341649                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56430.635104                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56430.635104                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 72494.897959                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 79812.500000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64343.947730                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58584.168510                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59091.236798                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 72494.897959                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 79812.500000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64343.947730                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58584.168510                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59091.236798                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
index 269726e62c891880e08c373e98f2772d2b928661..cc51e20ce3035e5699a4cb6f5f3078d08cc5561f 100644 (file)
@@ -4,11 +4,11 @@ sim_seconds                                  5.304497                       # Nu
 sim_ticks                                5304496750000                       # Number of ticks simulated
 final_tick                               5304496750000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 125034                       # Simulator instruction rate (inst/s)
-host_op_rate                                   239740                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             6206530470                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 832476                       # Number of bytes of host memory used
-host_seconds                                   854.66                       # Real time elapsed on the host
+host_inst_rate                                 156851                       # Simulator instruction rate (inst/s)
+host_op_rate                                   300747                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             7785889362                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 816820                       # Number of bytes of host memory used
+host_seconds                                   681.30                       # Real time elapsed on the host
 sim_insts                                   106862058                       # Number of instructions simulated
 sim_ops                                     204897478                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -199,6 +199,38 @@ system.physmem.wrQLenPdf::28                        0                       # Wh
 system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
 system.physmem.totQLat                              0                       # Total ticks spent queuing
 system.physmem.totMemAccLat                         0                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                            0                       # Total ticks spent in databus transfers
index c3991f43e8c048d49272119b8aa36cea631b1d66..b144561d01ec29f593fa2c1c10b0e0dc2b9daf85 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  5.137456                       # Number of seconds simulated
-sim_ticks                                5137456264000                       # Number of ticks simulated
-final_tick                               5137456264000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  5.139775                       # Number of seconds simulated
+sim_ticks                                5139775442500                       # Number of ticks simulated
+final_tick                               5139775442500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 293296                       # Simulator instruction rate (inst/s)
-host_op_rate                                   582999                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             6174974039                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 983548                       # Number of bytes of host memory used
-host_seconds                                   831.98                       # Real time elapsed on the host
-sim_insts                                   244016231                       # Number of instructions simulated
-sim_ops                                     485043652                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 241106                       # Simulator instruction rate (inst/s)
+host_op_rate                                   479260                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             5080243819                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 990760                       # Number of bytes of host memory used
+host_seconds                                  1011.72                       # Real time elapsed on the host
+sim_insts                                   243931071                       # Number of instructions simulated
+sim_ops                                     484875903                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::pc.south_bridge.ide      2422400                       # Number of bytes read from this memory
+system.physmem.bytes_read::pc.south_bridge.ide      2452480                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker          256                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           383808                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          5693376                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           137536                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          1729152                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.dtb.walker         2176                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           439552                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          5834944                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst            98048                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          1717440                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.dtb.walker         1664                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu2.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst           448384                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data          2947264                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             13764480                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       383808                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       137536                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst       448384                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          969728                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      9086592                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           9086592                       # Number of bytes written to this memory
-system.physmem.num_reads::pc.south_bridge.ide        37850                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::cpu2.inst           432064                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data          2820032                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             13796608                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       439552                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst        98048                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst       432064                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          969664                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      9118784                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           9118784                       # Number of bytes written to this memory
+system.physmem.num_reads::pc.south_bridge.ide        38320                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            4                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst              5997                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             88959                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              2149                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             27018                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.dtb.walker           34                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst              6868                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             91171                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              1532                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             26835                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.dtb.walker           26                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu2.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst              7006                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data             46051                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                215070                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          141978                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               141978                       # Number of write requests responded to by this memory
-system.physmem.bw_read::pc.south_bridge.ide       471517                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::cpu2.inst              6751                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data             44063                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                215572                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          142481                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               142481                       # Number of write requests responded to by this memory
+system.physmem.bw_read::pc.south_bridge.ide       477157                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker            50                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst               74708                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             1108209                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               26771                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              336577                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.dtb.walker           424                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst               85520                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             1135253                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               19076                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              334147                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.dtb.walker           324                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu2.itb.walker            25                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst               87277                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data              573682                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2679240                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst          74708                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          26771                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst          87277                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             188756                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1768695                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1768695                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1768695                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide       471517                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst               84063                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data              548668                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2684282                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst          85520                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          19076                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst          84063                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             188659                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1774160                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1774160                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1774160                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide       477157                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker           50                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst              74708                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            1108209                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              26771                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             336577                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.dtb.walker          424                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst              85520                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            1135253                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              19076                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             334147                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.dtb.walker          324                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu2.itb.walker           25                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst              87277                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data             573682                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4447935                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        102292                       # Number of read requests accepted
-system.physmem.writeReqs                        78374                       # Number of write requests accepted
-system.physmem.readBursts                      102292                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      78374                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  6544384                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      2304                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   5015936                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   6546688                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                5015936                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                       36                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::cpu2.inst              84063                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data             548668                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                4458442                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                         98736                       # Number of read requests accepted
+system.physmem.writeReqs                        74818                       # Number of write requests accepted
+system.physmem.readBursts                       98736                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      74818                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  6312704                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      6400                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   4788352                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   6319104                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                4788352                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      100                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs            862                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                6805                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                7244                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                6375                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                6857                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                6927                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                6780                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                5925                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                6310                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                5868                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                5795                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               5783                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               6231                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               6160                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               6316                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               6211                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               6669                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                5462                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                5811                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                4880                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                5445                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                5542                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                5461                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                4520                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                4685                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                4152                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                4422                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               4208                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               4507                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               4889                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               4664                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               4834                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               4892                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs            734                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0                6153                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                6286                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                6219                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                6279                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                6331                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                6377                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                5798                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                6202                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                5707                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                6391                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               5673                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               6223                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               6101                       # Per bank write bursts
+system.physmem.perBankRdBursts::13               6086                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               6643                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               6167                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                4924                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                4781                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                4796                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                4885                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                4841                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                4959                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                4374                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                4731                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                4283                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                4855                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               4375                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               4455                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               4488                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               4484                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               5021                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               4566                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           5                       # Number of times write queue was full causing retry
-system.physmem.totGap                    5136272146500                       # Total gap between requests
+system.physmem.numWrRetry                           4                       # Number of times write queue was full causing retry
+system.physmem.totGap                    5135962999500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  102292                       # Read request sizes (log2)
+system.physmem.readPktSize::6                   98736                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  78374                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     79930                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      8799                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      3355                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      1482                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      1139                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      1118                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                       809                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                       828                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                       776                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                       583                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      457                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      398                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      373                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      356                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      333                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      313                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      307                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                      303                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                      296                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                      282                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                       17                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  74818                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     76556                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      4428                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      2029                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      1295                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      1291                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      2072                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      1756                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      1697                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      1521                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                      1005                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                      865                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      756                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      662                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      578                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                      432                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                      398                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                      380                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                      350                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                      340                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                      203                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                       21                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
@@ -165,556 +165,474 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                      3289                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                      3317                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                      3333                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                      3348                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                      3412                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                      3499                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                      3502                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                      3527                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                      3740                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                      3713                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                     3732                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                     3757                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                     4015                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                     3738                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                     3805                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     3899                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     3928                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     3326                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     3289                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     3258                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     3232                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     3241                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                      189                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                      134                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                       32                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                       24                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                       19                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                       18                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                       17                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                       15                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                       15                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                       11                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        37207                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      310.623700                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     146.064630                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev    1005.971949                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64-67          16908     45.44%     45.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-131         5765     15.49%     60.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192-195         3845     10.33%     71.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-259         2398      6.45%     77.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320-323         1477      3.97%     81.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-387         1206      3.24%     84.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448-451          882      2.37%     87.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-515          634      1.70%     89.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576-579          564      1.52%     90.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-643          479      1.29%     91.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704-707          331      0.89%     92.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-771          285      0.77%     93.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832-835          209      0.56%     94.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-899          204      0.55%     94.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960-963          197      0.53%     95.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1027          303      0.81%     95.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088-1091          153      0.41%     96.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152-1155          117      0.31%     96.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216-1219           75      0.20%     96.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280-1283           61      0.16%     97.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344-1347          106      0.28%     97.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408-1411          199      0.53%     97.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472-1475           97      0.26%     98.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536-1539           87      0.23%     98.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600-1603           45      0.12%     98.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664-1667           43      0.12%     98.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1728-1731           26      0.07%     98.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1792-1795           28      0.08%     98.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856-1859           16      0.04%     98.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1920-1923           12      0.03%     98.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984-1987           10      0.03%     98.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2048-2051           10      0.03%     98.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112-2115           17      0.05%     98.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2176-2179            7      0.02%     98.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2240-2243           10      0.03%     98.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2304-2307            3      0.01%     98.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2368-2371            3      0.01%     98.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2432-2435            7      0.02%     98.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2496-2499            3      0.01%     98.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2560-2563            7      0.02%     98.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2624-2627            1      0.00%     98.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2688-2691            9      0.02%     99.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2752-2755            4      0.01%     99.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2816-2819            6      0.02%     99.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2880-2883            6      0.02%     99.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2944-2947            2      0.01%     99.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3008-3011            2      0.01%     99.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3072-3075           13      0.03%     99.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3136-3139            4      0.01%     99.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3200-3203            1      0.00%     99.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3264-3267            2      0.01%     99.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3328-3331            3      0.01%     99.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3392-3395            4      0.01%     99.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3456-3459            4      0.01%     99.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3520-3523            2      0.01%     99.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3584-3587            3      0.01%     99.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3648-3651            7      0.02%     99.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3712-3715            2      0.01%     99.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3776-3779            3      0.01%     99.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3840-3843            2      0.01%     99.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3904-3907           24      0.06%     99.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4032-4035            2      0.01%     99.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4096-4099           10      0.03%     99.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4160-4163            4      0.01%     99.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4288-4291           25      0.07%     99.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4352-4355            1      0.00%     99.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4480-4483            2      0.01%     99.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4544-4547            1      0.00%     99.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4608-4611            1      0.00%     99.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4672-4675            1      0.00%     99.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4736-4739            1      0.00%     99.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5056-5059            1      0.00%     99.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5120-5123            3      0.01%     99.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5184-5187            2      0.01%     99.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5248-5251            1      0.00%     99.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5312-5315            1      0.00%     99.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5376-5379            2      0.01%     99.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5504-5507           23      0.06%     99.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5632-5635            1      0.00%     99.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5760-5763            1      0.00%     99.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5824-5827            1      0.00%     99.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5952-5955            1      0.00%     99.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6016-6019            1      0.00%     99.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6080-6083            1      0.00%     99.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6272-6275            1      0.00%     99.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6400-6403            1      0.00%     99.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6464-6467            1      0.00%     99.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6528-6531            1      0.00%     99.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6592-6595            1      0.00%     99.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6720-6723            1      0.00%     99.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6848-6851            2      0.01%     99.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7040-7043            5      0.01%     99.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7104-7107            1      0.00%     99.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7168-7171            6      0.02%     99.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7360-7363            1      0.00%     99.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7552-7555            1      0.00%     99.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7616-7619            1      0.00%     99.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7680-7683            2      0.01%     99.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7744-7747            1      0.00%     99.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7872-7875            2      0.01%     99.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7936-7939            1      0.00%     99.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8064-8067            3      0.01%     99.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8192-8195            4      0.01%     99.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8384-8387            2      0.01%     99.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8640-8643            2      0.01%     99.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8768-8771            1      0.00%     99.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8896-8899            1      0.00%     99.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8960-8963            1      0.00%     99.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9088-9091            1      0.00%     99.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9216-9219            4      0.01%     99.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9408-9411            1      0.00%     99.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9536-9539            1      0.00%     99.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9600-9603            1      0.00%     99.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9728-9731            1      0.00%     99.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9792-9795            1      0.00%     99.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9856-9859            1      0.00%     99.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10048-10051            1      0.00%     99.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10176-10179            2      0.01%     99.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10496-10499            1      0.00%     99.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10560-10563            1      0.00%     99.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10752-10755            1      0.00%     99.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11008-11011            1      0.00%     99.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11136-11139            2      0.01%     99.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11264-11267            2      0.01%     99.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11520-11523            2      0.01%     99.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11648-11651            1      0.00%     99.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11712-11715            2      0.01%     99.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11840-11843            1      0.00%     99.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11968-11971            1      0.00%     99.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12032-12035            1      0.00%     99.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12224-12227            1      0.00%     99.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12288-12291            1      0.00%     99.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12544-12547            1      0.00%     99.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12672-12675            1      0.00%     99.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12736-12739            2      0.01%     99.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12800-12803            1      0.00%     99.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12928-12931            1      0.00%     99.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13056-13059            1      0.00%     99.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13120-13123            1      0.00%     99.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13248-13251            1      0.00%     99.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13440-13443            1      0.00%     99.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13504-13507            1      0.00%     99.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13568-13571            1      0.00%     99.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13696-13699            1      0.00%     99.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13888-13891            2      0.01%     99.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14144-14147            1      0.00%     99.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14272-14275            1      0.00%     99.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14336-14339            1      0.00%     99.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14400-14403            1      0.00%     99.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14592-14595            1      0.00%     99.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14656-14659            1      0.00%     99.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14720-14723            1      0.00%     99.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14784-14787            2      0.01%     99.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14912-14915            4      0.01%     99.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14976-14979            2      0.01%     99.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15040-15043            3      0.01%     99.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15104-15107            1      0.00%     99.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15168-15171            2      0.01%     99.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15232-15235            3      0.01%     99.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15296-15299            5      0.01%     99.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15360-15363            8      0.02%     99.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15424-15427            1      0.00%     99.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15488-15491            1      0.00%     99.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15552-15555            1      0.00%     99.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15680-15683            1      0.00%     99.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15808-15811            2      0.01%     99.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16000-16003            1      0.00%     99.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16064-16067            1      0.00%     99.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16128-16131            2      0.01%     99.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16192-16195            3      0.01%     99.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16256-16259           11      0.03%     99.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16320-16323           14      0.04%     99.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16384-16387           22      0.06%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          37207                       # Bytes accessed per row activation
-system.physmem.totQLat                     2596442750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                4566061500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    511280000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                  1458338750                       # Total ticks spent accessing banks
-system.physmem.avgQLat                       25391.59                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    14261.64                       # Average bank access latency per DRAM burst
+system.physmem.wrQLenPdf::0                       110                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                        67                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                        65                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                        61                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                        58                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                        57                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                        54                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                        54                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                        53                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                        53                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                       53                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                       52                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                       52                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                       52                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                       53                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     1029                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     1079                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     1337                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     3068                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     3176                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     3199                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     3215                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     3295                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     3317                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     3341                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     4472                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     3777                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     3885                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     4534                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     4146                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     4247                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     4212                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     4224                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     1287                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                     1217                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                     1095                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                     1013                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                     1004                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      996                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      896                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      877                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      856                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      814                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      759                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      656                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      558                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      491                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      418                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      353                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      269                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      223                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      163                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      123                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       95                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       57                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       43                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       31                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       20                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       14                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       10                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       11                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        8                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        22863                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      371.369637                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     216.870030                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     366.414967                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127           7224     31.60%     31.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         5292     23.15%     54.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         2324     10.16%     64.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         1423      6.22%     71.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639          882      3.86%     74.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          607      2.65%     77.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          442      1.93%     79.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          389      1.70%     81.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         4280     18.72%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          22863                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          4109                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        24.004867                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      117.614100                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-255            4100     99.78%     99.78% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::256-511             6      0.15%     99.93% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::512-767             1      0.02%     99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2560-2815            1      0.02%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::6656-6911            1      0.02%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            4109                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          4109                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        18.208323                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.187975                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        6.583219                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-1                44      1.07%      1.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::2-3                 6      0.15%      1.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-5                 4      0.10%      1.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::6-7                 4      0.10%      1.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-9                 2      0.05%      1.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::14-15               4      0.10%      1.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-17            2755     67.05%     68.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18-19             853     20.76%     89.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-21              55      1.34%     90.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22-23              41      1.00%     91.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-25              36      0.88%     92.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26-27              45      1.10%     93.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-29              25      0.61%     94.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30-31              36      0.88%     95.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-33              20      0.49%     95.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::34-35              26      0.63%     96.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-37              28      0.68%     96.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::38-39              10      0.24%     97.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-41              24      0.58%     97.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::42-43              13      0.32%     98.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-45              21      0.51%     98.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::46-47              18      0.44%     99.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-49               6      0.15%     99.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::50-51               4      0.10%     99.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-53              10      0.24%     99.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-57               1      0.02%     99.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::58-59               2      0.05%     99.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-61               1      0.02%     99.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::62-63               4      0.10%     99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-65               9      0.22%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-69               1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-77               1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            4109                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2553947750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                4444375250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    493180000                       # Total ticks spent in databus transfers
+system.physmem.totBankLat                  1397247500                       # Total ticks spent accessing banks
+system.physmem.avgQLat                       25892.65                       # Average queueing delay per DRAM burst
+system.physmem.avgBankLat                    14165.70                       # Average bank access latency per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  44653.24                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           1.27                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           0.98                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        1.27                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        0.98                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  45058.35                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           1.23                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           0.93                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        1.23                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        0.93                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         0.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                         0.11                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      86197                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     57226                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   84.30                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  73.02                       # Row buffer hit rate for writes
-system.physmem.avgGap                     28429655.53                       # Average gap between requests
-system.physmem.pageHitRate                      79.40                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               0.13                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                      6440814                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq              424797                       # Transaction distribution
-system.membus.trans_dist::ReadResp             424797                       # Transaction distribution
-system.membus.trans_dist::WriteReq               7056                       # Transaction distribution
-system.membus.trans_dist::WriteResp              7056                       # Transaction distribution
-system.membus.trans_dist::Writeback             78374                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              877                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp             877                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             80570                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            80570                       # Transaction distribution
-system.membus.trans_dist::MessageReq              957                       # Transaction distribution
-system.membus.trans_dist::MessageResp             957                       # Transaction distribution
-system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave         1914                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.apicbridge.master::total         1914                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       312158                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio       497710                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       221000                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      1030868                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        68894                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total        68894                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1101676                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave         3828                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.apicbridge.master::total         3828                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave       160435                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio       995417                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port      8741760                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::total      9897612                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      2820864                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::total      2820864                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            12722304                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus               32756791                       # Total data (bytes)
-system.membus.snoop_data_through_bus           332608                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy           164980499                       # Layer occupancy (ticks)
+system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        10.06                       # Average write queue length when enqueuing
+system.physmem.readRowHits                      80976                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     55952                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.10                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  74.78                       # Row buffer hit rate for writes
+system.physmem.avgGap                     29592881.75                       # Average gap between requests
+system.physmem.pageHitRate                      78.94                       # Row buffer hit rate, read and write combined
+system.physmem.prechargeAllPercent               0.12                       # Percentage of time for which DRAM has all the banks in precharge state
+system.membus.throughput                      6444852                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq              422305                       # Transaction distribution
+system.membus.trans_dist::ReadResp             422303                       # Transaction distribution
+system.membus.trans_dist::WriteReq               6370                       # Transaction distribution
+system.membus.trans_dist::WriteResp              6370                       # Transaction distribution
+system.membus.trans_dist::Writeback             74818                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq              747                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp             747                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             78043                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            78043                       # Transaction distribution
+system.membus.trans_dist::MessageReq              885                       # Transaction distribution
+system.membus.trans_dist::MessageResp             885                       # Transaction distribution
+system.membus.trans_dist::BadAddressError            2                       # Transaction distribution
+system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave         1770                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.apicbridge.master::total         1770                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       309432                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio       497538                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       212160                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio            4                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      1019134                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port        66106                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total        66106                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1087010                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave         3540                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.apicbridge.master::total         3540                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave       158682                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio       995073                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port      8391680                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::total      9545435                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      2715776                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::total      2715776                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total            12264751                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               32837413                       # Total data (bytes)
+system.membus.snoop_data_through_bus           287680                       # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy           162853500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy           315323500                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy           315156500                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             1914000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             1770000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer3.occupancy           859913497                       # Layer occupancy (ticks)
+system.membus.reqLayer3.occupancy           821391499                       # Layer occupancy (ticks)
 system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer0.occupancy             957000                       # Layer occupancy (ticks)
+system.membus.reqLayer4.occupancy                2500                       # Layer occupancy (ticks)
+system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
+system.membus.respLayer0.occupancy             885000                       # Layer occupancy (ticks)
 system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         1658568572                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         1625485201                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer4.occupancy          223775499                       # Layer occupancy (ticks)
+system.membus.respLayer4.occupancy          213559749                       # Layer occupancy (ticks)
 system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.l2c.tags.replacements                   103968                       # number of replacements
-system.l2c.tags.tagsinuse                64819.095791                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    3669692                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   168243                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    21.811855                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                   104632                       # number of replacements
+system.l2c.tags.tagsinuse                64756.494280                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    3664896                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   168700                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    21.724339                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   51211.809516                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     0.121912                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     1304.363790                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     4492.907273                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      251.742289                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     1518.622796                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.dtb.walker    11.780510                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.itb.walker     0.958868                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst     1352.233300                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data     4674.555536                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.781430                       # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::writebacks   51511.220399                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker     0.131167                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     1228.361726                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     4265.224240                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst      282.161159                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     1465.784470                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.dtb.walker    10.322385                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.itb.walker     0.042344                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst     1365.490726                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data     4627.755664                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.785999                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.itb.walker     0.000002                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.019903                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.068556                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.003841                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.023172                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.dtb.walker     0.000180                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.itb.walker     0.000015                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst       0.020633                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data       0.071328                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.989061                       # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024        64275                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           60                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          238                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         3733                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         7385                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        52859                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024     0.980759                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 33713228                       # Number of tag accesses
-system.l2c.tags.data_accesses                33713228                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker        21716                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker        11486                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst             326601                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             505560                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker        10498                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker         5651                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             148959                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data             223967                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.dtb.walker        55385                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.itb.walker        11312                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.inst             366888                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.data             576803                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                2264826                       # number of ReadReq hits
+system.l2c.tags.occ_percent::cpu0.inst       0.018743                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.065082                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.004305                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.022366                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.dtb.walker     0.000158                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.itb.walker     0.000001                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.inst       0.020836                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.data       0.070614                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.988106                       # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1024        64068                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           75                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          252                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         2732                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         7219                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        53790                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1024     0.977600                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 33688290                       # Number of tag accesses
+system.l2c.tags.data_accesses                33688290                       # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.dtb.walker        22061                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker        11615                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.inst             344470                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data             519863                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker        10165                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker         5243                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst             139799                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data             221175                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.dtb.walker        54188                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.itb.walker        10719                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.inst             354261                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.data             566062                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                2259621                       # number of ReadReq hits
 system.l2c.WriteReq_hits::cpu0.itb.walker            2                       # number of WriteReq hits
 system.l2c.WriteReq_hits::total                     2                       # number of WriteReq hits
-system.l2c.Writeback_hits::writebacks         1544272                       # number of Writeback hits
-system.l2c.Writeback_hits::total              1544272                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data             123                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data              38                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2.data              95                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                 256                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            65648                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            35064                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu2.data            65209                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               165921                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker         21716                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker         11488                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              326601                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              571208                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker         10498                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          5651                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              148959                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              259031                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.dtb.walker         55385                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.itb.walker         11312                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst              366888                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data              642012                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2430749                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker        21716                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker        11488                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             326601                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             571208                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker        10498                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         5651                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             148959                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             259031                       # number of overall hits
-system.l2c.overall_hits::cpu2.dtb.walker        55385                       # number of overall hits
-system.l2c.overall_hits::cpu2.itb.walker        11312                       # number of overall hits
-system.l2c.overall_hits::cpu2.inst             366888                       # number of overall hits
-system.l2c.overall_hits::cpu2.data             642012                       # number of overall hits
-system.l2c.overall_hits::total                2430749                       # number of overall hits
+system.l2c.Writeback_hits::writebacks         1545523                       # number of Writeback hits
+system.l2c.Writeback_hits::total              1545523                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data             137                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data              46                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu2.data              93                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                 276                       # number of UpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data            73996                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            34699                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu2.data            57996                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               166691                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.dtb.walker         22061                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker         11617                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst              344470                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              593859                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker         10165                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker          5243                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              139799                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              255874                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.dtb.walker         54188                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.itb.walker         10719                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.inst              354261                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.data              624058                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 2426314                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker        22061                       # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker        11617                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst             344470                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             593859                       # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker        10165                       # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker         5243                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             139799                       # number of overall hits
+system.l2c.overall_hits::cpu1.data             255874                       # number of overall hits
+system.l2c.overall_hits::cpu2.dtb.walker        54188                       # number of overall hits
+system.l2c.overall_hits::cpu2.itb.walker        10719                       # number of overall hits
+system.l2c.overall_hits::cpu2.inst             354261                       # number of overall hits
+system.l2c.overall_hits::cpu2.data             624058                       # number of overall hits
+system.l2c.overall_hits::total                2426314                       # number of overall hits
 system.l2c.ReadReq_misses::cpu0.itb.walker            4                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst             5997                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data            15878                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst             2150                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data             4005                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.dtb.walker           34                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.inst             6868                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data            16704                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst             1533                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data             3888                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.dtb.walker           26                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu2.itb.walker            2                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.inst             7008                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.data            12968                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                48046                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data           707                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data           185                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2.data           493                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              1385                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          73415                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          23238                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2.data          33467                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             130120                       # number of ReadExReq misses
+system.l2c.ReadReq_misses::cpu2.inst             6752                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.data            12246                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                48023                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data           754                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data           206                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu2.data           371                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              1331                       # number of UpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data          74862                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data          23137                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu2.data          32148                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             130147                       # number of ReadExReq misses
 system.l2c.demand_misses::cpu0.itb.walker            4                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst              5997                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data             89293                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              2150                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data             27243                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.dtb.walker           34                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst              6868                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data             91566                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst              1533                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data             27025                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.dtb.walker           26                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu2.itb.walker            2                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.inst              7008                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.data             46435                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                178166                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.inst              6752                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.data             44394                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                178170                       # number of demand (read+write) misses
 system.l2c.overall_misses::cpu0.itb.walker            4                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst             5997                       # number of overall misses
-system.l2c.overall_misses::cpu0.data            89293                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             2150                       # number of overall misses
-system.l2c.overall_misses::cpu1.data            27243                       # number of overall misses
-system.l2c.overall_misses::cpu2.dtb.walker           34                       # number of overall misses
+system.l2c.overall_misses::cpu0.inst             6868                       # number of overall misses
+system.l2c.overall_misses::cpu0.data            91566                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst             1533                       # number of overall misses
+system.l2c.overall_misses::cpu1.data            27025                       # number of overall misses
+system.l2c.overall_misses::cpu2.dtb.walker           26                       # number of overall misses
 system.l2c.overall_misses::cpu2.itb.walker            2                       # number of overall misses
-system.l2c.overall_misses::cpu2.inst             7008                       # number of overall misses
-system.l2c.overall_misses::cpu2.data            46435                       # number of overall misses
-system.l2c.overall_misses::total               178166                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu1.inst    161561250                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data    314335492                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.dtb.walker      2727499                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.itb.walker       170750                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.inst    583607489                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.data   1035968985                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total     2098371465                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data      3143902                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu2.data      6170749                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total      9314651                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data   1653854893                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu2.data   2482673598                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   4136528491                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu1.inst    161561250                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data   1968190385                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.dtb.walker      2727499                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.itb.walker       170750                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.inst    583607489                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.data   3518642583                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total      6234899956                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu1.inst    161561250                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data   1968190385                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.dtb.walker      2727499                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.itb.walker       170750                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.inst    583607489                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.data   3518642583                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total     6234899956                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.dtb.walker        21716                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker        11490                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst         332598                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data         521438                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker        10498                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker         5651                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst         151109                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data         227972                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.dtb.walker        55419                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.itb.walker        11314                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.inst         373896                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.data         589771                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2312872                       # number of ReadReq accesses(hits+misses)
+system.l2c.overall_misses::cpu2.inst             6752                       # number of overall misses
+system.l2c.overall_misses::cpu2.data            44394                       # number of overall misses
+system.l2c.overall_misses::total               178170                       # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu1.inst    112485250                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data    293047996                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.dtb.walker      2104000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.itb.walker       149000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.inst    524939486                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.data    946518491                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total     1879244223                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data      2976906                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu2.data      4826300                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total      7803206                       # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data   1584451415                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu2.data   2283457099                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   3867908514                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu1.inst    112485250                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data   1877499411                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.dtb.walker      2104000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.itb.walker       149000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.inst    524939486                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.data   3229975590                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total      5747152737                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu1.inst    112485250                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data   1877499411                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.dtb.walker      2104000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.itb.walker       149000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.inst    524939486                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.data   3229975590                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total     5747152737                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.dtb.walker        22061                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker        11619                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.inst         351338                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data         536567                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker        10165                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker         5243                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst         141332                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data         225063                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.dtb.walker        54214                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.itb.walker        10721                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.inst         361013                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.data         578308                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            2307644                       # number of ReadReq accesses(hits+misses)
 system.l2c.WriteReq_accesses::cpu0.itb.walker            2                       # number of WriteReq accesses(hits+misses)
 system.l2c.WriteReq_accesses::total                 2                       # number of WriteReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks      1544272                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total          1544272                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data          830                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data          223                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2.data          588                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            1641                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       139063                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data        58302                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu2.data        98676                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           296041                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker        21716                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker        11492                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst          332598                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data          660501                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker        10498                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker         5651                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          151109                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          286274                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.dtb.walker        55419                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.itb.walker        11314                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.inst          373896                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.data          688447                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2608915                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker        21716                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker        11492                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         332598                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data         660501                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker        10498                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker         5651                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         151109                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         286274                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.dtb.walker        55419                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.itb.walker        11314                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.inst         373896                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.data         688447                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2608915                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000348                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.018031                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.030450                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.014228                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.017568                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.000614                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.itb.walker     0.000177                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.inst      0.018743                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.data      0.021988                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.020773                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.851807                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.829596                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2.data     0.838435                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.843998                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.527926                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.398580                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2.data     0.339160                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.439534                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.000348                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.018031                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.135190                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.014228                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.095164                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.dtb.walker     0.000614                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.itb.walker     0.000177                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst       0.018743                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.data       0.067449                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.068291                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.000348                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.018031                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.135190                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.014228                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.095164                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.dtb.walker     0.000614                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.itb.walker     0.000177                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst      0.018743                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.data      0.067449                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.068291                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75144.767442                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 78485.765793                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 80220.558824                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker        85375                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.inst 83277.324344                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.data 79886.565777                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 43674.217729                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 16994.064865                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 12516.732252                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  6725.379783                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 71170.276831                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2.data 74182.735172                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 31790.105218                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 75144.767442                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 72245.728628                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 80220.558824                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.itb.walker        85375                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.inst 83277.324344                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.data 75775.655928                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 34994.892157                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 75144.767442                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 72245.728628                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 80220.558824                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.itb.walker        85375                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.inst 83277.324344                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.data 75775.655928                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 34994.892157                       # average overall miss latency
+system.l2c.Writeback_accesses::writebacks      1545523                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total          1545523                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data          891                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data          252                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu2.data          464                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            1607                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       148858                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data        57836                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu2.data        90144                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           296838                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker        22061                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker        11621                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst          351338                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data          685425                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker        10165                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker         5243                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          141332                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data          282899                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.dtb.walker        54214                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.itb.walker        10721                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.inst          361013                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.data          668452                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             2604484                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker        22061                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker        11621                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         351338                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data         685425                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker        10165                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker         5243                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         141332                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data         282899                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.dtb.walker        54214                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.itb.walker        10721                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.inst         361013                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.data         668452                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            2604484                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000344                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.019548                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.031131                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst      0.010847                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data      0.017275                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.dtb.walker     0.000480                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.itb.walker     0.000187                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.inst      0.018703                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.data      0.021176                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.020810                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.846240                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.817460                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu2.data     0.799569                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.828251                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.502909                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.400045                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu2.data     0.356629                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.438445                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.000344                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.019548                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.133590                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.010847                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.095529                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.dtb.walker     0.000480                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.itb.walker     0.000187                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.inst       0.018703                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.data       0.066413                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.068409                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.000344                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.019548                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.133590                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.010847                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.095529                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.dtb.walker     0.000480                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.itb.walker     0.000187                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.inst      0.018703                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.data      0.066413                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.068409                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 73375.896934                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 75372.426955                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 80923.076923                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker        74500                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.inst 77745.776955                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.data 77292.053813                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 39132.170481                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data        14451                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 13008.894879                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  5862.664162                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 68481.281713                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu2.data 71029.522801                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 29719.536478                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 73375.896934                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 69472.688659                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 80923.076923                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.itb.walker        74500                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.inst 77745.776955                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.data 72757.030004                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 32256.568092                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 73375.896934                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 69472.688659                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 80923.076923                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.itb.walker        74500                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.inst 77745.776955                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.data 72757.030004                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 32256.568092                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -723,131 +641,131 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               95311                       # number of writebacks
-system.l2c.writebacks::total                    95311                       # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu2.inst             2                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total                 2                       # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits::cpu2.inst              2                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                  2                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu2.inst             2                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                 2                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu1.inst         2150                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data         4005                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker           34                       # number of ReadReq MSHR misses
+system.l2c.writebacks::writebacks               95814                       # number of writebacks
+system.l2c.writebacks::total                    95814                       # number of writebacks
+system.l2c.ReadReq_mshr_hits::cpu2.inst             1                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::total                 1                       # number of ReadReq MSHR hits
+system.l2c.demand_mshr_hits::cpu2.inst              1                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                  1                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu2.inst             1                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total                 1                       # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses::cpu1.inst         1533                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.data         3888                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker           26                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu2.itb.walker            2                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.inst         7006                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.data        12968                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total           26165                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data          185                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu2.data          493                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total          678                       # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data        23238                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu2.data        33467                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total         56705                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst         2150                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data        27243                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.dtb.walker           34                       # number of demand (read+write) MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.inst         6751                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.data        12246                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total           24446                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data          206                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu2.data          371                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total          577                       # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data        23137                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu2.data        32148                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total         55285                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst         1533                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data        27025                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.dtb.walker           26                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu2.itb.walker            2                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.inst         7006                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.data        46435                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total            82870                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst         2150                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data        27243                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.dtb.walker           34                       # number of overall MSHR misses
+system.l2c.demand_mshr_misses::cpu2.inst         6751                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.data        44394                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total            79731                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst         1533                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data        27025                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.dtb.walker           26                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu2.itb.walker            2                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.inst         7006                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.data        46435                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total           82870                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    134244250                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data    264246008                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker      2308001                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker       145750                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.inst    495740261                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.data    873454007                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total   1770138277                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data      2450173                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data      5190488                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total      7640661                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   1355864107                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   2052275856                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   3408139963                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst    134244250                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data   1620110115                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker      2308001                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.itb.walker       145750                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.inst    495740261                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.data   2925729863                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total   5178278240                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst    134244250                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data   1620110115                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker      2308001                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.itb.walker       145750                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.inst    495740261                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.data   2925729863                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total   5178278240                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  28143642000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data  30477969500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total  58621611500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    483707000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data    766316000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   1250023000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data  28627349000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu2.data  31244285500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  59871634500                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.014228                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.017568                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.000614                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker     0.000177                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.018738                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.021988                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.011313                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.829596                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.838435                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.413163                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.398580                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.339160                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.191544                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.014228                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.095164                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.000614                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.itb.walker     0.000177                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.inst     0.018738                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.data     0.067449                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.031764                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.014228                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.095164                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.000614                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.itb.walker     0.000177                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.inst     0.018738                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.data     0.067449                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.031764                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62439.186047                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65979.028215                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 67882.382353                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker        72875                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 70759.386383                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 67354.565623                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 67652.905676                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 13244.178378                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10528.373225                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 11269.411504                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58346.850288                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 61322.372964                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 60102.988502                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62439.186047                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59468.858606                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 67882.382353                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker        72875                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 70759.386383                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 63006.996081                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 62486.765295                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62439.186047                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59468.858606                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 67882.382353                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker        72875                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 70759.386383                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 63006.996081                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 62486.765295                       # average overall mshr miss latency
+system.l2c.overall_mshr_misses::cpu2.inst         6751                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.data        44394                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total           79731                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst     93050250                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data    244480004                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker      1780500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker       125000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.inst    440173014                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.data    793487001                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total   1573095769                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data      2610195                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data      3849868                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total      6460063                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   1288379085                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2.data   1870619355                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   3158998440                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst     93050250                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data   1532859089                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker      1780500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.itb.walker       125000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.inst    440173014                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.data   2664106356                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   4732094209                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst     93050250                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data   1532859089                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker      1780500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.itb.walker       125000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.inst    440173014                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.data   2664106356                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   4732094209                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data  28007446000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data  30457930500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total  58465376500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    376483500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data    742130500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   1118614000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data  28383929500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2.data  31200061000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  59583990500                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.010847                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.017275                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker     0.000480                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker     0.000187                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.018700                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.021176                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.010593                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.817460                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data     0.799569                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.359054                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.400045                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2.data     0.356629                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.186246                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.010847                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.095529                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker     0.000480                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.itb.walker     0.000187                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst     0.018700                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.data     0.066413                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.030613                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.010847                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.095529                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker     0.000480                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.itb.walker     0.000187                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst     0.018700                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data     0.066413                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.030613                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60698.140900                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62880.659465                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 68480.769231                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker        62500                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 65201.157458                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 64795.606810                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 64349.822834                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 12670.849515                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10377.002695                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 11195.949740                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55684.794269                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 58187.736562                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 57140.244913                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60698.140900                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 56720.040296                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 68480.769231                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker        62500                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 65201.157458                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 60010.504933                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 59350.744491                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60698.140900                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 56720.040296                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 68480.769231                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker        62500                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 65201.157458                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 60010.504933                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 59350.744491                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -858,44 +776,44 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.iocache.tags.replacements                47574                       # number of replacements
-system.iocache.tags.tagsinuse                0.092731                       # Cycle average of tags in use
+system.iocache.tags.replacements                47572                       # number of replacements
+system.iocache.tags.tagsinuse                0.107425                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                47590                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs                47588                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         5000213887009                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.092731                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::pc.south_bridge.ide     0.005796                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.005796                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         5000219024509                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.107425                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::pc.south_bridge.ide     0.006714                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.006714                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               428661                       # Number of tag accesses
-system.iocache.tags.data_accesses              428661                       # Number of data accesses
-system.iocache.ReadReq_misses::pc.south_bridge.ide          909                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              909                       # number of ReadReq misses
+system.iocache.tags.tag_accesses               428643                       # Number of tag accesses
+system.iocache.tags.data_accesses              428643                       # Number of data accesses
+system.iocache.ReadReq_misses::pc.south_bridge.ide          907                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              907                       # number of ReadReq misses
 system.iocache.WriteReq_misses::pc.south_bridge.ide        46720                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total           46720                       # number of WriteReq misses
-system.iocache.demand_misses::pc.south_bridge.ide        47629                       # number of demand (read+write) misses
-system.iocache.demand_misses::total             47629                       # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide        47629                       # number of overall misses
-system.iocache.overall_misses::total            47629                       # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    135882017                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total    135882017                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::pc.south_bridge.ide   5955673280                       # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total   5955673280                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide   6091555297                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   6091555297                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide   6091555297                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   6091555297                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide          909                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            909                       # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::pc.south_bridge.ide        47627                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             47627                       # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide        47627                       # number of overall misses
+system.iocache.overall_misses::total            47627                       # number of overall misses
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    128792785                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total    128792785                       # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::pc.south_bridge.ide   5668191006                       # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total   5668191006                       # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide   5796983791                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   5796983791                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide   5796983791                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   5796983791                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::pc.south_bridge.ide          907                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            907                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::pc.south_bridge.ide        46720                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total         46720                       # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide        47629                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           47629                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide        47629                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          47629                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::pc.south_bridge.ide        47627                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           47627                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide        47627                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          47627                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteReq accesses
@@ -904,60 +822,60 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 149485.167217                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 149485.167217                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 127475.883562                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 127475.883562                       # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 127895.930987                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 127895.930987                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 127895.930987                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 127895.930987                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs         91729                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 141998.660419                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 141998.660419                       # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 121322.581464                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 121322.581464                       # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 121716.332983                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 121716.332983                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 121716.332983                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 121716.332983                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs         88529                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 5124                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 7334                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs    17.901835                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs    12.071039                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           46667                       # number of writebacks
 system.iocache.writebacks::total                46667                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          754                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          754                       # number of ReadReq MSHR misses
-system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide        24064                       # number of WriteReq MSHR misses
-system.iocache.WriteReq_mshr_misses::total        24064                       # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide        24818                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total        24818                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide        24818                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total        24818                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     96648017                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     96648017                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide   4703544282                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total   4703544282                       # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide   4800192299                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   4800192299                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide   4800192299                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   4800192299                       # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide     0.829483                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total     0.829483                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide     0.515068                       # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_miss_rate::total     0.515068                       # mshr miss rate for WriteReq accesses
-system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide     0.521069                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total     0.521069                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide     0.521069                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total     0.521069                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 128180.393899                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 128180.393899                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 195459.785655                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 195459.785655                       # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 193415.758683                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 193415.758683                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 193415.758683                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 193415.758683                       # average overall mshr miss latency
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          744                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          744                       # number of ReadReq MSHR misses
+system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide        22928                       # number of WriteReq MSHR misses
+system.iocache.WriteReq_mshr_misses::total        22928                       # number of WriteReq MSHR misses
+system.iocache.demand_mshr_misses::pc.south_bridge.ide        23672                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total        23672                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide        23672                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total        23672                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     90079785                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     90079785                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide   4474936508                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total   4474936508                       # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide   4565016293                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   4565016293                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide   4565016293                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   4565016293                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide     0.820287                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total     0.820287                       # mshr miss rate for ReadReq accesses
+system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide     0.490753                       # mshr miss rate for WriteReq accesses
+system.iocache.WriteReq_mshr_miss_rate::total     0.490753                       # mshr miss rate for WriteReq accesses
+system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide     0.497029                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total     0.497029                       # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide     0.497029                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total     0.497029                       # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 121074.979839                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 121074.979839                       # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 195173.434578                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 195173.434578                       # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 192844.554453                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 192844.554453                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 192844.554453                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 192844.554453                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_txs           31                       # Number of DMA read transactions (not PRD).
+system.pc.south_bridge.ide.disks0.dma_read_txs           32                       # Number of DMA read transactions (not PRD).
 system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
 system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
 system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
@@ -967,474 +885,476 @@ system.pc.south_bridge.ide.disks1.dma_read_txs            0
 system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
-system.toL2Bus.throughput                    52370833                       # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq            1836862                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           1836332                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq              7056                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp             7056                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           922959                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq             811                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp            811                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           181042                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          156978                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1050040                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      3684115                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side        38115                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side       140219                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               4912489                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     33600320                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    122621708                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side       135720                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side       527336                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size::total          156885084                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus             268925359                       # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus          127504                       # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy         5157428290                       # Layer occupancy (ticks)
+system.toL2Bus.throughput                    52329028                       # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq            1794981                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           1794440                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq              6370                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp             6370                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           902417                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq             716                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp            716                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           170908                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          147982                       # Transaction distribution
+system.toL2Bus.trans_dist::BadAddressError            2                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1004724                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      3613728                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side        35279                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side       136436                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               4790167                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     32150080                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    119808027                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side       127712                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side       515032                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size::total          152600851                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus             268845429                       # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus          114024                       # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy         5038805323                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.1                       # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy          1008000                       # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy           931500                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        2365130940                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        2262930320                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        4803653283                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        4696428413                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy          21171206                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy          19332464                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy          74417261                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy          72173756                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
-system.iobus.throughput                       1276721                       # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq               150736                       # Transaction distribution
-system.iobus.trans_dist::ReadResp              150736                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               30161                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              30161                       # Transaction distribution
-system.iobus.trans_dist::MessageReq               957                       # Transaction distribution
-system.iobus.trans_dist::MessageResp              957                       # Transaction distribution
+system.iobus.throughput                       1276348                       # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq               149977                       # Transaction distribution
+system.iobus.trans_dist::ReadResp              149977                       # Transaction distribution
+system.iobus.trans_dist::WriteReq               28411                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              28411                       # Transaction distribution
+system.iobus.trans_dist::MessageReq               885                       # Transaction distribution
+system.iobus.trans_dist::MessageResp              885                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           36                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio            2                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio         5986                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio         5752                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf            2                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio         1160                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio           46                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio           16                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio          582                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio           50                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio           24                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio           18                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio       287076                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio          580                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio       287032                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio          332                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio           86                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio        15082                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio        13448                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio            4                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio         2064                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total       312158                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        49636                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        49636                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         1914                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         1914                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  363708                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total       309432                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        47344                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        47344                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         1770                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         1770                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  358546                       # Packet count per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           18                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            1                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         3380                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         3245                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf            4                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio          580                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio           23                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio            8                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio          291                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio           25                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio           12                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio            9                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio       143538                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio         1160                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio       143516                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio          664                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio           43                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio         7541                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio         6724                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio            2                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio         4128                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total       160435                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      1576592                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total      1576592                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3828                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total         3828                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total              1740855                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus                 6559098                       # Total data (bytes)
-system.iobus.reqLayer0.occupancy              2255722                       # Layer occupancy (ticks)
+system.iobus.tot_pkt_size_system.bridge.master::total       158682                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      1503808                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total      1503808                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3540                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total         3540                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::total              1666030                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus                 6560144                       # Total data (bytes)
+system.iobus.reqLayer0.occupancy              2116890                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                28000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer2.occupancy                 2000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer3.occupancy              4948000                       # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy              4753000                       # Layer occupancy (ticks)
 system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer4.occupancy                 1000                       # Layer occupancy (ticks)
 system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer5.occupancy               758000                       # Layer occupancy (ticks)
+system.iobus.reqLayer5.occupancy               383000                       # Layer occupancy (ticks)
 system.iobus.reqLayer5.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer6.occupancy                39000                       # Layer occupancy (ticks)
+system.iobus.reqLayer6.occupancy                42000                       # Layer occupancy (ticks)
 system.iobus.reqLayer6.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer7.occupancy                15000                       # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy                21000                       # Layer occupancy (ticks)
 system.iobus.reqLayer7.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer8.occupancy                18000                       # Layer occupancy (ticks)
 system.iobus.reqLayer8.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer9.occupancy            143539000                       # Layer occupancy (ticks)
+system.iobus.reqLayer9.occupancy            143517000                       # Layer occupancy (ticks)
 system.iobus.reqLayer9.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer10.occupancy              458000                       # Layer occupancy (ticks)
+system.iobus.reqLayer10.occupancy              264000                       # Layer occupancy (ticks)
 system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer11.occupancy               86000                       # Layer occupancy (ticks)
 system.iobus.reqLayer11.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer13.occupancy            11248000                       # Layer occupancy (ticks)
+system.iobus.reqLayer13.occupancy            10048000                       # Layer occupancy (ticks)
 system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer17.occupancy                4000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer18.occupancy           218954798                       # Layer occupancy (ticks)
+system.iobus.reqLayer18.occupancy           209101042                       # Layer occupancy (ticks)
 system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer19.occupancy             1032000                       # Layer occupancy (ticks)
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy           306061000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy           303949000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            29747501                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            28759251                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer2.occupancy              957000                       # Layer occupancy (ticks)
+system.iobus.respLayer2.occupancy              885000                       # Layer occupancy (ticks)
 system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
 system.cpu0.apic_clk_domain.clock                8000                       # Clock period in ticks
-system.cpu0.numCycles                      1152461068                       # number of cpu cycles simulated
+system.cpu0.numCycles                      1144797664                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   71542662                       # Number of instructions committed
-system.cpu0.committedOps                    145644721                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses            133686522                       # Number of integer alu accesses
+system.cpu0.committedInsts                   72999922                       # Number of instructions committed
+system.cpu0.committedOps                    148305710                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses            136279674                       # Number of integer alu accesses
 system.cpu0.num_fp_alu_accesses                     0                       # Number of float alu accesses
-system.cpu0.num_func_calls                     963574                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts     14130614                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                   133686522                       # number of integer instructions
+system.cpu0.num_func_calls                    1016299                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts     14345558                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                   136279674                       # number of integer instructions
 system.cpu0.num_fp_insts                            0                       # number of float instructions
-system.cpu0.num_int_register_reads          245609809                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes         114802156                       # number of times the integer registers were written
+system.cpu0.num_int_register_reads          250792350                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes         116890419                       # number of times the integer registers were written
 system.cpu0.num_fp_register_reads                   0                       # number of times the floating registers were read
 system.cpu0.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu0.num_cc_register_reads            83145706                       # number of times the CC registers were read
-system.cpu0.num_cc_register_writes           55494396                       # number of times the CC registers were written
-system.cpu0.num_mem_refs                     13834339                       # number of memory refs
-system.cpu0.num_load_insts                   10142209                       # Number of load instructions
-system.cpu0.num_store_insts                   3692130                       # Number of store instructions
-system.cpu0.num_idle_cycles              1095316733.110107                       # Number of idle cycles
-system.cpu0.num_busy_cycles              57144334.889893                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.049585                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.950415                       # Percentage of idle cycles
-system.cpu0.Branches                         15442715                       # Number of branches fetched
+system.cpu0.num_cc_register_reads            84577193                       # number of times the CC registers were read
+system.cpu0.num_cc_register_writes           56435831                       # number of times the CC registers were written
+system.cpu0.num_mem_refs                     14370687                       # number of memory refs
+system.cpu0.num_load_insts                   10454117                       # Number of load instructions
+system.cpu0.num_store_insts                   3916570                       # Number of store instructions
+system.cpu0.num_idle_cycles              1087719763.352511                       # Number of idle cycles
+system.cpu0.num_busy_cycles              57077900.647489                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.049859                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.950141                       # Percentage of idle cycles
+system.cpu0.Branches                         15728655                       # Number of branches fetched
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu0.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu0.icache.tags.replacements           857108                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          510.816977                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs          128607019                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           857620                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs           149.958046                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle     147466681500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   303.791229                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst   134.865519                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu2.inst    72.160229                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.593342                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst     0.263409                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu2.inst     0.140938                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.997689                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements           853193                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          510.838528                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs          129757026                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           853705                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs           151.992815                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle     147468978000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   295.878537                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst   138.959383                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu2.inst    76.000608                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.577888                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst     0.271405                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu2.inst     0.148439                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.997732                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0           79                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          138                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          295                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0           86                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1          120                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          303                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses        130343050                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses       130343050                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     87032678                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst     38704601                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu2.inst      2869740                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total      128607019                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     87032678                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst     38704601                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu2.inst      2869740                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total       128607019                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     87032678                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst     38704601                       # number of overall hits
-system.cpu0.icache.overall_hits::cpu2.inst      2869740                       # number of overall hits
-system.cpu0.icache.overall_hits::total      128607019                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       332599                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst       151109                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu2.inst       394689                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       878397                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       332599                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst       151109                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu2.inst       394689                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        878397                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       332599                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst       151109                       # number of overall misses
-system.cpu0.icache.overall_misses::cpu2.inst       394689                       # number of overall misses
-system.cpu0.icache.overall_misses::total       878397                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   2111983250                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   5690259841                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total   7802243091                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst   2111983250                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu2.inst   5690259841                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total   7802243091                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst   2111983250                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu2.inst   5690259841                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total   7802243091                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     87365277                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst     38855710                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu2.inst      3264429                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total    129485416                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     87365277                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst     38855710                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu2.inst      3264429                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total    129485416                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     87365277                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst     38855710                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu2.inst      3264429                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total    129485416                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.003807                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.003889                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.120906                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.006784                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.003807                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst     0.003889                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu2.inst     0.120906                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.006784                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.003807                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst     0.003889                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu2.inst     0.120906                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.006784                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13976.555003                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14417.072280                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total  8882.365367                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13976.555003                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14417.072280                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total  8882.365367                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13976.555003                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14417.072280                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total  8882.365367                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs         6122                       # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses        131484548                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses       131484548                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     88843413                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst     38144708                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu2.inst      2768905                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total      129757026                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     88843413                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst     38144708                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu2.inst      2768905                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total       129757026                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     88843413                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst     38144708                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu2.inst      2768905                       # number of overall hits
+system.cpu0.icache.overall_hits::total      129757026                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       351339                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst       141332                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu2.inst       381133                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       873804                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       351339                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst       141332                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu2.inst       381133                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        873804                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       351339                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst       141332                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu2.inst       381133                       # number of overall misses
+system.cpu0.icache.overall_misses::total       873804                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst   1941508750                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu2.inst   5443063468                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total   7384572218                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst   1941508750                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu2.inst   5443063468                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total   7384572218                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst   1941508750                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu2.inst   5443063468                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total   7384572218                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     89194752                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst     38286040                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu2.inst      3150038                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total    130630830                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     89194752                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst     38286040                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu2.inst      3150038                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total    130630830                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     89194752                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst     38286040                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu2.inst      3150038                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total    130630830                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.003939                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst     0.003691                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu2.inst     0.120993                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.006689                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.003939                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst     0.003691                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu2.inst     0.120993                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.006689                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.003939                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst     0.003691                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu2.inst     0.120993                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.006689                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13737.219809                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14281.270496                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total  8451.062501                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13737.219809                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14281.270496                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total  8451.062501                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13737.219809                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14281.270496                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total  8451.062501                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs         4847                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              230                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              200                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs    26.617391                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs    24.235000                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        20763                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        20763                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu2.inst        20763                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        20763                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu2.inst        20763                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        20763                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       151109                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       373926                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       525035                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst       151109                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu2.inst       373926                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       525035                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst       151109                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu2.inst       373926                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       525035                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   1808966750                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   4711215798                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total   6520182548                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   1808966750                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   4711215798                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total   6520182548                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   1808966750                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   4711215798                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total   6520182548                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.003889                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.114546                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.004055                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.003889                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.114546                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.004055                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.003889                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.114546                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.004055                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11971.270738                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12599.326599                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12418.567425                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11971.270738                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12599.326599                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12418.567425                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11971.270738                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12599.326599                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12418.567425                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst        20086                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        20086                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu2.inst        20086                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        20086                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu2.inst        20086                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        20086                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst       141332                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst       361047                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       502379                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst       141332                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu2.inst       361047                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       502379                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst       141332                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu2.inst       361047                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       502379                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst   1658307250                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst   4510414171                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total   6168721421                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst   1658307250                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst   4510414171                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total   6168721421                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst   1658307250                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst   4510414171                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total   6168721421                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.003691                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.114617                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.003846                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst     0.003691                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst     0.114617                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.003846                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst     0.003691                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst     0.114617                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.003846                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11733.416707                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12492.595621                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12279.019268                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11733.416707                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12492.595621                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12279.019268                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11733.416707                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12492.595621                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12279.019268                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements          1634697                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          511.999455                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           19613816                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          1635209                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            11.994684                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.replacements          1636224                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          511.999323                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           19637131                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          1636736                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            11.997739                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle          7549500                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   200.851253                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data   304.204078                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu2.data     6.944124                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.392288                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data     0.594149                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu2.data     0.013563                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   276.200499                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data   230.134495                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu2.data     5.664329                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.539454                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data     0.449481                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu2.data     0.011063                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_percent::total     0.999999                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0          226                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          259                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           27                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0          259                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1          236                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           17                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         88202622                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        88202622                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data      5007486                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data      2456211                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu2.data      4066814                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total       11530511                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      3548930                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data      1627224                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu2.data      2905330                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       8081484                       # number of WriteReq hits
-system.cpu0.dcache.demand_hits::cpu0.data      8556416                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data      4083435                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu2.data      6972144                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        19611995                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data      8556416                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data      4083435                       # number of overall hits
-system.cpu0.dcache.overall_hits::cpu2.data      6972144                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       19611995                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       521438                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data       227972                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu2.data       965445                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      1714855                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       139893                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data        58525                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu2.data       116582                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       315000                       # number of WriteReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       661331                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data       286497                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu2.data      1082027                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       2029855                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       661331                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data       286497                       # number of overall misses
-system.cpu0.dcache.overall_misses::cpu2.data      1082027                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      2029855                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   3246346508                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu2.data  15541427611                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  18787774119                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   2199408780                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu2.data   3682017546                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total   5881426326                       # number of WriteReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data   5445755288                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu2.data  19223445157                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  24669200445                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data   5445755288                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu2.data  19223445157                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  24669200445                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      5528924                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data      2684183                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu2.data      5032259                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total     13245366                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      3688823                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data      1685749                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu2.data      3021912                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      8396484                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data      9217747                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data      4369932                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu2.data      8054171                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     21641850                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data      9217747                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data      4369932                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu2.data      8054171                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     21641850                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.094311                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.084932                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.191851                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.129468                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.037923                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.034718                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.038579                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.037516                       # miss rate for WriteReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.071745                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data     0.065561                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu2.data     0.134344                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.093793                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.071745                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data     0.065561                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu2.data     0.134344                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.093793                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14240.110663                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16097.683049                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 10955.896632                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37580.671166                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 31583.070680                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 18671.194686                       # average WriteReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 19008.070898                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17766.141840                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 12153.183575                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19008.070898                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 17766.141840                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 12153.183575                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs       177963                       # number of cycles access was blocked
+system.cpu0.dcache.tags.tag_accesses         88232962                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        88232962                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data      5302290                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data      2343807                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu2.data      3905907                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total       11552004                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      3762855                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data      1548346                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu2.data      2772193                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       8083394                       # number of WriteReq hits
+system.cpu0.dcache.demand_hits::cpu0.data      9065145                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data      3892153                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu2.data      6678100                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        19635398                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data      9065145                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data      3892153                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu2.data      6678100                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       19635398                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       536567                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data       225063                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu2.data       936224                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      1697854                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       149749                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data        58088                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu2.data       107958                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       315795                       # number of WriteReq misses
+system.cpu0.dcache.demand_misses::cpu0.data       686316                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data       283151                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu2.data      1044182                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       2013649                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data       686316                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data       283151                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu2.data      1044182                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      2013649                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data   3188254504                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu2.data  14965969569                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  18154224073                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data   2125358780                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu2.data   3377412183                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total   5502770963                       # number of WriteReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data   5313613284                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu2.data  18343381752                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  23656995036                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data   5313613284                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu2.data  18343381752                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  23656995036                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      5838857                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data      2568870                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu2.data      4842131                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total     13249858                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      3912604                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data      1606434                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu2.data      2880151                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      8399189                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data      9751461                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data      4175304                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu2.data      7722282                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     21649047                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data      9751461                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data      4175304                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu2.data      7722282                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     21649047                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.091896                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data     0.087612                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu2.data     0.193350                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.128141                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.038273                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data     0.036160                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu2.data     0.037483                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.037598                       # miss rate for WriteReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.070381                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data     0.067816                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu2.data     0.135217                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.093013                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.070381                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data     0.067816                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu2.data     0.135217                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.093013                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14166.053523                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15985.458148                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 10692.452987                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 36588.603154                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 31284.501223                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 17425.136443                       # average WriteReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 18766.005714                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17567.226549                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 11748.321101                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 18766.005714                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 17567.226549                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 11748.321101                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs       168342                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs            11847                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs            11795                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    15.021778                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    14.272319                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks      1544272                       # number of writebacks
-system.cpu0.dcache.writebacks::total          1544272                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       375629                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       375629                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data        17363                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total        17363                       # number of WriteReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu2.data       392992                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total       392992                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu2.data       392992                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total       392992                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       227972                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       589816                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       817788                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        58525                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        99219                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       157744                       # number of WriteReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data       286497                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu2.data       689035                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       975532                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data       286497                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu2.data       689035                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       975532                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2789367492                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   8524003053                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  11313370545                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   2071430220                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   3281431451                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   5352861671                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   4860797712                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data  11805434504                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  16666232216                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   4860797712                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data  11805434504                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  16666232216                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  30612926500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data  33246502500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  63859429000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    519657500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    815190500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1334848000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data  31132584000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data  34061693000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  65194277000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.084932                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.117207                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.061741                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.034718                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.032833                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.018787                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.065561                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.085550                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.045076                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.065561                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.085550                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.045076                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12235.570561                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14451.969857                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13834.111707                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35393.937975                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 33072.611607                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33933.852768                       # average WriteReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 16966.312778                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17133.287139                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17084.249636                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16966.312778                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17133.287139                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17084.249636                       # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks      1545523                       # number of writebacks
+system.cpu0.dcache.writebacks::total          1545523                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data       357871                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       357871                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data        17395                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total        17395                       # number of WriteReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu2.data       375266                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total       375266                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu2.data       375266                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total       375266                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data       225063                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data       578353                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       803416                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data        58088                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data        90563                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       148651                       # number of WriteReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data       283151                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu2.data       668916                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       952067                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data       283151                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu2.data       668916                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       952067                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data   2737161496                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data   8309689554                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  11046851050                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data   1998659220                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data   2996226317                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4994885537                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data   4735820716                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data  11305915871                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  16041736587                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data   4735820716                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data  11305915871                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  16041736587                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data  30467694000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data  33225580500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  63693274500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    404660000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data    790542000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1195202000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data  30872354000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data  34016122500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  64888476500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.087612                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.119442                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.060636                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.036160                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.031444                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.017698                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data     0.067816                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data     0.086622                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.043977                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data     0.067816                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data     0.086622                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.043977                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12161.756913                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14367.850697                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13749.851945                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34407.437336                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 33084.441958                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33601.425735                       # average WriteReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 16725.424653                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16901.846975                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16849.377814                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16725.424653                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16901.846975                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16849.377814                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -1445,307 +1365,307 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.numCycles                      2606011326                       # number of cpu cycles simulated
+system.cpu1.numCycles                      2608015730                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   35164948                       # Number of instructions committed
-system.cpu1.committedOps                     68413270                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             63529188                       # Number of integer alu accesses
+system.cpu1.committedInsts                   34716890                       # Number of instructions committed
+system.cpu1.committedOps                     67541836                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             62669042                       # Number of integer alu accesses
 system.cpu1.num_fp_alu_accesses                     0                       # Number of float alu accesses
-system.cpu1.num_func_calls                     457891                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      6471423                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    63529188                       # number of integer instructions
+system.cpu1.num_func_calls                     430919                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      6413966                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    62669042                       # number of integer instructions
 system.cpu1.num_fp_insts                            0                       # number of float instructions
-system.cpu1.num_int_register_reads          117257194                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          54850904                       # number of times the integer registers were written
+system.cpu1.num_int_register_reads          115548964                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          54160900                       # number of times the integer registers were written
 system.cpu1.num_fp_register_reads                   0                       # number of times the floating registers were read
 system.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu1.num_cc_register_reads            36014934                       # number of times the CC registers were read
-system.cpu1.num_cc_register_writes           26882843                       # number of times the CC registers were written
-system.cpu1.num_mem_refs                      4560424                       # number of memory refs
-system.cpu1.num_load_insts                    2872895                       # Number of load instructions
-system.cpu1.num_store_insts                   1687529                       # Number of store instructions
-system.cpu1.num_idle_cycles              2475874291.383945                       # Number of idle cycles
-system.cpu1.num_busy_cycles              130137034.616055                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.049937                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.950063                       # Percentage of idle cycles
-system.cpu1.Branches                          7096172                       # Number of branches fetched
+system.cpu1.num_cc_register_reads            35562537                       # number of times the CC registers were read
+system.cpu1.num_cc_register_writes           26614034                       # number of times the CC registers were written
+system.cpu1.num_mem_refs                      4364452                       # number of memory refs
+system.cpu1.num_load_insts                    2756893                       # Number of load instructions
+system.cpu1.num_store_insts                   1607559                       # Number of store instructions
+system.cpu1.num_idle_cycles              2483429860.768801                       # Number of idle cycles
+system.cpu1.num_busy_cycles              124585869.231199                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.047770                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.952230                       # Percentage of idle cycles
+system.cpu1.Branches                          7003911                       # Number of branches fetched
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu2.branchPred.lookups               29049356                       # Number of BP lookups
-system.cpu2.branchPred.condPredicted         29049356                       # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect           330189                       # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups            26516680                       # Number of BTB lookups
-system.cpu2.branchPred.BTBHits               25920061                       # Number of BTB hits
+system.cpu2.branchPred.lookups               28782114                       # Number of BP lookups
+system.cpu2.branchPred.condPredicted         28782114                       # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect           316524                       # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups            26348266                       # Number of BTB lookups
+system.cpu2.branchPred.BTBHits               25752004                       # Number of BTB hits
 system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct            97.750024                       # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS                 553809                       # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect             66194                       # Number of incorrect RAS predictions.
-system.cpu2.numCycles                       157465018                       # number of cpu cycles simulated
+system.cpu2.branchPred.BTBHitPct            97.736997                       # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS                 537542                       # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect             63717                       # Number of incorrect RAS predictions.
+system.cpu2.numCycles                       155552038                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles          10014190                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts                     143120520                       # Number of instructions fetch has processed
-system.cpu2.fetch.Branches                   29049356                       # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches          26473870                       # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles                     54776048                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles                1540394                       # Number of cycles fetch has spent squashing
-system.cpu2.fetch.TlbCycles                     78659                       # Number of cycles fetch has spent waiting for tlb
-system.cpu2.fetch.BlockedCycles              25463388                       # Number of cycles fetch has spent blocked
-system.cpu2.fetch.MiscStallCycles                3574                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.PendingDrainCycles             6100                       # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu2.fetch.PendingTrapStallCycles        25165                       # Number of stall cycles due to pending traps
-system.cpu2.fetch.IcacheWaitRetryStallCycles          454                       # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines                  3264432                       # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes               152504                       # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.ItlbSquashes                   2125                       # Number of outstanding ITLB misses that were squashed
-system.cpu2.fetch.rateDist::samples          91560833                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean             3.080398                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev            3.405930                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.icacheStallCycles           9686701                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts                     141772190                       # Number of instructions fetch has processed
+system.cpu2.fetch.Branches                   28782114                       # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches          26289546                       # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles                     54340809                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles                1470890                       # Number of cycles fetch has spent squashing
+system.cpu2.fetch.TlbCycles                     70055                       # Number of cycles fetch has spent waiting for tlb
+system.cpu2.fetch.BlockedCycles              24627328                       # Number of cycles fetch has spent blocked
+system.cpu2.fetch.MiscStallCycles                4722                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.PendingDrainCycles             7901                       # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu2.fetch.PendingTrapStallCycles        23768                       # Number of stall cycles due to pending traps
+system.cpu2.fetch.IcacheWaitRetryStallCycles          376                       # Number of stall cycles due to full MSHR
+system.cpu2.fetch.CacheLines                  3150040                       # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes               144648                       # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.ItlbSquashes                   2015                       # Number of outstanding ITLB misses that were squashed
+system.cpu2.fetch.rateDist::samples          89899907                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean             3.110146                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev            3.408280                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0                36927513     40.33%     40.33% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1                  611138      0.67%     41.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2                23812381     26.01%     67.01% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3                  328703      0.36%     67.36% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4                  619714      0.68%     68.04% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5                  832275      0.91%     68.95% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6                  355282      0.39%     69.34% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7                  540716      0.59%     69.93% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8                27533111     30.07%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0                35694732     39.70%     39.70% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1                  594255      0.66%     40.37% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2                23712499     26.38%     66.74% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3                  314699      0.35%     67.09% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4                  599600      0.67%     67.76% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5                  812421      0.90%     68.66% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6                  338881      0.38%     69.04% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7                  517837      0.58%     69.62% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8                27314983     30.38%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total            91560833                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate                 0.184481                       # Number of branch fetches per cycle
-system.cpu2.fetch.rate                       0.908904                       # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles                11521398                       # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles             24357574                       # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles                 32837645                       # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles              1316376                       # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles               1196608                       # Number of cycles decode is squashing
-system.cpu2.decode.DecodedInsts             281192085                       # Number of instructions handled by decode
+system.cpu2.fetch.rateDist::total            89899907                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate                 0.185032                       # Number of branch fetches per cycle
+system.cpu2.fetch.rate                       0.911413                       # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles                11154829                       # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles             23540580                       # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles                 30801007                       # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles              1287318                       # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles               1141583                       # Number of cycles decode is squashing
+system.cpu2.decode.DecodedInsts             278785410                       # Number of instructions handled by decode
 system.cpu2.decode.SquashedInsts                   11                       # Number of squashed instructions handled by decode
-system.cpu2.rename.SquashCycles               1196608                       # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles                12539536                       # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles               14626708                       # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles       4503596                       # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles                 32964525                       # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles              5398696                       # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts             280154725                       # Number of instructions processed by rename
-system.cpu2.rename.ROBFullEvents                 7234                       # Number of times rename has blocked due to ROB full
-system.cpu2.rename.IQFullEvents               2491982                       # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LSQFullEvents              2219031                       # Number of times rename has blocked due to LSQ full
-system.cpu2.rename.RenamedOperands          334708153                       # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups            610319016                       # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups       374834819                       # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups               56                       # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps            324049688                       # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps                10658465                       # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts            153621                       # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts        154561                       # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts                 11685330                       # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads             6409686                       # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores            3556417                       # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads           350066                       # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores          288206                       # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded                 278401976                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded             420214                       # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued                276663998                       # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued            65469                       # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined        7519016                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined     11586940                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved         57670                       # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples     91560833                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean        3.021641                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev       2.405034                       # Number of insts issued each cycle
+system.cpu2.rename.SquashCycles               1141583                       # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles                12143079                       # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles               13933433                       # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles       4524497                       # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles                 30930733                       # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles              5252059                       # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts             277791777                       # Number of instructions processed by rename
+system.cpu2.rename.ROBFullEvents                 7238                       # Number of times rename has blocked due to ROB full
+system.cpu2.rename.IQFullEvents               2464468                       # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LSQFullEvents              2117220                       # Number of times rename has blocked due to LSQ full
+system.cpu2.rename.RenamedOperands          331976691                       # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups            604531856                       # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups       371338716                       # Number of integer rename lookups
+system.cpu2.rename.fp_rename_lookups               38                       # Number of floating rename lookups
+system.cpu2.rename.CommittedMaps            321781805                       # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps                10194886                       # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts            148461                       # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts        149473                       # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts                 11392573                       # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads             6171654                       # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores            3395563                       # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads           345995                       # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores          292325                       # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded                 276091246                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded             414813                       # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued                274477250                       # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued            60541                       # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined        7173454                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined     11041443                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved         56132                       # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples     89899907                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean        3.053143                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev       2.400877                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0           27548029     30.09%     30.09% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1            6302445      6.88%     36.97% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2            4040687      4.41%     41.38% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3            2809709      3.07%     44.45% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4           25166051     27.49%     71.94% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5            1389542      1.52%     73.46% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6           23947180     26.15%     99.61% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7             301462      0.33%     99.94% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8              55728      0.06%    100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0           26563563     29.55%     29.55% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1            6130901      6.82%     36.37% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2            3934206      4.38%     40.74% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3            2710119      3.01%     43.76% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4           25036419     27.85%     71.61% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5            1342117      1.49%     73.10% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6           23840310     26.52%     99.62% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7             288717      0.32%     99.94% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8              53555      0.06%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total       91560833                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total       89899907                       # Number of insts issued each cycle
 system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu                 136321     35.17%     35.17% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult                   124      0.03%     35.21% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv                      0      0.00%     35.21% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     35.21% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     35.21% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     35.21% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult                   0      0.00%     35.21% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     35.21% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     35.21% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     35.21% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     35.21% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     35.21% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     35.21% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     35.21% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     35.21% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult                    0      0.00%     35.21% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     35.21% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift                   0      0.00%     35.21% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     35.21% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     35.21% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     35.21% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     35.21% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     35.21% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     35.21% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     35.21% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     35.21% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     35.21% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     35.21% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     35.21% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead                194124     50.09%     85.29% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite                56993     14.71%    100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu                 122290     33.50%     33.50% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult                   245      0.07%     33.57% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv                      0      0.00%     33.57% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd                    0      0.00%     33.57% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp                    0      0.00%     33.57% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt                    0      0.00%     33.57% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult                   0      0.00%     33.57% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv                    0      0.00%     33.57% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%     33.57% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd                     0      0.00%     33.57% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%     33.57% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu                     0      0.00%     33.57% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp                     0      0.00%     33.57% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt                     0      0.00%     33.57% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc                    0      0.00%     33.57% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult                    0      0.00%     33.57% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%     33.57% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift                   0      0.00%     33.57% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%     33.57% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%     33.57% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%     33.57% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%     33.57% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%     33.57% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%     33.57% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%     33.57% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%     33.57% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%     33.57% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%     33.57% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%     33.57% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead                189949     52.03%     85.60% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite                52573     14.40%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu2.iq.FU_type_0::No_OpClass            81905      0.03%      0.03% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu            266468718     96.31%     96.34% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult               56660      0.02%     96.37% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv                48242      0.02%     96.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     96.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     96.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     96.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     96.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     96.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     96.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     96.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     96.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     96.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     96.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     96.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     96.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     96.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     96.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     96.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     96.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     96.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     96.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     96.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     96.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     96.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     96.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     96.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     96.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     96.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead             6674536      2.41%     98.79% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite            3333937      1.21%    100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::No_OpClass            80536      0.03%      0.03% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu            264658650     96.42%     96.45% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult               54855      0.02%     96.47% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv                48402      0.02%     96.49% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     96.49% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     96.49% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     96.49% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     96.49% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     96.49% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     96.49% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     96.49% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     96.49% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     96.49% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     96.49% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     96.49% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     96.49% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     96.49% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     96.49% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     96.49% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     96.49% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     96.49% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     96.49% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     96.49% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     96.49% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     96.49% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     96.49% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     96.49% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     96.49% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.49% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     96.49% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead             6455691      2.35%     98.84% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite            3179116      1.16%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total             276663998                       # Type of FU issued
-system.cpu2.iq.rate                          1.756987                       # Inst issue rate
-system.cpu2.iq.fu_busy_cnt                     387562                       # FU busy when requested
-system.cpu2.iq.fu_busy_rate                  0.001401                       # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads         645385259                       # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes        286345237                       # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses    275267423                       # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads                 94                       # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes               106                       # Number of floating instruction queue writes
-system.cpu2.iq.fp_inst_queue_wakeup_accesses           22                       # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses             276969613                       # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses                     42                       # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads          657734                       # Number of loads that had data forwarded from stores
+system.cpu2.iq.FU_type_0::total             274477250                       # Type of FU issued
+system.cpu2.iq.rate                          1.764537                       # Inst issue rate
+system.cpu2.iq.fu_busy_cnt                     365057                       # FU busy when requested
+system.cpu2.iq.fu_busy_rate                  0.001330                       # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads         639321511                       # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes        283683445                       # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses    273115126                       # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.fp_inst_queue_reads                 61                       # Number of floating instruction queue reads
+system.cpu2.iq.fp_inst_queue_writes                70                       # Number of floating instruction queue writes
+system.cpu2.iq.fp_inst_queue_wakeup_accesses           18                       # Number of floating instruction queue wakeup accesses
+system.cpu2.iq.int_alu_accesses             274761742                       # Number of integer alu accesses
+system.cpu2.iq.fp_alu_accesses                     29                       # Number of floating point alu accesses
+system.cpu2.iew.lsq.thread0.forwLoads          634301                       # Number of loads that had data forwarded from stores
 system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads      1052819                       # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses         6947                       # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation         4672                       # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores       529632                       # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedLoads      1002623                       # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses         6718                       # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation         4440                       # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores       510444                       # Number of stores squashed
 system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads       656268                       # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked        10631                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu2.iew.lsq.thread0.rescheduledLoads       656391                       # Number of loads that were rescheduled
+system.cpu2.iew.lsq.thread0.cacheBlocked        10280                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles               1196608                       # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles                9811775                       # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles               820688                       # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts          278822190                       # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts            75669                       # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts              6409704                       # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts             3556417                       # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts            239796                       # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents                634227                       # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents                 4101                       # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents          4672                       # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect        184871                       # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect       190702                       # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts              375573                       # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts            276137017                       # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts              6556879                       # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts           526981                       # Number of squashed instructions skipped in execute
+system.cpu2.iew.iewSquashCycles               1141583                       # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles                9227965                       # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles               815382                       # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts          276506059                       # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts            71664                       # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts              6171654                       # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts             3395563                       # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts            234992                       # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents                633068                       # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewLSQFullEvents                 3849                       # Number of times the LSQ has become full, causing a stall
+system.cpu2.iew.memOrderViolationEvents          4440                       # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect        176570                       # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect       182317                       # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts              358887                       # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts            273973436                       # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts              6342946                       # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts           503814                       # Number of squashed instructions skipped in execute
 system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
 system.cpu2.iew.exec_nop                            0                       # number of nop insts executed
-system.cpu2.iew.exec_refs                     9821909                       # number of memory reference insts executed
-system.cpu2.iew.exec_branches                28090459                       # Number of branches executed
-system.cpu2.iew.exec_stores                   3265030                       # Number of stores executed
-system.cpu2.iew.exec_rate                    1.753640                       # Inst execution rate
-system.cpu2.iew.wb_sent                     275979435                       # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count                    275267445                       # cumulative count of insts written-back
-system.cpu2.iew.wb_producers                214496489                       # num instructions producing a value
-system.cpu2.iew.wb_consumers                350700107                       # num instructions consuming a value
+system.cpu2.iew.exec_refs                     9455734                       # number of memory reference insts executed
+system.cpu2.iew.exec_branches                27867681                       # Number of branches executed
+system.cpu2.iew.exec_stores                   3112788                       # Number of stores executed
+system.cpu2.iew.exec_rate                    1.761298                       # Inst execution rate
+system.cpu2.iew.wb_sent                     273823666                       # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count                    273115144                       # cumulative count of insts written-back
+system.cpu2.iew.wb_producers                212986974                       # num instructions producing a value
+system.cpu2.iew.wb_consumers                348231532                       # num instructions consuming a value
 system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate                      1.748118                       # insts written-back per cycle
-system.cpu2.iew.wb_fanout                    0.611624                       # average fanout of values written-back
+system.cpu2.iew.wb_rate                      1.755780                       # insts written-back per cycle
+system.cpu2.iew.wb_fanout                    0.611625                       # average fanout of values written-back
 system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts        7834345                       # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls         362544                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts           332977                       # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples     90364225                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean     2.998816                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev     2.871519                       # Number of insts commited each cycle
+system.cpu2.commit.commitSquashedInsts        7474898                       # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls         358681                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts           318992                       # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples     88758324                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean     3.031021                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev     2.870805                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0     32381210     35.83%     35.83% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1      4545159      5.03%     40.86% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2      1281676      1.42%     42.28% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3     24783522     27.43%     69.71% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4       890698      0.99%     70.69% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5       597656      0.66%     71.36% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6       358639      0.40%     71.75% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7     23381642     25.87%     97.63% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8      2144023      2.37%    100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0     31301057     35.27%     35.27% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1      4393147      4.95%     40.22% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2      1229186      1.38%     41.60% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3     24655081     27.78%     69.38% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4       868070      0.98%     70.36% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5       585819      0.66%     71.02% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6       347474      0.39%     71.41% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7     23302544     26.25%     97.66% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8      2075946      2.34%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total     90364225                       # Number of insts commited each cycle
-system.cpu2.commit.committedInsts           137308621                       # Number of instructions committed
-system.cpu2.commit.committedOps             270985661                       # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total     88758324                       # Number of insts commited each cycle
+system.cpu2.commit.committedInsts           136214259                       # Number of instructions committed
+system.cpu2.commit.committedOps             269028357                       # Number of ops (including micro ops) committed
 system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu2.commit.refs                       8383670                       # Number of memory references committed
-system.cpu2.commit.loads                      5356885                       # Number of loads committed
-system.cpu2.commit.membars                     165489                       # Number of memory barriers committed
-system.cpu2.commit.branches                  27738642                       # Number of branches committed
+system.cpu2.commit.refs                       8054150                       # Number of memory references committed
+system.cpu2.commit.loads                      5169031                       # Number of loads committed
+system.cpu2.commit.membars                     165004                       # Number of memory barriers committed
+system.cpu2.commit.branches                  27530478                       # Number of branches committed
 system.cpu2.commit.fp_insts                         0                       # Number of committed floating point instructions.
-system.cpu2.commit.int_insts                247503684                       # Number of committed integer instructions.
-system.cpu2.commit.function_calls              442390                       # Number of function calls committed.
-system.cpu2.commit.bw_lim_events              2144023                       # number cycles where commit BW limit reached
+system.cpu2.commit.int_insts                245624895                       # Number of committed integer instructions.
+system.cpu2.commit.function_calls              430032                       # Number of function calls committed.
+system.cpu2.commit.bw_lim_events              2075946                       # number cycles where commit BW limit reached
 system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu2.rob.rob_reads                   367011505                       # The number of ROB reads
-system.cpu2.rob.rob_writes                  558841004                       # The number of ROB writes
-system.cpu2.timesIdled                         481956                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles                       65904185                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles                  4905068069                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts                  137308621                       # Number of Instructions Simulated
-system.cpu2.committedOps                    270985661                       # Number of Ops (including micro ops) Simulated
-system.cpu2.committedInsts_total            137308621                       # Number of Instructions Simulated
-system.cpu2.cpi                              1.146796                       # CPI: Cycles Per Instruction
-system.cpu2.cpi_total                        1.146796                       # CPI: Total CPI of All Threads
-system.cpu2.ipc                              0.871994                       # IPC: Instructions Per Cycle
-system.cpu2.ipc_total                        0.871994                       # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads               367544012                       # number of integer regfile reads
-system.cpu2.int_regfile_writes              220503659                       # number of integer regfile writes
-system.cpu2.fp_regfile_reads                    72990                       # number of floating regfile reads
-system.cpu2.fp_regfile_writes                   72968                       # number of floating regfile writes
-system.cpu2.cc_regfile_reads                140406201                       # number of cc regfile reads
-system.cpu2.cc_regfile_writes               108013944                       # number of cc regfile writes
-system.cpu2.misc_regfile_reads               89640596                       # number of misc regfile reads
-system.cpu2.misc_regfile_writes                136839                       # number of misc regfile writes
+system.cpu2.rob.rob_reads                   363157720                       # The number of ROB reads
+system.cpu2.rob.rob_writes                  554152180                       # The number of ROB writes
+system.cpu2.timesIdled                         477715                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles                       65652131                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles                  4906975665                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts                  136214259                       # Number of Instructions Simulated
+system.cpu2.committedOps                    269028357                       # Number of Ops (including micro ops) Simulated
+system.cpu2.committedInsts_total            136214259                       # Number of Instructions Simulated
+system.cpu2.cpi                              1.141966                       # CPI: Cycles Per Instruction
+system.cpu2.cpi_total                        1.141966                       # CPI: Total CPI of All Threads
+system.cpu2.ipc                              0.875683                       # IPC: Instructions Per Cycle
+system.cpu2.ipc_total                        0.875683                       # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads               364409735                       # number of integer regfile reads
+system.cpu2.int_regfile_writes              218808578                       # number of integer regfile writes
+system.cpu2.fp_regfile_reads                    73042                       # number of floating regfile reads
+system.cpu2.fp_regfile_writes                   73024                       # number of floating regfile writes
+system.cpu2.cc_regfile_reads                139320542                       # number of cc regfile reads
+system.cpu2.cc_regfile_writes               107246688                       # number of cc regfile writes
+system.cpu2.misc_regfile_reads               88724841                       # number of misc regfile reads
+system.cpu2.misc_regfile_writes                132896                       # number of misc regfile writes
 system.cpu2.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu2.kern.inst.quiesce                       0                       # number of quiesce instructions executed
 
index 8c91cbc4e6b13c2657e7f5ad4ad93de6c38d2afc..7e42f0daefeb3dd828c301967c53e4fe1a9760b3 100644 (file)
@@ -1,56 +1,56 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.026912                       # Number of seconds simulated
-sim_ticks                                 26911921000                       # Number of ticks simulated
-final_tick                                26911921000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.026923                       # Number of seconds simulated
+sim_ticks                                 26922512500                       # Number of ticks simulated
+final_tick                                26922512500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 176190                       # Simulator instruction rate (inst/s)
-host_op_rate                                   177456                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               52341651                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 402844                       # Number of bytes of host memory used
-host_seconds                                   514.16                       # Real time elapsed on the host
+host_inst_rate                                 143955                       # Simulator instruction rate (inst/s)
+host_op_rate                                   144989                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               42782119                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 446112                       # Number of bytes of host memory used
+host_seconds                                   629.29                       # Real time elapsed on the host
 sim_insts                                    90589798                       # Number of instructions simulated
 sim_ops                                      91240351                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             45504                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data            947776                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               993280                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        45504                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           45504                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst                711                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data              14809                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                 15520                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              1690849                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             35217701                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                36908551                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         1690849                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            1690849                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             1690849                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            35217701                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               36908551                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                         15520                       # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst             45248                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data            947648                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               992896                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        45248                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           45248                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                707                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data              14807                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                 15514                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              1680675                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             35199092                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                36879767                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1680675                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1680675                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             1680675                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            35199092                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               36879767                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                         15514                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                       15520                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                       15514                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                   993280                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                   992896                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                    993280                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                    992896                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              1                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                 989                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                 988                       # Per bank write bursts
 system.physmem.perBankRdBursts::1                 886                       # Per bank write bursts
 system.physmem.perBankRdBursts::2                 942                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                1029                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                1049                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                1028                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                1050                       # Per bank write bursts
 system.physmem.perBankRdBursts::5                1105                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                1079                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                1079                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                1078                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                1078                       # Per bank write bursts
 system.physmem.perBankRdBursts::8                1024                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                 959                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                 956                       # Per bank write bursts
 system.physmem.perBankRdBursts::10                938                       # Per bank write bursts
 system.physmem.perBankRdBursts::11                899                       # Per bank write bursts
 system.physmem.perBankRdBursts::12                904                       # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     26911727500                       # Total gap between requests
+system.physmem.totGap                     26922312500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                   15520                       # Read request sizes (log2)
+system.physmem.readPktSize::6                   15514                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -90,10 +90,10 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     11175                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      4158                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       167                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        13                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                     10767                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      4517                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       211                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        12                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         4                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
@@ -154,167 +154,104 @@ system.physmem.wrQLenPdf::28                        0                       # Wh
 system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          622                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean     1591.562701                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     476.433802                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev    2197.906875                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64-65            160     25.72%     25.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-129           68     10.93%     36.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192-193           41      6.59%     43.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-257           21      3.38%     46.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320-321           13      2.09%     48.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-385            6      0.96%     49.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448-449           27      4.34%     54.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-513           12      1.93%     55.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576-577            5      0.80%     56.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-641           10      1.61%     58.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704-705            3      0.48%     58.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-769            4      0.64%     59.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832-833            5      0.80%     60.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-897            8      1.29%     61.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960-961            3      0.48%     62.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1025            3      0.48%     62.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088-1089            6      0.96%     63.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152-1153            2      0.32%     63.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216-1217            2      0.32%     64.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280-1281            3      0.48%     64.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344-1345            2      0.32%     64.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408-1409            4      0.64%     65.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472-1473            6      0.96%     66.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536-1537           19      3.05%     69.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600-1601            6      0.96%     70.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664-1665            6      0.96%     71.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1792-1793            3      0.48%     72.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856-1857            3      0.48%     72.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984-1985            1      0.16%     72.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2048-2049            6      0.96%     73.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112-2113            2      0.32%     73.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2176-2177            6      0.96%     74.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2304-2305            2      0.32%     75.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2368-2369            1      0.16%     75.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2496-2497            3      0.48%     75.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2560-2561            1      0.16%     76.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2624-2625            2      0.32%     76.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2688-2689            1      0.16%     76.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2752-2753            5      0.80%     77.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2816-2817            4      0.64%     77.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2944-2945            2      0.32%     78.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3008-3009            3      0.48%     78.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3072-3073            4      0.64%     79.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3136-3137            2      0.32%     79.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3200-3201            2      0.32%     80.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3264-3265            2      0.32%     80.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3392-3393            3      0.48%     80.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3456-3457            1      0.16%     81.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3520-3521            2      0.32%     81.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3584-3585            1      0.16%     81.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3648-3649            3      0.48%     81.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3712-3713            3      0.48%     82.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3776-3777            2      0.32%     82.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3904-3905            1      0.16%     82.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3968-3969            1      0.16%     83.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4032-4033            1      0.16%     83.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4096-4097            3      0.48%     83.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4160-4161            2      0.32%     84.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4224-4225            1      0.16%     84.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4416-4417            3      0.48%     84.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4480-4481            4      0.64%     85.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4544-4545            4      0.64%     86.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4608-4609            1      0.16%     86.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4672-4673            3      0.48%     86.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4736-4737            2      0.32%     86.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4800-4801            2      0.32%     87.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4864-4865            1      0.16%     87.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4928-4929            2      0.32%     87.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4992-4993            1      0.16%     87.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5056-5057            2      0.32%     88.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5120-5121            5      0.80%     89.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5184-5185            3      0.48%     89.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5248-5249            4      0.64%     90.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5376-5377            2      0.32%     90.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5440-5441            6      0.96%     91.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5504-5505            3      0.48%     91.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5568-5569            1      0.16%     92.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5696-5697            1      0.16%     92.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5824-5825            1      0.16%     92.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5888-5889            1      0.16%     92.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6016-6017            3      0.48%     93.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6080-6081            1      0.16%     93.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6144-6145            2      0.32%     93.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6208-6209            1      0.16%     93.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6272-6273            2      0.32%     94.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6336-6337            3      0.48%     94.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6400-6401            1      0.16%     94.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6528-6529            2      0.32%     95.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6592-6593            1      0.16%     95.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6656-6657            3      0.48%     95.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6720-6721            1      0.16%     95.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6784-6785            1      0.16%     95.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6912-6913            1      0.16%     96.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6976-6977            1      0.16%     96.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7040-7041            1      0.16%     96.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7104-7105            2      0.32%     96.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7168-7169            1      0.16%     96.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7424-7425            1      0.16%     97.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7616-7617            1      0.16%     97.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7680-7681            1      0.16%     97.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7744-7745            1      0.16%     97.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7872-7873            1      0.16%     97.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8128-8129            2      0.32%     98.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8192-8193           12      1.93%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            622                       # Bytes accessed per row activation
-system.physmem.totQLat                      103005000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 356453750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     77600000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                   175848750                       # Total ticks spent accessing banks
-system.physmem.avgQLat                        6636.92                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    11330.46                       # Average bank access latency per DRAM burst
+system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples          880                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      935.927273                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     827.602742                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     262.440032                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             41      4.66%      4.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           26      2.95%      7.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           13      1.48%      9.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            4      0.45%      9.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            5      0.57%     10.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            2      0.23%     10.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            2      0.23%     10.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            1      0.11%     10.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          786     89.32%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total            880                       # Bytes accessed per row activation
+system.physmem.totQLat                      108095000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 369557500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     77570000                       # Total ticks spent in databus transfers
+system.physmem.totBankLat                   183892500                       # Total ticks spent accessing banks
+system.physmem.avgQLat                        6967.58                       # Average queueing delay per DRAM burst
+system.physmem.avgBankLat                    11853.33                       # Average bank access latency per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  22967.38                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          36.91                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  23820.90                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          36.88                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       36.91                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       36.88                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.29                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.29                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         0.01                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      14898                       # Number of row buffer hits during reads
+system.physmem.readRowHits                      14141                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   95.99                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   91.15                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                      1734003.06                       # Average gap between requests
-system.physmem.pageHitRate                      95.99                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               0.99                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                     36908551                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq                 982                       # Transaction distribution
-system.membus.trans_dist::ReadResp                982                       # Transaction distribution
+system.physmem.avgGap                      1735355.97                       # Average gap between requests
+system.physmem.pageHitRate                      91.15                       # Row buffer hit rate, read and write combined
+system.physmem.prechargeAllPercent               1.09                       # Percentage of time for which DRAM has all the banks in precharge state
+system.membus.throughput                     36879767                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq                 976                       # Transaction distribution
+system.membus.trans_dist::ReadResp                976                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq                1                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp               1                       # Transaction distribution
 system.membus.trans_dist::ReadExReq             14538                       # Transaction distribution
 system.membus.trans_dist::ReadExResp            14538                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        31042                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  31042                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       993280                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total              993280                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus                 993280                       # Total data (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        31030                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  31030                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       992896                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total              992896                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus                 992896                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy            19254500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy            19225500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          145212249                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy          144897999                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.5                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                26683530                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          22001633                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            843091                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             11366562                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                11283436                       # Number of BTB hits
+system.cpu.branchPred.lookups                26688187                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          22005801                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            842567                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             11378681                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                11285656                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             99.268679                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                   69998                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                165                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             99.182462                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                   69960                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                176                       # Number of incorrect RAS predictions.
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -400,133 +337,133 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  442                       # Number of system calls
-system.cpu.numCycles                         53823843                       # number of cpu cycles simulated
+system.cpu.numCycles                         53845026                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           14173676                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      127895760                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    26683530                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           11353434                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      24037387                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 4765940                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles               11314746                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.icacheStallCycles           14173388                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      127901014                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    26688187                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           11355616                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      24038968                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 4766662                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles               11320590                       # Number of cycles fetch has spent blocked
 system.cpu.fetch.MiscStallCycles                  107                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingTrapStallCycles             8                       # Number of stall cycles due to pending traps
 system.cpu.fetch.IcacheWaitRetryStallCycles           29                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  13845039                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                329540                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples           53432137                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.410093                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.214797                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines                  13845523                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                330018                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples           53440501                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.409803                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.214653                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 29433098     55.09%     55.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  3389468      6.34%     61.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  2029496      3.80%     65.23% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  1553729      2.91%     68.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  1668795      3.12%     71.26% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  2919650      5.46%     76.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  1509735      2.83%     79.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1090422      2.04%     81.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                  9837744     18.41%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 29439765     55.09%     55.09% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  3390250      6.34%     61.43% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  2029247      3.80%     65.23% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  1554755      2.91%     68.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  1667292      3.12%     71.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  2920236      5.46%     76.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  1512043      2.83%     79.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1089860      2.04%     81.59% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                  9837053     18.41%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total             53432137                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.495757                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.376192                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 16937041                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles               9161066                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  22405812                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               1030640                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                3897578                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              4444113                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                  8703                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              126077551                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                 42669                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                3897578                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 18718868                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 3591285                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         186478                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  21552610                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               5485318                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              123153621                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                     8                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 426233                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               4596906                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents             1480                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           143604331                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             536493258                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        499981919                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups               760                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total             53440501                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.495648                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.375354                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 16937222                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles               9166719                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  22408314                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               1029433                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                3898813                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              4444354                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                  8681                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              126084070                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                 42675                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                3898813                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 18718559                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 3593311                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         188330                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  21554671                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               5486817                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              123168222                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                    14                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 424808                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               4599857                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents             1460                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           143625263                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             536555031                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        500037832                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups               718                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             107414186                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 36190145                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               4605                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts           4603                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  12541075                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             29476574                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores             5520683                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           2151148                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          1293650                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  118168195                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                8471                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 105168426                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued             79356                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        26740210                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     65568590                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            253                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples      53432137                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.968262                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.908954                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                 36211077                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               4609                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           4607                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  12545622                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             29481569                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores             5520172                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           2131780                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          1278964                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  118183319                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                8477                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 105169429                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued             79348                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        26754797                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     65616265                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            259                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples      53440501                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.967972                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.909350                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            15374181     28.77%     28.77% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            11650585     21.80%     50.58% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             8250698     15.44%     66.02% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             6826591     12.78%     78.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             4953996      9.27%     88.07% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             2948586      5.52%     93.59% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             2456814      4.60%     98.18% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              528614      0.99%     99.17% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              442072      0.83%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            15384800     28.79%     28.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            11651642     21.80%     50.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             8259769     15.46%     66.05% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             6813523     12.75%     78.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             4933870      9.23%     88.03% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             2968386      5.55%     93.58% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             2461371      4.61%     98.19% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              525076      0.98%     99.17% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              442064      0.83%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total        53432137                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        53440501                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                   45737      6.91%      6.91% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                     27      0.00%      6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      6.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                 340297     51.45%     58.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                275411     41.64%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                   46222      6.98%      6.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                     26      0.00%      6.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      6.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      6.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      6.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      6.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      6.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      6.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      6.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      6.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      6.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      6.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      6.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      6.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      6.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      6.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      6.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      6.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      6.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      6.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      6.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      6.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      6.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      6.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      6.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      6.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      6.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      6.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      6.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 339934     51.34%     58.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                275932     41.67%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              74430007     70.77%     70.77% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              74431142     70.77%     70.77% # Type of FU issued
 system.cpu.iq.FU_type_0::IntMult                10980      0.01%     70.78% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     70.78% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     70.78% # Type of FU issued
@@ -549,90 +486,90 @@ system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     70.78% # Ty
 system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     70.78% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     70.78% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatCmp               1      0.00%     70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt             130      0.00%     70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt             132      0.00%     70.78% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     70.78% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMisc            172      0.00%     70.78% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            3      0.00%     70.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            2      0.00%     70.78% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             25613380     24.35%     95.14% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             5113753      4.86%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             25611933     24.35%     95.14% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             5115067      4.86%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              105168426                       # Type of FU issued
-system.cpu.iq.rate                           1.953938                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                      661472                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.006290                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          264509133                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         144921601                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    102693545                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 684                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                985                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses          281                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              105829562                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     336                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads           441614                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              105169429                       # Type of FU issued
+system.cpu.iq.rate                           1.953187                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                      662114                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.006296                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          264520145                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         144951370                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    102696867                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 676                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                925                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses          287                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              105831206                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     337                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads           441415                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      6902608                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         6756                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation         6465                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores       775839                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      6907603                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         6432                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation         6446                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores       775328                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            2                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked         31615                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked         31602                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                3897578                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                  958412                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                126923                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           118189357                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            310100                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              29476574                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts              5520683                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               4583                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  65855                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                  6705                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents           6465                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         447219                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       445977                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               893196                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             104191790                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              25292626                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts            976636                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                3898813                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                  959371                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                127029                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           118204490                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            309594                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              29481569                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts              5520172                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               4589                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  66074                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                  6711                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents           6446                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         446623                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       445838                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               892461                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             104194994                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              25292197                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            974435                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                         12691                       # number of nop insts executed
-system.cpu.iew.exec_refs                     30349836                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 21326689                       # Number of branches executed
-system.cpu.iew.exec_stores                    5057210                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.935792                       # Inst execution rate
-system.cpu.iew.wb_sent                      102971901                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     102693826                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  62250392                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 104309215                       # num instructions consuming a value
+system.cpu.iew.exec_nop                         12694                       # number of nop insts executed
+system.cpu.iew.exec_refs                     30350924                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 21328461                       # Number of branches executed
+system.cpu.iew.exec_stores                    5058727                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.935090                       # Inst execution rate
+system.cpu.iew.wb_sent                      102975092                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     102697154                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  62242577                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 104291686                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.907962                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.596787                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.907273                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.596812                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        26939334                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts        26954537                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls            8218                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            834485                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples     49534559                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.842208                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.540547                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts            833969                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples     49541688                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.841943                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.539958                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     20043988     40.46%     40.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     13146531     26.54%     67.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      4167490      8.41%     75.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      3431351      6.93%     82.35% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1535298      3.10%     85.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5       726633      1.47%     86.91% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       954931      1.93%     88.84% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       253243      0.51%     89.35% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      5275094     10.65%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     20036957     40.44%     40.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     13159597     26.56%     67.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      4169965      8.42%     75.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      3431804      6.93%     82.35% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1536139      3.10%     85.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5       734203      1.48%     86.93% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       944467      1.91%     88.84% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       252800      0.51%     89.35% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      5275756     10.65%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total     49534559                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total     49541688                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts             90602407                       # Number of instructions committed
 system.cpu.commit.committedOps               91252960                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -643,239 +580,237 @@ system.cpu.commit.branches                   18732304                       # Nu
 system.cpu.commit.fp_insts                         48                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                  72525674                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                56148                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events               5275094                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events               5275756                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    162446025                       # The number of ROB reads
-system.cpu.rob.rob_writes                   240301749                       # The number of ROB writes
-system.cpu.timesIdled                           46102                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          391706                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                    162467695                       # The number of ROB reads
+system.cpu.rob.rob_writes                   240333520                       # The number of ROB writes
+system.cpu.timesIdled                           46195                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          404525                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                    90589798                       # Number of Instructions Simulated
 system.cpu.committedOps                      91240351                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total              90589798                       # Number of Instructions Simulated
-system.cpu.cpi                               0.594149                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.594149                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.683079                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.683079                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                495606364                       # number of integer regfile reads
-system.cpu.int_regfile_writes               120553547                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                       143                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                      349                       # number of floating regfile writes
-system.cpu.misc_regfile_reads                29209842                       # number of misc regfile reads
+system.cpu.cpi                               0.594383                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.594383                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.682417                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.682417                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                495621667                       # number of integer regfile reads
+system.cpu.int_regfile_writes               120557380                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                       149                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                      361                       # number of floating regfile writes
+system.cpu.misc_regfile_reads                29211256                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                   7784                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput              4497544713                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq         904632                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp        904632                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       942884                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq            2                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp            2                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq        43696                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp        43696                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1476                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2838066                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           2839542                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        47168                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    120990272                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      121037440                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus         121037440                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus          128                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy     1888491000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.throughput              4495994050                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq         904654                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp        904654                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       942932                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq            1                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp            1                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq        43718                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp        43718                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1467                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2838210                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           2839677                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        46912                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    120996480                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      121043392                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         121043392                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus           64                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy     1888584500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          7.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1225749                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       1216499                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1424096491                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1423941741                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          5.3                       # Layer utilization (%)
 system.cpu.icache.tags.replacements                 3                       # number of replacements
-system.cpu.icache.tags.tagsinuse           632.652083                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            13844045                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               737                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          18784.321574                       # Average number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           632.458088                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            13844537                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               733                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          18887.499318                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   632.652083                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.308912                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.308912                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          734                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           38                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           16                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3            4                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst   632.458088                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.308817                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.308817                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          730                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           37                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           14                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4          676                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.358398                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          27690815                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         27690815                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     13844045                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        13844045                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      13844045                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         13844045                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     13844045                       # number of overall hits
-system.cpu.icache.overall_hits::total        13844045                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          993                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           993                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          993                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            993                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          993                       # number of overall misses
-system.cpu.icache.overall_misses::total           993                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     66969998                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     66969998                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     66969998                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     66969998                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     66969998                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     66969998                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     13845038                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     13845038                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     13845038                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     13845038                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     13845038                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     13845038                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000072                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000072                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000072                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000072                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000072                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000072                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67442.092649                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 67442.092649                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 67442.092649                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 67442.092649                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 67442.092649                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 67442.092649                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          594                       # number of cycles access was blocked
+system.cpu.icache.tags.occ_task_id_percent::1024     0.356445                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          27691778                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         27691778                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     13844537                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        13844537                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      13844537                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         13844537                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     13844537                       # number of overall hits
+system.cpu.icache.overall_hits::total        13844537                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          985                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           985                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          985                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            985                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          985                       # number of overall misses
+system.cpu.icache.overall_misses::total           985                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     65965748                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     65965748                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     65965748                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     65965748                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     65965748                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     65965748                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     13845522                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     13845522                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     13845522                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     13845522                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     13845522                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     13845522                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000071                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000071                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000071                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000071                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000071                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000071                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66970.302538                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 66970.302538                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 66970.302538                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 66970.302538                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 66970.302538                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 66970.302538                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          596                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                10                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                12                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    59.400000                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    49.666667                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          254                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          254                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          254                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          254                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          254                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          254                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          739                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          739                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          739                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          739                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          739                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          739                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     50789000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     50789000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     50789000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     50789000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     50789000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     50789000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          251                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          251                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          251                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          251                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          251                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          251                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          734                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          734                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          734                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          734                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          734                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          734                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     51030750                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     51030750                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     51030750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     51030750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     51030750                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     51030750                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000053                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000053                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000053                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000053                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000053                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000053                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68726.657645                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68726.657645                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68726.657645                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 68726.657645                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68726.657645                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 68726.657645                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69524.182561                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69524.182561                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69524.182561                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 69524.182561                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69524.182561                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 69524.182561                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        10731.098995                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1831378                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs            15503                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs           118.130555                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse        10726.796939                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            1831454                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs            15497                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs           118.181196                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  9880.580291                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   618.669492                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   231.849212                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.301531                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.018880                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.007075                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.327487                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        15503                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           41                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1           28                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          515                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1301                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        13618                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.473114                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         15188896                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        15188896                       # Number of data accesses
+system.cpu.l2cache.tags.occ_blocks::writebacks  9879.688406                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   618.475949                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   228.632584                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.301504                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.018874                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.006977                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.327356                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        15497                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           40                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           27                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          514                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1300                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        13616                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.472931                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         15189647                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        15189647                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst           25                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data       903612                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total         903637                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       942884                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       942884                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data            1                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total            1                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data        29158                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total        29158                       # number of ReadExReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data       903641                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         903666                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       942932                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       942932                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data        29180                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total        29180                       # number of ReadExReq hits
 system.cpu.l2cache.demand_hits::cpu.inst           25                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       932770                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total          932795                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       932821                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          932846                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.inst           25                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       932770                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         932795                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          712                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data          281                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total          993                       # number of ReadReq misses
+system.cpu.l2cache.overall_hits::cpu.data       932821                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         932846                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          708                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data          279                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total          987                       # number of ReadReq misses
 system.cpu.l2cache.UpgradeReq_misses::cpu.data            1                       # number of UpgradeReq misses
 system.cpu.l2cache.UpgradeReq_misses::total            1                       # number of UpgradeReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data        14538                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total        14538                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          712                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data        14819                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total         15531                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          712                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data        14819                       # number of overall misses
-system.cpu.l2cache.overall_misses::total        15531                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     49793250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     21247250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     71040500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    962911000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    962911000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     49793250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    984158250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total   1033951500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     49793250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    984158250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total   1033951500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          737                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data       903893                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total       904630                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       942884                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       942884                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data            2                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total            2                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data        43696                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total        43696                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          737                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       947589                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       948326                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          737                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       947589                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       948326                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.966079                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.000311                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.001098                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.500000                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.500000                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.332708                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.332708                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.966079                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.015639                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.016377                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.966079                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.015639                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.016377                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69934.339888                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75612.989324                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 71541.289023                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66234.076214                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66234.076214                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69934.339888                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66411.920507                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 66573.401584                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69934.339888                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66411.920507                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 66573.401584                       # average overall miss latency
+system.cpu.l2cache.demand_misses::cpu.inst          708                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data        14817                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total         15525                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          708                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data        14817                       # number of overall misses
+system.cpu.l2cache.overall_misses::total        15525                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     50040500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     21343000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     71383500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    975716500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    975716500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     50040500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    997059500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   1047100000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     50040500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    997059500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   1047100000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          733                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data       903920                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       904653                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       942932                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       942932                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data            1                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total            1                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data        43718                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total        43718                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          733                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       947638                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       948371                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          733                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       947638                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       948371                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.965894                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.000309                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.001091                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data            1                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.332540                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.332540                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.965894                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.015636                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.016370                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.965894                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.015636                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.016370                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70678.672316                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76498.207885                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 72323.708207                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67114.905764                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67114.905764                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70678.672316                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 67291.590740                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 67446.054750                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70678.672316                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 67291.590740                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 67446.054750                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -893,191 +828,191 @@ system.cpu.l2cache.demand_mshr_hits::total           11                       #
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.data           10                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total           11                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          711                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          271                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total          982                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          707                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          269                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total          976                       # number of ReadReq MSHR misses
 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            1                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.UpgradeReq_mshr_misses::total            1                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        14538                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total        14538                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          711                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data        14809                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total        15520                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          711                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data        14809                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total        15520                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     40836000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     17269250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     58105250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          707                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data        14807                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total        15514                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          707                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data        14807                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total        15514                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     41129750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     17372750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     58502500                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        10001                       # number of UpgradeReq MSHR miss cycles
 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        10001                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    780533500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    780533500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     40836000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    797802750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    838638750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     40836000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    797802750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    838638750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.964722                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.000300                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.001086                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.500000                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.500000                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.332708                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.332708                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.964722                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.015628                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.016366                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.964722                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.015628                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.016366                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57434.599156                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63724.169742                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59170.315682                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    793837000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    793837000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     41129750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    811209750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    852339500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     41129750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    811209750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    852339500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.964529                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.000298                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.001079                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.332540                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.332540                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.964529                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.015625                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.016359                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.964529                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.015625                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.016359                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58175.035361                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64582.713755                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59941.086066                       # average ReadReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        10001                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 53689.193837                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53689.193837                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57434.599156                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53872.830711                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54036.001933                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57434.599156                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53872.830711                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54036.001933                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54604.278443                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54604.278443                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58175.035361                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 54785.557507                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54940.021916                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58175.035361                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 54785.557507                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54940.021916                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements            943493                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          3671.741279                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            28144387                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            947589                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             29.701049                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        8006035000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  3671.741279                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.896421                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.896421                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements            943542                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          3671.682953                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            28143982                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            947638                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             29.699086                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        8008531250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  3671.682953                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.896407                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.896407                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          445                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         3140                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          511                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          464                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         3129                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          503                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          59988391                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         59988391                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     23603738                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        23603738                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      4532850                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        4532850                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data         3905                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total         3905                       # number of LoadLockedReq hits
+system.cpu.dcache.tags.tag_accesses          59988388                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         59988388                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     23603660                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        23603660                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      4532519                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        4532519                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data         3912                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total         3912                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data         3887                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total         3887                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      28136588                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         28136588                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     28136588                       # number of overall hits
-system.cpu.dcache.overall_hits::total        28136588                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1173883                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1173883                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       202131                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       202131                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data      28136179                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         28136179                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     28136179                       # number of overall hits
+system.cpu.dcache.overall_hits::total        28136179                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1173928                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1173928                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       202462                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       202462                       # number of WriteReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            7                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            7                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      1376014                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1376014                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1376014                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1376014                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  13893935229                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  13893935229                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   8459874583                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   8459874583                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data      1376390                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1376390                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1376390                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1376390                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  13893768230                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  13893768230                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   8571552365                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   8571552365                       # number of WriteReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       251500                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::total       251500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  22353809812                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  22353809812                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  22353809812                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  22353809812                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     24777621                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     24777621                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data  22465320595                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  22465320595                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  22465320595                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  22465320595                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     24777588                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     24777588                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data      4734981                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total      4734981                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data         3912                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total         3912                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data         3919                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total         3919                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data         3887                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total         3887                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     29512602                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     29512602                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     29512602                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     29512602                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.047377                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.047377                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.042689                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.042689                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.001789                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.001789                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.046625                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.046625                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.046625                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.046625                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11835.877365                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 11835.877365                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41853.424675                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 41853.424675                       # average WriteReq miss latency
+system.cpu.dcache.demand_accesses::cpu.data     29512569                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     29512569                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     29512569                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     29512569                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.047379                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.047379                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.042759                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.042759                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.001786                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.001786                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.046637                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.046637                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.046637                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.046637                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11835.281406                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 11835.281406                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42336.598300                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 42336.598300                       # average WriteReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 35928.571429                       # average LoadLockedReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 35928.571429                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 16245.336030                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 16245.336030                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 16245.336030                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 16245.336030                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs       154233                       # number of cycles access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 16321.915006                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 16321.915006                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 16321.915006                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 16321.915006                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       154484                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs             23951                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs             23933                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     6.439522                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     6.454853                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       942884                       # number of writebacks
-system.cpu.dcache.writebacks::total            942884                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       269973                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       269973                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       158450                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       158450                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks       942932                       # number of writebacks
+system.cpu.dcache.writebacks::total            942932                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       269988                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       269988                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       158763                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       158763                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            7                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total            7                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       428423                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       428423                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       428423                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       428423                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       903910                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       903910                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data        43681                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total        43681                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       947591                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       947591                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       947591                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       947591                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   9994274260                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   9994274260                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1319346668                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   1319346668                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  11313620928                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  11313620928                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  11313620928                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  11313620928                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.036481                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.036481                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009225                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009225                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.032108                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.032108                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.032108                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.032108                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11056.713899                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11056.713899                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30204.131499                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30204.131499                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11939.350340                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 11939.350340                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11939.350340                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 11939.350340                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_hits::cpu.data       428751                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       428751                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       428751                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       428751                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       903940                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       903940                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data        43699                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total        43699                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       947639                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       947639                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       947639                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       947639                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   9994791010                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   9994791010                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1332397702                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   1332397702                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  11327188712                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  11327188712                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  11327188712                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  11327188712                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.036482                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.036482                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009229                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009229                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.032110                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.032110                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.032110                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.032110                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11056.918612                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11056.918612                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30490.347651                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30490.347651                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11953.063046                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 11953.063046                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11953.063046                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 11953.063046                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 167e490747776879a5c9dfa99e5d1bd021405b8e..1b324ac262d87afea791338632dbc23852b3a5c9 100644 (file)
@@ -1,76 +1,76 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.065614                       # Number of seconds simulated
-sim_ticks                                 65613727000                       # Number of ticks simulated
-final_tick                                65613727000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.065578                       # Number of seconds simulated
+sim_ticks                                 65578127500                       # Number of ticks simulated
+final_tick                                65578127500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 111661                       # Simulator instruction rate (inst/s)
-host_op_rate                                   196618                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               46373693                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 390932                       # Number of bytes of host memory used
-host_seconds                                  1414.89                       # Real time elapsed on the host
+host_inst_rate                                  88175                       # Simulator instruction rate (inst/s)
+host_op_rate                                   155262                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               36599742                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 427692                       # Number of bytes of host memory used
+host_seconds                                  1791.76                       # Real time elapsed on the host
 sim_insts                                   157988547                       # Number of instructions simulated
 sim_ops                                     278192464                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             63616                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           1883136                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              1946752                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        63616                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           63616                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks        10688                       # Number of bytes written to this memory
-system.physmem.bytes_written::total             10688                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst                994                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data              29424                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                 30418                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks             167                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                  167                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               969553                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             28700336                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                29669889                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          969553                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             969553                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks            162893                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                 162893                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks            162893                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              969553                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            28700336                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               29832782                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                         30419                       # Number of read requests accepted
-system.physmem.writeReqs                          167                       # Number of write requests accepted
-system.physmem.readBursts                       30419                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                        167                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  1943936                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      2880                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                      9856                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   1946816                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                  10688                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                       45                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst             63744                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           1882880                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              1946624                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        63744                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           63744                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks        10368                       # Number of bytes written to this memory
+system.physmem.bytes_written::total             10368                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst                996                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data              29420                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                 30416                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks             162                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                  162                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               972031                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             28712012                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                29684044                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          972031                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             972031                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks            158101                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                 158101                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks            158101                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              972031                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            28712012                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               29842145                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                         30418                       # Number of read requests accepted
+system.physmem.writeReqs                          162                       # Number of write requests accepted
+system.physmem.readBursts                       30418                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                        162                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  1942912                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      3840                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                      8384                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   1946752                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                  10368                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                       60                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                1928                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                2077                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                2029                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                1927                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                1927                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                2065                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                2026                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                1928                       # Per bank write bursts
 system.physmem.perBankRdBursts::4                2026                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                1899                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                1963                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                1900                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                1961                       # Per bank write bursts
 system.physmem.perBankRdBursts::7                1862                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                1939                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                1940                       # Per bank write bursts
 system.physmem.perBankRdBursts::9                1933                       # Per bank write bursts
 system.physmem.perBankRdBursts::10               1805                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               1795                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               1796                       # Per bank write bursts
 system.physmem.perBankRdBursts::12               1792                       # Per bank write bursts
 system.physmem.perBankRdBursts::13               1800                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               1821                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               1778                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                  15                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                  95                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                   7                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                  11                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                   6                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               1818                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               1779                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                  10                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                  71                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                   3                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                  17                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                  12                       # Per bank write bursts
 system.physmem.perBankWrBursts::5                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                  12                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                  10                       # Per bank write bursts
 system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::9                   5                       # Per bank write bursts
@@ -82,26 +82,26 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     65613689500                       # Total gap between requests
+system.physmem.totGap                     65578111000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                   30419                       # Read request sizes (log2)
+system.physmem.readPktSize::6                   30418                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                    167                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     29918                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                    162                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     29902                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::1                       362                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        73                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        18                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        70                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        19                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         5                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -129,280 +129,243 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                         8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                         8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                         8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                         8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                         8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                         8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                         8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                         8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                         8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                         8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                        7                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                        7                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                        7                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                        7                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                        7                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                        6                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::18                        7                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::19                        7                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::20                        7                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::21                        7                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         1275                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean     1527.767843                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     562.023414                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev    1657.823974                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64               326     25.57%     25.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128              105      8.24%     33.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192               43      3.37%     37.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256               28      2.20%     39.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320               22      1.73%     41.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384               22      1.73%     42.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448               19      1.49%     44.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512               15      1.18%     45.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576               17      1.33%     46.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640               13      1.02%     47.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704               46      3.61%     51.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768               12      0.94%     52.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832                8      0.63%     53.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896                7      0.55%     53.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960               12      0.94%     54.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024              11      0.86%     55.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088               8      0.63%     56.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152              16      1.25%     57.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216               7      0.55%     57.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280               9      0.71%     58.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344               9      0.71%     59.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408               7      0.55%     59.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472              11      0.86%     60.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536               6      0.47%     61.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600              14      1.10%     62.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664               4      0.31%     62.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1728               9      0.71%     63.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1792               6      0.47%     63.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856               3      0.24%     63.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1920              12      0.94%     64.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984              12      0.94%     65.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2048               8      0.63%     66.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112              32      2.51%     68.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2176               7      0.55%     69.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2240               7      0.55%     70.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2304               5      0.39%     70.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2368               6      0.47%     70.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2432              10      0.78%     71.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2496               5      0.39%     72.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2560               7      0.55%     72.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2624               3      0.24%     72.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2688               9      0.71%     73.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2752               7      0.55%     74.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2816               6      0.47%     74.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2880               5      0.39%     74.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2944              11      0.86%     75.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3008               9      0.71%     76.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3072               7      0.55%     77.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3136               5      0.39%     77.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3200               5      0.39%     77.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3264               8      0.63%     78.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3328              11      0.86%     79.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3392               9      0.71%     80.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3456              10      0.78%     80.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3520              12      0.94%     81.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3584              15      1.18%     82.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3648              10      0.78%     83.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3712              14      1.10%     84.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3776               9      0.71%     85.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3840               8      0.63%     86.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3904               8      0.63%     86.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3968              15      1.18%     88.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4032              13      1.02%     89.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4096              11      0.86%     89.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4160              21      1.65%     91.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4224              10      0.78%     92.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4288               6      0.47%     92.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4352               7      0.55%     93.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4416               4      0.31%     93.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4480               5      0.39%     94.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4544               4      0.31%     94.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4608               4      0.31%     94.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4672               6      0.47%     95.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4736               7      0.55%     95.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4800               5      0.39%     96.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4864               6      0.47%     96.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4928               5      0.39%     96.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4992               6      0.47%     97.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5056               5      0.39%     97.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5120               6      0.47%     98.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5184               4      0.31%     98.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5248               2      0.16%     98.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5312               2      0.16%     98.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5376               2      0.16%     99.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5440               2      0.16%     99.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5568               1      0.08%     99.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5696               1      0.08%     99.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5952               1      0.08%     99.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6016               1      0.08%     99.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6080               1      0.08%     99.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6208               1      0.08%     99.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6592               1      0.08%     99.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6656               3      0.24%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           1275                       # Bytes accessed per row activation
-system.physmem.totQLat                       92483500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 678771000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    151870000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                   434417500                       # Total ticks spent accessing banks
-system.physmem.avgQLat                        3044.82                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    14302.28                       # Average bank access latency per DRAM burst
+system.physmem.wrQLenPdf::22                        7                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                        7                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                        7                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                        7                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                        7                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                        7                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples         1672                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      934.162679                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     823.717230                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     264.349754                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             77      4.61%      4.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           54      3.23%      7.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           19      1.14%      8.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           10      0.60%      9.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           11      0.66%     10.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            5      0.30%     10.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            6      0.36%     10.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            4      0.24%     11.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         1486     88.88%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           1672                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples             7                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean      4327.142857                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       47.742498                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev    11404.448466                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023              6     85.71%     85.71% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::29696-30719            1     14.29%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total               7                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples             7                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        18.714286                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.459831                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        3.545621                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16                  3     42.86%     42.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                  3     42.86%     85.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                  1     14.29%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total               7                       # Writes before turning the bus around for reads
+system.physmem.totQLat                       98355750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 704267000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    151790000                       # Total ticks spent in databus transfers
+system.physmem.totBankLat                   454121250                       # Total ticks spent accessing banks
+system.physmem.avgQLat                        3239.86                       # Average queueing delay per DRAM burst
+system.physmem.avgBankLat                    14958.87                       # Average bank access latency per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  22347.11                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  23198.73                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                          29.63                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           0.15                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       29.67                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBW                           0.13                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       29.69                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.16                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.23                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.23                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         0.01                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                         9.96                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      29156                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                        97                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   95.99                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  58.08                       # Row buffer hit rate for writes
-system.physmem.avgGap                      2145219.69                       # Average gap between requests
-system.physmem.pageHitRate                      95.78                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               0.92                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                     29832782                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq                1416                       # Transaction distribution
-system.membus.trans_dist::ReadResp               1415                       # Transaction distribution
-system.membus.trans_dist::Writeback               167                       # Transaction distribution
+system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        15.72                       # Average write queue length when enqueuing
+system.physmem.readRowHits                      27690                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                        93                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   91.21                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  57.41                       # Row buffer hit rate for writes
+system.physmem.avgGap                      2144477.14                       # Average gap between requests
+system.physmem.pageHitRate                      91.03                       # Row buffer hit rate, read and write combined
+system.physmem.prechargeAllPercent               1.03                       # Percentage of time for which DRAM has all the banks in precharge state
+system.membus.throughput                     29841169                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq                1415                       # Transaction distribution
+system.membus.trans_dist::ReadResp               1412                       # Transaction distribution
+system.membus.trans_dist::Writeback               162                       # Transaction distribution
 system.membus.trans_dist::ReadExReq             29003                       # Transaction distribution
 system.membus.trans_dist::ReadExResp            29003                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        61004                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total        61004                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  61004                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port      1957440                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total      1957440                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total             1957440                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus                1957440                       # Total data (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        60995                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total        60995                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  60995                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port      1956928                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total      1956928                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total             1956928                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus                1956928                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy            34950500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy            34882000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          284209000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy          284250750                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.4                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                33859770                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          33859770                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            774913                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             19306649                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                19202709                       # Number of BTB hits
+system.cpu.branchPred.lookups                33848859                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          33848859                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            773675                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             19289255                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                19197917                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             99.461636                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 5016745                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect               5399                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             99.526482                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 5013789                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect               5382                       # Number of incorrect RAS predictions.
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                  444                       # Number of system calls
-system.cpu.numCycles                        131227460                       # number of cpu cycles simulated
+system.cpu.numCycles                        131156258                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           26135230                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      182265293                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    33859770                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           24219454                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      55459629                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 5354571                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles               44982751                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                   52                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles           314                       # Number of stall cycles due to pending traps
+system.cpu.fetch.icacheStallCycles           26124618                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      182201449                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    33848859                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           24211706                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      55441130                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 5339784                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles               44953696                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                   48                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles           286                       # Number of stall cycles due to pending traps
 system.cpu.fetch.IcacheWaitRetryStallCycles            1                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  25575393                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                166244                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          131122211                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.450609                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.313707                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines                  25565447                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                166050                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          131050652                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.451103                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.313857                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 78139546     59.59%     59.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  1960111      1.49%     61.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  2942175      2.24%     63.33% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  3833696      2.92%     66.26% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  7767416      5.92%     72.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  4757872      3.63%     75.81% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  2665225      2.03%     77.84% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1316047      1.00%     78.84% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 27740123     21.16%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 78085477     59.58%     59.58% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  1960121      1.50%     61.08% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  2941365      2.24%     63.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  3832581      2.92%     66.25% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  7765611      5.93%     72.17% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  4754905      3.63%     75.80% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  2663892      2.03%     77.84% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1315906      1.00%     78.84% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 27730794     21.16%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            131122211                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.258024                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.388926                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 36831320                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              37195756                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  43906245                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               8644656                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                4544234                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts              318852911                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles                4544234                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 42322552                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 9742718                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           7418                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  46754999                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              27750290                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              315016174                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                   215                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                  26317                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents              25895473                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands           317188133                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             836523485                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        515056961                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups               484                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            131050652                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.258080                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.389194                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 36811004                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              37176024                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  43889002                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               8643749                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                4530873                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts              318736109                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles                4530873                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 42298555                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 9762867                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           7405                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  46737142                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              27713810                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              314904511                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                   214                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                  26056                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents              25855633                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands           317074927                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             836235433                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        514870937                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups               492                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             279212747                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 37975386                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                483                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            481                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  62628696                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            101555761                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            34778058                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          39627069                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          5861390                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  311484166                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                1638                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 300275524                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued             89306                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        32714418                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     46115217                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved           1193                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     131122211                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.290043                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.698539                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                 37862180                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                484                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            482                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  62586078                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            101522320                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            34765778                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          39602927                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          5818030                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  311370743                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                1646                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 300208382                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued             88815                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        32598997                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     45935189                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           1201                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     131050652                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.290781                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.700647                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            24369701     18.59%     18.59% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            23163237     17.67%     36.25% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            25526976     19.47%     55.72% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            25864200     19.73%     75.44% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            18882898     14.40%     89.85% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             8250397      6.29%     96.14% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             3948647      3.01%     99.15% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              938964      0.72%     99.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              177191      0.14%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            24364795     18.59%     18.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            23214690     17.71%     36.31% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            25426307     19.40%     55.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            25814267     19.70%     75.41% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            18862103     14.39%     89.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             8277108      6.32%     96.11% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             3959654      3.02%     99.14% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              947423      0.72%     99.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              184305      0.14%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       131122211                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       131050652                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                   31436      1.53%      1.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                   31474      1.53%      1.53% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                      0      0.00%      1.53% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%      1.53% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatAdd                     0      0.00%      1.53% # attempts to use FU when none available
@@ -431,118 +394,118 @@ system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      1.53% # at
 system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      1.53% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      1.53% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      1.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                1917677     93.05%     94.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                111849      5.43%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                1916835     93.04%     94.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                111878      5.43%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass             31277      0.01%      0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             169841029     56.56%     56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                11216      0.00%     56.58% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                   331      0.00%     56.58% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                  34      0.00%     56.58% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     56.58% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     56.58% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     56.58% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     56.58% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     56.58% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     56.58% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     56.58% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     56.58% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     56.58% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     56.58% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     56.58% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     56.58% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     56.58% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     56.58% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     56.58% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     56.58% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     56.58% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     56.58% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     56.58% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     56.58% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     56.58% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     56.58% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     56.58% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     56.58% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     56.58% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             97301451     32.40%     88.98% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            33090186     11.02%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             169792966     56.56%     56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                11226      0.00%     56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                   332      0.00%     56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                  31      0.00%     56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             97287204     32.41%     88.98% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            33085346     11.02%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              300275524                       # Type of FU issued
-system.cpu.iq.rate                           2.288206                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     2060962                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.006864                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          733823004                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         344232038                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    298020704                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 523                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                719                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses          156                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              302304968                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     241                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         54149706                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              300208382                       # Type of FU issued
+system.cpu.iq.rate                           2.288937                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2060187                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.006863                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          733615929                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         344003056                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    297961989                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 489                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                706                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses          149                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              302237064                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     228                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         54184589                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     10776376                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        31265                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        33344                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      3338306                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     10742935                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        32064                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        33208                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      3326026                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads         3224                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          8563                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked          8575                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                4544234                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 2798212                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                162335                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           311485804                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            196342                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             101555761                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             34778058                       # Number of dispatched store instructions
+system.cpu.iew.iewSquashCycles                4530873                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 2837927                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                162034                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           311372389                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            196090                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             101522320                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             34765778                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts                470                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                   2616                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 73755                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          33344                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         393170                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       428306                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               821476                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             298872684                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              96891554                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           1402840                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewIQFullEvents                   2524                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 73590                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          33208                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         392510                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       427924                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               820434                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             298810960                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              96874788                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1397422                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                    129817497                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 30820824                       # Number of branches executed
-system.cpu.iew.exec_stores                   32925943                       # Number of stores executed
-system.cpu.iew.exec_rate                     2.277516                       # Inst execution rate
-system.cpu.iew.wb_sent                      298390596                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     298020860                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 218260006                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 296755223                       # num instructions consuming a value
+system.cpu.iew.exec_refs                    129797042                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 30816203                       # Number of branches executed
+system.cpu.iew.exec_stores                   32922254                       # Number of stores executed
+system.cpu.iew.exec_rate                     2.278282                       # Inst execution rate
+system.cpu.iew.wb_sent                      298329085                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     297962138                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 218205948                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 296684532                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       2.271025                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.735488                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       2.271810                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.735481                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        33306189                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts        33192838                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             445                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            774954                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    126577977                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.197795                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.970921                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts            773712                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    126519779                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.198806                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.971927                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     58251121     46.02%     46.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     19170530     15.15%     61.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     11719383      9.26%     70.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      9409192      7.43%     77.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1839491      1.45%     79.31% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      2078967      1.64%     80.95% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      1287907      1.02%     81.97% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       695737      0.55%     82.52% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     22125649     17.48%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     58265880     46.05%     46.05% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     19155859     15.14%     61.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     11581370      9.15%     70.35% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      9445264      7.47%     77.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1880302      1.49%     79.30% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      2071430      1.64%     80.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      1302334      1.03%     81.97% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       693009      0.55%     82.51% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     22124331     17.49%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    126577977                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    126519779                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            157988547                       # Number of instructions committed
 system.cpu.commit.committedOps              278192464                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -553,100 +516,100 @@ system.cpu.commit.branches                   29309705                       # Nu
 system.cpu.commit.fp_insts                         40                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                 278169481                       # Number of committed integer instructions.
 system.cpu.commit.function_calls              4237596                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events              22125649                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events              22124331                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    415950981                       # The number of ROB reads
-system.cpu.rob.rob_writes                   627545399                       # The number of ROB writes
-system.cpu.timesIdled                           13719                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          105249                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                    415780750                       # The number of ROB reads
+system.cpu.rob.rob_writes                   627305222                       # The number of ROB writes
+system.cpu.timesIdled                           13712                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          105606                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   157988547                       # Number of Instructions Simulated
 system.cpu.committedOps                     278192464                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total             157988547                       # Number of Instructions Simulated
-system.cpu.cpi                               0.830614                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.830614                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.203929                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.203929                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                483744129                       # number of integer regfile reads
-system.cpu.int_regfile_writes               234595251                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                       141                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                       77                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 107058970                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                 64002830                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               191827908                       # number of misc regfile reads
+system.cpu.cpi                               0.830163                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.830163                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.204583                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.204583                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                483659759                       # number of integer regfile reads
+system.cpu.int_regfile_writes               234542237                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                       137                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                       71                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 107049810                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                 63997871                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               191792946                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput              4042576518                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq        1995299                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       1995298                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      2066887                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq        82323                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp        82323                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         2022                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6220108                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           6222130                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        64704                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    265183808                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      265248512                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus         265248512                       # Total data (bytes)
+system.cpu.toL2Bus.throughput              4044284064                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq        1995295                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       1995292                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      2066395                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq        82322                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp        82322                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         2024                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6219602                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           6221626                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        64768                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    265151808                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      265216576                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         265216576                       # Total data (bytes)
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy     4139141500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.occupancy     4138401000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          6.3                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1689999                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       1688749                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    3122002000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    3121628749                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          4.8                       # Layer utilization (%)
-system.cpu.icache.tags.replacements                57                       # number of replacements
-system.cpu.icache.tags.tagsinuse           819.642194                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            25574088                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              1011                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          25295.833828                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements                55                       # number of replacements
+system.cpu.icache.tags.tagsinuse           821.703802                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            25564150                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              1012                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          25261.017787                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   819.642194                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.400216                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.400216                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          954                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst   821.703802                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.401223                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.401223                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          957                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           51                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           25                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3           11                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          867                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.465820                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          51151797                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         51151797                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     25574088                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        25574088                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      25574088                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         25574088                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     25574088                       # number of overall hits
-system.cpu.icache.overall_hits::total        25574088                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         1305                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          1305                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         1305                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           1305                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         1305                       # number of overall misses
-system.cpu.icache.overall_misses::total          1305                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     88661748                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     88661748                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     88661748                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     88661748                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     88661748                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     88661748                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     25575393                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     25575393                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     25575393                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     25575393                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     25575393                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     25575393                       # number of overall (read+write) accesses
+system.cpu.icache.tags.age_task_id_blocks_1024::2           26                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3           10                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          870                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.467285                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          51131906                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         51131906                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     25564150                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        25564150                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      25564150                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         25564150                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     25564150                       # number of overall hits
+system.cpu.icache.overall_hits::total        25564150                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1297                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1297                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1297                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1297                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1297                       # number of overall misses
+system.cpu.icache.overall_misses::total          1297                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     90379749                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     90379749                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     90379749                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     90379749                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     90379749                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     90379749                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     25565447                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     25565447                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     25565447                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     25565447                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     25565447                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     25565447                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000051                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000051                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000051                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000051                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000051                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000051                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67940.036782                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 67940.036782                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 67940.036782                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 67940.036782                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 67940.036782                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 67940.036782                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69683.692367                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 69683.692367                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 69683.692367                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 69683.692367                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 69683.692367                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 69683.692367                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs          114                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 3                       # number of cycles access was blocked
@@ -655,129 +618,129 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs           38
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          294                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          294                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          294                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          294                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          294                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          294                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         1011                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         1011                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         1011                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         1011                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         1011                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         1011                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     69226501                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     69226501                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     69226501                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     69226501                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     69226501                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     69226501                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          285                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          285                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          285                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          285                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          285                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          285                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         1012                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         1012                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         1012                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         1012                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         1012                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         1012                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     70911751                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     70911751                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     70911751                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     70911751                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     70911751                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     70911751                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000040                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000040                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000040                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000040                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000040                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000040                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68473.294758                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68473.294758                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68473.294758                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 68473.294758                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68473.294758                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 68473.294758                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70070.900198                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70070.900198                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70070.900198                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 70070.900198                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70070.900198                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 70070.900198                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements              479                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        20806.493932                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            4029616                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs            30401                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs           132.548798                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse        20808.807905                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            4029125                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs            30398                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs           132.545727                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 19891.107618                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   670.515764                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   244.870550                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.607028                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.020463                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.007473                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.634964                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        29922                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           57                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_blocks::writebacks 19891.385936                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   670.059760                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   247.362209                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.607037                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.020449                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.007549                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.635034                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        29919                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1           65                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          773                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1381                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        27646                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.913147                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         33268796                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        33268796                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst           17                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data      1993866                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1993883                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      2066887                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      2066887                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data        53320                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total        53320                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst           17                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      2047186                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2047203                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst           17                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      2047186                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2047203                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          994                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data          422                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         1416                       # number of ReadReq misses
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          763                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1379                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        27657                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.913055                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         33264816                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        33264816                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst           16                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data      1993864                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        1993880                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      2066395                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      2066395                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data        53319                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total        53319                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst           16                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      2047183                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2047199                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst           16                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      2047183                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2047199                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          996                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data          419                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total         1415                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data        29003                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total        29003                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          994                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data        29425                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total         30419                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          994                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data        29425                       # number of overall misses
-system.cpu.l2cache.overall_misses::total        30419                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     68041000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     29989500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     98030500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   1876802500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   1876802500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     68041000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data   1906792000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total   1974833000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     68041000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data   1906792000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total   1974833000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst         1011                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      1994288                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      1995299                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      2066887                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      2066887                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data        82323                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total        82323                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         1011                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      2076611                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2077622                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         1011                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      2076611                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2077622                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.983185                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.000212                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.000710                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.352307                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.352307                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.983185                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.014170                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses::cpu.inst          996                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data        29422                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total         30418                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          996                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data        29422                       # number of overall misses
+system.cpu.l2cache.overall_misses::total        30418                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     69735750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     30889250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    100625000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   1899321750                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   1899321750                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     69735750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   1930211000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   1999946750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     69735750                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   1930211000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   1999946750                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst         1012                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      1994283                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      1995295                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      2066395                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      2066395                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data        82322                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total        82322                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         1012                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      2076605                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2077617                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         1012                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      2076605                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2077617                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.984190                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.000210                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.000709                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.352312                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.352312                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.984190                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.014168                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::total     0.014641                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.983185                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.014170                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.984190                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.014168                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.014641                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68451.710262                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71065.165877                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 69230.579096                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 64710.633383                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 64710.633383                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68451.710262                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 64801.767205                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 64921.036194                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68451.710262                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 64801.767205                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 64921.036194                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70015.813253                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73721.360382                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 71113.074205                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 65487.078923                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65487.078923                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70015.813253                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65604.343688                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 65748.791834                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70015.813253                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65604.343688                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 65748.791834                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -786,167 +749,167 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks          167                       # number of writebacks
-system.cpu.l2cache.writebacks::total              167                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          994                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          422                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         1416                       # number of ReadReq MSHR misses
+system.cpu.l2cache.writebacks::writebacks          162                       # number of writebacks
+system.cpu.l2cache.writebacks::total              162                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          996                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          419                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         1415                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        29003                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total        29003                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          994                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data        29425                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total        30419                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          994                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data        29425                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total        30419                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     55574500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     24773500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     80348000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   1511756500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   1511756500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     55574500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   1536530000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   1592104500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     55574500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   1536530000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   1592104500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.983185                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.000212                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.000710                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.352307                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.352307                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.983185                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.014170                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          996                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data        29422                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total        30418                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          996                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data        29422                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total        30418                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     57248250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     25743750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     82992000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   1534558750                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   1534558750                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     57248250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   1560302500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   1617550750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     57248250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   1560302500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   1617550750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.984190                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.000210                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.000709                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.352312                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.352312                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.984190                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.014168                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.014641                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.983185                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.014170                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.984190                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.014168                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.014641                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55909.959759                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58704.976303                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56742.937853                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52124.142330                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52124.142330                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55909.959759                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52218.521665                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52339.146586                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55909.959759                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52218.521665                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52339.146586                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57478.162651                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61440.930788                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58651.590106                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52910.345482                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52910.345482                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57478.162651                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53031.829923                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53177.419620                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57478.162651                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53031.829923                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53177.419620                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements           2072514                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4069.513707                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            71413623                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           2076610                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             34.389521                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle       20690834250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4069.513707                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.993534                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.993534                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements           2072506                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4069.429006                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            71361494                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           2076602                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             34.364550                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle       20660759250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4069.429006                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.993513                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.993513                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          593                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         3349                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          154                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          573                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         3367                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          156                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         150351466                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        150351466                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     40071930                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        40071930                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     31341693                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       31341693                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      71413623                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         71413623                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     71413623                       # number of overall hits
-system.cpu.dcache.overall_hits::total        71413623                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      2625746                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       2625746                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data        98059                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total        98059                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      2723805                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2723805                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      2723805                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2723805                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  31399016250                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  31399016250                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   2779679498                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   2779679498                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  34178695748                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  34178695748                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  34178695748                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  34178695748                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     42697676                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     42697676                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses         150248380                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        150248380                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     40019790                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        40019790                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     31341704                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       31341704                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      71361494                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         71361494                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     71361494                       # number of overall hits
+system.cpu.dcache.overall_hits::total        71361494                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      2626347                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       2626347                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data        98048                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        98048                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      2724395                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2724395                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2724395                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2724395                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  31407355250                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  31407355250                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   2801736997                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   2801736997                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  34209092247                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  34209092247                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  34209092247                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  34209092247                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     42646137                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     42646137                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     31439752                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     31439752                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     74137428                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     74137428                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     74137428                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     74137428                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.061496                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.061496                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data     74085889                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     74085889                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     74085889                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     74085889                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.061585                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.061585                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.003119                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.003119                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.036740                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.036740                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.036740                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.036740                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11958.131613                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 11958.131613                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28347.010453                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 28347.010453                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 12548.143405                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 12548.143405                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 12548.143405                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 12548.143405                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs        32707                       # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data     0.036773                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.036773                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.036773                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.036773                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11958.570307                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 11958.570307                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28575.157035                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 28575.157035                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 12556.583112                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 12556.583112                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 12556.583112                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 12556.583112                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs        32689                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs              9497                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              9492                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     3.443930                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     3.443847                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      2066887                       # number of writebacks
-system.cpu.dcache.writebacks::total           2066887                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       631351                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       631351                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        15843                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        15843                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       647194                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       647194                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       647194                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       647194                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1994395                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1994395                       # number of ReadReq MSHR misses
+system.cpu.dcache.writebacks::writebacks      2066395                       # number of writebacks
+system.cpu.dcache.writebacks::total           2066395                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       631958                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       631958                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        15832                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        15832                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       647790                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       647790                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       647790                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       647790                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1994389                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1994389                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data        82216                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total        82216                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      2076611                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      2076611                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      2076611                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      2076611                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  21996462750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  21996462750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2491650748                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   2491650748                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  24488113498                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  24488113498                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  24488113498                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  24488113498                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.046710                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.046710                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_misses::cpu.data      2076605                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      2076605                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      2076605                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      2076605                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  21997400000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  21997400000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2514181749                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   2514181749                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  24511581749                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  24511581749                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  24511581749                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  24511581749                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.046766                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.046766                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.002615                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.002615                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.028010                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.028010                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.028010                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.028010                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11029.140541                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11029.140541                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30306.153887                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30306.153887                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11792.345075                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 11792.345075                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11792.345075                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 11792.345075                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.028030                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.028030                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.028030                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.028030                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11029.643665                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11029.643665                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30580.200314                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30580.200314                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11803.680406                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 11803.680406                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11803.680406                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 11803.680406                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 4ea8f08d5695b426882eaeccebeb5280ce2f9725..50a810bbd0a5b6d25f5a14ba5a9eb70d9939c710 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.202697                       # Number of seconds simulated
-sim_ticks                                202696649500                       # Number of ticks simulated
-final_tick                               202696649500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.202387                       # Number of seconds simulated
+sim_ticks                                202386636500                       # Number of ticks simulated
+final_tick                               202386636500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 142513                       # Simulator instruction rate (inst/s)
-host_op_rate                                   160675                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               57175030                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 274024                       # Number of bytes of host memory used
-host_seconds                                  3545.20                       # Real time elapsed on the host
+host_inst_rate                                 118405                       # Simulator instruction rate (inst/s)
+host_op_rate                                   133495                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               47430504                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 317288                       # Number of bytes of host memory used
+host_seconds                                  4267.01                       # Real time elapsed on the host
 sim_insts                                   505237723                       # Number of instructions simulated
 sim_ops                                     569624283                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            215936                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9269696                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              9485632                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       215936                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          215936                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      6249792                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6249792                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               3374                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             144839                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                148213                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           97653                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                97653                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst              1065316                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             45731866                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                46797182                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         1065316                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            1065316                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          30833228                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               30833228                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          30833228                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             1065316                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            45731866                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               77630410                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        148213                       # Number of read requests accepted
-system.physmem.writeReqs                        97653                       # Number of write requests accepted
-system.physmem.readBursts                      148213                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      97653                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  9481152                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      4480                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   6249152                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   9485632                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                6249792                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                       70                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst            215296                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9261568                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              9476864                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       215296                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          215296                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      6245824                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           6245824                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               3364                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             144712                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                148076                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           97591                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                97591                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst              1063786                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             45761757                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                46825542                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1063786                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1063786                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          30860852                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               30860852                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          30860852                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             1063786                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            45761757                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               77686394                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        148077                       # Number of read requests accepted
+system.physmem.writeReqs                        97591                       # Number of write requests accepted
+system.physmem.readBursts                      148077                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      97591                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  9467712                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      9216                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   6243712                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   9476928                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                6245824                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      144                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs              7                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                9594                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                9237                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                9258                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                8983                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                9776                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                9641                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                9120                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                8318                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                8799                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                8914                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               8952                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               9727                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               9657                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               9778                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               8939                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               9450                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                6271                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                6158                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                6091                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                5883                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                6254                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                6272                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6041                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                5553                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                5808                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                5908                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               5990                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6516                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               6373                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               6333                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               6051                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               6141                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs              9                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0                9595                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                9241                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                9230                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                8948                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                9774                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                9652                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                9107                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                8317                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                8793                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                8911                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               8931                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               9713                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               9649                       # Per bank write bursts
+system.physmem.perBankRdBursts::13               9746                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               8931                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               9395                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                6267                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                6152                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                6088                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                5869                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                6257                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                6287                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6043                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                5545                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                5805                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                5895                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               5984                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6504                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               6370                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               6330                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               6044                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               6118                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    202696525000                       # Total gap between requests
+system.physmem.totGap                    202386616500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  148213                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  148077                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  97653                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    138426                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      9137                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       517                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        50                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        11                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  97591                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    138091                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      9280                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       494                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        59                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         9                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
@@ -129,177 +129,177 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                      4327                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                      4407                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                      4462                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                      4491                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                      4457                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                      4447                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                      4477                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                      4461                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                      4448                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                      4431                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                     4431                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                     4427                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                     4432                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                     4427                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                     4424                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     4406                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     4407                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4429                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4442                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     4421                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     4459                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     4501                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                       15                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                        6                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                        1                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        69151                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      227.469277                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     137.950297                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     327.311281                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64             32073     46.38%     46.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128            12750     18.44%     64.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192             5391      7.80%     72.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256             3340      4.83%     77.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320             2388      3.45%     80.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384             2364      3.42%     84.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448             3443      4.98%     89.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512             1961      2.84%     92.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576              807      1.17%     93.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640              577      0.83%     94.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704              471      0.68%     94.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768              358      0.52%     95.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832              272      0.39%     95.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896              260      0.38%     96.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960              188      0.27%     96.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024             160      0.23%     96.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088             170      0.25%     96.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152             142      0.21%     97.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216             124      0.18%     97.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280             152      0.22%     97.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344             134      0.19%     97.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408             815      1.18%     98.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472             105      0.15%     98.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536             136      0.20%     99.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600              73      0.11%     99.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664              89      0.13%     99.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1728              48      0.07%     99.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1792              64      0.09%     99.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856              20      0.03%     99.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1920              34      0.05%     99.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984              22      0.03%     99.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2048              21      0.03%     99.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112               9      0.01%     99.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2176              15      0.02%     99.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2240               7      0.01%     99.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2304              10      0.01%     99.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2368               5      0.01%     99.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2432               4      0.01%     99.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2496               7      0.01%     99.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2560               7      0.01%     99.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2624              10      0.01%     99.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2688               8      0.01%     99.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2752               7      0.01%     99.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2816               6      0.01%     99.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2880               4      0.01%     99.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2944               4      0.01%     99.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3008               2      0.00%     99.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3072               4      0.01%     99.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3136               2      0.00%     99.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3200               3      0.00%     99.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3264               4      0.01%     99.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3328               5      0.01%     99.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3392               2      0.00%     99.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3456               1      0.00%     99.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3520               4      0.01%     99.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3584               4      0.01%     99.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3648               3      0.00%     99.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3712               2      0.00%     99.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3776               4      0.01%     99.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3904               1      0.00%     99.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3968               1      0.00%     99.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4032               2      0.00%     99.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4096               2      0.00%     99.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4160               1      0.00%     99.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4224               2      0.00%     99.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4352               1      0.00%     99.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4416               4      0.01%     99.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4480               1      0.00%     99.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4544               3      0.00%     99.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4608               1      0.00%     99.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4672               3      0.00%     99.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4736               1      0.00%     99.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4800               4      0.01%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4864               4      0.01%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4928               6      0.01%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4992               8      0.01%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5056               4      0.01%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5120               4      0.01%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5248               1      0.00%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5376               1      0.00%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5504               1      0.00%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          69151                       # Bytes accessed per row activation
-system.physmem.totQLat                     1733842500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                4938805000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    740715000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                  2464247500                       # Total ticks spent accessing banks
-system.physmem.avgQLat                       11703.84                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    16634.25                       # Average bank access latency per DRAM burst
+system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     1942                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2167                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     2625                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     4944                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     5396                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     5464                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     5496                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     5554                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     5550                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     5554                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     6518                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     5915                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     5951                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     7213                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     5991                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     5771                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     5705                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     5565                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      917                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      289                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      217                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      195                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      188                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      173                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      176                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      168                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      166                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      165                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      160                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      152                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      153                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      152                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      156                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      153                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      146                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      142                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      128                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      125                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      124                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        39628                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      257.573029                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     159.018208                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     287.256707                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          15558     39.26%     39.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        11171     28.19%     67.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         4346     10.97%     78.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2186      5.52%     83.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         1365      3.44%     87.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          780      1.97%     89.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          563      1.42%     90.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          515      1.30%     92.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         3144      7.93%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          39628                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5484                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        26.971554                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      384.653172                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           5482     99.96%     99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047            1      0.02%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::27648-28671            1      0.02%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            5484                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5484                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.789570                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.450739                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        4.762634                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-17            3346     61.01%     61.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18-19            1810     33.01%     94.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-21             182      3.32%     97.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22-23              11      0.20%     97.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-25               3      0.05%     97.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26-27               4      0.07%     97.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-29               3      0.05%     97.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30-31               1      0.02%     97.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-33               3      0.05%     97.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::34-35               1      0.02%     97.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-37               1      0.02%     97.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::38-39              12      0.22%     98.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-41              29      0.53%     98.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::42-43              19      0.35%     98.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-45               8      0.15%     99.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::46-47               7      0.13%     99.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-49               7      0.13%     99.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::50-51               8      0.15%     99.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-53               9      0.16%     99.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::54-55               6      0.11%     99.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-57               4      0.07%     99.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::58-59               3      0.05%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::62-63               1      0.02%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-65               2      0.04%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::66-67               1      0.02%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-73               1      0.02%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-77               1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::90-91               1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5484                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     1351646500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                4559189000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    739665000                       # Total ticks spent in databus transfers
+system.physmem.totBankLat                  2467877500                       # Total ticks spent accessing banks
+system.physmem.avgQLat                        9136.88                       # Average queueing delay per DRAM burst
+system.physmem.avgBankLat                    16682.40                       # Average bank access latency per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  33338.09                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  30819.28                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                          46.78                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          30.83                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       46.80                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       30.83                       # Average system write bandwidth in MiByte/s
+system.physmem.avgWrBW                          30.85                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       46.83                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       30.86                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.61                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.37                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.24                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         0.02                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                         8.92                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     118670                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     57965                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   80.11                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  59.36                       # Row buffer hit rate for writes
-system.physmem.avgGap                       824418.69                       # Average gap between requests
-system.physmem.pageHitRate                      71.86                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               4.58                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                     77630410                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq               46935                       # Transaction distribution
-system.membus.trans_dist::ReadResp              46935                       # Transaction distribution
-system.membus.trans_dist::Writeback             97653                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq                7                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp               7                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            101278                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           101278                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       394093                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 394093                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15735424                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            15735424                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus               15735424                       # Total data (bytes)
+system.physmem.avgRdQLen                         1.05                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        20.36                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     116029                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     64903                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   78.43                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  66.51                       # Row buffer hit rate for writes
+system.physmem.avgGap                       823821.65                       # Average gap between requests
+system.physmem.pageHitRate                      73.69                       # Row buffer hit rate, read and write combined
+system.physmem.prechargeAllPercent               4.51                       # Percentage of time for which DRAM has all the banks in precharge state
+system.membus.throughput                     77686394                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq               46784                       # Transaction distribution
+system.membus.trans_dist::ReadResp              46783                       # Transaction distribution
+system.membus.trans_dist::Writeback             97591                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq                9                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp               9                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            101293                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           101293                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       393762                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 393762                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15722688                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total            15722688                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               15722688                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy          1083458000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy          1083423500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.5                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         1398218993                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         1396187241                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.7                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups               182767812                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         143090812                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           7262422                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             93142512                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                87193307                       # Number of BTB hits
+system.cpu.branchPred.lookups               182802497                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         143128799                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           7265604                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             92710665                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                87222146                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             93.612793                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                12680291                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect             116092                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             94.079949                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                12678300                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             116271                       # Number of incorrect RAS predictions.
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -385,134 +385,134 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  548                       # Number of system calls
-system.cpu.numCycles                        405393300                       # number of cpu cycles simulated
+system.cpu.numCycles                        404773274                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          119358761                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      761461935                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   182767812                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           99873598                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     170116443                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                35667741                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles               77537943                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                   37                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles           427                       # Number of stall cycles due to pending traps
+system.cpu.fetch.icacheStallCycles          119371431                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      761670050                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   182802497                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           99900446                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     170159805                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                35695191                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles               77489066                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                   40                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles           409                       # Number of stall cycles due to pending traps
 system.cpu.fetch.IcacheWaitRetryStallCycles           15                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 114511433                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               2436940                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          394614975                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.164245                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.986660                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines                 114520254                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               2435167                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          394646362                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.164609                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.986746                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                224511182     56.89%     56.89% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 14185619      3.59%     60.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 22882928      5.80%     66.29% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 22735959      5.76%     72.05% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 20902964      5.30%     77.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 11599090      2.94%     80.29% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 13052635      3.31%     83.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 11995684      3.04%     86.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 52748914     13.37%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                224499175     56.89%     56.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 14180048      3.59%     60.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 22900330      5.80%     66.28% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 22746018      5.76%     72.05% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 20904181      5.30%     77.34% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 11597078      2.94%     80.28% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 13062660      3.31%     83.59% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 11996924      3.04%     86.63% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 52759948     13.37%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            394614975                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.450841                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.878329                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                129045860                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              73029235                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 158776788                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               6235766                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               27527326                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             26113836                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 76704                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              825433505                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                295928                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles               27527326                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                135634392                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                10115343                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       47882338                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 158241210                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              15214366                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              800503248                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                  1357                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                3055222                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               8963577                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents              323                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           954180101                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            3518022066                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       3236814887                       # Number of integer rename lookups
+system.cpu.fetch.rateDist::total            394646362                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.451617                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.881720                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                129065441                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              72977589                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 158843318                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               6208520                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               27551494                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             26113840                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 76933                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              825615862                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                295408                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles               27551494                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                135663599                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                10124037                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       47858907                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 158270703                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              15177622                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              800676203                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                  1362                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                3041401                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               8927839                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents              380                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           954380743                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            3518821037                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       3237543722                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups               408                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             666252291                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                287927810                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts            2293035                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts        2293033                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  41823481                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            170244853                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            73468690                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          28584671                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         15947575                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  754970143                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             3775446                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 665247715                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           1368678                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       187299729                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    479807189                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         797814                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     394614975                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.685815                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.734907                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                288128452                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            2293069                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts        2293066                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  41767697                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            170285712                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            73492930                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          28608200                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         15804502                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  755130380                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             3775454                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 665331830                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           1375167                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       187454297                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    480174835                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         797822                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     394646362                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.685894                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.735410                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           139112608     35.25%     35.25% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            69963718     17.73%     52.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            71480339     18.11%     71.10% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            53412881     13.54%     84.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            31169155      7.90%     92.53% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            15993671      4.05%     96.58% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             8759011      2.22%     98.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             2903101      0.74%     99.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             1820491      0.46%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           139160941     35.26%     35.26% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            69972049     17.73%     52.99% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            71433490     18.10%     71.09% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            53381143     13.53%     84.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            31203736      7.91%     92.53% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            16006372      4.06%     96.58% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             8742132      2.22%     98.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             2922216      0.74%     99.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             1824283      0.46%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       394614975                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       394646362                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  480625      5.03%      5.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      5.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      5.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      5.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      5.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      5.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      5.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      5.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      5.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      5.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      5.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      5.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      5.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      5.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      5.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      5.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      5.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      5.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      5.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      5.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      5.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      5.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      5.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      5.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      5.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      5.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      5.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      5.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      5.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                6529255     68.28%     73.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               2553152     26.70%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  481604      5.01%      5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                6543314     68.07%     73.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               2587932     26.92%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             447743251     67.30%     67.30% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               383309      0.06%     67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             447808389     67.31%     67.31% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               383403      0.06%     67.36% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.36% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                  94      0.00%     67.36% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.36% # Type of FU issued
@@ -540,84 +540,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.00%     67.36% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.36% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.36% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.36% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            153363071     23.05%     90.42% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            63757987      9.58%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            153377795     23.05%     90.42% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            63762146      9.58%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              665247715                       # Type of FU issued
-system.cpu.iq.rate                           1.640993                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     9563032                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.014375                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         1736041890                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         946851577                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    645982069                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 225                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                304                       # Number of floating instruction queue writes
+system.cpu.iq.FU_type_0::total              665331830                       # Type of FU issued
+system.cpu.iq.rate                           1.643715                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     9612850                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.014448                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         1736297816                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         947166381                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    646062448                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 223                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                298                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              674810634                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses              674944567                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                     113                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          8546846                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads          8567764                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     44215298                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        41270                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       810207                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     16608213                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     44256157                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        42344                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       810357                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     16632453                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        19520                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          8279                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        19504                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          8568                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               27527326                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 5271033                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                384981                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           760303523                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts           1119045                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             170244853                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             73468690                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            2286904                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 219731                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 11453                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         810207                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        4335544                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      4001823                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              8337367                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             655831134                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             150081839                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           9416581                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles               27551494                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 5275843                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                386509                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           760464256                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           1125230                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             170285712                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             73492930                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            2286912                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 220350                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 11309                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         810357                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        4338774                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      4002387                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              8341161                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             655913475                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             150097155                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           9418355                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                       1557934                       # number of nop insts executed
-system.cpu.iew.exec_refs                    212547196                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                138487054                       # Number of branches executed
-system.cpu.iew.exec_stores                   62465357                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.617765                       # Inst execution rate
-system.cpu.iew.wb_sent                      650951989                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     645982085                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 374676308                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 646230138                       # num instructions consuming a value
+system.cpu.iew.exec_nop                       1558422                       # number of nop insts executed
+system.cpu.iew.exec_refs                    212571042                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                138499517                       # Number of branches executed
+system.cpu.iew.exec_stores                   62473887                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.620447                       # Inst execution rate
+system.cpu.iew.wb_sent                      651035258                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     646062464                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 374747617                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 646369396                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.593470                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.579788                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.596109                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.579773                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts       189364408                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       189524475                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls         2977632                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           7188399                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    367087649                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.555400                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.230509                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           7191502                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    367094868                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.555370                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.229648                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    159393543     43.42%     43.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     98511772     26.84%     70.26% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     33830447      9.22%     79.47% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     18783252      5.12%     84.59% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     16176645      4.41%     89.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      7442765      2.03%     91.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      6952611      1.89%     92.92% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      3163238      0.86%     93.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     22833376      6.22%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    159372239     43.41%     43.41% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     98509322     26.83%     70.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     33822268      9.21%     79.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     18793314      5.12%     84.58% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     16194287      4.41%     88.99% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      7448885      2.03%     91.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      7004810      1.91%     92.93% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      3214010      0.88%     93.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     22735733      6.19%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    367087649                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    367094868                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            506581607                       # Number of instructions committed
 system.cpu.commit.committedOps              570968167                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -628,239 +628,243 @@ system.cpu.commit.branches                  121548301                       # Nu
 system.cpu.commit.fp_insts                         16                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                 470727693                       # Number of committed integer instructions.
 system.cpu.commit.function_calls              9757362                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events              22833376                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events              22735733                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   1104579710                       # The number of ROB reads
-system.cpu.rob.rob_writes                  1548313166                       # The number of ROB writes
-system.cpu.timesIdled                          328667                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        10778325                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                   1104844639                       # The number of ROB reads
+system.cpu.rob.rob_writes                  1548657613                       # The number of ROB writes
+system.cpu.timesIdled                          329536                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        10126912                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   505237723                       # Number of Instructions Simulated
 system.cpu.committedOps                     569624283                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total             505237723                       # Number of Instructions Simulated
-system.cpu.cpi                               0.802381                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.802381                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.246290                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.246290                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               3058357965                       # number of integer regfile reads
-system.cpu.int_regfile_writes               751931601                       # number of integer regfile writes
+system.cpu.cpi                               0.801154                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.801154                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.248199                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.248199                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               3058738251                       # number of integer regfile reads
+system.cpu.int_regfile_writes               752038270                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
-system.cpu.misc_regfile_reads               237823379                       # number of misc regfile reads
+system.cpu.misc_regfile_reads               237846973                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                2977084                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput               733902057                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq         864632                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp        864632                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      1110906                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq           71                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp           71                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       348829                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       348829                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        33629                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3504262                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           3537891                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1073600                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    147680832                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      148754432                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus         148754432                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus         5056                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy     2273126497                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.throughput               735012008                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq         864661                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp        864660                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      1110883                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq           79                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp           79                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       348779                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       348779                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        33728                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3504101                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           3537829                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1076352                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    147674432                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      148750784                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         148750784                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus         5824                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy     2273084998                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      25848480                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      25918735                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1823961981                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1823048732                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.9                       # Layer utilization (%)
-system.cpu.icache.tags.replacements             14927                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1097.546967                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           114490465                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             16785                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           6820.998808                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements             14973                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1095.994633                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           114499162                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             16828                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           6804.086166                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1097.546967                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.535912                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.535912                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1858                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           40                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           58                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           78                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          302                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1380                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.907227                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         229039718                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        229039718                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    114490465                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       114490465                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     114490465                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        114490465                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    114490465                       # number of overall hits
-system.cpu.icache.overall_hits::total       114490465                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        20967                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         20967                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        20967                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          20967                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        20967                       # number of overall misses
-system.cpu.icache.overall_misses::total         20967                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    566965977                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    566965977                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    566965977                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    566965977                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    566965977                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    566965977                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    114511432                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    114511432                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    114511432                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    114511432                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    114511432                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    114511432                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000183                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000183                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000183                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000183                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000183                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000183                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27040.872657                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 27040.872657                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 27040.872657                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 27040.872657                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 27040.872657                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 27040.872657                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         1029                       # number of cycles access was blocked
+system.cpu.icache.tags.occ_blocks::cpu.inst  1095.994633                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.535154                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.535154                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1855                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           43                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           54                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           79                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          300                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1379                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.905762                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         229057415                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        229057415                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    114499162                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       114499162                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     114499162                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        114499162                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    114499162                       # number of overall hits
+system.cpu.icache.overall_hits::total       114499162                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        21091                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         21091                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        21091                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          21091                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        21091                       # number of overall misses
+system.cpu.icache.overall_misses::total         21091                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    555853234                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    555853234                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    555853234                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    555853234                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    555853234                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    555853234                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    114520253                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    114520253                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    114520253                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    114520253                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    114520253                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    114520253                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000184                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000184                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000184                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000184                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000184                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000184                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26354.996634                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 26354.996634                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 26354.996634                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 26354.996634                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 26354.996634                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 26354.996634                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          663                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                12                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                11                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    85.750000                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    60.272727                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         4113                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         4113                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         4113                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         4113                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         4113                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         4113                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        16854                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        16854                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        16854                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        16854                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        16854                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        16854                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    413760769                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    413760769                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    413760769                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    413760769                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    413760769                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    413760769                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000147                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000147                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000147                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000147                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000147                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000147                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24549.707429                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24549.707429                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24549.707429                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 24549.707429                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24549.707429                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 24549.707429                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         4181                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         4181                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         4181                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         4181                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         4181                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         4181                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        16910                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        16910                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        16910                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        16910                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        16910                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        16910                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    402050014                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    402050014                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    402050014                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    402050014                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    402050014                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    402050014                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000148                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000148                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000148                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000148                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000148                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000148                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23775.873093                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23775.873093                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23775.873093                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 23775.873093                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23775.873093                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 23775.873093                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           115464                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        27088.798678                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1780777                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           146712                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            12.137910                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle     102535173000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 23012.092696                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   360.882153                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  3715.823828                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.702273                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.011013                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.113398                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.826685                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        31248                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           69                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1            2                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2200                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         7669                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        21308                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.953613                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         19090479                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        19090479                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst        13395                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data       804194                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total         817589                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      1110906                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      1110906                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data           66                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total           66                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       247549                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       247549                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        13395                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      1051743                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         1065138                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst        13395                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      1051743                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        1065138                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         3380                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data        43584                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        46964                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data            5                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total            5                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       101280                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       101280                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         3380                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       144864                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        148244                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         3380                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       144864                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       148244                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    262616000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data   3492071500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total   3754687500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   7549884498                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   7549884498                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    262616000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  11041955998                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  11304571998                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    262616000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  11041955998                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  11304571998                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst        16775                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data       847778                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total       864553                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      1110906                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      1110906                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data           71                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total           71                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       348829                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       348829                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        16775                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      1196607                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      1213382                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        16775                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      1196607                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      1213382                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.201490                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.051410                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.054322                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.070423                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.070423                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.290343                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.290343                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.201490                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.121062                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.122174                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.201490                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.121062                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.122174                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77697.041420                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80122.785885                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 79948.205008                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74544.673164                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74544.673164                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77697.041420                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76222.912511                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 76256.523016                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77697.041420                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76222.912511                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 76256.523016                       # average overall miss latency
+system.cpu.l2cache.tags.replacements           115331                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        27082.895535                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            1781400                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           146592                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            12.152096                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle     102338963500                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 23017.339474                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   360.906574                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  3704.649487                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.702433                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.011014                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.113057                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.826504                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        31261                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           76                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1            4                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2190                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         7667                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        21324                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.954010                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         19089931                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        19089931                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst        13449                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data       804311                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         817760                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      1110883                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      1110883                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data           71                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total           71                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       247485                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       247485                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst        13449                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      1051796                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         1065245                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst        13449                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      1051796                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        1065245                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         3370                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data        43440                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        46810                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data            8                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total            8                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       101294                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       101294                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         3370                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       144734                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        148104                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         3370                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       144734                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       148104                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    250298750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data   3365658750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   3615957500                       # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data        23499                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total        23499                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   7297338249                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   7297338249                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    250298750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  10662996999                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  10913295749                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    250298750                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  10662996999                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  10913295749                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst        16819                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data       847751                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       864570                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      1110883                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      1110883                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data           79                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total           79                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       348779                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       348779                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        16819                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      1196530                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      1213349                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        16819                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      1196530                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      1213349                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.200369                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.051241                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.054143                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.101266                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.101266                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.290425                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.290425                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.200369                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.120961                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.122062                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.200369                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.120961                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.122062                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74272.626113                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77478.332182                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 77247.543260                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data  2937.375000                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total  2937.375000                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72041.169753                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72041.169753                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74272.626113                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73673.062300                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 73686.704944                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74272.626113                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73673.062300                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 73686.704944                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -869,203 +873,203 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        97653                       # number of writebacks
-system.cpu.l2cache.writebacks::total            97653                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            6                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           23                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total           29                       # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst            6                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data           23                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total           29                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst            6                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data           23                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total           29                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3374                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        43561                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        46935                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            5                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total            5                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       101280                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       101280                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3374                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       144841                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       148215                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3374                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       144841                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       148215                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    219732000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   2944554000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   3164286000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        50005                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        50005                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6265225502                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6265225502                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    219732000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   9209779502                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   9429511502                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    219732000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   9209779502                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   9429511502                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.201133                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.051383                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.054288                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.070423                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.070423                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.290343                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.290343                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.201133                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.121043                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.122150                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.201133                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.121043                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.122150                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65125.074096                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67596.106609                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67418.472355                       # average ReadReq mshr miss latency
+system.cpu.l2cache.writebacks::writebacks        97591                       # number of writebacks
+system.cpu.l2cache.writebacks::total            97591                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            5                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           21                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total           26                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst            5                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data           21                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           26                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst            5                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data           21                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total           26                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3365                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        43419                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        46784                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            8                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total            8                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       101294                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       101294                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3365                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       144713                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       148078                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3365                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       144713                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       148078                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    207676000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   2821069500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   3028745500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        80008                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        80008                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6013621251                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6013621251                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    207676000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   8834690751                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   9042366751                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    207676000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8834690751                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   9042366751                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.200071                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.051217                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.054112                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.101266                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.101266                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.290425                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.290425                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.200071                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.120944                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.122041                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.200071                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.120944                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.122041                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61716.493314                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64973.156913                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64738.917151                       # average ReadReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        10001                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61860.441370                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61860.441370                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65125.074096                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63585.445433                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63620.493891                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65125.074096                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63585.445433                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63620.493891                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59367.990710                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59367.990710                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61716.493314                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61049.738109                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61064.889795                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61716.493314                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61049.738109                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61064.889795                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements           1192511                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4057.506365                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           190177939                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1196607                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            158.930993                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.replacements           1192434                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4057.447359                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           190168921                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1196530                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            158.933684                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle        4256684250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4057.506365                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.990602                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.990602                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data  4057.447359                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.990588                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.990588                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           36                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           22                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         2352                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3         1686                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           41                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           26                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         2348                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         1681                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         391455847                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        391455847                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    136212044                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       136212044                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     50988351                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       50988351                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data      1488804                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total      1488804                       # number of LoadLockedReq hits
+system.cpu.dcache.tags.tag_accesses         391443552                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        391443552                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    136203085                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       136203085                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     50988219                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       50988219                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data      1488837                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total      1488837                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data      1488541                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total      1488541                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     187200395                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        187200395                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    187200395                       # number of overall hits
-system.cpu.dcache.overall_hits::total       187200395                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1700889                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1700889                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      3250955                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      3250955                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data           36                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total           36                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      4951844                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        4951844                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      4951844                       # number of overall misses
-system.cpu.dcache.overall_misses::total       4951844                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  29691567711                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  29691567711                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  72513714730                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  72513714730                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       595500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total       595500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 102205282441                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 102205282441                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 102205282441                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 102205282441                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    137912933                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    137912933                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_hits::cpu.data     187191304                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        187191304                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    187191304                       # number of overall hits
+system.cpu.dcache.overall_hits::total       187191304                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1703703                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1703703                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      3251087                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      3251087                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data           39                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total           39                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data      4954790                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        4954790                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      4954790                       # number of overall misses
+system.cpu.dcache.overall_misses::total       4954790                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  29263316713                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  29263316713                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  70545580472                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  70545580472                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       635500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total       635500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  99808897185                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  99808897185                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  99808897185                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  99808897185                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    137906788                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    137906788                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     54239306                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     54239306                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data      1488840                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total      1488840                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data      1488876                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total      1488876                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data      1488541                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total      1488541                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    192152239                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    192152239                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    192152239                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    192152239                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.012333                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.012333                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.059937                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.059937                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000024                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000024                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.025770                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.025770                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.025770                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.025770                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17456.499343                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 17456.499343                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 22305.357881                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 22305.357881                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16541.666667                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16541.666667                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 20639.842944                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 20639.842944                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 20639.842944                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 20639.842944                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs        17574                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets        52604                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs              1663                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets             661                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    10.567649                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    79.582451                       # average number of cycles each access was blocked
+system.cpu.dcache.demand_accesses::cpu.data    192146094                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    192146094                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    192146094                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    192146094                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.012354                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.012354                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.059940                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.059940                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000026                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000026                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.025787                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.025787                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.025787                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.025787                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17176.301687                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 17176.301687                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21699.074947                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 21699.074947                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16294.871795                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16294.871795                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 20143.920769                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 20143.920769                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 20143.920769                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 20143.920769                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs        17635                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets        54424                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              1686                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets             666                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    10.459668                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    81.717718                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      1110906                       # number of writebacks
-system.cpu.dcache.writebacks::total           1110906                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       852565                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       852565                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      2902601                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      2902601                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           36                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total           36                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      3755166                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      3755166                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      3755166                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      3755166                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       848324                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       848324                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       348354                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       348354                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1196678                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1196678                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1196678                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1196678                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  12420423026                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  12420423026                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10423297989                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  10423297989                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  22843721015                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  22843721015                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  22843721015                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  22843721015                       # number of overall MSHR miss cycles
+system.cpu.dcache.writebacks::writebacks      1110883                       # number of writebacks
+system.cpu.dcache.writebacks::total           1110883                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       855409                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       855409                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      2902772                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      2902772                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           39                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total           39                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      3758181                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      3758181                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      3758181                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      3758181                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       848294                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       848294                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       348315                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       348315                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1196609                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1196609                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1196609                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1196609                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  12295329526                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  12295329526                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10170217738                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  10170217738                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  22465547264                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  22465547264                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  22465547264                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  22465547264                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006151                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006151                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006423                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006423                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006422                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006422                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006228                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total     0.006228                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006228                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.006228                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14641.131249                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14641.131249                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29921.568258                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29921.568258                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19089.279668                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 19089.279668                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19089.279668                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 19089.279668                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14494.184240                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14494.184240                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29198.334088                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29198.334088                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18774.342550                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 18774.342550                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18774.342550                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 18774.342550                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 7553b77093323c3c173957f841e07d4336b9e8d3..a5895db0e5c2e2785ffbe720c1d46da54e9740f6 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.459119                       # Number of seconds simulated
-sim_ticks                                459118646000                       # Number of ticks simulated
-final_tick                               459118646000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.458346                       # Number of seconds simulated
+sim_ticks                                458345683000                       # Number of ticks simulated
+final_tick                               458345683000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  66655                       # Simulator instruction rate (inst/s)
-host_op_rate                                   123253                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               37009979                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 397004                       # Number of bytes of host memory used
-host_seconds                                 12405.27                       # Real time elapsed on the host
+host_inst_rate                                  77949                       # Simulator instruction rate (inst/s)
+host_op_rate                                   144137                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               43207948                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 382980                       # Number of bytes of host memory used
+host_seconds                                 10607.90                       # Real time elapsed on the host
 sim_insts                                   826877109                       # Number of instructions simulated
 sim_ops                                    1528988701                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            202048                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          24472064                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             24674112                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       202048                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          202048                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     18787264                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          18787264                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               3157                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             382376                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                385533                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          293551                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               293551                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               440078                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             53302266                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                53742344                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          440078                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             440078                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          40920281                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               40920281                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          40920281                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              440078                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            53302266                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               94662625                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        385533                       # Number of read requests accepted
-system.physmem.writeReqs                       293551                       # Number of write requests accepted
-system.physmem.readBursts                      385533                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     293551                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 24663104                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     11008                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  18787008                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  24674112                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               18787264                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      172                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst            201344                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          24476224                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             24677568                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       201344                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          201344                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     18790080                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          18790080                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               3146                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             382441                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                385587                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          293595                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               293595                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               439284                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             53401232                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                53840516                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          439284                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             439284                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          40995434                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               40995434                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          40995434                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              439284                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            53401232                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               94835949                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        385587                       # Number of read requests accepted
+system.physmem.writeReqs                       293595                       # Number of write requests accepted
+system.physmem.readBursts                      385587                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     293595                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 24655680                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     21888                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  18787904                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  24677568                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               18790080                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      342                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs         134286                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               24058                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               26419                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               24669                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               24489                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               23234                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               23657                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               24395                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               24194                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               23609                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               23827                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              24795                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              24049                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              23230                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              22964                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              23781                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              23991                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               18530                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               19817                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               18937                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               18901                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               18031                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               18405                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs         137451                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               23999                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               26321                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               24635                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               24488                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               23208                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               23662                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               24431                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               24245                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               23683                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               23822                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              24823                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              24044                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              23228                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              22920                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              23793                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              23943                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               18539                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               19811                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               18919                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               18907                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               18016                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               18404                       # Per bank write bursts
 system.physmem.perBankWrBursts::6               18977                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               18937                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               18537                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               18113                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              18820                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              17706                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               18938                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               18573                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               18106                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              18839                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              17716                       # Per bank write bursts
 system.physmem.perBankWrBursts::12              17343                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              16958                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              17714                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              17821                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              16932                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              17725                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              17816                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    459118532000                       # Total gap between requests
+system.physmem.totGap                    458345657000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  385533                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  385587                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 293551                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    380740                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      4302                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       283                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        32                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         4                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 293595                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    380584                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      4329                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       291                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        30                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         9                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
@@ -129,327 +129,303 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                     13202                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                     13291                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                     13315                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                     13330                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                     13327                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                     13318                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                     13375                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                     13367                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                     13375                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                     13396                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                    13419                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                    13353                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                    13357                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                    13368                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                    13341                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    13319                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    13314                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    13315                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    13324                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    13309                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    13490                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    13282                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                       17                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                       12                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                        6                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                        7                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       147556                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      294.463932                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     155.686360                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     443.719039                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64             63845     43.27%     43.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128            27907     18.91%     62.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192            12368      8.38%     70.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256             7167      4.86%     75.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320             4813      3.26%     78.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384             3571      2.42%     81.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448             2697      1.83%     82.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512             2226      1.51%     84.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576             1892      1.28%     85.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640             1575      1.07%     86.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704             1962      1.33%     88.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768             1193      0.81%     88.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832             1191      0.81%     89.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896             1073      0.73%     90.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960              940      0.64%     91.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024             929      0.63%     91.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088            1014      0.69%     92.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152            1122      0.76%     93.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216            1123      0.76%     93.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280             892      0.60%     94.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344             768      0.52%     95.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408            5249      3.56%     98.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472             304      0.21%     98.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536             220      0.15%     98.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600             176      0.12%     99.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664             127      0.09%     99.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1728              88      0.06%     99.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1792              94      0.06%     99.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856              86      0.06%     99.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1920              56      0.04%     99.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984              55      0.04%     99.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2048              48      0.03%     99.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112              43      0.03%     99.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2176              26      0.02%     99.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2240              35      0.02%     99.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2304              32      0.02%     99.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2368              24      0.02%     99.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2432              27      0.02%     99.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2496              18      0.01%     99.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2560              18      0.01%     99.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2624              24      0.02%     99.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2688              20      0.01%     99.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2752              23      0.02%     99.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2816              17      0.01%     99.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2880              18      0.01%     99.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2944              20      0.01%     99.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3008              16      0.01%     99.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3072              19      0.01%     99.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3136              14      0.01%     99.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3200              17      0.01%     99.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3264              12      0.01%     99.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3328              19      0.01%     99.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3392               5      0.00%     99.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3456              18      0.01%     99.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3520              12      0.01%     99.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3584               8      0.01%     99.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3648              14      0.01%     99.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3712              10      0.01%     99.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3776              15      0.01%     99.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3840               9      0.01%     99.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3904               9      0.01%     99.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3968              11      0.01%     99.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4032              10      0.01%     99.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4096              12      0.01%     99.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4160              14      0.01%     99.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4224              20      0.01%     99.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4288              31      0.02%     99.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4352               4      0.00%     99.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4416              10      0.01%     99.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4480               3      0.00%     99.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4544               5      0.00%     99.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4608               2      0.00%     99.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4672               6      0.00%     99.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4736               6      0.00%     99.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4800               2      0.00%     99.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4864               4      0.00%     99.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4928               2      0.00%     99.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4992               4      0.00%     99.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5056               3      0.00%     99.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5120               3      0.00%     99.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5184               4      0.00%     99.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5312               6      0.00%     99.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5376               1      0.00%     99.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5440               5      0.00%     99.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5504               3      0.00%     99.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5568               3      0.00%     99.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5632               2      0.00%     99.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5696               4      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5760               6      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5824               2      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5888               9      0.01%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5952               3      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6016              11      0.01%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6080               4      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6144               1      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6208               3      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6272              19      0.01%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6336               3      0.00%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6528               1      0.00%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7872               1      0.00%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         147556                       # Bytes accessed per row activation
-system.physmem.totQLat                     3828283250                       # Total ticks spent queuing
-system.physmem.totMemAccLat               12084928250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   1926805000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                  6329840000                       # Total ticks spent accessing banks
-system.physmem.avgQLat                        9934.28                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    16425.74                       # Average bank access latency per DRAM burst
+system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     6249                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     6906                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     8122                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    15790                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    16374                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    16588                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    16668                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    16965                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    16912                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    16903                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    21550                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    17962                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    17787                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    22491                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    17603                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    17344                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    17191                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    16827                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     1360                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      517                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      374                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      342                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      329                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      344                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      307                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      311                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      306                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      285                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      286                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      273                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                      282                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                      272                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      274                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      257                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      261                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      248                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      239                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      236                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      235                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        96485                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      354.073856                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     206.339683                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     360.153261                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          30862     31.99%     31.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        25245     26.16%     58.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         9104      9.44%     67.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         4981      5.16%     72.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         3508      3.64%     76.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         2549      2.64%     79.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1904      1.97%     81.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1721      1.78%     82.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        16611     17.22%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          96485                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         16638                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        23.153564                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      214.001392                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023          16625     99.92%     99.92% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047            8      0.05%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-3071            3      0.02%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3072-4095            1      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::25600-26623            1      0.01%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total           16638                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         16638                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.644008                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.412925                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        3.984420                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19           15809     95.02%     95.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             568      3.41%     98.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              13      0.08%     98.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31               7      0.04%     98.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35               5      0.03%     98.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39              61      0.37%     98.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43             106      0.64%     99.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47              27      0.16%     99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51              20      0.12%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55               3      0.02%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               1      0.01%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               6      0.04%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67               1      0.01%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79               1      0.01%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83               1      0.01%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               2      0.01%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99               1      0.01%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103             2      0.01%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107             2      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127             1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131             1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           16638                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2817376000                       # Total ticks spent queuing
+system.physmem.totMemAccLat               11128592250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1926225000                       # Total ticks spent in databus transfers
+system.physmem.totBankLat                  6384991250                       # Total ticks spent accessing banks
+system.physmem.avgQLat                        7313.21                       # Average queueing delay per DRAM burst
+system.physmem.avgBankLat                    16573.85                       # Average bank access latency per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  31360.02                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          53.72                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          40.92                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       53.74                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       40.92                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  28887.05                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          53.79                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          40.99                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       53.84                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       41.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.74                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.42                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.32                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         0.03                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                         9.64                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     326971                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    204381                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   84.85                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  69.62                       # Row buffer hit rate for writes
-system.physmem.avgGap                       676085.04                       # Average gap between requests
-system.physmem.pageHitRate                      78.27                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               5.79                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                     94662625                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq              178699                       # Transaction distribution
-system.membus.trans_dist::ReadResp             178699                       # Transaction distribution
-system.membus.trans_dist::Writeback            293551                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq           134286                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp          134286                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            206834                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           206834                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1333189                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1333189                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1333189                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     43461376                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     43461376                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            43461376                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus               43461376                       # Total data (bytes)
+system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        22.28                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     317177                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    216322                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.33                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  73.68                       # Row buffer hit rate for writes
+system.physmem.avgGap                       674849.54                       # Average gap between requests
+system.physmem.pageHitRate                      78.59                       # Row buffer hit rate, read and write combined
+system.physmem.prechargeAllPercent               5.94                       # Percentage of time for which DRAM has all the banks in precharge state
+system.membus.throughput                     94835949                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq              178789                       # Transaction distribution
+system.membus.trans_dist::ReadResp             178789                       # Transaction distribution
+system.membus.trans_dist::Writeback            293595                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq           137451                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp          137451                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            206798                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           206798                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1339671                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1339671                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1339671                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     43467648                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     43467648                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total            43467648                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               43467648                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy          3389612000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy          3393086500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.7                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         3899599974                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.8                       # Layer utilization (%)
+system.membus.respLayer1.occupancy         3901807065                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              0.9                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups               205593718                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         205593718                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           9903647                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            117157105                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               114691543                       # Number of BTB hits
+system.cpu.branchPred.lookups               205603387                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         205603387                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           9902113                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            117080162                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               114702381                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             97.895508                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                25059747                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect            1804675                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             97.969100                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                25060949                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect            1802781                       # Number of incorrect RAS predictions.
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                  551                       # Number of system calls
-system.cpu.numCycles                        918398587                       # number of cpu cycles simulated
+system.cpu.numCycles                        916852867                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          167393029                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     1131661435                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   205593718                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          139751290                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     352253008                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                71076779                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles              305103735                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                48807                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        255424                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles           42                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 162015300                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               2531137                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          885975121                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.376486                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.323818                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          167425421                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     1131697501                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   205603387                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          139763330                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     352285469                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                71105811                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles              304521969                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                48109                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        252946                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles           61                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 162022121                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               2522560                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          885484431                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.378017                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.324314                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                537792455     60.70%     60.70% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 23395629      2.64%     63.34% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 25258320      2.85%     66.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 27887801      3.15%     69.34% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 17745441      2.00%     71.34% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 22910084      2.59%     73.93% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 29420868      3.32%     77.25% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 26641357      3.01%     80.26% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                174923166     19.74%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                537271116     60.68%     60.68% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 23397088      2.64%     63.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 25262126      2.85%     66.17% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 27864383      3.15%     69.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 17763945      2.01%     71.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 22926561      2.59%     73.91% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 29429676      3.32%     77.24% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 26640012      3.01%     80.24% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                174929524     19.76%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            885975121                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.223861                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.232212                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                222542151                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             260234378                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 295346908                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              46930608                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               60921076                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts             2071264981                       # Number of instructions handled by decode
+system.cpu.fetch.rateDist::total            885484431                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.224249                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.234328                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                222585266                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             259638923                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 295357907                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              46951879                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               60950456                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts             2071410922                       # Number of instructions handled by decode
 system.cpu.decode.SquashedInsts                     1                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles               60921076                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                256051169                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles               115707666                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          18212                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 306637897                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles             146639101                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             2035099231                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                 19841                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents               24966361                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents             106369922                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands          2138037437                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            5150524594                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       3273371991                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups             41733                       # Number of floating rename lookups
+system.cpu.rename.SquashCycles               60950456                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                256114538                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles               114960463                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          17780                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 306643544                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles             146797650                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             2035254884                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                 19108                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               24985336                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents             106570240                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands          2138126742                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            5150804980                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       3273565222                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups             40421                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps            1614040854                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                523996583                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               1255                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts           1189                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 346554163                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            495859665                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           194411587                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads         195293101                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         54696349                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 1975355646                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded               13955                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1772015968                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            483793                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       441457587                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    735091170                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved          13403                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     885975121                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.000074                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.882925                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                524085888                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               1238                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           1169                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 346813798                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            495843290                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           194454992                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads         195400842                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         54863800                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 1975546158                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded               13200                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1772179882                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            484148                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       441719386                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    735183548                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved          12648                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     885484431                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.001368                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.882860                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           269258289     30.39%     30.39% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           151881714     17.14%     47.53% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           137407528     15.51%     63.04% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           131753954     14.87%     77.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            91677002     10.35%     88.26% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            55986071      6.32%     94.58% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            34414851      3.88%     98.47% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7            11835829      1.34%     99.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             1759883      0.20%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           268514596     30.32%     30.32% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           152316057     17.20%     47.53% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           137257157     15.50%     63.03% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           131678995     14.87%     77.90% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            91673992     10.35%     88.25% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            56016548      6.33%     94.58% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            34412328      3.89%     98.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7            11858214      1.34%     99.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             1756544      0.20%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       885975121                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       885484431                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 4932504     32.46%     32.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     32.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     32.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     32.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     32.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     32.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     32.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     32.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     32.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     32.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     32.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     32.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     32.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     32.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     32.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     32.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     32.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     32.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     32.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     32.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     32.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     32.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     32.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     32.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     32.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     32.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     32.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     32.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     32.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                7653540     50.37%     82.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               2609071     17.17%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 4914226     32.32%     32.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     32.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     32.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     32.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     32.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     32.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     32.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     32.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     32.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     32.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     32.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     32.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     32.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     32.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     32.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     32.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     32.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     32.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     32.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     32.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     32.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     32.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     32.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     32.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     32.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     32.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     32.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     32.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     32.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                7684512     50.55%     82.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               2604414     17.13%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass           2623104      0.15%      0.15% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1165669250     65.78%     65.93% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               353281      0.02%     65.95% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv               3880805      0.22%     66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                  50      0.00%     66.17% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass           2627261      0.15%      0.15% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1165804408     65.78%     65.93% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               352994      0.02%     65.95% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv               3880826      0.22%     66.17% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                  67      0.00%     66.17% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.17% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     66.17% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     66.17% # Type of FU issued
@@ -475,84 +451,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.17% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.17% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.17% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            429265174     24.22%     90.39% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           170224304      9.61%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            429279214     24.22%     90.39% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           170235112      9.61%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1772015968                       # Type of FU issued
-system.cpu.iq.rate                           1.929463                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    15195115                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.008575                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         4445670799                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        2417030484                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1744778187                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads               15166                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes              51932                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses         3516                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             1784580890                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                    7089                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads        172585161                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             1772179882                       # Type of FU issued
+system.cpu.iq.rate                           1.932895                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    15203152                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.008579                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         4445517936                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        2417485915                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1744947174                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads               13559                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes              50440                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses         3261                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             1784749273                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                    6500                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads        172700004                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    111758592                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses       386790                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       327293                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     45251401                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads    111742246                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       386565                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       329489                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     45294806                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        14735                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked           596                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        14850                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked           595                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               60921076                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                68026001                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               7165661                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          1975369601                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            781836                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             495860749                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            194411587                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               3446                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                4462926                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 83952                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         327293                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        5902213                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      4423139                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             10325352                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            1752891418                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             424133385                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          19124550                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles               60950456                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                66921774                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               7152270                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          1975559358                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            792714                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             495844403                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            194454992                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               3102                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                4466928                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 83631                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         329489                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        5907148                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      4425214                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             10332362                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1753055321                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             424140880                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          19124561                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                    590919865                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                167459905                       # Number of branches executed
-system.cpu.iew.exec_stores                  166786480                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.908639                       # Inst execution rate
-system.cpu.iew.wb_sent                     1749637243                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    1744781703                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1324895228                       # num instructions producing a value
-system.cpu.iew.wb_consumers                1945542332                       # num instructions consuming a value
+system.cpu.iew.exec_refs                    590933103                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                167483673                       # Number of branches executed
+system.cpu.iew.exec_stores                  166792223                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.912036                       # Inst execution rate
+system.cpu.iew.wb_sent                     1749807321                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1744950435                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1324909698                       # num instructions producing a value
+system.cpu.iew.wb_consumers                1945755632                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.899809                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.680990                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.903196                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.680923                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts       446410033                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       446599399                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             552                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           9933076                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    825054045                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.853198                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.435700                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           9930890                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    824533975                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.854367                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.435928                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    333030107     40.36%     40.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    193187610     23.42%     63.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     63292581      7.67%     71.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     92556987     11.22%     82.67% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     24936073      3.02%     85.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     27503514      3.33%     89.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      9360719      1.13%     90.16% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     11372840      1.38%     91.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     69813614      8.46%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    332362619     40.31%     40.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    193345604     23.45%     63.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     63386723      7.69%     71.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     92493757     11.22%     82.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     24926721      3.02%     85.69% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     27481357      3.33%     89.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      9323499      1.13%     90.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     11375843      1.38%     91.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     69837852      8.47%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    825054045                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    824533975                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            826877109                       # Number of instructions committed
 system.cpu.commit.committedOps             1528988701                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -563,245 +539,245 @@ system.cpu.commit.branches                  149758583                       # Nu
 system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                1526605509                       # Number of committed integer instructions.
 system.cpu.commit.function_calls             17673145                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events              69813614                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events              69837852                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   2730639165                       # The number of ROB reads
-system.cpu.rob.rob_writes                  4011880242                       # The number of ROB writes
-system.cpu.timesIdled                         3355901                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        32423466                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                   2730284223                       # The number of ROB reads
+system.cpu.rob.rob_writes                  4012285085                       # The number of ROB writes
+system.cpu.timesIdled                         3361589                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        31368436                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   826877109                       # Number of Instructions Simulated
 system.cpu.committedOps                    1528988701                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total             826877109                       # Number of Instructions Simulated
-system.cpu.cpi                               1.110683                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.110683                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.900347                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.900347                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               2716194969                       # number of integer regfile reads
-system.cpu.int_regfile_writes              1420370160                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                      3538                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                       76                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 597194910                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                405402169                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               964642327                       # number of misc regfile reads
+system.cpu.cpi                               1.108814                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.108814                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.901865                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.901865                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               2716343034                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1420512883                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                      3304                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                       92                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 597249207                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                405429285                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               964722506                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput               698022201                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq        1904986                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       1904985                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      2330749                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq       135709                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp       135709                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       771688                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       771688                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       149463                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7670245                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           7819708                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       436992                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    311346432                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      311783424                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus         311783424                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus      8691584                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy     4905579957                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.throughput               699635153                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq        1908088                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       1908087                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      2330726                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq       138856                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp       138856                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       771730                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       771730                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       152619                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7676496                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           7829115                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       437120                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    311344320                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      311781440                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         311781440                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus      8893312                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy     4908984370                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy     214416742                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy     219136241                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    3952860716                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    3952027365                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.9                       # Layer utilization (%)
-system.cpu.icache.tags.replacements              5299                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1035.961197                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           161868793                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              6888                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          23500.115128                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements              5320                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1037.745275                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           161872406                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              6896                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          23473.376740                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1035.961197                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.505840                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.505840                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1589                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst  1037.745275                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.506712                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.506712                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1576                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           58                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1            5                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           43                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          245                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1238                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.775879                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         324173234                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        324173234                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    161870665                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       161870665                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     161870665                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        161870665                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    161870665                       # number of overall hits
-system.cpu.icache.overall_hits::total       161870665                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       144635                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        144635                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       144635                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         144635                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       144635                       # number of overall misses
-system.cpu.icache.overall_misses::total        144635                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    939845985                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    939845985                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    939845985                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    939845985                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    939845985                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    939845985                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    162015300                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    162015300                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    162015300                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    162015300                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    162015300                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    162015300                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000893                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000893                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000893                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000893                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000893                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000893                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  6498.053618                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total  6498.053618                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst  6498.053618                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total  6498.053618                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst  6498.053618                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total  6498.053618                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          251                       # number of cycles access was blocked
+system.cpu.icache.tags.age_task_id_blocks_1024::1            6                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           46                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          238                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1228                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.769531                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         324190030                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        324190030                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    161874355                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       161874355                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     161874355                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        161874355                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    161874355                       # number of overall hits
+system.cpu.icache.overall_hits::total       161874355                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       147766                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        147766                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       147766                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         147766                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       147766                       # number of overall misses
+system.cpu.icache.overall_misses::total        147766                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    941588486                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    941588486                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    941588486                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    941588486                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    941588486                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    941588486                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    162022121                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    162022121                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    162022121                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    162022121                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    162022121                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    162022121                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000912                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000912                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000912                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000912                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000912                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000912                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  6372.159265                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total  6372.159265                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst  6372.159265                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total  6372.159265                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst  6372.159265                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total  6372.159265                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          953                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 6                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 8                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    41.833333                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs   119.125000                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2000                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         2000                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         2000                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         2000                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         2000                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         2000                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       142635                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       142635                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       142635                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       142635                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       142635                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       142635                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    558603007                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    558603007                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    558603007                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    558603007                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    558603007                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    558603007                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000880                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000880                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000880                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000880                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000880                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000880                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  3916.310912                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  3916.310912                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  3916.310912                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total  3916.310912                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  3916.310912                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total  3916.310912                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1977                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         1977                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         1977                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         1977                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         1977                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         1977                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       145789                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       145789                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       145789                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       145789                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       145789                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       145789                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    560897259                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    560897259                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    560897259                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    560897259                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    560897259                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    560897259                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000900                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000900                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000900                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000900                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000900                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000900                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  3847.322219                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  3847.322219                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  3847.322219                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total  3847.322219                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  3847.322219                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total  3847.322219                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           352851                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        29668.075307                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            3697142                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           385214                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             9.597631                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle     199249645000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 21122.585790                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   223.642071                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  8321.847447                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.644610                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.006825                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.253963                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.905398                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        32363                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           77                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          239                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3        11704                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        20343                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.987640                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         41217237                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        41217237                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst         3670                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data      1586809                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1590479                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      2330749                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      2330749                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data         1446                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total         1446                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       564831                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       564831                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         3670                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      2151640                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2155310                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         3670                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      2151640                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2155310                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         3159                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data       175542                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total       178701                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data       134263                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total       134263                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       206857                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       206857                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         3159                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       382399                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        385558                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         3159                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       382399                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       385558                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    240297250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data  13188147460                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total  13428444710                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data      6534219                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total      6534219                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  15150269977                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  15150269977                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    240297250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  28338417437                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  28578714687                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    240297250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  28338417437                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  28578714687                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst         6829                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      1762351                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      1769180                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      2330749                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      2330749                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data       135709                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total       135709                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       771688                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       771688                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         6829                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      2534039                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2540868                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         6829                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      2534039                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2540868                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.462586                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.099607                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.101008                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.989345                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.989345                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.268058                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.268058                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.462586                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.150905                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.151743                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.462586                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.150905                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.151743                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76067.505540                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75128.159985                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 75144.765334                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data    48.667310                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total    48.667310                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73240.305994                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73240.305994                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76067.505540                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74106.933954                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 74122.997544                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76067.505540                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74106.933954                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 74122.997544                       # average overall miss latency
+system.cpu.l2cache.tags.replacements           352905                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        29664.192610                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            3697555                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           385281                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             9.597034                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle     198720708500                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 21111.841089                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   223.120798                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  8329.230723                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.644282                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.006809                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.254188                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.905279                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        32376                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           79                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          246                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        11697                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        20354                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.988037                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         41242263                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        41242263                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst         3684                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data      1586656                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        1590340                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      2330726                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      2330726                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data         1427                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total         1427                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       564910                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       564910                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst         3684                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      2151566                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2155250                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         3684                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      2151566                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2155250                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         3147                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data       175643                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total       178790                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data       137429                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total       137429                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       206820                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       206820                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         3147                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       382463                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        385610                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         3147                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       382463                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       385610                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    236007500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data  12735446955                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total  12971454455                       # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data      6722711                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total      6722711                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  14644727978                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  14644727978                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    236007500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  27380174933                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  27616182433                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    236007500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  27380174933                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  27616182433                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst         6831                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      1762299                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      1769130                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      2330726                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      2330726                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data       138856                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total       138856                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       771730                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       771730                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         6831                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      2534029                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2540860                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         6831                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      2534029                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2540860                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.460694                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.099667                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.101061                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.989723                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.989723                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.267995                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.267995                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.460694                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.150931                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.151764                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.460694                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.150931                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.151764                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74994.439148                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72507.569075                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 72551.342105                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data    48.917703                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total    48.917703                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70809.051243                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70809.051243                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74994.439148                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71589.081644                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 71616.873092                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74994.439148                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71589.081644                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 71616.873092                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -810,182 +786,176 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       293551                       # number of writebacks
-system.cpu.l2cache.writebacks::total           293551                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            1                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total            1                       # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total            1                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total            1                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3158                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       175542                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total       178700                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data       134263                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total       134263                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       206857                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       206857                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3158                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       382399                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       385557                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3158                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       382399                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       385557                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    200687250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  10949056460                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  11149743710                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   1346042939                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   1346042939                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  12524505023                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  12524505023                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    200687250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  23473561483                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  23674248733                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    200687250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  23473561483                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  23674248733                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.462440                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.099607                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.101007                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.989345                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.989345                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.268058                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.268058                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.462440                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.150905                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.151742                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.462440                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.150905                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.151742                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63548.844205                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62372.859259                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62393.641354                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10025.419803                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10025.419803                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60546.682119                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60546.682119                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63548.844205                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61384.997040                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61402.720565                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63548.844205                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61384.997040                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61402.720565                       # average overall mshr miss latency
+system.cpu.l2cache.writebacks::writebacks       293595                       # number of writebacks
+system.cpu.l2cache.writebacks::total           293595                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3147                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       175643                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total       178790                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data       137429                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total       137429                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       206820                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       206820                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3147                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       382463                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       385610                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3147                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       382463                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       385610                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    196679500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  10498248955                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  10694928455                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   1378003511                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   1378003511                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  12022304022                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  12022304022                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    196679500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  22520552977                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  22717232477                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    196679500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  22520552977                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  22717232477                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.460694                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.099667                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.101061                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.989723                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.989723                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.267995                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.267995                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.460694                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.150931                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.151764                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.460694                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.150931                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.151764                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62497.457896                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59770.380573                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59818.381649                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10027.021306                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10027.021306                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58129.310618                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58129.310618                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62497.457896                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58882.958553                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58912.456827                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62497.457896                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58882.958553                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58912.456827                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements           2529943                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4088.243531                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           396026298                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           2534039                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            156.282637                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        1794365000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4088.243531                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.998106                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.998106                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements           2529933                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4088.224261                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           395924693                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           2534029                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            156.243158                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        1796857250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4088.224261                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.998102                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.998102                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           27                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           21                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          730                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3         3318                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           26                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           16                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          753                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         3301                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         801176347                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        801176347                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    247278807                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       247278807                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    148236045                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      148236045                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data     395514852                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        395514852                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    395514852                       # number of overall hits
-system.cpu.dcache.overall_hits::total       395514852                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      2882145                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       2882145                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       924157                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       924157                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      3806302                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3806302                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      3806302                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3806302                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  58050756258                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  58050756258                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  26834846719                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  26834846719                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  84885602977                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  84885602977                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  84885602977                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  84885602977                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    250160952                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    250160952                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses         800965525                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        800965525                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    247184750                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       247184750                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    148232864                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      148232864                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     395417614                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        395417614                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    395417614                       # number of overall hits
+system.cpu.dcache.overall_hits::total       395417614                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      2870796                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       2870796                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       927338                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       927338                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      3798134                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3798134                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      3798134                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3798134                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  57044971459                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  57044971459                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  26405527365                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  26405527365                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  83450498824                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  83450498824                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  83450498824                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  83450498824                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    250055546                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    250055546                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    149160202                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    149160202                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    399321154                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    399321154                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    399321154                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    399321154                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.011521                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.011521                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.006196                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.006196                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.009532                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.009532                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.009532                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.009532                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20141.511360                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 20141.511360                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29037.108109                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 29037.108109                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 22301.331575                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 22301.331575                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 22301.331575                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 22301.331575                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs         7238                       # number of cycles access was blocked
+system.cpu.dcache.demand_accesses::cpu.data    399215748                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    399215748                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    399215748                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    399215748                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.011481                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.011481                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.006217                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.006217                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.009514                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.009514                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.009514                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.009514                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19870.785475                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 19870.785475                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28474.544734                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 28474.544734                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 21971.446722                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 21971.446722                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 21971.446722                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 21971.446722                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs         6569                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs               664                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs               666                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    10.900602                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.863363                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      2330749                       # number of writebacks
-system.cpu.dcache.writebacks::total           2330749                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      1119535                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      1119535                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        17020                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        17020                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1136555                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1136555                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1136555                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1136555                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1762610                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1762610                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       907137                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       907137                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      2669747                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      2669747                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      2669747                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      2669747                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  30854243503                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  30854243503                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  24711423781                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  24711423781                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  55565667284                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  55565667284                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  55565667284                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  55565667284                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.007046                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.007046                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006082                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006082                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006686                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.006686                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006686                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.006686                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17504.861259                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17504.861259                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27241.115489                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27241.115489                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20813.083518                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20813.083518                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20813.083518                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 20813.083518                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks      2330726                       # number of writebacks
+system.cpu.dcache.writebacks::total           2330726                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      1108238                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      1108238                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        17013                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        17013                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      1125251                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1125251                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1125251                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1125251                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1762558                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1762558                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       910325                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       910325                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      2672883                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      2672883                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      2672883                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      2672883                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  30399879250                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  30399879250                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  24280652885                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  24280652885                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  54680532135                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  54680532135                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  54680532135                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  54680532135                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.007049                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.007049                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006103                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006103                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006695                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.006695                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006695                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.006695                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17247.590859                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17247.590859                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26672.510241                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26672.510241                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20457.510536                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 20457.510536                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20457.510536                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 20457.510536                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index eb5995295a698577f2fb6206cc5f1167a7951aa8..4b6099b5244a5b5d4173afa2f7b90295a2332082 100644 (file)
@@ -4,11 +4,11 @@ sim_seconds                                  0.139926                       # Nu
 sim_ticks                                139926186500                       # Number of ticks simulated
 final_tick                               139926186500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 138827                       # Simulator instruction rate (inst/s)
-host_op_rate                                   138827                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               48726388                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 236592                       # Number of bytes of host memory used
-host_seconds                                  2871.67                       # Real time elapsed on the host
+host_inst_rate                                 124689                       # Simulator instruction rate (inst/s)
+host_op_rate                                   124689                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               43764124                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 271420                       # Number of bytes of host memory used
+host_seconds                                  3197.28                       # Real time elapsed on the host
 sim_insts                                   398664595                       # Number of instructions simulated
 sim_ops                                     398664595                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -90,11 +90,11 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      4635                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      1820                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       581                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       229                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        62                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      4589                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      1831                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       611                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       237                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        59                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -154,79 +154,60 @@ system.physmem.wrQLenPdf::28                        0                       # Wh
 system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         1198                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      387.899833                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     185.568922                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     772.018563                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64-65            419     34.97%     34.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-129          201     16.78%     51.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192-193          128     10.68%     62.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-257           91      7.60%     70.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320-321           61      5.09%     75.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-385           40      3.34%     78.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448-449           30      2.50%     80.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-513           22      1.84%     82.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576-577           25      2.09%     84.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-641           18      1.50%     86.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704-705           20      1.67%     88.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-769            8      0.67%     88.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832-833           17      1.42%     90.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-897           10      0.83%     90.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960-961            8      0.67%     91.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1025            6      0.50%     92.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088-1089           10      0.83%     92.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152-1153            7      0.58%     93.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216-1217            7      0.58%     94.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280-1281            1      0.08%     94.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344-1345            4      0.33%     94.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408-1409            4      0.33%     94.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472-1473            2      0.17%     95.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536-1537            5      0.42%     95.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600-1601            5      0.42%     95.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664-1665            4      0.33%     96.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1728-1729            1      0.08%     96.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1792-1793            2      0.17%     96.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856-1857            1      0.08%     96.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984-1985            2      0.17%     96.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2048-2049            1      0.08%     96.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112-2113            2      0.17%     96.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2176-2177            1      0.08%     97.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2240-2241            1      0.08%     97.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2304-2305            2      0.17%     97.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2368-2369            1      0.08%     97.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2432-2433            1      0.08%     97.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2496-2497            4      0.33%     97.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2560-2561            2      0.17%     98.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2624-2625            1      0.08%     98.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2688-2689            2      0.17%     98.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2752-2753            1      0.08%     98.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2816-2817            1      0.08%     98.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2880-2881            1      0.08%     98.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3008-3009            2      0.17%     98.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3136-3137            1      0.08%     98.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3200-3201            1      0.08%     98.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3456-3457            1      0.08%     98.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3584-3585            1      0.08%     99.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4032-4033            1      0.08%     99.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4224-4225            1      0.08%     99.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4544-4545            1      0.08%     99.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5056-5057            1      0.08%     99.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5376-5377            1      0.08%     99.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5440-5441            1      0.08%     99.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6528-6529            1      0.08%     99.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7104-7105            1      0.08%     99.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7616-7617            1      0.08%     99.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8128-8129            1      0.08%     99.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8192-8193            2      0.17%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           1198                       # Bytes accessed per row activation
-system.physmem.totQLat                       59880500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 197624250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples          558                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      480.917563                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     280.270360                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     415.877438                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            147     26.34%     26.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          107     19.18%     45.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           50      8.96%     54.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           28      5.02%     59.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           15      2.69%     62.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           15      2.69%     64.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            7      1.25%     66.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            5      0.90%     67.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          184     32.97%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total            558                       # Bytes accessed per row activation
+system.physmem.totQLat                       59527000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 199924500                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                     36640000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                   101103750                       # Total ticks spent accessing banks
-system.physmem.avgQLat                        8171.47                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    13796.91                       # Average bank access latency per DRAM burst
+system.physmem.totBankLat                   103757500                       # Total ticks spent accessing banks
+system.physmem.avgQLat                        8123.23                       # Average queueing delay per DRAM burst
+system.physmem.avgBankLat                    14159.05                       # Average bank access latency per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  26968.37                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  27282.27                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           3.35                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        3.35                       # Average system read bandwidth in MiByte/s
@@ -235,15 +216,15 @@ system.physmem.peakBW                        12800.00                       # Th
 system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         0.00                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       6130                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       5962                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   83.65                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   81.36                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
 system.physmem.avgGap                     19094720.66                       # Average gap between requests
-system.physmem.pageHitRate                      83.65                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               0.42                       # Percentage of time for which DRAM has all the banks in precharge state
+system.physmem.pageHitRate                      81.36                       # Row buffer hit rate, read and write combined
+system.physmem.prechargeAllPercent               0.43                       # Percentage of time for which DRAM has all the banks in precharge state
 system.membus.throughput                      3351710                       # Throughput (bytes/s)
 system.membus.trans_dist::ReadReq                4183                       # Transaction distribution
 system.membus.trans_dist::ReadResp               4183                       # Transaction distribution
@@ -257,7 +238,7 @@ system.membus.data_through_bus                 468992                       # To
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
 system.membus.reqLayer0.occupancy             8743500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           68145750                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           68133000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                53489673                       # Number of BP lookups
@@ -273,22 +254,22 @@ system.cpu.dtb.fetch_hits                           0                       # IT
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     94754637                       # DTB read hits
+system.cpu.dtb.read_hits                     94754639                       # DTB read hits
 system.cpu.dtb.read_misses                         21                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                 94754658                       # DTB read accesses
-system.cpu.dtb.write_hits                    73521124                       # DTB write hits
+system.cpu.dtb.read_accesses                 94754660                       # DTB read accesses
+system.cpu.dtb.write_hits                    73521131                       # DTB write hits
 system.cpu.dtb.write_misses                        35                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                73521159                       # DTB write accesses
-system.cpu.dtb.data_hits                    168275761                       # DTB hits
+system.cpu.dtb.write_accesses                73521166                       # DTB write accesses
+system.cpu.dtb.data_hits                    168275770                       # DTB hits
 system.cpu.dtb.data_misses                         56                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                168275817                       # DTB accesses
-system.cpu.itb.fetch_hits                    48611324                       # ITB hits
+system.cpu.dtb.data_accesses                168275826                       # DTB accesses
+system.cpu.itb.fetch_hits                    48611322                       # ITB hits
 system.cpu.itb.fetch_misses                     44520                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                48655844                       # ITB accesses
+system.cpu.itb.fetch_accesses                48655842                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -307,13 +288,13 @@ system.cpu.numWorkItemsStarted                      0                       # nu
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.branch_predictor.predictedTaken     29230505                       # Number of Branches Predicted As Taken (True).
 system.cpu.branch_predictor.predictedNotTaken     24259168                       # Number of Branches Predicted As Not Taken (False).
-system.cpu.regfile_manager.intRegFileReads    280386579                       # Number of Reads from Int. Register File
+system.cpu.regfile_manager.intRegFileReads    280386572                       # Number of Reads from Int. Register File
 system.cpu.regfile_manager.intRegFileWrites    159335859                       # Number of Writes to Int. Register File
-system.cpu.regfile_manager.intRegFileAccesses    439722438                       # Total Accesses (Read+Write) to the Int. Register File
-system.cpu.regfile_manager.floatRegFileReads    119631950                       # Number of Reads from FP Register File
+system.cpu.regfile_manager.intRegFileAccesses    439722431                       # Total Accesses (Read+Write) to the Int. Register File
+system.cpu.regfile_manager.floatRegFileReads    119631955                       # Number of Reads from FP Register File
 system.cpu.regfile_manager.floatRegFileWrites    100196481                       # Number of Writes to FP Register File
-system.cpu.regfile_manager.floatRegFileAccesses    219828431                       # Total Accesses (Read+Write) to the FP Register File
-system.cpu.regfile_manager.regForwards      100484574                       # Number of Registers Read Through Forwarding Logic
+system.cpu.regfile_manager.floatRegFileAccesses    219828436                       # Total Accesses (Read+Write) to the FP Register File
+system.cpu.regfile_manager.regForwards      100484576                       # Number of Registers Read Through Forwarding Logic
 system.cpu.agen_unit.agens                  168485322                       # Number of Address Generations
 system.cpu.execution_unit.predictedTakenIncorrect     14315634                       # Number of Branches Incorrectly Predicted As Taken.
 system.cpu.execution_unit.predictedNotTakenIncorrect       833366                       # Number of Branches Incorrectly Predicted As Not Taken).
@@ -324,12 +305,12 @@ system.cpu.execution_unit.executions        205475782                       # Nu
 system.cpu.mult_div_unit.multiplies           2124323                       # Number of Multipy Operations Executed
 system.cpu.mult_div_unit.divides                    0                       # Number of Divide Operations Executed
 system.cpu.contextSwitches                          1                       # Number of context switches
-system.cpu.threadCycles                     279400617                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles                     279400810                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
 system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled                            7206                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        13545708                       # Number of cycles cpu's stages were not processed
-system.cpu.runCycles                        266306666                       # Number of cycles cpu stages are processed.
-system.cpu.activity                         95.159695                       # Percentage of cycles cpu is active
+system.cpu.timesIdled                            7266                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        13545705                       # Number of cycles cpu's stages were not processed
+system.cpu.runCycles                        266306669                       # Number of cycles cpu stages are processed.
+system.cpu.activity                         95.159696                       # Percentage of cycles cpu is active
 system.cpu.comLoads                          94754489                       # Number of Load instructions committed
 system.cpu.comStores                         73520729                       # Number of Store instructions committed
 system.cpu.comBranches                       44587532                       # Number of Branches instructions committed
@@ -350,27 +331,27 @@ system.cpu.ipc_total                         1.424553                       # IP
 system.cpu.stage0.idleCycles                 78104700                       # Number of cycles 0 instructions are processed.
 system.cpu.stage0.runCycles                 201747674                       # Number of cycles 1+ instructions are processed.
 system.cpu.stage0.utilization               72.090750                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles                107200641                       # Number of cycles 0 instructions are processed.
-system.cpu.stage1.runCycles                 172651733                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization               61.693860                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles                107200637                       # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles                 172651737                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization               61.693862                       # Percentage of cycles stage was utilized (processing insts).
 system.cpu.stage2.idleCycles                102637143                       # Number of cycles 0 instructions are processed.
 system.cpu.stage2.runCycles                 177215231                       # Number of cycles 1+ instructions are processed.
 system.cpu.stage2.utilization               63.324541                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage3.idleCycles                181107759                       # Number of cycles 0 instructions are processed.
-system.cpu.stage3.runCycles                  98744615                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage3.utilization               35.284537                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles                 90384394                       # Number of cycles 0 instructions are processed.
-system.cpu.stage4.runCycles                 189467980                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization               67.702831                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles                181107747                       # Number of cycles 0 instructions are processed.
+system.cpu.stage3.runCycles                  98744627                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage3.utilization               35.284541                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles                 90384400                       # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles                 189467974                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization               67.702829                       # Percentage of cycles stage was utilized (processing insts).
 system.cpu.icache.tags.replacements              1975                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1830.939408                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            48606790                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse          1830.934233                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            48606787                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs              3903                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          12453.699718                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs          12453.698950                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1830.939408                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.894013                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.894013                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1830.934233                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.894011                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.894011                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1928                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0          104                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          135                       # Occupied blocks per task id
@@ -378,44 +359,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2          322
 system.cpu.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4         1366                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.941406                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          97226551                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         97226551                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     48606790                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        48606790                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      48606790                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         48606790                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     48606790                       # number of overall hits
-system.cpu.icache.overall_hits::total        48606790                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         4534                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          4534                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         4534                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           4534                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         4534                       # number of overall misses
-system.cpu.icache.overall_misses::total          4534                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    280061250                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    280061250                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    280061250                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    280061250                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    280061250                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    280061250                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     48611324                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     48611324                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     48611324                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     48611324                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     48611324                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     48611324                       # number of overall (read+write) accesses
+system.cpu.icache.tags.tag_accesses          97226547                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         97226547                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     48606787                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        48606787                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      48606787                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         48606787                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     48606787                       # number of overall hits
+system.cpu.icache.overall_hits::total        48606787                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         4535                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          4535                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         4535                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           4535                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         4535                       # number of overall misses
+system.cpu.icache.overall_misses::total          4535                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    279787250                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    279787250                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    279787250                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    279787250                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    279787250                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    279787250                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     48611322                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     48611322                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     48611322                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     48611322                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     48611322                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     48611322                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000093                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000093                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000093                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000093                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000093                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000093                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61769.133216                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 61769.133216                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 61769.133216                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 61769.133216                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 61769.133216                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 61769.133216                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61695.093716                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 61695.093716                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 61695.093716                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 61695.093716                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 61695.093716                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 61695.093716                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs          330                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 3                       # number of cycles access was blocked
@@ -424,36 +405,36 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          110
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          631                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          631                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          631                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          631                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          631                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          631                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          632                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          632                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          632                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          632                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          632                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          632                       # number of overall MSHR hits
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst         3903                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total         3903                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst         3903                       # number of demand (read+write) MSHR misses
 system.cpu.icache.demand_mshr_misses::total         3903                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst         3903                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total         3903                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    244179750                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    244179750                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    244179750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    244179750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    244179750                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    244179750                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    243875500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    243875500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    243875500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    243875500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    243875500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    243875500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000080                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000080                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000080                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000080                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000080                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000080                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62562.067640                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62562.067640                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62562.067640                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 62562.067640                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62562.067640                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 62562.067640                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62484.114783                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62484.114783                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62484.114783                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 62484.114783                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62484.114783                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 62484.114783                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.throughput                 3981070                       # Throughput (bytes/s)
 system.cpu.toL2Bus.trans_dist::ReadReq           4850                       # Transaction distribution
@@ -471,21 +452,21 @@ system.cpu.toL2Bus.data_through_bus            557056                       # To
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
 system.cpu.toL2Bus.reqLayer0.occupancy        5001000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       6459750                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       6445500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy       6671999                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy       6649999                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         3906.845611                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse         3906.832917                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                753                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs             4717                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.159635                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks   370.534640                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2908.739390                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   627.571581                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks   370.533355                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2908.730052                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   627.569510                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.011308                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.088768                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.088767                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.019152                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.119227                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024         4717                       # Occupied blocks per task id
@@ -520,17 +501,17 @@ system.cpu.l2cache.demand_misses::total          7328                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst         3359                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data         3969                       # number of overall misses
 system.cpu.l2cache.overall_misses::total         7328                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    234790750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     62080250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    296871000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    227075250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    227075250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    234790750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    289155500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    523946250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    234790750                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    289155500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    523946250                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    234486500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     61133000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    295619500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    230289500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    230289500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    234486500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    291422500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    525909000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    234486500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    291422500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    525909000                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst         3903                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data          947                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total         4850                       # number of ReadReq accesses(hits+misses)
@@ -555,17 +536,17 @@ system.cpu.l2cache.demand_miss_rate::total     0.909745                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.860620                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.955925                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.909745                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69899.002679                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75340.109223                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 70970.834329                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72201.987281                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72201.987281                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69899.002679                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72853.489544                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 71499.215338                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69899.002679                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72853.489544                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 71499.215338                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69808.425127                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74190.533981                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 70671.647143                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73224.006359                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73224.006359                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69808.425127                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73424.666163                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 71767.057860                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69808.425127                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73424.666163                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 71767.057860                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -585,17 +566,17 @@ system.cpu.l2cache.demand_mshr_misses::total         7328
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         3359                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data         3969                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total         7328                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    192686250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     51812250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    244498500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    188269250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    188269250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    192686250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    240081500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    432767750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    192686250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    240081500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    432767750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    192420000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     50867000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    243287000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    191492500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    191492500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    192420000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    242359500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    434779500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    192420000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    242359500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    434779500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.860620                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.870116                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.862474                       # mshr miss rate for ReadReq accesses
@@ -607,27 +588,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.909745
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.860620                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.955925                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.909745                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57364.170884                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62878.944175                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58450.513985                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59863.036566                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59863.036566                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57364.170884                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60489.166037                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59056.734443                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57364.170884                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60489.166037                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59056.734443                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57284.906222                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61731.796117                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58160.889314                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60887.917329                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60887.917329                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57284.906222                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61063.114135                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59331.263646                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57284.906222                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61063.114135                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59331.263646                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.dcache.tags.replacements               764                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          3284.890275                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           168254255                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          3284.879976                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           168254239                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs              4152                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          40523.664499                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          40523.660645                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  3284.890275                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.801975                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.801975                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data  3284.879976                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.801973                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.801973                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         3388                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           43                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           17                       # Occupied blocks per task id
@@ -639,28 +620,28 @@ system.cpu.dcache.tags.tag_accesses         336554588                       # Nu
 system.cpu.dcache.tags.data_accesses        336554588                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data     94753181                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        94753181                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     73501074                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       73501074                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data     168254255                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        168254255                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    168254255                       # number of overall hits
-system.cpu.dcache.overall_hits::total       168254255                       # number of overall hits
+system.cpu.dcache.WriteReq_hits::cpu.data     73501058                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       73501058                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     168254239                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        168254239                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    168254239                       # number of overall hits
+system.cpu.dcache.overall_hits::total       168254239                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data         1308                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total          1308                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data        19655                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total        19655                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data        20963                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total          20963                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data        20963                       # number of overall misses
-system.cpu.dcache.overall_misses::total         20963                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     88453749                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     88453749                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   1129220750                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   1129220750                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data   1217674499                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total   1217674499                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data   1217674499                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total   1217674499                       # number of overall miss cycles
+system.cpu.dcache.WriteReq_misses::cpu.data        19671                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        19671                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data        20979                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total          20979                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data        20979                       # number of overall misses
+system.cpu.dcache.overall_misses::total         20979                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     87087749                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     87087749                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   1166784250                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   1166784250                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data   1253871999                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total   1253871999                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data   1253871999                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total   1253871999                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data     94754489                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total     94754489                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     73520729                       # number of WriteReq accesses(hits+misses)
@@ -671,25 +652,25 @@ system.cpu.dcache.overall_accesses::cpu.data    168275218
 system.cpu.dcache.overall_accesses::total    168275218                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000014                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.000014                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000267                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.000267                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000268                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.000268                       # miss rate for WriteReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.000125                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     0.000125                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.000125                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.000125                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67625.190367                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 67625.190367                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57452.085983                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 57452.085983                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 58086.843438                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 58086.843438                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 58086.843438                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 58086.843438                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs        33688                       # number of cycles access was blocked
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66580.847859                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 66580.847859                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59314.943318                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 59314.943318                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 59767.958387                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 59767.958387                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 59767.958387                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 59767.958387                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs        33117                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs               584                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs               591                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    57.684932                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    56.035533                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
@@ -697,12 +678,12 @@ system.cpu.dcache.writebacks::writebacks          649                       # nu
 system.cpu.dcache.writebacks::total               649                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data          358                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total          358                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        16453                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        16453                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data        16811                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total        16811                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data        16811                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total        16811                       # number of overall MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        16469                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        16469                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data        16827                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total        16827                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data        16827                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total        16827                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data          950                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total          950                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data         3202                       # number of WriteReq MSHR misses
@@ -711,14 +692,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data         4152
 system.cpu.dcache.demand_mshr_misses::total         4152                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data         4152                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total         4152                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     64535001                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     64535001                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    230815000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    230815000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    295350001                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    295350001                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    295350001                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    295350001                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     63587751                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     63587751                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    234030250                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    234030250                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    297618001                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    297618001                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    297618001                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    297618001                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000010                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000010                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000044                       # mshr miss rate for WriteReq accesses
@@ -727,14 +708,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000025
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000025                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000025                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000025                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67931.580000                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67931.580000                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72084.634603                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72084.634603                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71134.393304                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 71134.393304                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71134.393304                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 71134.393304                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66934.474737                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66934.474737                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73088.772642                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73088.772642                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71680.636079                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 71680.636079                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71680.636079                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 71680.636079                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 39e558e65cdd7a4fab6677cb07a515022ede6002..8d6cbc0065fe4299efca7f59ba9325ab017fc864 100644 (file)
@@ -1,61 +1,61 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.077516                       # Number of seconds simulated
-sim_ticks                                 77516381000                       # Number of ticks simulated
-final_tick                                77516381000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.077418                       # Number of seconds simulated
+sim_ticks                                 77417500000                       # Number of ticks simulated
+final_tick                                77417500000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 222910                       # Simulator instruction rate (inst/s)
-host_op_rate                                   222910                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               46007212                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 236600                       # Number of bytes of host memory used
-host_seconds                                  1684.87                       # Real time elapsed on the host
+host_inst_rate                                 187521                       # Simulator instruction rate (inst/s)
+host_op_rate                                   187521                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               38653802                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 273448                       # Number of bytes of host memory used
+host_seconds                                  2002.84                       # Real time elapsed on the host
 sim_insts                                   375574808                       # Number of instructions simulated
 sim_ops                                     375574808                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            221184                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data            255424                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               476608                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       221184                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          221184                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               3456                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               3991                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  7447                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              2853384                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3295097                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 6148481                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         2853384                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            2853384                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             2853384                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             3295097                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6148481                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                          7447                       # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst            220992                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data            255488                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               476480                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       220992                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          220992                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               3453                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               3992                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  7445                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              2854548                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3300132                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 6154681                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         2854548                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            2854548                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             2854548                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             3300132                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                6154681                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                          7445                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                        7447                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                        7445                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                   476608                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                   476480                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                    476608                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                    476480                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
 system.physmem.perBankRdBursts::0                 524                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                 653                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                 654                       # Per bank write bursts
 system.physmem.perBankRdBursts::2                 449                       # Per bank write bursts
 system.physmem.perBankRdBursts::3                 600                       # Per bank write bursts
 system.physmem.perBankRdBursts::4                 447                       # Per bank write bursts
 system.physmem.perBankRdBursts::5                 455                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                 515                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                 518                       # Per bank write bursts
 system.physmem.perBankRdBursts::7                 524                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                 439                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                 407                       # Per bank write bursts
-system.physmem.perBankRdBursts::10                340                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                 436                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                 405                       # Per bank write bursts
+system.physmem.perBankRdBursts::10                339                       # Per bank write bursts
 system.physmem.perBankRdBursts::11                306                       # Per bank write bursts
 system.physmem.perBankRdBursts::12                414                       # Per bank write bursts
-system.physmem.perBankRdBursts::13                542                       # Per bank write bursts
-system.physmem.perBankRdBursts::14                453                       # Per bank write bursts
+system.physmem.perBankRdBursts::13                541                       # Per bank write bursts
+system.physmem.perBankRdBursts::14                454                       # Per bank write bursts
 system.physmem.perBankRdBursts::15                379                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     77516291500                       # Total gap between requests
+system.physmem.totGap                     77417410500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                    7447                       # Read request sizes (log2)
+system.physmem.readPktSize::6                    7445                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -90,12 +90,12 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      4394                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      2044                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       706                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       246                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        55                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      4367                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      2023                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       735                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       258                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        59                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
@@ -154,72 +154,60 @@ system.physmem.wrQLenPdf::28                        0                       # Wh
 system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         1164                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      404.618557                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     188.969320                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     801.678722                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64-65            417     35.82%     35.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-129          184     15.81%     51.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192-193          111      9.54%     61.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-257           97      8.33%     69.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320-321           49      4.21%     73.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-385           38      3.26%     76.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448-449           28      2.41%     79.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-513           28      2.41%     81.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576-577           22      1.89%     83.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-641           22      1.89%     85.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704-705            9      0.77%     86.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-769           13      1.12%     87.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832-833           15      1.29%     88.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-897           15      1.29%     90.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960-961            6      0.52%     90.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1025            7      0.60%     91.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088-1089           16      1.37%     92.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152-1153            3      0.26%     92.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216-1217            5      0.43%     93.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280-1281            2      0.17%     93.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344-1345            3      0.26%     93.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408-1409           11      0.95%     94.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472-1473            4      0.34%     94.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536-1537            6      0.52%     95.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600-1601            3      0.26%     95.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664-1665            4      0.34%     96.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1728-1729            3      0.26%     96.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1920-1921            3      0.26%     96.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984-1985            3      0.26%     96.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2048-2049            3      0.26%     97.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112-2113            2      0.17%     97.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2176-2177            5      0.43%     97.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2304-2305            1      0.09%     97.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2368-2369            1      0.09%     97.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2496-2497            2      0.17%     98.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2752-2753            1      0.09%     98.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2816-2817            1      0.09%     98.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3072-3073            1      0.09%     98.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3136-3137            2      0.17%     98.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3264-3265            2      0.17%     98.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3328-3329            1      0.09%     98.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3392-3393            1      0.09%     98.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3904-3905            1      0.09%     98.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4032-4033            2      0.17%     99.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4288-4289            1      0.09%     99.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4544-4545            1      0.09%     99.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4800-4801            1      0.09%     99.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5056-5057            1      0.09%     99.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6592-6593            1      0.09%     99.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6912-6913            1      0.09%     99.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7232-7233            1      0.09%     99.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8000-8001            1      0.09%     99.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8192-8193            3      0.26%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           1164                       # Bytes accessed per row activation
-system.physmem.totQLat                       59914250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 199861750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     37235000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                   102712500                       # Total ticks spent accessing banks
-system.physmem.avgQLat                        8045.42                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    13792.47                       # Average bank access latency per DRAM burst
+system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples          629                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      457.157393                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     257.861215                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     416.549348                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            187     29.73%     29.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          122     19.40%     49.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           53      8.43%     57.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           24      3.82%     61.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           18      2.86%     64.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           15      2.38%     66.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            7      1.11%     67.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            3      0.48%     68.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          200     31.80%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total            629                       # Bytes accessed per row activation
+system.physmem.totQLat                       62316500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 205595250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     37225000                       # Total ticks spent in databus transfers
+system.physmem.totBankLat                   106053750                       # Total ticks spent accessing banks
+system.physmem.avgQLat                        8370.25                       # Average queueing delay per DRAM burst
+system.physmem.avgBankLat                    14244.96                       # Average bank access latency per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  26837.89                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  27615.21                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           6.15                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        6.15                       # Average system read bandwidth in MiByte/s
@@ -228,60 +216,60 @@ system.physmem.peakBW                        12800.00                       # Th
 system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.05                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         0.00                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       6283                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       6071                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   84.37                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   81.54                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                     10409062.91                       # Average gap between requests
-system.physmem.pageHitRate                      84.37                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               0.56                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                      6148481                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq                4317                       # Transaction distribution
-system.membus.trans_dist::ReadResp               4317                       # Transaction distribution
-system.membus.trans_dist::ReadExReq              3130                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             3130                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        14894                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  14894                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       476608                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total              476608                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus                 476608                       # Total data (bytes)
+system.physmem.avgGap                     10398577.64                       # Average gap between requests
+system.physmem.pageHitRate                      81.54                       # Row buffer hit rate, read and write combined
+system.physmem.prechargeAllPercent               0.52                       # Percentage of time for which DRAM has all the banks in precharge state
+system.membus.throughput                      6154681                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq                4313                       # Transaction distribution
+system.membus.trans_dist::ReadResp               4313                       # Transaction distribution
+system.membus.trans_dist::ReadExReq              3132                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             3132                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        14890                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  14890                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       476480                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total              476480                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus                 476480                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy             9290500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy             9329500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           69562000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           69519750                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                50307155                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          29267262                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           1212205                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             26317352                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                23268236                       # Number of BTB hits
+system.cpu.branchPred.lookups                50246060                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          29233966                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           1199560                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             25853120                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                23225371                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             88.414047                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 9019862                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect               1049                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             89.835853                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 9012456                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect               1102                       # Number of incorrect RAS predictions.
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    101828804                       # DTB read hits
-system.cpu.dtb.read_misses                      77910                       # DTB read misses
-system.cpu.dtb.read_acv                         48604                       # DTB read access violations
-system.cpu.dtb.read_accesses                101906714                       # DTB read accesses
-system.cpu.dtb.write_hits                    78465960                       # DTB write hits
-system.cpu.dtb.write_misses                      1494                       # DTB write misses
-system.cpu.dtb.write_acv                            4                       # DTB write access violations
-system.cpu.dtb.write_accesses                78467454                       # DTB write accesses
-system.cpu.dtb.data_hits                    180294764                       # DTB hits
-system.cpu.dtb.data_misses                      79404                       # DTB misses
-system.cpu.dtb.data_acv                         48608                       # DTB access violations
-system.cpu.dtb.data_accesses                180374168                       # DTB accesses
-system.cpu.itb.fetch_hits                    50297233                       # ITB hits
-system.cpu.itb.fetch_misses                       369                       # ITB misses
+system.cpu.dtb.read_hits                    101798719                       # DTB read hits
+system.cpu.dtb.read_misses                      78049                       # DTB read misses
+system.cpu.dtb.read_acv                         48607                       # DTB read access violations
+system.cpu.dtb.read_accesses                101876768                       # DTB read accesses
+system.cpu.dtb.write_hits                    78433341                       # DTB write hits
+system.cpu.dtb.write_misses                      1499                       # DTB write misses
+system.cpu.dtb.write_acv                            2                       # DTB write access violations
+system.cpu.dtb.write_accesses                78434840                       # DTB write accesses
+system.cpu.dtb.data_hits                    180232060                       # DTB hits
+system.cpu.dtb.data_misses                      79548                       # DTB misses
+system.cpu.dtb.data_acv                         48609                       # DTB access violations
+system.cpu.dtb.data_accesses                180311608                       # DTB accesses
+system.cpu.itb.fetch_hits                    50221171                       # ITB hits
+system.cpu.itb.fetch_misses                       373                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                50297602                       # ITB accesses
+system.cpu.itb.fetch_accesses                50221544                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -295,105 +283,105 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                  215                       # Number of system calls
-system.cpu.numCycles                        155032764                       # number of cpu cycles simulated
+system.cpu.numCycles                        154835002                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           51194259                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      449183474                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    50307155                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           32288098                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      78871433                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 6172161                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles               19742008                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                  181                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles         10560                       # Number of stall cycles due to pending traps
+system.cpu.fetch.icacheStallCycles           51111974                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      448661331                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    50246060                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           32237827                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      78769244                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 6113875                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles               19767092                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                  184                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles         10735                       # Number of stall cycles due to pending traps
 system.cpu.fetch.IcacheWaitRetryStallCycles           18                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  50297233                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                412894                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          154739151                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.902843                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.324835                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines                  50221171                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                406319                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          154534598                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.903307                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.325117                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 75867718     49.03%     49.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  4287409      2.77%     51.80% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  6889018      4.45%     56.25% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  5374428      3.47%     59.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 11763624      7.60%     67.33% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  7816659      5.05%     72.38% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  5616009      3.63%     76.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1833388      1.18%     77.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 35290898     22.81%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 75765354     49.03%     49.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  4278797      2.77%     51.80% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  6878880      4.45%     56.25% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  5365294      3.47%     59.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 11742013      7.60%     67.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  7808130      5.05%     72.37% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  5610858      3.63%     76.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1827134      1.18%     77.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 35258138     22.82%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            154739151                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.324494                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.897345                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 56553436                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              15088868                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  74238964                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               3941383                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                4916500                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              9487386                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                  4275                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              445247195                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                 12161                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                4916500                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 59699528                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 4890372                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         419538                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  75126102                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               9687111                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              440708166                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                   170                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                  18989                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               8005915                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands           287519835                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             579387338                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        414037453                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups         165349884                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            154534598                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.324514                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.897674                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 56469798                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              15107857                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  74141890                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               3943911                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                4871142                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              9469846                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                  4291                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              444777840                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                 12202                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                4871142                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 59608441                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 4896661                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         418311                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  75037002                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               9703041                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              440308504                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                   162                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                  18256                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               8013879                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands           287257669                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             578877349                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        413693152                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups         165184196                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             259532329                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 27987506                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts              36934                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            290                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  27862892                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            104720393                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            80633883                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           8938676                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          6410471                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  408405086                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                 279                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 401961016                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            974295                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        32695397                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     15321612                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved             64                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     154739151                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.597668                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.996651                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                 27725340                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts              36879                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            302                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  27905569                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            104673865                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            80579462                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           8919028                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          6395315                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  408114726                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                 290                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 401714158                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            971094                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        32406044                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     15222181                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             75                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     154534598                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.599510                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.995704                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            28425455     18.37%     18.37% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            25900888     16.74%     35.11% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            25580333     16.53%     51.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            24228882     15.66%     67.30% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            21279905     13.75%     81.05% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            15505585     10.02%     91.07% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             8490760      5.49%     96.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             3998033      2.58%     99.14% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             1329310      0.86%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            28287072     18.30%     18.30% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            25862273     16.74%     35.04% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            25616970     16.58%     51.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            24199972     15.66%     67.28% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            21258651     13.76%     81.03% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            15520360     10.04%     91.08% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             8472156      5.48%     96.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             3988463      2.58%     99.14% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             1328681      0.86%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       154739151                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       154534598                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                   33873      0.29%      0.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                   33844      0.29%      0.29% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                      0      0.00%      0.29% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                 57850      0.49%      0.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                  5381      0.05%      0.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                  5383      0.05%      0.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult              1948507     16.46%     17.33% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv               1748153     14.77%     32.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                 57389      0.49%      0.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                  4757      0.04%      0.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                  5293      0.04%      0.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult              1937864     16.39%     17.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv               1755771     14.85%     32.09% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     32.09% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdAdd                      0      0.00%     32.09% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     32.09% # attempts to use FU when none available
@@ -415,118 +403,118 @@ system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     32.09% # at
 system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     32.09% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     32.09% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     32.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                5077908     42.90%     74.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               2960216     25.01%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                5068587     42.87%     74.96% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               2960872     25.04%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass             33581      0.01%      0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             155836212     38.77%     38.78% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult              2126206      0.53%     39.31% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     39.31% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd            32826139      8.17%     47.47% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp             7503461      1.87%     49.34% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt             2792900      0.69%     50.03% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult           16557877      4.12%     54.15% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv             1579224      0.39%     54.55% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     54.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     54.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     54.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     54.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     54.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     54.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     54.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     54.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     54.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     54.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     54.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     54.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     54.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     54.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     54.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     54.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     54.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     54.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     54.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     54.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     54.55% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            103415841     25.73%     80.27% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            79289575     19.73%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             155710180     38.76%     38.77% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult              2126250      0.53%     39.30% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     39.30% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd            32800446      8.17%     47.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp             7495713      1.87%     49.33% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt             2793863      0.70%     50.03% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult           16555604      4.12%     54.15% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv             1576822      0.39%     54.54% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     54.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     54.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     54.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     54.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     54.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     54.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     54.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     54.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     54.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     54.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     54.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     54.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     54.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     54.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     54.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     54.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     54.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     54.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     54.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     54.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     54.54% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            103379318     25.73%     80.27% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            79242381     19.73%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              401961016                       # Type of FU issued
-system.cpu.iq.rate                           2.592749                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    11837271                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.029449                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          634505774                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         260497209                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    234812479                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads           336966975                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes          180652533                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses    161419314                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              241576222                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses               172188484                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         15052407                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              401714158                       # Type of FU issued
+system.cpu.iq.rate                           2.594466                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    11824377                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.029435                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          633974130                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         260128925                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    234699525                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads           336784255                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes          180440959                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses    161353653                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              241409796                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses               172095158                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         15058802                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      9965906                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses       111384                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        48996                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      7113154                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      9919378                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       112340                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        48844                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      7058733                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads       260897                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          3921                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads       260875                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          3830                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                4916500                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 2514816                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                370985                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           433209224                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            130318                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             104720393                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             80633883                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                279                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                     90                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                    76                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          48996                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         956631                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       408580                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1365211                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             398393230                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             101955347                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           3567786                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                4871142                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 2518143                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                371002                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           432897365                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            126094                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             104673865                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             80579462                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                290                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                     87                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                    80                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          48844                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         943634                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       406077                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              1349711                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             398212292                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             101925424                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           3501866                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                      24803859                       # number of nop insts executed
-system.cpu.iew.exec_refs                    180422830                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 46575028                       # Number of branches executed
-system.cpu.iew.exec_stores                   78467483                       # Number of stores executed
-system.cpu.iew.exec_rate                     2.569736                       # Inst execution rate
-system.cpu.iew.wb_sent                      396861814                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     396231793                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 193564452                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 271143010                       # num instructions consuming a value
+system.cpu.iew.exec_nop                      24782349                       # number of nop insts executed
+system.cpu.iew.exec_refs                    180360292                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 46546611                       # Number of branches executed
+system.cpu.iew.exec_stores                   78434868                       # Number of stores executed
+system.cpu.iew.exec_rate                     2.571849                       # Inst execution rate
+system.cpu.iew.wb_sent                      396683492                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     396053178                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 193508627                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 271030051                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       2.555794                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.713883                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       2.557905                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.713975                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        34575269                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts        34263124                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             215                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           1208013                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    149822651                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.660910                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.995203                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           1195351                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    149663456                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.663740                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.995900                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     55444795     37.01%     37.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     22572345     15.07%     52.07% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     13039783      8.70%     60.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     11474023      7.66%     68.43% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      8200661      5.47%     73.91% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      5438800      3.63%     77.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      5171862      3.45%     80.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      3280269      2.19%     83.18% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     25200113     16.82%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     55327244     36.97%     36.97% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     22535122     15.06%     52.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     13022576      8.70%     60.73% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     11475094      7.67%     68.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      8197799      5.48%     73.87% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      5452875      3.64%     77.51% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      5172237      3.46%     80.97% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      3274038      2.19%     83.16% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     25206471     16.84%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    149822651                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    149663456                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            398664583                       # Number of instructions committed
 system.cpu.commit.committedOps              398664583                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -537,228 +525,228 @@ system.cpu.commit.branches                   44587533                       # Nu
 system.cpu.commit.fp_insts                  155295106                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                 316365839                       # Number of committed integer instructions.
 system.cpu.commit.function_calls              8007752                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events              25200113                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events              25206471                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    557859413                       # The number of ROB reads
-system.cpu.rob.rob_writes                   871404727                       # The number of ROB writes
-system.cpu.timesIdled                            3579                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          293613                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                    557381715                       # The number of ROB reads
+system.cpu.rob.rob_writes                   870735186                       # The number of ROB writes
+system.cpu.timesIdled                            3600                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          300404                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   375574808                       # Number of Instructions Simulated
 system.cpu.committedOps                     375574808                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total             375574808                       # Number of Instructions Simulated
-system.cpu.cpi                               0.412788                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.412788                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               2.422551                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         2.422551                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                398219851                       # number of integer regfile reads
-system.cpu.int_regfile_writes               170183531                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                 156589680                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                104065109                       # number of floating regfile writes
+system.cpu.cpi                               0.412261                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.412261                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               2.425645                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         2.425645                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                398046268                       # number of integer regfile reads
+system.cpu.int_regfile_writes               170097469                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                 156518592                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                104028166                       # number of floating regfile writes
 system.cpu.misc_regfile_reads                  350572                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput                 7356381                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq           5061                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp          5061                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback          659                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq         3190                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp         3190                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         8138                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9023                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             17161                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       260416                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       309824                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total         570240                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus            570240                       # Total data (bytes)
+system.cpu.toL2Bus.throughput                 7364950                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq           5055                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp          5055                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback          661                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq         3193                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp         3193                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         8124                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9033                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             17157                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       259968                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       310208                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total         570176                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus            570176                       # Total data (bytes)
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy        5114000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.occupancy        5115500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       6775000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       6740250                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy       6675000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy       6663250                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.icache.tags.replacements              2141                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1831.580097                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            50291612                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              4069                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          12359.698206                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements              2135                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1832.551439                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            50215552                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              4062                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          12362.272772                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1831.580097                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.894326                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.894326                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1928                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          125                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          133                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          336                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1334                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.941406                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         100598535                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        100598535                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     50291612                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        50291612                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      50291612                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         50291612                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     50291612                       # number of overall hits
-system.cpu.icache.overall_hits::total        50291612                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         5621                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          5621                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         5621                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           5621                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         5621                       # number of overall misses
-system.cpu.icache.overall_misses::total          5621                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    330634250                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    330634250                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    330634250                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    330634250                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    330634250                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    330634250                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     50297233                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     50297233                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     50297233                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     50297233                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     50297233                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     50297233                       # number of overall (read+write) accesses
+system.cpu.icache.tags.occ_blocks::cpu.inst  1832.551439                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.894801                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.894801                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1927                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          123                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          149                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          309                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1346                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.940918                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         100446404                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        100446404                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     50215552                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        50215552                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      50215552                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         50215552                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     50215552                       # number of overall hits
+system.cpu.icache.overall_hits::total        50215552                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         5619                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          5619                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         5619                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           5619                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         5619                       # number of overall misses
+system.cpu.icache.overall_misses::total          5619                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    332785750                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    332785750                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    332785750                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    332785750                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    332785750                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    332785750                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     50221171                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     50221171                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     50221171                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     50221171                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     50221171                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     50221171                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000112                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000112                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000112                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000112                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000112                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000112                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58821.250667                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 58821.250667                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 58821.250667                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 58821.250667                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 58821.250667                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 58821.250667                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          892                       # number of cycles access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59225.084535                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 59225.084535                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 59225.084535                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 59225.084535                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 59225.084535                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 59225.084535                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          251                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 6                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 3                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs   148.666667                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    83.666667                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1552                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         1552                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         1552                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         1552                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         1552                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         1552                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4069                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         4069                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         4069                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         4069                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         4069                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         4069                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    249126500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    249126500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    249126500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    249126500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    249126500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    249126500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1557                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         1557                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         1557                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         1557                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         1557                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         1557                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4062                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         4062                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         4062                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         4062                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         4062                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         4062                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    250275250                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    250275250                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    250275250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    250275250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    250275250                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    250275250                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000081                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000081                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000081                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000081                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000081                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000081                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61225.485377                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61225.485377                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61225.485377                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 61225.485377                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61225.485377                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 61225.485377                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61613.798621                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61613.798621                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61613.798621                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 61613.798621                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61613.798621                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 61613.798621                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         4006.698259                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs                830                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             4855                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.170958                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         4014.912123                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs                831                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs             4850                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.171340                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks   372.314002                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2972.989124                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   661.395133                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks   372.322070                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2981.516963                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   661.073090                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.011362                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.090728                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.020184                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.122275                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024         4855                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.090989                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.020174                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.122525                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         4850                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          149                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1           96                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          579                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         4031                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.148163                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses            79325                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses           79325                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst          613                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data          131                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total            744                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks          659                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total          659                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data           60                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total           60                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst          613                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data          191                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total             804                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst          613                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data          191                       # number of overall hits
-system.cpu.l2cache.overall_hits::total            804                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         3456                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data          861                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         4317                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data         3130                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total         3130                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         3456                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data         3991                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total          7447                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         3456                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data         3991                       # number of overall misses
-system.cpu.l2cache.overall_misses::total         7447                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    238915500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     66414500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    305330000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    225828500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    225828500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    238915500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    292243000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    531158500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    238915500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    292243000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    531158500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst         4069                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data          992                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total         5061                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks          659                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total          659                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data         3190                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total         3190                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         4069                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data         4182                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total         8251                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         4069                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data         4182                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total         8251                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.849349                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.867944                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.852993                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.981191                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.981191                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.849349                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.954328                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.902557                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.849349                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.954328                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.902557                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69130.642361                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77136.469222                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 70727.356961                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72149.680511                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72149.680511                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69130.642361                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73225.507392                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 71325.164496                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69130.642361                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73225.507392                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 71325.164496                       # average overall miss latency
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          114                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          550                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         4037                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.148010                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses            79315                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses           79315                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst          609                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data          133                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total            742                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks          661                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total          661                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data           61                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total           61                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst          609                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data          194                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total             803                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst          609                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data          194                       # number of overall hits
+system.cpu.l2cache.overall_hits::total            803                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         3453                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data          860                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total         4313                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data         3132                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total         3132                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         3453                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data         3992                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total          7445                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         3453                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data         3992                       # number of overall misses
+system.cpu.l2cache.overall_misses::total         7445                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    240112000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     66837250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    306949250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    229848000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    229848000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    240112000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    296685250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    536797250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    240112000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    296685250                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    536797250                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst         4062                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data          993                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total         5055                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks          661                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total          661                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data         3193                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total         3193                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         4062                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data         4186                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total         8248                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         4062                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data         4186                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total         8248                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.850074                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.866062                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.853215                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.980896                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.980896                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.850074                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.953655                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.902643                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.850074                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.953655                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.902643                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69537.214017                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77717.732558                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 71168.386274                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73386.973180                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73386.973180                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69537.214017                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74319.952405                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 72101.712559                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69537.214017                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74319.952405                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 72101.712559                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -767,155 +755,155 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3456                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          861                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         4317                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         3130                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total         3130                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3456                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data         3991                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         7447                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3456                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data         3991                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total         7447                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    195042500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     55799500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    250842000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    187339500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    187339500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    195042500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    243139000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    438181500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    195042500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    243139000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    438181500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.849349                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.867944                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.852993                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.981191                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.981191                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.849349                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.954328                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.902557                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.849349                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.954328                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.902557                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56435.908565                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64807.781649                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58105.628909                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59852.875399                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59852.875399                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56435.908565                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60921.824104                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58840.002686                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56435.908565                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60921.824104                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58840.002686                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3453                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          860                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         4313                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         3132                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         3132                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3453                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data         3992                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         7445                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3453                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data         3992                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total         7445                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    196358500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     56239750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    252598250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    191312000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    191312000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    196358500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    247551750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    443910250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    196358500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    247551750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    443910250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.850074                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.866062                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.853215                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.980896                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.980896                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.850074                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.953655                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.902643                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.850074                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.953655                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.902643                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56866.058500                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65395.058140                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58566.716902                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61083.014049                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61083.014049                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56866.058500                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62011.961423                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59625.285426                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56866.058500                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62011.961423                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59625.285426                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements               780                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          3295.992263                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           160011153                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs              4182                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          38261.873027                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.replacements               784                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          3296.614513                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           159974752                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs              4186                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          38216.615385                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  3295.992263                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.804686                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.804686                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data  3296.614513                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.804838                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.804838                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         3402                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           47                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           17                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          215                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          214                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3            6                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         3117                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         3118                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.830566                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         320069754                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        320069754                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     86510267                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        86510267                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     73500882                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       73500882                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data            4                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total            4                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data     160011149                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        160011149                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    160011149                       # number of overall hits
-system.cpu.dcache.overall_hits::total       160011149                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data         1786                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total          1786                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data        19847                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total        19847                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data        21633                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total          21633                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data        21633                       # number of overall misses
-system.cpu.dcache.overall_misses::total         21633                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data    114228250                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total    114228250                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   1085833087                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   1085833087                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data   1200061337                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total   1200061337                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data   1200061337                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total   1200061337                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     86512053                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     86512053                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses         319997054                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        319997054                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     86473896                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        86473896                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     73500850                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       73500850                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data            6                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total            6                       # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits::cpu.data     159974746                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        159974746                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    159974746                       # number of overall hits
+system.cpu.dcache.overall_hits::total       159974746                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data         1803                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total          1803                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data        19879                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        19879                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data        21682                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total          21682                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data        21682                       # number of overall misses
+system.cpu.dcache.overall_misses::total         21682                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data    116178750                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total    116178750                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   1100405079                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   1100405079                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data   1216583829                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total   1216583829                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data   1216583829                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total   1216583829                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     86475699                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     86475699                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     73520729                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     73520729                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data            4                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total            4                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    160032782                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    160032782                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    160032782                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    160032782                       # number of overall (read+write) accesses
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data            6                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total            6                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    159996428                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    159996428                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    159996428                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    159996428                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000021                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.000021                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000270                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.000270                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.000135                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.000135                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.000135                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.000135                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63957.586786                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 63957.586786                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54710.187283                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 54710.187283                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 55473.643831                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 55473.643831                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 55473.643831                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 55473.643831                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs        40366                       # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data     0.000136                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.000136                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.000136                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.000136                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64436.356073                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 64436.356073                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55355.152623                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 55355.152623                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 56110.314039                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 56110.314039                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 56110.314039                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 56110.314039                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs        40445                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs               653                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs               670                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    61.816233                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    60.365672                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks          659                       # number of writebacks
-system.cpu.dcache.writebacks::total               659                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          794                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          794                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        16657                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        16657                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data        17451                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total        17451                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data        17451                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total        17451                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data          992                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          992                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data         3190                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total         3190                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data         4182                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total         4182                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data         4182                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total         4182                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     68767000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     68767000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    229720000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    229720000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    298487000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    298487000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    298487000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    298487000                       # number of overall MSHR miss cycles
+system.cpu.dcache.writebacks::writebacks          661                       # number of writebacks
+system.cpu.dcache.writebacks::total               661                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          810                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          810                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        16686                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        16686                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data        17496                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total        17496                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data        17496                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total        17496                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          993                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          993                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data         3193                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         3193                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data         4186                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         4186                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data         4186                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         4186                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     69211250                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     69211250                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    233753500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    233753500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    302964750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    302964750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    302964750                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    302964750                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000011                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000011                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000043                       # mshr miss rate for WriteReq accesses
@@ -924,14 +912,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000026
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000026                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000026                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000026                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 69321.572581                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69321.572581                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72012.539185                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72012.539185                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71374.222860                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 71374.222860                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71374.222860                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 71374.222860                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 69699.144008                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69699.144008                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73208.111494                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73208.111494                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72375.716675                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 72375.716675                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72375.716675                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 72375.716675                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 634fe5f9a4ade6a3c7c0298048f5374bfcd58365..648c5ea6fe999f1a9eb85f18a49b7cbac9ace855 100644 (file)
@@ -1,62 +1,62 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.068504                       # Number of seconds simulated
-sim_ticks                                 68503867000                       # Number of ticks simulated
-final_tick                                68503867000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.068245                       # Number of seconds simulated
+sim_ticks                                 68245472000                       # Number of ticks simulated
+final_tick                                68245472000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 147835                       # Simulator instruction rate (inst/s)
-host_op_rate                                   189000                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               37091215                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 278164                       # Number of bytes of host memory used
-host_seconds                                  1846.90                       # Real time elapsed on the host
+host_inst_rate                                 123424                       # Simulator instruction rate (inst/s)
+host_op_rate                                   157791                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               30849723                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 321440                       # Number of bytes of host memory used
+host_seconds                                  2212.19                       # Real time elapsed on the host
 sim_insts                                   273036725                       # Number of instructions simulated
 sim_ops                                     349064449                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            193984                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data            272256                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               466240                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       193984                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          193984                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               3031                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               4254                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  7285                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              2831723                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3974316                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 6806039                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         2831723                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            2831723                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             2831723                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             3974316                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6806039                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                          7286                       # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst            193792                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data            272576                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               466368                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       193792                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          193792                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               3028                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               4259                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  7287                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              2839632                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3994053                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 6833684                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         2839632                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            2839632                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             2839632                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             3994053                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                6833684                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                          7288                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                        7286                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                        7288                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                   466304                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                   466432                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                    466304                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                    466432                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs              2                       # Number of requests that are neither read nor write
+system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
 system.physmem.perBankRdBursts::0                 606                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                 800                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                 802                       # Per bank write bursts
 system.physmem.perBankRdBursts::2                 608                       # Per bank write bursts
 system.physmem.perBankRdBursts::3                 526                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                 443                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                 354                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                 164                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                 219                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                 207                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                 291                       # Per bank write bursts
-system.physmem.perBankRdBursts::10                322                       # Per bank write bursts
-system.physmem.perBankRdBursts::11                415                       # Per bank write bursts
-system.physmem.perBankRdBursts::12                529                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                 441                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                 356                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                 162                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                 220                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                 205                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                 290                       # Per bank write bursts
+system.physmem.perBankRdBursts::10                324                       # Per bank write bursts
+system.physmem.perBankRdBursts::11                417                       # Per bank write bursts
+system.physmem.perBankRdBursts::12                531                       # Per bank write bursts
 system.physmem.perBankRdBursts::13                687                       # Per bank write bursts
 system.physmem.perBankRdBursts::14                611                       # Per bank write bursts
-system.physmem.perBankRdBursts::15                504                       # Per bank write bursts
+system.physmem.perBankRdBursts::15                502                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     68503846500                       # Total gap between requests
+system.physmem.totGap                     68245446000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                    7286                       # Read request sizes (log2)
+system.physmem.readPktSize::6                    7288                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -90,12 +90,12 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      4373                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      2103                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       567                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       176                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        66                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      4342                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      2121                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       590                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       174                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        61                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
@@ -154,124 +154,102 @@ system.physmem.wrQLenPdf::28                        0                       # Wh
 system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         1286                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      361.604977                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     163.647663                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     753.981601                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64-65            537     41.76%     41.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-129          220     17.11%     58.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192-193          131     10.19%     69.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-257           77      5.99%     75.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320-321           39      3.03%     78.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-385           38      2.95%     81.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448-449           26      2.02%     83.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-513           31      2.41%     85.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576-577           17      1.32%     86.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-641           23      1.79%     88.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704-705            6      0.47%     89.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-769           16      1.24%     90.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832-833            3      0.23%     90.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-897            8      0.62%     91.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960-961            7      0.54%     91.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1025            7      0.54%     92.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088-1089            5      0.39%     92.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152-1153            8      0.62%     93.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216-1217            5      0.39%     93.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280-1281            6      0.47%     94.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344-1345            1      0.08%     94.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408-1409            4      0.31%     94.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472-1473            4      0.31%     94.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536-1537            6      0.47%     95.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600-1601            3      0.23%     95.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664-1665            3      0.23%     95.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1728-1729            3      0.23%     95.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1792-1793            4      0.31%     96.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1920-1921            2      0.16%     96.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984-1985            3      0.23%     96.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2048-2049            2      0.16%     96.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112-2113            4      0.31%     97.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2176-2177            2      0.16%     97.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2240-2241            1      0.08%     97.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2304-2305            1      0.08%     97.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2368-2369            2      0.16%     97.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2496-2497            1      0.08%     97.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2560-2561            1      0.08%     97.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2624-2625            1      0.08%     97.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2752-2753            1      0.08%     97.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2816-2817            1      0.08%     97.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2880-2881            2      0.16%     98.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2944-2945            1      0.08%     98.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3008-3009            2      0.16%     98.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3072-3073            1      0.08%     98.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3136-3137            1      0.08%     98.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3200-3201            1      0.08%     98.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3328-3329            1      0.08%     98.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3584-3585            2      0.16%     98.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3712-3713            1      0.08%     98.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3840-3841            1      0.08%     98.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4032-4033            1      0.08%     99.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4096-4097            1      0.08%     99.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4160-4161            1      0.08%     99.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4608-4609            3      0.23%     99.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4736-4737            1      0.08%     99.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6464-6465            1      0.08%     99.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6528-6529            1      0.08%     99.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6656-6657            1      0.08%     99.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7552-7553            1      0.08%     99.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8192-8193            2      0.16%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           1286                       # Bytes accessed per row activation
-system.physmem.totQLat                       62980000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 198080000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     36430000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                    98670000                       # Total ticks spent accessing banks
-system.physmem.avgQLat                        8643.97                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    13542.41                       # Average bank access latency per DRAM burst
+system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples          580                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      479.779310                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     274.986956                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     421.744260                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            159     27.41%     27.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          117     20.17%     47.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           45      7.76%     55.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           23      3.97%     59.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           14      2.41%     61.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           13      2.24%     63.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            6      1.03%     65.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            2      0.34%     65.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          201     34.66%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total            580                       # Bytes accessed per row activation
+system.physmem.totQLat                       57907000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 195684500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     36440000                       # Total ticks spent in databus transfers
+system.physmem.totBankLat                   101337500                       # Total ticks spent accessing banks
+system.physmem.avgQLat                        7945.53                       # Average queueing delay per DRAM burst
+system.physmem.avgBankLat                    13904.71                       # Average bank access latency per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  27186.38                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           6.81                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  26850.23                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           6.83                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        6.81                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        6.83                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.05                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         0.00                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.16                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       6000                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       5839                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.35                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   80.12                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                      9402120.02                       # Average gap between requests
-system.physmem.pageHitRate                      82.35                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               1.05                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                      6806039                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq                4462                       # Transaction distribution
-system.membus.trans_dist::ReadResp               4461                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq                2                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
-system.membus.trans_dist::ReadExReq              2824                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             2824                       # Transaction distribution
+system.physmem.avgGap                      9364084.25                       # Average gap between requests
+system.physmem.pageHitRate                      80.12                       # Row buffer hit rate, read and write combined
+system.physmem.prechargeAllPercent               1.16                       # Percentage of time for which DRAM has all the banks in precharge state
+system.membus.throughput                      6833684                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq                4468                       # Transaction distribution
+system.membus.trans_dist::ReadResp               4467                       # Transaction distribution
+system.membus.trans_dist::ReadExReq              2820                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             2820                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        14575                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count::total                  14575                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       466240                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total              466240                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus                 466240                       # Total data (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       466368                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total              466368                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus                 466368                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy             8931500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy             8915000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           67747998                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           67732500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                35407535                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          21210003                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           1658535                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             19582924                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                16814113                       # Number of BTB hits
+system.cpu.branchPred.lookups                35342667                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          21189046                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           1621967                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             18355176                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                16729462                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             85.861095                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 6780652                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect               8453                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             91.143021                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 6774978                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect               8404                       # Number of incorrect RAS predictions.
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -357,100 +335,100 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  191                       # Number of system calls
-system.cpu.numCycles                        137007735                       # number of cpu cycles simulated
+system.cpu.numCycles                        136490945                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           38995510                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      317974758                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    35407535                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           23594765                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      70934448                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 6878177                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles               21511393                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                  109                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          1738                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles           61                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  37596145                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                512137                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          136651264                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.983546                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.454335                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           38825213                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      317051968                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    35342667                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           23504440                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      70679896                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 6716000                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles               21545367                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                  106                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles          1322                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles           66                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  37451719                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                502899                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          136134435                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.985255                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.454681                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 66349844     48.55%     48.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  6791529      4.97%     53.52% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  5702360      4.17%     57.70% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  6103499      4.47%     62.16% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  4918940      3.60%     65.76% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  4085838      2.99%     68.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  3180821      2.33%     71.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  4138782      3.03%     74.11% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 35379651     25.89%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 66077496     48.54%     48.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  6747770      4.96%     53.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  5691244      4.18%     57.68% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  6070617      4.46%     62.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  4899295      3.60%     65.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  4080163      3.00%     68.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  3177720      2.33%     71.07% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  4131471      3.03%     74.10% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 35258659     25.90%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            136651264                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.258435                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.320853                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 45513422                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              16662187                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  66798256                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               2538078                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                5139321                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              7340905                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 69056                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              401756741                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                208904                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                5139321                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 51060721                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 1905439                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         332675                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  63727748                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              14485360                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              394162913                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                    18                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                1657895                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents              10187119                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents            22377                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           432668253                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            2737675688                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1575239963                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups         200387111                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            136134435                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.258938                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.322879                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 45319095                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              16701200                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  66547822                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               2552537                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                5013781                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              7320658                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 69067                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              400437341                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                211449                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                5013781                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 50843684                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 1928767                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         335631                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  63516277                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              14496295                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              392925979                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                    32                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                1658279                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents              10203172                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents            22306                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           431444746                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            2730832248                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1570013245                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups         200164445                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             384566193                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 48102060                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts              11946                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts          11945                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  36528458                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            103595819                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            91394334                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           4295156                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          5297473                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  384542604                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded               22919                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 374214780                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           1210476                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        34753044                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    100302329                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            799                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     136651264                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.738466                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.024544                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                 46878553                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts              11940                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts          11939                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  36493417                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            103352368                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            91160183                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           4261604                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          5303451                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  383671023                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded               22900                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 373754233                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           1199031                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        33881433                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     97712598                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            780                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     136134435                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.745479                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.022556                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            25105050     18.37%     18.37% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            19938594     14.59%     32.96% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            20566375     15.05%     48.01% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            18171632     13.30%     61.31% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            24028761     17.58%     78.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            15737538     11.52%     90.41% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             8814188      6.45%     96.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             3372330      2.47%     99.33% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              916796      0.67%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            24740289     18.17%     18.17% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            19905513     14.62%     32.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            20515084     15.07%     47.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            18158642     13.34%     61.20% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            24030824     17.65%     78.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            15691878     11.53%     90.38% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             8802431      6.47%     96.85% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             3372838      2.48%     99.33% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              916936      0.67%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       136651264                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       136134435                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                    8713      0.05%      0.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                   4693      0.03%      0.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                    8938      0.05%      0.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                   4692      0.03%      0.08% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.08% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.08% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.08% # attempts to use FU when none available
@@ -469,127 +447,127 @@ system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      0.08% # at
 system.cpu.iq.fu_full::SimdShift                    0      0.00%      0.08% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      0.08% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      0.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd             46317      0.26%      0.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd             46049      0.26%      0.34% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      0.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp              3518      0.02%      0.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt               440      0.00%      0.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp              3482      0.02%      0.36% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt               434      0.00%      0.36% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatDiv                 2      0.00%      0.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc           186929      1.05%      1.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult             4248      0.02%      1.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc        241299      1.36%      2.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc           186470      1.05%      1.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult             3938      0.02%      1.43% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc        241178      1.36%      2.80% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      2.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                9275439     52.33%     55.13% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               7953254     44.87%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                9277159     52.37%     55.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               7942822     44.84%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             126461637     33.79%     33.79% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult              2175765      0.58%     34.38% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     34.38% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     34.38% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     34.38% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     34.38% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     34.38% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     34.38% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     34.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     34.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     34.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     34.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    4      0.00%     34.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     34.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     34.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     34.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     34.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     34.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     34.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     34.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd         6779975      1.81%     36.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     36.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp         8474577      2.26%     38.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt         3430301      0.92%     39.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv         1595259      0.43%     39.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc       20865413      5.58%     45.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult        7172902      1.92%     47.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc      7130224      1.91%     49.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt         175286      0.05%     49.24% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            101650995     27.16%     76.40% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            88302442     23.60%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             126226981     33.77%     33.77% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult              2175715      0.58%     34.35% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     34.35% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     34.35% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     34.35% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     34.35% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     34.35% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     34.35% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     34.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     34.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     34.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     34.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    4      0.00%     34.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     34.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     34.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     34.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     34.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     34.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     34.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     34.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd         6775957      1.81%     36.17% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     36.17% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp         8464752      2.26%     38.43% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt         3426733      0.92%     39.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv         1595441      0.43%     39.78% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc       20845390      5.58%     45.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult        7170609      1.92%     47.27% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc      7125607      1.91%     49.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt         175287      0.05%     49.23% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            101514689     27.16%     76.39% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            88257068     23.61%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              374214780                       # Type of FU issued
-system.cpu.iq.rate                           2.731341                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    17724852                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.047365                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          654627146                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         288999508                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    250114053                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads           249389006                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes          130333197                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses    118063719                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              263337797                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses               128601835                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         11086522                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              373754233                       # Type of FU issued
+system.cpu.iq.rate                           2.738308                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    17715164                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.047398                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          653197592                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         287339977                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    249810515                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads           249359504                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes          130249499                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses    118015221                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              262881293                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses               128588104                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         11104968                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      8947071                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses       108758                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        14277                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      9018751                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      8703620                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       109542                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        14223                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      8784600                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads       174712                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          1900                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads       184473                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          1790                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                5139321                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                  272764                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                 35129                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           384567184                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            874047                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             103595819                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             91394334                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts              11885                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                    347                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                   280                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          14277                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        1299093                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       369514                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1668607                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             370257441                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             100364532                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           3957339                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                5013781                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                  291002                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                 36408                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           383695470                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            852736                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             103352368                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             91160183                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts              11866                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                    327                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                   282                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          14223                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        1256888                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       362770                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              1619658                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             369836414                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             100211998                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           3917819                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                          1661                       # number of nop insts executed
-system.cpu.iew.exec_refs                    187583075                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 32009347                       # Number of branches executed
-system.cpu.iew.exec_stores                   87218543                       # Number of stores executed
-system.cpu.iew.exec_rate                     2.702456                       # Inst execution rate
-system.cpu.iew.wb_sent                      368846220                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     368177772                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 183055174                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 363803620                       # num instructions consuming a value
+system.cpu.iew.exec_nop                          1547                       # number of nop insts executed
+system.cpu.iew.exec_refs                    187429987                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 31988466                       # Number of branches executed
+system.cpu.iew.exec_stores                   87217989                       # Number of stores executed
+system.cpu.iew.exec_rate                     2.709604                       # Inst execution rate
+system.cpu.iew.wb_sent                      368475660                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     367825736                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 182824140                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 363330392                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       2.687277                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.503170                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       2.694873                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.503190                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        35502239                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts        34630475                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls           22120                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           1589851                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    131511943                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.654246                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.658719                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           1553283                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    131120654                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.662167                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.659302                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     34696225     26.38%     26.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     28452590     21.63%     48.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     13345612     10.15%     58.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     11442919      8.70%     66.87% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     13780020     10.48%     77.34% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      7417113      5.64%     82.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      3869989      2.94%     85.93% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      3892889      2.96%     88.89% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     14614586     11.11%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     34358811     26.20%     26.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     28410916     21.67%     47.87% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     13299289     10.14%     58.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     11469684      8.75%     66.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     13783827     10.51%     77.27% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      7406623      5.65%     82.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      3875247      2.96%     85.88% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      3903446      2.98%     88.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     14612811     11.14%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    131511943                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    131120654                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            273037337                       # Number of instructions committed
 system.cpu.commit.committedOps              349065061                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -600,238 +578,230 @@ system.cpu.commit.branches                   30563497                       # Nu
 system.cpu.commit.fp_insts                  114216705                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                 279584611                       # Number of committed integer instructions.
 system.cpu.commit.function_calls              6225112                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events              14614586                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events              14612811                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    501462134                       # The number of ROB reads
-system.cpu.rob.rob_writes                   774278104                       # The number of ROB writes
-system.cpu.timesIdled                            6640                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          356471                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                    500200856                       # The number of ROB reads
+system.cpu.rob.rob_writes                   772408679                       # The number of ROB writes
+system.cpu.timesIdled                            6691                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          356510                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   273036725                       # Number of Instructions Simulated
 system.cpu.committedOps                     349064449                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total             273036725                       # Number of Instructions Simulated
-system.cpu.cpi                               0.501792                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.501792                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.992856                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.992856                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               1769894079                       # number of integer regfile reads
-system.cpu.int_regfile_writes               233026497                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                 188140638                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                132514898                       # number of floating regfile writes
-system.cpu.misc_regfile_reads              1201076625                       # number of misc regfile reads
+system.cpu.cpi                               0.499900                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.499900                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               2.000402                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         2.000402                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               1768035388                       # number of integer regfile reads
+system.cpu.int_regfile_writes               232615737                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                 188041949                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                132439422                       # number of floating regfile writes
+system.cpu.misc_regfile_reads              1200568638                       # number of misc regfile reads
 system.cpu.misc_regfile_writes               34421755                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput                20069641                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq          17607                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp         17606                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback         1035                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq            2                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp            2                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq         2841                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp         2841                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        31671                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        10259                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             41930                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1013312                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       361280                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total        1374592                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus           1374592                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus          256                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy       11777500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.throughput                20175639                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq          17638                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp         17637                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback         1039                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq         2838                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp         2838                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        31713                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        10277                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             41990                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1014784                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       362112                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total        1376896                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus           1376896                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy       11796500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      24288488                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      24305488                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy       7388212                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy       7381711                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.icache.tags.replacements             13947                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1848.346697                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            37578823                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             15836                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           2372.999684                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements             13966                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1849.581585                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            37434387                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             15856                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           2360.897263                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1848.346697                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.902513                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.902513                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1889                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           53                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst  1849.581585                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.903116                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.903116                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1890                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           52                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1           92                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          205                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          206                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3            9                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1530                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.922363                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          75208123                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         75208123                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     37578823                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        37578823                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      37578823                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         37578823                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     37578823                       # number of overall hits
-system.cpu.icache.overall_hits::total        37578823                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        17320                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         17320                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        17320                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          17320                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        17320                       # number of overall misses
-system.cpu.icache.overall_misses::total         17320                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    450229234                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    450229234                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    450229234                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    450229234                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    450229234                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    450229234                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     37596143                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     37596143                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     37596143                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     37596143                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     37596143                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     37596143                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000461                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000461                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000461                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000461                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000461                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000461                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25994.759469                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 25994.759469                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 25994.759469                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 25994.759469                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 25994.759469                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 25994.759469                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         2351                       # number of cycles access was blocked
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1531                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.922852                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          74919290                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         74919290                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     37434387                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        37434387                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      37434387                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         37434387                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     37434387                       # number of overall hits
+system.cpu.icache.overall_hits::total        37434387                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        17330                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         17330                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        17330                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          17330                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        17330                       # number of overall misses
+system.cpu.icache.overall_misses::total         17330                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    451723484                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    451723484                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    451723484                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    451723484                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    451723484                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    451723484                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     37451717                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     37451717                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     37451717                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     37451717                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     37451717                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     37451717                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000463                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000463                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000463                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000463                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000463                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000463                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26065.982920                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 26065.982920                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 26065.982920                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 26065.982920                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 26065.982920                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 26065.982920                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         1035                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                25                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                26                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    94.040000                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    39.807692                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1482                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         1482                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         1482                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         1482                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         1482                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         1482                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        15838                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        15838                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        15838                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        15838                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        15838                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        15838                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    359653509                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    359653509                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    359653509                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    359653509                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    359653509                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    359653509                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000421                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000421                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000421                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000421                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000421                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000421                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22708.265501                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22708.265501                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22708.265501                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 22708.265501                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22708.265501                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 22708.265501                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1473                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         1473                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         1473                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         1473                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         1473                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         1473                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        15857                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        15857                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        15857                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        15857                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        15857                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        15857                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    359348009                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    359348009                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    359348009                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    359348009                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    359348009                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    359348009                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000423                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000423                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000423                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000423                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000423                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000423                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22661.790313                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22661.790313                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22661.790313                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 22661.790313                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22661.790313                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 22661.790313                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         3937.367139                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs              13183                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             5383                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             2.449006                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         3939.930856                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs              13213                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs             5393                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             2.450028                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks   378.211483                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2780.743240                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   778.412416                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.011542                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.084862                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.023755                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.120159                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024         5383                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           60                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1           69                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1236                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3           11                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         4007                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.164276                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses           180072                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses          180072                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst        12790                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data          299                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total          13089                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks         1035                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total         1035                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data           17                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total           17                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        12790                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data          316                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total           13106                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst        12790                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data          316                       # number of overall hits
-system.cpu.l2cache.overall_hits::total          13106                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         3044                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data         1470                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         4514                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data            2                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total            2                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data         2824                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total         2824                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         3044                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data         4294                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total          7338                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         3044                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data         4294                       # number of overall misses
-system.cpu.l2cache.overall_misses::total         7338                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    215877500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data    110553500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    326431000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    198942750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    198942750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    215877500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    309496250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    525373750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    215877500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    309496250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    525373750                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst        15834                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data         1769                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total        17603                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks         1035                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total         1035                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data            2                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total            2                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data         2841                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total         2841                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        15834                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data         4610                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total        20444                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        15834                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data         4610                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total        20444                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.192245                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.830978                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.256434                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data            1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.994016                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.994016                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.192245                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.931453                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.358932                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.192245                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.931453                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.358932                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70919.021025                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75206.462585                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 72315.241471                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70447.149433                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70447.149433                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70919.021025                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72076.443875                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 71596.313709                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70919.021025                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72076.443875                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 71596.313709                       # average overall miss latency
+system.cpu.l2cache.tags.occ_blocks::writebacks   375.867414                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2777.143346                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   786.920096                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.011471                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.084752                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.024015                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.120237                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         5393                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           58                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           71                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1243                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3           10                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         4011                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.164581                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses           180351                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses          180351                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst        12816                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data          303                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total          13119                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks         1039                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total         1039                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data           18                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total           18                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst        12816                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data          321                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total           13137                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst        12816                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data          321                       # number of overall hits
+system.cpu.l2cache.overall_hits::total          13137                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         3041                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data         1478                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total         4519                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data         2820                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total         2820                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         3041                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data         4298                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total          7339                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         3041                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data         4298                       # number of overall misses
+system.cpu.l2cache.overall_misses::total         7339                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    215304250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data    106779500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    322083750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    200114250                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    200114250                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    215304250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    306893750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    522198000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    215304250                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    306893750                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    522198000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst        15857                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data         1781                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total        17638                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks         1039                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total         1039                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data         2838                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total         2838                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        15857                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data         4619                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total        20476                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        15857                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data         4619                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total        20476                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.191777                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.829871                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.256208                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.993658                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.993658                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.191777                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.930504                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.358420                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.191777                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.930504                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.358420                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70800.476817                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72245.940460                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 71273.235229                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70962.500000                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70962.500000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70800.476817                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71403.850628                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 71153.835672                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70800.476817                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71403.850628                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 71153.835672                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -841,185 +811,177 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets          nan
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           12                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           40                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total           52                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           39                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total           51                       # number of ReadReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.inst           12                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data           40                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total           52                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data           39                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           51                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.inst           12                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data           40                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total           52                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3032                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data         1430                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         4462                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            2                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total            2                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         2824                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total         2824                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3032                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data         4254                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         7286                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3032                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data         4254                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total         7286                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    177153750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     90029000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    267182750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        20002                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        20002                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    164034250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    164034250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    177153750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    254063250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    431217000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    177153750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    254063250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    431217000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.191487                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.808366                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.253480                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.994016                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.994016                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.191487                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.922777                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.356388                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.191487                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.922777                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.356388                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58428.017810                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62957.342657                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59879.594352                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        10001                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58085.782578                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58085.782578                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58428.017810                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59723.377997                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59184.326105                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58428.017810                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59723.377997                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59184.326105                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_hits::cpu.data           39                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total           51                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3029                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data         1439                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         4468                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         2820                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         2820                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3029                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data         4259                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         7288                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3029                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data         4259                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total         7288                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    176626500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     86490250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    263116750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    165285750                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    165285750                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    176626500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    251776000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    428402500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    176626500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    251776000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    428402500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.191020                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.807973                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.253317                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.993658                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.993658                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.191020                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.922061                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.355929                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.191020                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.922061                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.355929                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58311.819082                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60104.412787                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58889.156222                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58611.968085                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58611.968085                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58311.819082                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59116.224466                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58781.901756                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58311.819082                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59116.224466                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58781.901756                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements              1413                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          3103.986618                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           170973728                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs              4610                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          37087.576573                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.replacements              1416                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          3111.494128                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           170791722                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs              4619                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          36975.908638                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  3103.986618                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.757809                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.757809                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         3197                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           24                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           31                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          682                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3           11                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         2449                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.780518                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         342002086                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        342002086                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     88920204                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        88920204                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     82031597                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       82031597                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data        11020                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total        11020                       # number of LoadLockedReq hits
+system.cpu.dcache.tags.occ_blocks::cpu.data  3111.494128                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.759642                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.759642                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         3203                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           23                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           34                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          686                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3           10                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         2450                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.781982                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         341638239                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        341638239                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     88738255                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        88738255                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     82031563                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       82031563                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data        11009                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total        11009                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data        10895                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total        10895                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     170951801                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        170951801                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    170951801                       # number of overall hits
-system.cpu.dcache.overall_hits::total       170951801                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data         3952                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total          3952                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data        21068                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total        21068                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data     170769818                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        170769818                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    170769818                       # number of overall hits
+system.cpu.dcache.overall_hits::total       170769818                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data         3984                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total          3984                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data        21102                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        21102                       # number of WriteReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            2                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            2                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data        25020                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total          25020                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data        25020                       # number of overall misses
-system.cpu.dcache.overall_misses::total         25020                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data    237491705                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total    237491705                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   1258064893                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   1258064893                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data        25086                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total          25086                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data        25086                       # number of overall misses
+system.cpu.dcache.overall_misses::total         25086                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data    232475203                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total    232475203                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   1255700879                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   1255700879                       # number of WriteReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       170250                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::total       170250                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data   1495556598                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total   1495556598                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data   1495556598                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total   1495556598                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     88924156                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     88924156                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data   1488176082                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total   1488176082                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data   1488176082                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total   1488176082                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     88742239                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     88742239                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     82052665                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     82052665                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data        11022                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total        11022                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data        11011                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total        11011                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data        10895                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total        10895                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    170976821                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    170976821                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    170976821                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    170976821                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000044                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.000044                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data    170794904                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    170794904                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    170794904                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    170794904                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000045                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.000045                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000257                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.000257                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000181                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000181                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.000146                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.000146                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.000146                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.000146                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60094.054909                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 60094.054909                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59714.490839                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 59714.490839                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000182                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000182                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.000147                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.000147                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.000147                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.000147                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58352.209588                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 58352.209588                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59506.249597                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 59506.249597                       # average WriteReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        85125                       # average LoadLockedReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        85125                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 59774.444365                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 59774.444365                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 59774.444365                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 59774.444365                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs        27944                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets         1224                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs               406                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets              12                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    68.827586                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          102                       # average number of cycles each access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 59322.972255                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 59322.972255                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 59322.972255                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 59322.972255                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs        26768                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets         1267                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs               424                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets              13                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    63.132075                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    97.461538                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks         1035                       # number of writebacks
-system.cpu.dcache.writebacks::total              1035                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data         2181                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total         2181                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        18227                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        18227                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks         1039                       # number of writebacks
+system.cpu.dcache.writebacks::total              1039                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data         2202                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total         2202                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        18265                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        18265                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            2                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total            2                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data        20408                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total        20408                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data        20408                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total        20408                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data         1771                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total         1771                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data         2841                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total         2841                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data         4612                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total         4612                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data         4612                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total         4612                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    115481540                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total    115481540                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    201937248                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    201937248                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    317418788                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    317418788                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    317418788                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    317418788                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_hits::cpu.data        20467                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total        20467                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data        20467                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total        20467                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data         1782                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total         1782                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data         2837                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         2837                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data         4619                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         4619                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data         4619                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         4619                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    111706789                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total    111706789                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    203137000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    203137000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    314843789                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    314843789                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    314843789                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    314843789                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000020                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000020                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000035                       # mshr miss rate for WriteReq accesses
@@ -1028,14 +990,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000027
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000027                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000027                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000027                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65206.967815                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65206.967815                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71079.636748                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71079.636748                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68824.542064                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 68824.542064                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68824.542064                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 68824.542064                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62686.189113                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62686.189113                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71602.749383                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71602.749383                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68162.760121                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 68162.760121                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68162.760121                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 68162.760121                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 130b228281b659f48cc8e046df613c0ef2cbba2c..55140cd2813e5ad09f993cf658ab1b9ccf3db0fd 100644 (file)
@@ -1,69 +1,69 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.631518                       # Number of seconds simulated
-sim_ticks                                631518097500                       # Number of ticks simulated
-final_tick                               631518097500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.629599                       # Number of seconds simulated
+sim_ticks                                629599373500                       # Number of ticks simulated
+final_tick                               629599373500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 171044                       # Simulator instruction rate (inst/s)
-host_op_rate                                   171044                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               59250964                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 240608                       # Number of bytes of host memory used
-host_seconds                                 10658.36                       # Real time elapsed on the host
+host_inst_rate                                 142688                       # Simulator instruction rate (inst/s)
+host_op_rate                                   142688                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               49278187                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 277460                       # Number of bytes of host memory used
+host_seconds                                 12776.43                       # Real time elapsed on the host
 sim_insts                                  1823043370                       # Number of instructions simulated
 sim_ops                                    1823043370                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            176128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          30295488                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             30471616                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       176128                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          176128                       # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu.inst            176768                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          30295936                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             30472704                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       176768                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          176768                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::writebacks      4282112                       # Number of bytes written to this memory
 system.physmem.bytes_written::total           4282112                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               2752                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             473367                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                476119                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst               2762                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             473374                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                476136                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks           66908                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                66908                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               278896                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             47972478                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                48251374                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          278896                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             278896                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           6780664                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                6780664                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           6780664                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              278896                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            47972478                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               55032038                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        476119                       # Number of read requests accepted
+system.physmem.bw_read::cpu.inst               280763                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             48119387                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                48400150                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          280763                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             280763                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           6801328                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                6801328                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           6801328                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              280763                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            48119387                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               55201478                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        476136                       # Number of read requests accepted
 system.physmem.writeReqs                        66908                       # Number of write requests accepted
-system.physmem.readBursts                      476119                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                      476136                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                      66908                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 30465984                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      5632                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   4281664                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  30471616                       # Total read bytes from the system interface side
+system.physmem.bytesReadDRAM                 30452800                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     19904                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   4280256                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  30472704                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                4282112                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                       88                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.servicedByWrQ                      311                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               29449                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               29798                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               29850                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               29793                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               29695                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               29771                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               29867                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               29856                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               29771                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               29894                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              29844                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              29915                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              29793                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              29587                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              29511                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              29637                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               29443                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               29785                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               29834                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               29781                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               29679                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               29744                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               29853                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               29847                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               29759                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               29871                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              29836                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              29910                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              29783                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              29571                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              29499                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              29630                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                4125                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                4164                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                4223                       # Per bank write bursts
@@ -74,7 +74,7 @@ system.physmem.perBankWrBursts::6                4262                       # Pe
 system.physmem.perBankWrBursts::7                4226                       # Per bank write bursts
 system.physmem.perBankWrBursts::8                4233                       # Per bank write bursts
 system.physmem.perBankWrBursts::9                4334                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               4241                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               4219                       # Per bank write bursts
 system.physmem.perBankWrBursts::11               4241                       # Per bank write bursts
 system.physmem.perBankWrBursts::12               4098                       # Per bank write bursts
 system.physmem.perBankWrBursts::13               4100                       # Per bank write bursts
@@ -82,14 +82,14 @@ system.physmem.perBankWrBursts::14               4096                       # Pe
 system.physmem.perBankWrBursts::15               4157                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    631518039500                       # Total gap between requests
+system.physmem.totGap                    629599315500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  476119                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  476136                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -97,11 +97,11 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                  66908                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    408579                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     66870                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       429                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       136                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        15                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                    405282                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     66881                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      3493                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       148                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        19                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -129,223 +129,175 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                      2992                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                      2992                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                      2992                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                      2992                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                      2992                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                      2992                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                      2992                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                      2991                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                      2991                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                      2991                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                     2992                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                     3005                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                     2994                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                     3962                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                     3023                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2994                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     2995                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     2994                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     3015                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     2993                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     2991                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     3033                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       182335                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      190.554573                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     126.681752                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     408.631079                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64             68422     37.53%     37.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128            48844     26.79%     64.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192            37964     20.82%     85.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256            20159     11.06%     96.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320              264      0.14%     96.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384              246      0.13%     96.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448              141      0.08%     96.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512              184      0.10%     96.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576              113      0.06%     96.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640              137      0.08%     96.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704               96      0.05%     96.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768              186      0.10%     96.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832               81      0.04%     96.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896              159      0.09%     97.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960              151      0.08%     97.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024             133      0.07%     97.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088             108      0.06%     97.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152             148      0.08%     97.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216             143      0.08%     97.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280              80      0.04%     97.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344             131      0.07%     97.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408            1760      0.97%     98.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472            1531      0.84%     99.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536              10      0.01%     99.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600              19      0.01%     99.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664              18      0.01%     99.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1728               8      0.00%     99.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1792              14      0.01%     99.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856              14      0.01%     99.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1920              13      0.01%     99.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984              14      0.01%     99.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2048               6      0.00%     99.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112              10      0.01%     99.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2176              10      0.01%     99.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2240              20      0.01%     99.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2304              12      0.01%     99.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2368              11      0.01%     99.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2432              18      0.01%     99.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2496              13      0.01%     99.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2560              12      0.01%     99.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2624              17      0.01%     99.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2688              12      0.01%     99.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2752              11      0.01%     99.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2816              14      0.01%     99.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2880              18      0.01%     99.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2944              12      0.01%     99.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3008              10      0.01%     99.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3072              14      0.01%     99.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3136              17      0.01%     99.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3200              14      0.01%     99.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3264              13      0.01%     99.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3328               6      0.00%     99.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3392              12      0.01%     99.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3456               9      0.00%     99.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3520               8      0.00%     99.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3584              11      0.01%     99.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3648              18      0.01%     99.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3712               9      0.00%     99.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3776              16      0.01%     99.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3840              12      0.01%     99.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3904              17      0.01%     99.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3968              14      0.01%     99.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4032              15      0.01%     99.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4096               5      0.00%     99.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4160              16      0.01%     99.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4224              14      0.01%     99.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4288              17      0.01%     99.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4352              13      0.01%     99.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4416              15      0.01%     99.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4480              11      0.01%     99.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4544              18      0.01%     99.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4608              12      0.01%     99.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4672               8      0.00%     99.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4736               9      0.00%     99.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4800              12      0.01%     99.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4864               6      0.00%     99.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4928              11      0.01%     99.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4992              11      0.01%     99.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5056              15      0.01%     99.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5120              12      0.01%     99.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5184              12      0.01%     99.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5248              11      0.01%     99.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5312              16      0.01%     99.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5376              12      0.01%     99.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5440              11      0.01%     99.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5504              13      0.01%     99.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5568              16      0.01%     99.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5632              12      0.01%     99.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5696              12      0.01%     99.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5760              17      0.01%     99.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5824              10      0.01%     99.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5888              11      0.01%     99.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5952              22      0.01%     99.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6016              11      0.01%     99.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6080               8      0.00%     99.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6144              12      0.01%     99.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6208              26      0.01%     99.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6272              26      0.01%     99.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6336              39      0.02%     99.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6400              37      0.02%     99.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6464               7      0.00%     99.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6528               7      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6592               6      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6656               3      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6720               7      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6784               8      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6848              54      0.03%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6912               1      0.00%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8128               1      0.00%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         182335                       # Bytes accessed per row activation
-system.physmem.totQLat                     2888040000                       # Total ticks spent queuing
-system.physmem.totMemAccLat               14116017500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2380155000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                  8847822500                       # Total ticks spent accessing banks
-system.physmem.avgQLat                        6066.92                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    18586.65                       # Average bank access latency per DRAM burst
+system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      959                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      960                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     2490                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     4004                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     4022                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     4041                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     4041                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     4042                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     4043                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     4046                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     4182                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     4155                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     4085                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     4086                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     4055                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     4061                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     4041                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     4044                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     1513                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       22                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        21634                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      530.927244                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     283.070424                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     451.227629                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127           7470     34.53%     34.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         2793     12.91%     47.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383          292      1.35%     48.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511          662      3.06%     51.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639          618      2.86%     54.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          184      0.85%     55.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          105      0.49%     56.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           67      0.31%     56.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         9443     43.65%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          21634                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          4040                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean       114.953218                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       36.941709                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     1121.982719                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           4021     99.53%     99.53% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::10240-12287            1      0.02%     99.55% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::12288-14335            6      0.15%     99.70% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::14336-16383           11      0.27%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::32768-34815            1      0.02%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            4040                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          4040                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.554208                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.524474                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.020237                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               3080     76.24%     76.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                645     15.97%     92.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                312      7.72%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                  2      0.05%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                  1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            4040                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     3865744500                       # Total ticks spent queuing
+system.physmem.totMemAccLat               15098494500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2379125000                       # Total ticks spent in databus transfers
+system.physmem.totBankLat                  8853625000                       # Total ticks spent accessing banks
+system.physmem.avgQLat                        8124.30                       # Average queueing delay per DRAM burst
+system.physmem.avgBankLat                    18606.89                       # Average bank access latency per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29653.57                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          48.24                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           6.78                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       48.25                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        6.78                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  31731.19                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          48.37                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           6.80                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       48.40                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        6.80                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.43                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.38                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.05                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         0.02                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        10.28                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     310714                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     49883                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   65.27                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  74.55                       # Row buffer hit rate for writes
-system.physmem.avgGap                      1162958.82                       # Average gap between requests
-system.physmem.pageHitRate                      66.42                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent              25.73                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                     55031937                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq              409266                       # Transaction distribution
-system.membus.trans_dist::ReadResp             409265                       # Transaction distribution
+system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        24.48                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     304858                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     50638                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   64.07                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  75.68                       # Row buffer hit rate for writes
+system.physmem.avgGap                      1159389.14                       # Average gap between requests
+system.physmem.pageHitRate                      65.50                       # Row buffer hit rate, read and write combined
+system.physmem.prechargeAllPercent              25.10                       # Percentage of time for which DRAM has all the banks in precharge state
+system.membus.throughput                     55201376                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq              409283                       # Transaction distribution
+system.membus.trans_dist::ReadResp             409282                       # Transaction distribution
 system.membus.trans_dist::Writeback             66908                       # Transaction distribution
 system.membus.trans_dist::ReadExReq             66853                       # Transaction distribution
 system.membus.trans_dist::ReadExResp            66853                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1019145                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1019145                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     34753664                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            34753664                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus               34753664                       # Total data (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1019179                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1019179                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     34754752                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total            34754752                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               34754752                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy          1230652000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy          1216217500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         4488013500                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         4476344750                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.7                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups               388926557                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         255987580                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          25808786                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            317451636                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               258383726                       # Number of BTB hits
+system.cpu.branchPred.lookups               388794194                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         256437181                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          25515612                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            316966671                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               257889505                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             81.393100                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                57269217                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect               6785                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             81.361710                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                56977055                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect               6765                       # Number of incorrect RAS predictions.
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    522276153                       # DTB read hits
-system.cpu.dtb.read_misses                     591029                       # DTB read misses
+system.cpu.dtb.read_hits                    520530320                       # DTB read hits
+system.cpu.dtb.read_misses                     596868                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                522867182                       # DTB read accesses
-system.cpu.dtb.write_hits                   283024283                       # DTB write hits
-system.cpu.dtb.write_misses                     50282                       # DTB write misses
+system.cpu.dtb.read_accesses                521127188                       # DTB read accesses
+system.cpu.dtb.write_hits                   282735636                       # DTB write hits
+system.cpu.dtb.write_misses                     50248                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses               283074565                       # DTB write accesses
-system.cpu.dtb.data_hits                    805300436                       # DTB hits
-system.cpu.dtb.data_misses                     641311                       # DTB misses
+system.cpu.dtb.write_accesses               282785884                       # DTB write accesses
+system.cpu.dtb.data_hits                    803265956                       # DTB hits
+system.cpu.dtb.data_misses                     647116                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                805941747                       # DTB accesses
-system.cpu.itb.fetch_hits                   394923336                       # ITB hits
-system.cpu.itb.fetch_misses                       673                       # ITB misses
+system.cpu.dtb.data_accesses                803913072                       # DTB accesses
+system.cpu.itb.fetch_hits                   392575649                       # ITB hits
+system.cpu.itb.fetch_misses                       637                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses               394924009                       # ITB accesses
+system.cpu.itb.fetch_accesses               392576286                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -359,238 +311,238 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   39                       # Number of system calls
-system.cpu.numCycles                       1263036196                       # number of cpu cycles simulated
+system.cpu.numCycles                       1259198748                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          410109214                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     3275361918                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   388926557                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          315652943                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     630278695                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles               157942220                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles               76359250                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                  149                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          7183                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles           36                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 394923336                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes              11250823                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples         1248398019                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.623652                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.139094                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          407695740                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     3264617465                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   388794194                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          314866560                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     628012855                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles               156754099                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles               76226521                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                  146                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles          6801                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles           25                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 392575649                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes              11023705                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples         1242691149                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.627055                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.139887                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                618119324     49.51%     49.51% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 57470502      4.60%     54.12% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 43321703      3.47%     57.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 71848580      5.76%     63.34% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                129169735     10.35%     73.69% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 46220345      3.70%     77.39% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 41223036      3.30%     80.69% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  7614963      0.61%     81.30% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                233409831     18.70%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                614678294     49.46%     49.46% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 57194010      4.60%     54.07% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 43037577      3.46%     57.53% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 71548664      5.76%     63.29% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                128942698     10.38%     73.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 45555972      3.67%     77.33% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 41222741      3.32%     80.65% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  8274333      0.67%     81.31% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                232236860     18.69%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1248398019                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.307930                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.593245                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                438388192                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              62722156                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 606598506                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               9057712                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles              131631453                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             31714965                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 12425                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             3194311917                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                 46335                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles              131631453                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                467678494                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                27888696                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          27235                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 586017174                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              35154967                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             3095577926                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                   161                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                  15278                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents              28853292                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands          2054701913                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            3579840200                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       3494452830                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups          85387369                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total           1242691149                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.308763                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.592615                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                436055809                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              62292865                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 604244409                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               9361042                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles              130737024                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             31725769                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 12419                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             3186787270                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                 46304                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles              130737024                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                465340122                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                27154826                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          26997                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 583972819                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              35459361                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             3088232608                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                   174                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                  15483                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents              29158265                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands          2049406757                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            3572462908                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       3487065334                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups          85397573                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps            1384969070                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                669732843                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               4230                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts             93                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 109697167                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            743928173                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           351370571                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          69056444                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          8824928                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 2623617019                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                  88                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                2160251371                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued          17943532                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       800506398                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    726504541                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved             49                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples    1248398019                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.730419                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.803325                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                664437687                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               4235                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts             98                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 110031896                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            740965992                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           350476523                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          68460641                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          8808840                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 2617422170                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                  92                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                2156741664                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued          17943359                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       794308745                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    722892982                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             53                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    1242691149                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.735541                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.803084                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           451794387     36.19%     36.19% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           196881068     15.77%     51.96% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           251357257     20.13%     72.10% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           120660419      9.67%     81.76% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4           104720933      8.39%     90.15% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            79314003      6.35%     96.50% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            24236778      1.94%     98.44% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7            17665275      1.42%     99.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             1767899      0.14%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           447799861     36.03%     36.03% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           195733301     15.75%     51.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           250780419     20.18%     71.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           120973704      9.73%     81.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4           105324665      8.48%     90.18% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            78133504      6.29%     96.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            24822476      2.00%     98.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7            17360375      1.40%     99.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             1762844      0.14%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      1248398019                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1242691149                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 1146213      3.11%      3.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      3.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      3.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      3.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      3.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      3.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      3.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      3.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      3.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      3.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      3.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      3.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      3.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      3.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      3.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      3.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      3.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      3.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      3.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      3.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      3.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      3.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      3.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      3.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      3.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      3.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      3.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      3.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      3.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               25664248     69.68%     72.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite              10022787     27.21%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 1146236      3.14%      3.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      3.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      3.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      3.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      3.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      3.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      3.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      3.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      3.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      3.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      3.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      3.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      3.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      3.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      3.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      3.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      3.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      3.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      3.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      3.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      3.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      3.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      3.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      3.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      3.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      3.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      3.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      3.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      3.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               25360136     69.42%     72.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite              10022546     27.44%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass              2752      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1234386709     57.14%     57.14% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                17098      0.00%     57.14% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     57.14% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd            27851280      1.29%     58.43% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp             8254692      0.38%     58.81% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt             7204649      0.33%     59.15% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  4      0.00%     59.15% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     59.15% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     59.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     59.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     59.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     59.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     59.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     59.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     59.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     59.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     59.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     59.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     59.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     59.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     59.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     59.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     59.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     59.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     59.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     59.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     59.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     59.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     59.15% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            589426190     27.29%     86.43% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           293107997     13.57%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1232941102     57.17%     57.17% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                17091      0.00%     57.17% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     57.17% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd            27851332      1.29%     58.46% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp             8254696      0.38%     58.84% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt             7204650      0.33%     59.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  4      0.00%     59.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     59.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     59.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     59.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     59.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     59.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     59.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     59.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     59.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     59.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     59.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     59.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     59.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     59.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     59.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     59.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     59.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     59.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     59.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     59.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     59.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     59.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     59.18% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            587650943     27.25%     86.42% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           292819094     13.58%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             2160251371                       # Type of FU issued
-system.cpu.iq.rate                           1.710364                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    36833248                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.017050                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         5472576321                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        3336085108                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1990052081                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads           151101220                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes           88112403                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses     73609796                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             2119632115                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                77449752                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         62130294                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             2156741664                       # Type of FU issued
+system.cpu.iq.rate                           1.712789                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    36528918                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.016937                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         5459545573                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        3323652243                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1987168817                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads           151101181                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes           88152162                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses     73609871                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             2115818130                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                77449700                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         62140575                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    232858147                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        12904                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        76517                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores    140575675                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads    229895966                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        17367                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        75928                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores    139681627                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads         4420                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          2986                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads         4415                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          2851                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles              131631453                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                13854870                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                540713                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          2987064964                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            734565                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             743928173                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            351370571                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                 88                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 134613                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles              130737024                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                13158740                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                531547                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          2980853453                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            734148                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             740965992                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            350476523                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                 92                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 133073                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewLSQFullEvents                  1496                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          76517                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect       25801220                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect        30372                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             25831592                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            2066130188                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             522867337                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          94121183                       # Number of squashed instructions skipped in execute
+system.cpu.iew.memOrderViolationEvents          75928                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect       25509079                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect        28871                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             25537950                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            2062960594                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             521127327                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          93781070                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                     363447857                       # number of nop insts executed
-system.cpu.iew.exec_refs                    805942372                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                277625839                       # Number of branches executed
-system.cpu.iew.exec_stores                  283075035                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.635844                       # Inst execution rate
-system.cpu.iew.wb_sent                     2066015513                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    2063661877                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1180966911                       # num instructions producing a value
-system.cpu.iew.wb_consumers                1753315239                       # num instructions consuming a value
+system.cpu.iew.exec_nop                     363431191                       # number of nop insts executed
+system.cpu.iew.exec_refs                    803913709                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                277349504                       # Number of branches executed
+system.cpu.iew.exec_stores                  282786382                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.638312                       # Inst execution rate
+system.cpu.iew.wb_sent                     2062843616                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    2060778688                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1180081311                       # num instructions producing a value
+system.cpu.iew.wb_consumers                1751769057                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.633890                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.673562                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.636579                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.673651                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts       961121274                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       954910834                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              39                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts          25796748                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples   1116766566                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.798932                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.506928                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts          25503576                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples   1111954125                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.806718                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.513025                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    497624741     44.56%     44.56% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    228755331     20.48%     65.04% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2    119853188     10.73%     75.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     58815833      5.27%     81.04% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     50567042      4.53%     85.57% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     24161277      2.16%     87.73% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6     19140455      1.71%     89.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     16628477      1.49%     90.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8    101220222      9.06%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    493953799     44.42%     44.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    227598258     20.47%     64.89% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2    120157352     10.81%     75.70% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     59117436      5.32%     81.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     49692095      4.47%     85.48% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     24169379      2.17%     87.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     18838880      1.69%     89.35% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     16341629      1.47%     90.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8    102085297      9.18%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total   1116766566                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total   1111954125                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts           2008987604                       # Number of instructions committed
 system.cpu.commit.committedOps             2008987604                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -601,229 +553,229 @@ system.cpu.commit.branches                  266706457                       # Nu
 system.cpu.commit.fp_insts                   71824891                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                1778941351                       # Number of committed integer instructions.
 system.cpu.commit.function_calls             39955347                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events             101220222                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events             102085297                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   3980018812                       # The number of ROB reads
-system.cpu.rob.rob_writes                  6071851301                       # The number of ROB writes
-system.cpu.timesIdled                          346634                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        14638177                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                   3968130856                       # The number of ROB reads
+system.cpu.rob.rob_writes                  6058536012                       # The number of ROB writes
+system.cpu.timesIdled                          350219                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        16507599                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                  1823043370                       # Number of Instructions Simulated
 system.cpu.committedOps                    1823043370                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total            1823043370                       # Number of Instructions Simulated
-system.cpu.cpi                               0.692817                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.692817                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.443382                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.443382                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               2627972093                       # number of integer regfile reads
-system.cpu.int_regfile_writes              1496658985                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                  78811105                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                 52661052                       # number of floating regfile writes
+system.cpu.cpi                               0.690712                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.690712                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.447780                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.447780                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               2624503768                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1494046892                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                  78811207                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                 52661075                       # number of floating regfile writes
 system.cpu.misc_regfile_reads                       1                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput               165988542                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq        1470277                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       1470276                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback        95971                       # Transaction distribution
+system.cpu.toL2Bus.throughput               166495312                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq        1470280                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       1470279                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback        95977                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq        71640                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp        71640                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        20049                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3159755                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           3179804                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       641536                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    104183232                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      104824768                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus         104824768                       # Total data (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        20109                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3159707                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           3179816                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       643456                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    104181888                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      104825344                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         104825344                       # Total data (bytes)
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy      914915000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.occupancy      914925500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      15531000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      15572000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2359590250                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    2358250250                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.4                       # Layer utilization (%)
-system.cpu.icache.tags.replacements              8311                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1658.001589                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           394910393                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             10024                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          39396.487729                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements              8345                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1652.999012                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           392562699                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             10054                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          39045.424607                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1658.001589                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.809571                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.809571                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1713                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           77                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           68                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst  1652.999012                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.807128                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.807128                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1709                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           84                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           71                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2            1                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1567                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.836426                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         789856696                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        789856696                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    394910393                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       394910393                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     394910393                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        394910393                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    394910393                       # number of overall hits
-system.cpu.icache.overall_hits::total       394910393                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        12943                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         12943                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        12943                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          12943                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        12943                       # number of overall misses
-system.cpu.icache.overall_misses::total         12943                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    383664999                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    383664999                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    383664999                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    383664999                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    383664999                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    383664999                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    394923336                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    394923336                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    394923336                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    394923336                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    394923336                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    394923336                       # number of overall (read+write) accesses
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1553                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.834473                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         785161352                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        785161352                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    392562699                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       392562699                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     392562699                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        392562699                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    392562699                       # number of overall hits
+system.cpu.icache.overall_hits::total       392562699                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        12950                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         12950                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        12950                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          12950                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        12950                       # number of overall misses
+system.cpu.icache.overall_misses::total         12950                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    384762999                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    384762999                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    384762999                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    384762999                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    384762999                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    384762999                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    392575649                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    392575649                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    392575649                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    392575649                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    392575649                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    392575649                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000033                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000033                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000033                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000033                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000033                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000033                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29642.663911                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 29642.663911                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 29642.663911                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 29642.663911                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 29642.663911                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 29642.663911                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          707                       # number of cycles access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29711.428494                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 29711.428494                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 29711.428494                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 29711.428494                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 29711.428494                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 29711.428494                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          621                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                13                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    54.384615                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    47.769231                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2918                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         2918                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         2918                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         2918                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         2918                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         2918                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        10025                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        10025                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        10025                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        10025                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        10025                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        10025                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    281678249                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    281678249                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    281678249                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    281678249                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    281678249                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    281678249                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000025                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000025                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000025                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000025                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000025                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000025                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28097.580948                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28097.580948                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28097.580948                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 28097.580948                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28097.580948                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 28097.580948                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2895                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         2895                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         2895                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         2895                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         2895                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         2895                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        10055                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        10055                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        10055                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        10055                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        10055                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        10055                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    283775749                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    283775749                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    283775749                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    283775749                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    283775749                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    283775749                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000026                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000026                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000026                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000026                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000026                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000026                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28222.351964                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28222.351964                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28222.351964                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 28222.351964                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28222.351964                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 28222.351964                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           443340                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        32689.012035                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1090033                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           476076                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             2.289620                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           443357                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        32688.486835                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            1090024                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           476094                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             2.289514                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  1332.840421                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    35.208896                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 31320.962718                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.040675                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks  1336.366869                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    35.201228                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 31316.918737                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.040783                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001074                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.955840                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.997589                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        32736                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          156                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          188                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.955717                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.997573                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        32737                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          163                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          198                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::2          505                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5021                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        26866                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.999023                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         13650820                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        13650820                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst         7273                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data      1053738                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1061011                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks        95971                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total        95971                       # number of Writeback hits
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5022                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        26849                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.999054                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         13650910                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        13650910                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst         7293                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data      1053704                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        1060997                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks        95977                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total        95977                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data         4787                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total         4787                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         7273                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      1058525                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         1065798                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         7273                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      1058525                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        1065798                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         2752                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data       406514                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total       409266                       # number of ReadReq misses
+system.cpu.l2cache.demand_hits::cpu.inst         7293                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      1058491                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         1065784                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         7293                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      1058491                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        1065784                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         2762                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data       406521                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total       409283                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data        66853                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total        66853                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         2752                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       473367                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        476119                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         2752                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       473367                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       476119                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    198912250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data  29323124000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total  29522036250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   5227072250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   5227072250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    198912250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  34550196250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  34749108500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    198912250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  34550196250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  34749108500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst        10025                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      1460252                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      1470277                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks        95971                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total        95971                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.demand_misses::cpu.inst         2762                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       473374                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        476136                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         2762                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       473374                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       476136                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    200785000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data  29850948750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total  30051733750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   5675940500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   5675940500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    200785000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  35526889250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  35727674250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    200785000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  35526889250                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  35727674250                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst        10055                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      1460225                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      1470280                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks        95977                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total        95977                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data        71640                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total        71640                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        10025                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      1531892                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      1541917                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        10025                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      1531892                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      1541917                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.274514                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.278386                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.278360                       # miss rate for ReadReq accesses
+system.cpu.l2cache.demand_accesses::cpu.inst        10055                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      1531865                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      1541920                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        10055                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      1531865                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      1541920                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.274689                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.278396                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.278371                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.933180                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total     0.933180                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.274514                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.309008                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.308784                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.274514                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.309008                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.308784                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72279.160610                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72133.122106                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 72134.104103                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78187.549549                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78187.549549                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72279.160610                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72988.180946                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 72984.082761                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72279.160610                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72988.180946                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 72984.082761                       # average overall miss latency
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.274689                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.309018                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.308794                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.274689                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.309018                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.308794                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72695.510500                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73430.274820                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 73425.316346                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 84901.806950                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 84901.806950                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72695.510500                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75050.360286                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 75036.700123                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72695.510500                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75050.360286                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 75036.700123                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -834,187 +786,181 @@ system.cpu.l2cache.fast_writes                      0                       # nu
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        66908                       # number of writebacks
 system.cpu.l2cache.writebacks::total            66908                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2752                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       406514                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total       409266                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2762                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       406521                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total       409283                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66853                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total        66853                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         2752                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       473367                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       476119                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         2752                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       473367                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       476119                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    164196250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  24183867000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  24348063250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4422430250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4422430250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    164196250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  28606297250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  28770493500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    164196250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  28606297250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  28770493500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.274514                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.278386                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.278360                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         2762                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       473374                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       476136                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         2762                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       473374                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       476136                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    165956500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  24727472750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  24893429250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4868551500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4868551500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    165956500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  29596024250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  29761980750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    165956500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  29596024250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  29761980750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.274689                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.278396                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.278371                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.933180                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.933180                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.274514                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.309008                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.308784                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.274514                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.309008                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.308784                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59664.335029                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59490.858863                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59492.025358                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66151.560139                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66151.560139                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59664.335029                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60431.540961                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60427.106459                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59664.335029                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60431.540961                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60427.106459                       # average overall mshr miss latency
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.274689                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.309018                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.308794                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.274689                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.309018                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.308794                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60085.626358                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60827.048910                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60822.045504                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72824.727387                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72824.727387                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60085.626358                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62521.440235                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62507.310411                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60085.626358                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62521.440235                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62507.310411                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements           1527796                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4094.588575                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           667945835                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1531892                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            436.026714                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         408904250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4094.588575                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.replacements           1527769                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4094.584887                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           666211737                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1531865                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            434.902382                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         409920250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4094.584887                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999655                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999655                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           86                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          284                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          969                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           84                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          290                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          967                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3         2365                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4          392                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4          390                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1343398986                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1343398986                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    458212871                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       458212871                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    209732941                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      209732941                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data           23                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total           23                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data     667945812                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        667945812                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    667945812                       # number of overall hits
-system.cpu.dcache.overall_hits::total       667945812                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1925756                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1925756                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1061955                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1061955                       # number of WriteReq misses
+system.cpu.dcache.tags.tag_accesses        1339886951                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1339886951                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    456456827                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       456456827                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    209754882                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      209754882                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data           28                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total           28                       # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits::cpu.data     666211709                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        666211709                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    666211709                       # number of overall hits
+system.cpu.dcache.overall_hits::total       666211709                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1925791                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1925791                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1040014                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1040014                       # number of WriteReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            1                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            1                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      2987711                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2987711                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      2987711                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2987711                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  77391157750                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  77391157750                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  46191876602                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  46191876602                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        78000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total        78000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 123583034352                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 123583034352                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 123583034352                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 123583034352                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    460138627                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    460138627                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data      2965805                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2965805                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2965805                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2965805                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  77884724250                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  77884724250                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  53548786128                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  53548786128                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        73000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total        73000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 131433510378                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 131433510378                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 131433510378                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 131433510378                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    458382618                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    458382618                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    210794896                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    210794896                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data           24                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total           24                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    670933523                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    670933523                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    670933523                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    670933523                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.004185                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.004185                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.005038                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.005038                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.041667                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.041667                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.004453                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.004453                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.004453                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.004453                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40187.416137                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 40187.416137                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43497.018802                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 43497.018802                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        78000                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        78000                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 41363.784634                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 41363.784634                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 41363.784634                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 41363.784634                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs        17901                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets          132                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs               338                       # number of cycles access was blocked
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data           29                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total           29                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    669177514                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    669177514                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    669177514                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    669177514                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.004201                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.004201                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.004934                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.004934                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.034483                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.034483                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.004432                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.004432                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.004432                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.004432                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40442.978625                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 40442.978625                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51488.524316                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 51488.524316                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        73000                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        73000                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 44316.302110                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 44316.302110                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 44316.302110                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 44316.302110                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs        18203                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets          134                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs               374                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               1                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    52.961538                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          132                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    48.671123                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          134                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks        95971                       # number of writebacks
-system.cpu.dcache.writebacks::total             95971                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       465505                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       465505                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       990315                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       990315                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1455820                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1455820                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1455820                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1455820                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1460251                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1460251                       # number of ReadReq MSHR misses
+system.cpu.dcache.writebacks::writebacks        95977                       # number of writebacks
+system.cpu.dcache.writebacks::total             95977                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       465566                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       465566                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       968374                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       968374                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            1                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total            1                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      1433940                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1433940                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1433940                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1433940                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1460225                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1460225                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data        71640                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total        71640                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data            1                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total            1                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1531891                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1531891                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1531891                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1531891                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  41321289000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  41321289000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5347166250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   5347166250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data        76000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total        76000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  46668455250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  46668455250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  46668455250                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  46668455250                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.003174                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.003174                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1531865                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1531865                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1531865                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1531865                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  41848820250                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  41848820250                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5798224000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   5798224000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  47647044250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  47647044250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  47647044250                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  47647044250                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.003186                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.003186                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000340                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000340                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.041667                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.041667                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002283                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.002283                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002283                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.002283                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28297.387915                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28297.387915                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74639.394891                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74639.394891                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data        76000                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total        76000                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30464.605674                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 30464.605674                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30464.605674                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 30464.605674                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002289                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.002289                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002289                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.002289                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28659.158863                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28659.158863                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80935.566723                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80935.566723                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31103.944701                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 31103.944701                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31103.944701                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 31103.944701                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index b6f8c26dcef8bdbd53465dc71ea187d9aa5c0978..067d517cb5c6ab8261348839985f43b9592ed07c 100644 (file)
@@ -1,95 +1,95 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.629535                       # Number of seconds simulated
-sim_ticks                                629535413500                       # Number of ticks simulated
-final_tick                               629535413500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.629657                       # Number of seconds simulated
+sim_ticks                                629657386500                       # Number of ticks simulated
+final_tick                               629657386500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 106173                       # Simulator instruction rate (inst/s)
-host_op_rate                                   144593                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               48281629                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 278772                       # Number of bytes of host memory used
-host_seconds                                 13038.82                       # Real time elapsed on the host
+host_inst_rate                                  85982                       # Simulator instruction rate (inst/s)
+host_op_rate                                   117096                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               39107572                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 322024                       # Number of bytes of host memory used
+host_seconds                                 16100.65                       # Real time elapsed on the host
 sim_insts                                  1384370590                       # Number of instructions simulated
 sim_ops                                    1885325342                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            155136                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          30242496                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             30397632                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       155136                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          155136                       # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu.inst            155392                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          30242880                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             30398272                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       155392                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          155392                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::writebacks      4230272                       # Number of bytes written to this memory
 system.physmem.bytes_written::total           4230272                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               2424                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             472539                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                474963                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst               2428                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             472545                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                474973                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks           66098                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                66098                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               246429                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             48039388                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                48285817                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          246429                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             246429                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           6719673                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                6719673                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           6719673                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              246429                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            48039388                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               55005490                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        474963                       # Number of read requests accepted
+system.physmem.bw_read::cpu.inst               246788                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             48030692                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                48277480                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          246788                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             246788                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           6718371                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                6718371                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           6718371                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              246788                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            48030692                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               54995851                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        474973                       # Number of read requests accepted
 system.physmem.writeReqs                        66098                       # Number of write requests accepted
-system.physmem.readBursts                      474963                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                      474973                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                      66098                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 30390400                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      7232                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   4229888                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  30397632                       # Total read bytes from the system interface side
+system.physmem.bytesReadDRAM                 30370688                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     27584                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   4228672                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  30398272                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                4230272                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      113                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.servicedByWrQ                      431                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           4262                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               29871                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               29675                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               29749                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               29712                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               29816                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               29834                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               29642                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               29444                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               29480                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               29489                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              29547                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              29649                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              29701                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              29813                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              29629                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              29799                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs           4296                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               29858                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               29659                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               29728                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               29690                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               29781                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               29808                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               29619                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               29428                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               29461                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               29473                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              29524                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              29641                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              29683                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              29785                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              29611                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              29793                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                4174                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                4102                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                4138                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                4148                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                4226                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                4224                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                4173                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                4096                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                4096                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                4100                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                4137                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                4146                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                4223                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                4223                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                4171                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                4094                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                4094                       # Per bank write bursts
 system.physmem.perBankWrBursts::9                4093                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               4095                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               4093                       # Per bank write bursts
 system.physmem.perBankWrBursts::11               4097                       # Per bank write bursts
 system.physmem.perBankWrBursts::12               4098                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               4096                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               4094                       # Per bank write bursts
 system.physmem.perBankWrBursts::14               4096                       # Per bank write bursts
 system.physmem.perBankWrBursts::15               4140                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    629535350500                       # Total gap between requests
+system.physmem.totGap                    629657309500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  474963                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  474973                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -97,11 +97,11 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                  66098                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    407876                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     66617                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       275                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        64                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        16                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                    407581                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     66607                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       273                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        61                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        18                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -129,194 +129,157 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                      3005                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                      3005                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                      3005                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                      3005                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                      3005                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                      3005                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                      3004                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                      3004                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                      3004                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                      3004                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                     3004                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                     3004                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                     3004                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                     3004                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                     3004                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     3004                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     3004                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     3004                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     3004                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     3005                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     3005                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     3006                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       190822                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      181.419082                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     122.160667                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     377.205430                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64             76972     40.34%     40.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128            49989     26.20%     66.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192            37639     19.72%     86.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256            19482     10.21%     96.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320              187      0.10%     96.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384              252      0.13%     96.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448               85      0.04%     96.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512              218      0.11%     96.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576               85      0.04%     96.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640              231      0.12%     97.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704               52      0.03%     97.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768              225      0.12%     97.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832               65      0.03%     97.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896              188      0.10%     97.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960               60      0.03%     97.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024             181      0.09%     97.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088              44      0.02%     97.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152             201      0.11%     97.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216              67      0.04%     97.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280             181      0.09%     97.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344              66      0.03%     97.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408            3167      1.66%     99.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472              20      0.01%     99.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536              13      0.01%     99.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600              12      0.01%     99.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664              12      0.01%     99.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1728              13      0.01%     99.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1792              17      0.01%     99.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856              15      0.01%     99.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1920              15      0.01%     99.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984              19      0.01%     99.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2048              10      0.01%     99.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112              18      0.01%     99.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2176              13      0.01%     99.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2240              11      0.01%     99.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2304              14      0.01%     99.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2368              14      0.01%     99.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2432              15      0.01%     99.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2496              21      0.01%     99.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2560              12      0.01%     99.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2624              17      0.01%     99.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2688              16      0.01%     99.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2752              16      0.01%     99.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2816              13      0.01%     99.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2880              12      0.01%     99.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2944              12      0.01%     99.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3008              14      0.01%     99.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3072               9      0.00%     99.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3136              19      0.01%     99.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3200              10      0.01%     99.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3264              20      0.01%     99.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3328              10      0.01%     99.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3392              16      0.01%     99.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3456              12      0.01%     99.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3520              21      0.01%     99.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3584              13      0.01%     99.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3648              16      0.01%     99.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3712              15      0.01%     99.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3776              18      0.01%     99.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3840               7      0.00%     99.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3904              15      0.01%     99.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3968              17      0.01%     99.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4032              14      0.01%     99.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4096              12      0.01%     99.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4160              28      0.01%     99.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4224              16      0.01%     99.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4288              14      0.01%     99.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4352               7      0.00%     99.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4416              17      0.01%     99.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4480              11      0.01%     99.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4544              14      0.01%     99.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4608              12      0.01%     99.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4672              19      0.01%     99.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4736              10      0.01%     99.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4800              13      0.01%     99.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4864               9      0.00%     99.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4928              17      0.01%     99.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4992               8      0.00%     99.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5056              17      0.01%     99.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5120               7      0.00%     99.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5184               9      0.00%     99.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5248               9      0.00%     99.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5312              13      0.01%     99.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5376              11      0.01%     99.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5440              14      0.01%     99.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5504              12      0.01%     99.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5568              15      0.01%     99.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5632              15      0.01%     99.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5696              31      0.02%     99.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5760              73      0.04%     99.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5824              59      0.03%     99.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5888               4      0.00%     99.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5952               3      0.00%     99.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6016               6      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6080               8      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6144              53      0.03%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6208               4      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6272              19      0.01%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         190822                       # Bytes accessed per row activation
-system.physmem.totQLat                     3804806750                       # Total ticks spent queuing
-system.physmem.totMemAccLat               15248020500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2374250000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                  9068963750                       # Total ticks spent accessing banks
-system.physmem.avgQLat                        8012.65                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    19098.59                       # Average bank access latency per DRAM burst
+system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      941                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      941                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                      965                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     3991                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     3992                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     3994                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     3993                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     4172                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     4867                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     4005                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     5495                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     4100                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     4045                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     4370                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     4016                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     3998                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     4000                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     3993                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      196                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        28167                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      403.324742                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     187.656646                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     439.024801                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          14746     52.35%     52.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         2789      9.90%     62.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383          571      2.03%     64.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511          164      0.58%     64.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           93      0.33%     65.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          524      1.86%     67.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          314      1.11%     68.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           86      0.31%     68.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         8880     31.53%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          28167                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          3992                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        48.707415                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       36.187766                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      506.851977                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           3989     99.92%     99.92% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047            1      0.03%     99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-3071            1      0.03%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::31744-32767            1      0.03%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            3992                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          3992                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.551353                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.521439                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.024563                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               3052     76.45%     76.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                627     15.71%     92.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                310      7.77%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                  1      0.03%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                  1      0.03%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                  1      0.03%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            3992                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     3604221250                       # Total ticks spent queuing
+system.physmem.totMemAccLat               15074013750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2372710000                       # Total ticks spent in databus transfers
+system.physmem.totBankLat                  9097082500                       # Total ticks spent accessing banks
+system.physmem.avgQLat                        7595.16                       # Average queueing delay per DRAM burst
+system.physmem.avgBankLat                    19170.24                       # Average bank access latency per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  32111.24                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          48.27                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  31765.39                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          48.23                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           6.72                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       48.29                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       48.28                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        6.72                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.43                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.38                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.05                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         0.02                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                         6.84                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     300749                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     49371                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   63.34                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  74.69                       # Row buffer hit rate for writes
-system.physmem.avgGap                      1163520.10                       # Average gap between requests
-system.physmem.pageHitRate                      64.72                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent              24.30                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                     55005389                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq              408886                       # Transaction distribution
-system.membus.trans_dist::ReadResp             408885                       # Transaction distribution
+system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        24.85                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     295971                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     49954                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   62.37                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  75.58                       # Row buffer hit rate for writes
+system.physmem.avgGap                      1163724.00                       # Average gap between requests
+system.physmem.pageHitRate                      63.98                       # Row buffer hit rate, read and write combined
+system.physmem.prechargeAllPercent              24.27                       # Percentage of time for which DRAM has all the banks in precharge state
+system.membus.throughput                     54995851                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq              408896                       # Transaction distribution
+system.membus.trans_dist::ReadResp             408896                       # Transaction distribution
 system.membus.trans_dist::Writeback             66098                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             4262                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            4262                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             4296                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            4296                       # Transaction distribution
 system.membus.trans_dist::ReadExReq             66077                       # Transaction distribution
 system.membus.trans_dist::ReadExResp            66077                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1024547                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1024547                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     34627840                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            34627840                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus               34627840                       # Total data (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1024636                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1024636                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     34628544                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total            34628544                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               34628544                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy          1215457500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy          1215525500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         4442862738                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         4444359954                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.7                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups               438247722                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         350864471                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          30620817                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            248480162                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               229339460                       # Number of BTB hits
+system.cpu.branchPred.lookups               438199522                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         350949441                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          30620410                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            248742563                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               229772650                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             92.296889                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                52915671                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect            2805331                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             92.373676                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                52962534                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect            2805242                       # Number of incorrect RAS predictions.
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -402,100 +365,100 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                 1411                       # Number of system calls
-system.cpu.numCycles                       1259070828                       # number of cpu cycles simulated
+system.cpu.numCycles                       1259314774                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          354141020                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     2279761292                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   438247722                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          282255131                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     601258233                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles               157188182                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles              134732573                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                  615                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles         11340                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles          159                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 334734643                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes              11658358                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples         1216659303                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.575913                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.175897                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          354212583                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     2278943291                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   438199522                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          282735184                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     601285341                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles               157201665                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles              134990206                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                  592                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles         11080                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles          114                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 334803997                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes              11648696                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples         1217029612                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.574413                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.174582                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                615445842     50.58%     50.58% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 42369042      3.48%     54.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 95794203      7.87%     61.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 57788183      4.75%     66.69% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 71908380      5.91%     72.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 44699403      3.67%     76.27% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 31096366      2.56%     78.83% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 31485891      2.59%     81.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                226071993     18.58%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                615789102     50.60%     50.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 42212896      3.47%     54.07% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 95956201      7.88%     61.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 57716133      4.74%     66.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 72254915      5.94%     72.63% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 44707595      3.67%     76.30% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 31168110      2.56%     78.86% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 31500430      2.59%     81.45% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                225724230     18.55%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1216659303                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.348072                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.810670                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                405371770                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             106745247                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 560687148                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              17351012                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles              126504126                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             44828011                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 11498                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             3022924000                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                 26519                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles              126504126                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                441422956                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                38086039                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         457739                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 539750713                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              70437730                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             2941757147                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                    93                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                4808697                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents              54385461                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents              740                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands          2930215043                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups           14237570542                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups      12151139431                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups          84006834                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total           1217029612                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.347967                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.809669                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                405265267                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             107157501                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 560735859                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              17352207                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles              126518778                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             44627065                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 11198                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             3022541715                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                 25538                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles              126518778                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                441244328                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                38456610                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         454301                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 539911121                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              70444474                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             2941731616                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                    86                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                4811465                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents              54362751                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents              733                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands          2929353177                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups           14237214542                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups      12151315514                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups          83979009                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps            1993140090                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                937074953                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts              20556                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts          18072                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 179296103                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            971747851                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           485687926                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          36754298                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         38315968                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 2792666387                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded               27976                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                2435151733                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued          13267287                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       894813074                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined   2341267254                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved           6592                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples    1216659303                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.001507                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.873340                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                936213087                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts              20203                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts          17724                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 179723252                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            971631963                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           486198822                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          36723664                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         38677099                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 2793016392                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded               27622                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                2435260833                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued          13305109                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       895166670                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined   2343525890                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           6238                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    1217029612                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.000987                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.873461                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           380682463     31.29%     31.29% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           183043299     15.04%     46.33% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           204121257     16.78%     63.11% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           169552429     13.94%     77.05% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4           132904836     10.92%     87.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            92976040      7.64%     95.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            37964484      3.12%     98.73% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7            12393775      1.02%     99.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             3020720      0.25%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           381057421     31.31%     31.31% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           183026992     15.04%     46.35% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           204041316     16.77%     63.11% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           169676462     13.94%     77.06% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4           132865899     10.92%     87.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            92968001      7.64%     95.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            37978061      3.12%     98.73% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7            12373824      1.02%     99.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             3041636      0.25%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      1216659303                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1217029612                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  714585      0.82%      0.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                  24381      0.03%      0.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  714935      0.82%      0.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                  24383      0.03%      0.84% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.84% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.84% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.84% # attempts to use FU when none available
@@ -523,13 +486,13 @@ system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      0.84% # at
 system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      0.84% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      0.84% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      0.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               55158409     62.92%     63.76% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite              31764976     36.24%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               55166828     62.92%     63.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite              31766374     36.23%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1104245990     45.35%     45.35% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult             11223912      0.46%     45.81% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1104417509     45.35%     45.35% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult             11223990      0.46%     45.81% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     45.81% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   3      0.00%     45.81% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     45.81% # Type of FU issued
@@ -548,93 +511,93 @@ system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     45.81% # Ty
 system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     45.81% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     45.81% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     45.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd         1375289      0.06%     45.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     45.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp         6876479      0.28%     46.15% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt         5502438      0.23%     46.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               1      0.00%     46.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc       23399832      0.96%     47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     47.33% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            840060400     34.50%     81.83% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           442467389     18.17%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd         1375289      0.06%     45.87% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     45.87% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp         6876473      0.28%     46.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt         5501794      0.23%     46.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               1      0.00%     46.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc       23394204      0.96%     47.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     47.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     47.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     47.34% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            839996872     34.49%     81.83% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           442474698     18.17%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             2435151733                       # Type of FU issued
-system.cpu.iq.rate                           1.934086                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    87662351                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.035999                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         6065394864                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        3604907210                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   2250139818                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads           122497543                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes           82667139                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses     56433103                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             2459502901                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                63311183                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         84462690                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             2435260833                       # Type of FU issued
+system.cpu.iq.rate                           1.933798                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    87672520                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.036001                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         6066045738                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        3605651148                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   2250091074                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads           122483169                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes           82625914                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses     56426435                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             2459629474                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                63303879                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         84463938                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    340360670                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         9529                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation      1430281                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores    208692629                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads    340244782                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        10257                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation      1430041                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores    209203525                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            5                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked           365                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked           356                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles              126504126                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                16045638                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               1563592                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          2792706809                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts           1386483                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             971747851                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            485687926                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts              17990                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                1559989                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                  2525                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents        1430281                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect       32383306                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      1525297                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             33908603                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            2359934527                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             794158761                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          75217206                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles              126518778                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                16487163                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               1561706                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          2793056470                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           1389243                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             971631963                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            486198822                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts              17636                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                1558036                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                  2522                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents        1430041                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect       32401956                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      1516006                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             33917962                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            2359922616                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             794093704                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          75338217                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                         12446                       # number of nop insts executed
-system.cpu.iew.exec_refs                   1217435347                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                319532182                       # Number of branches executed
-system.cpu.iew.exec_stores                  423276586                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.874346                       # Inst execution rate
-system.cpu.iew.wb_sent                     2332318600                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    2306572921                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1349155649                       # num instructions producing a value
-system.cpu.iew.wb_consumers                2527421878                       # num instructions consuming a value
+system.cpu.iew.exec_nop                         12456                       # number of nop insts executed
+system.cpu.iew.exec_refs                   1217365234                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                319562430                       # Number of branches executed
+system.cpu.iew.exec_stores                  423271530                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.873974                       # Inst execution rate
+system.cpu.iew.wb_sent                     2332280723                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    2306517509                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1349120960                       # num instructions producing a value
+system.cpu.iew.wb_consumers                2527351065                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.831964                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.533807                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.831566                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.533808                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts       907370579                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       907720231                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls           21384                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts          30609580                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples   1090155177                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.729420                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.397089                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts          30609492                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples   1090510834                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.728856                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.396955                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    449868742     41.27%     41.27% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    288583282     26.47%     67.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     95106533      8.72%     76.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     70222065      6.44%     82.90% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     46473839      4.26%     87.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     22181225      2.03%     89.20% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6     15848509      1.45%     90.66% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     10986576      1.01%     91.66% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     90884406      8.34%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    450229589     41.29%     41.29% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    288600221     26.46%     67.75% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     95089363      8.72%     76.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     70207190      6.44%     82.91% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     46482431      4.26%     87.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     22180112      2.03%     89.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     15844912      1.45%     90.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     10980043      1.01%     91.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     90896973      8.34%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total   1090155177                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total   1090510834                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts           1384381606                       # Number of instructions committed
 system.cpu.commit.committedOps             1885336358                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -645,240 +608,240 @@ system.cpu.commit.branches                  298259106                       # Nu
 system.cpu.commit.fp_insts                   52289415                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                1653698867                       # Number of committed integer instructions.
 system.cpu.commit.function_calls             41577833                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events              90884406                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events              90896973                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   3791959363                       # The number of ROB reads
-system.cpu.rob.rob_writes                  5711929117                       # The number of ROB writes
-system.cpu.timesIdled                          353184                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        42411525                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                   3792652105                       # The number of ROB reads
+system.cpu.rob.rob_writes                  5712643141                       # The number of ROB writes
+system.cpu.timesIdled                          352993                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        42285162                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                  1384370590                       # Number of Instructions Simulated
 system.cpu.committedOps                    1885325342                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total            1384370590                       # Number of Instructions Simulated
-system.cpu.cpi                               0.909490                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.909490                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.099518                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.099518                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads              11767673388                       # number of integer regfile reads
-system.cpu.int_regfile_writes              2220511965                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                  68796181                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                 49544953                       # number of floating regfile writes
-system.cpu.misc_regfile_reads              1678583418                       # number of misc regfile reads
+system.cpu.cpi                               0.909666                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.909666                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.099305                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.099305                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads              11767299799                       # number of integer regfile reads
+system.cpu.int_regfile_writes              2220455487                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                  68795103                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                 49537962                       # number of floating regfile writes
+system.cpu.misc_regfile_reads              1678438007                       # number of misc regfile reads
 system.cpu.misc_regfile_writes               13772902                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput               169029894                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq        1493831                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       1493830                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback        96313                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         4265                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         4265                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq        72518                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp        72518                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        54300                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3178976                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           3233276                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1601152                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    104536256                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      106137408                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus         106137408                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus       272896                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy      929776999                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.throughput               168942873                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq        1493289                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       1493289                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback        96321                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         4299                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp         4299                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq        72517                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp        72517                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        53208                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3179025                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           3232233                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1565120                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    104535936                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      106101056                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         106101056                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus       275072                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy      929534000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      44342246                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      43545495                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2368551488                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    2368755772                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.4                       # Layer utilization (%)
-system.cpu.icache.tags.replacements             23332                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1641.273486                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           334698554                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             25017                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          13378.844546                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements             22771                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1640.597248                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           334768394                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             24455                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          13689.159436                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1641.273486                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.801403                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.801403                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1685                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           64                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           65                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2            2                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1551                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.822754                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         669498564                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        669498564                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    334702534                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       334702534                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     334702534                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        334702534                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    334702534                       # number of overall hits
-system.cpu.icache.overall_hits::total       334702534                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        32107                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         32107                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        32107                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          32107                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        32107                       # number of overall misses
-system.cpu.icache.overall_misses::total         32107                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    545585992                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    545585992                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    545585992                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    545585992                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    545585992                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    545585992                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    334734641                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    334734641                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    334734641                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    334734641                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    334734641                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    334734641                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000096                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000096                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000096                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000096                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000096                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000096                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16992.742766                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 16992.742766                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 16992.742766                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 16992.742766                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 16992.742766                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 16992.742766                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         2092                       # number of cycles access was blocked
+system.cpu.icache.tags.occ_blocks::cpu.inst  1640.597248                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.801073                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.801073                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1684                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           68                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           66                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2            4                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1545                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.822266                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         669636743                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        669636743                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    334772400                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       334772400                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     334772400                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        334772400                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    334772400                       # number of overall hits
+system.cpu.icache.overall_hits::total       334772400                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        31595                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         31595                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        31595                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          31595                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        31595                       # number of overall misses
+system.cpu.icache.overall_misses::total         31595                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    539866742                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    539866742                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    539866742                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    539866742                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    539866742                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    539866742                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    334803995                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    334803995                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    334803995                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    334803995                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    334803995                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    334803995                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000094                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000094                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000094                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000094                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000094                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000094                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17087.094224                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 17087.094224                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 17087.094224                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 17087.094224                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 17087.094224                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 17087.094224                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         1720                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                38                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                34                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    55.052632                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    50.588235                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2825                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         2825                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         2825                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         2825                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         2825                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         2825                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        29282                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        29282                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        29282                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        29282                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        29282                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        29282                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    435718750                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    435718750                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    435718750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    435718750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    435718750                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    435718750                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000087                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000087                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000087                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000087                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000087                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000087                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14880.088450                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14880.088450                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14880.088450                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 14880.088450                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14880.088450                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 14880.088450                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2842                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         2842                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         2842                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         2842                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         2842                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         2842                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        28753                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        28753                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        28753                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        28753                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        28753                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        28753                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    429678502                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    429678502                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    429678502                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    429678502                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    429678502                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    429678502                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000086                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000086                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000086                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000086                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000086                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000086                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14943.779849                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14943.779849                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14943.779849                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 14943.779849                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14943.779849                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 14943.779849                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           442179                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        32678.084712                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1110777                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           474927                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             2.338837                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           442191                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        32677.338993                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            1109910                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           474938                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             2.336958                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  1317.536898                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    51.699719                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 31308.848096                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.040208                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001578                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.955470                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.997256                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        32748                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           99                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_blocks::writebacks  1321.185121                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    50.537350                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 31305.616521                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.040319                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001542                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.955372                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.997233                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        32747                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          106                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          154                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          507                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5020                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        26968                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.999390                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         13848752                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        13848752                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst        22592                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data      1058063                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1080655                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks        96313                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total        96313                       # number of Writeback hits
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          505                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5025                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        26957                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.999359                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         13844482                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        13844482                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst        22025                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data      1058044                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        1080069                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks        96321                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total        96321                       # number of Writeback hits
 system.cpu.l2cache.UpgradeReq_hits::cpu.data            3                       # number of UpgradeReq hits
 system.cpu.l2cache.UpgradeReq_hits::total            3                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data         6441                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total         6441                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        22592                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      1064504                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         1087096                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst        22592                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      1064504                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        1087096                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         2426                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data       406486                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total       408912                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data         4262                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total         4262                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_hits::cpu.data         6440                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total         6440                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst        22025                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      1064484                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         1086509                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst        22025                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      1064484                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        1086509                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         2430                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data       406492                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total       408922                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data         4296                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total         4296                       # number of UpgradeReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data        66077                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total        66077                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         2426                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       472563                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        474989                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         2426                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       472563                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       474989                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    176218750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data  30746506500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total  30922725250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   4757394750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   4757394750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    176218750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  35503901250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  35680120000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    176218750                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  35503901250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  35680120000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst        25018                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      1464549                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      1489567                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks        96313                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total        96313                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data         4265                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total         4265                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data        72518                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total        72518                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        25018                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      1537067                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      1562085                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        25018                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      1537067                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      1562085                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.096970                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.277550                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.274517                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.999297                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.999297                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.911181                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.911181                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.096970                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.307445                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.304074                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.096970                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.307445                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.304074                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72637.572135                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75639.767421                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 75621.955947                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71997.741272                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71997.741272                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72637.572135                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75130.514344                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 75117.781675                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72637.572135                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75130.514344                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 75117.781675                       # average overall miss latency
+system.cpu.l2cache.demand_misses::cpu.inst         2430                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       472569                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        474999                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         2430                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       472569                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       474999                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    176338750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data  30866203500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total  31042542250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   4447510000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   4447510000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    176338750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  35313713500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  35490052250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    176338750                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  35313713500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  35490052250                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst        24455                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      1464536                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      1488991                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks        96321                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total        96321                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data         4299                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total         4299                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data        72517                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total        72517                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        24455                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      1537053                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      1561508                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        24455                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      1537053                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      1561508                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.099366                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.277557                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.274630                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.999302                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.999302                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.911193                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.911193                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.099366                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.307451                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.304192                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.099366                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.307451                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.304192                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72567.386831                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75933.114305                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 75913.113626                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67307.989164                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67307.989164                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72567.386831                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74727.105460                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 74716.056771                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72567.386831                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74727.105460                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 74716.056771                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -898,177 +861,177 @@ system.cpu.l2cache.demand_mshr_hits::total           26                       #
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            2                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.data           24                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total           26                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2424                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       406462                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total       408886                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         4262                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total         4262                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2428                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       406468                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total       408896                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         4296                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total         4296                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66077                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total        66077                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         2424                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       472539                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       474963                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         2424                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       472539                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       474963                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    145637750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  25686438000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  25832075750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     42624262                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     42624262                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   3924978750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   3924978750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    145637750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  29611416750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  29757054500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    145637750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  29611416750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  29757054500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.096890                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.277534                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.274500                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.999297                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.999297                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.911181                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.911181                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.096890                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.307429                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.304057                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.096890                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.307429                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.304057                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60081.580033                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63195.176917                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63176.718572                       # average ReadReq mshr miss latency
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         2428                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       472545                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       474973                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         2428                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       472545                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       474973                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    145726000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  25804582750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  25950308750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     42964296                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     42964296                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   3615056500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   3615056500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    145726000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  29419639250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  29565365250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    145726000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  29419639250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  29565365250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.099284                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.277540                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.274613                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.999302                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.999302                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.911193                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.911193                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.099284                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.307436                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.304176                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.099284                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.307436                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.304176                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60018.945634                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63484.905946                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63464.325281                       # average ReadReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        10001                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59400.074913                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59400.074913                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60081.580033                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62664.492772                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62651.310734                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60081.580033                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62664.492772                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62651.310734                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54709.755286                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54709.755286                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60018.945634                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62257.857453                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62246.412428                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60018.945634                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62257.857453                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62246.412428                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements           1532970                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4094.376677                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           971409331                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1537066                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            631.989343                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         400505250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4094.376677                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999604                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999604                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements           1532957                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4094.373897                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           971355471                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1537053                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            631.959647                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         402104250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4094.373897                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999603                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999603                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           46                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          262                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          977                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3         2409                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4          402                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           48                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          265                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          973                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         2410                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4          400                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1949922120                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1949922120                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    695282746                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       695282746                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    276093049                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      276093049                       # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses        1949798453                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1949798453                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    695221170                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       695221170                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    276100593                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      276100593                       # number of WriteReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data        10000                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total        10000                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data         9985                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total         9985                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     971375795                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        971375795                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    971375795                       # number of overall hits
-system.cpu.dcache.overall_hits::total       971375795                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1954115                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1954115                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       842629                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       842629                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data     971321763                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        971321763                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    971321763                       # number of overall hits
+system.cpu.dcache.overall_hits::total       971321763                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1953864                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1953864                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       835085                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       835085                       # number of WriteReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            3                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            3                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      2796744                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2796744                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      2796744                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2796744                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  80415220057                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  80415220057                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  58619966916                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  58619966916                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       211750                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total       211750                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 139035186973                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 139035186973                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 139035186973                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 139035186973                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    697236861                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    697236861                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data      2788949                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2788949                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2788949                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2788949                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  82025897599                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  82025897599                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  54715114042                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  54715114042                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       225000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total       225000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 136741011641                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 136741011641                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 136741011641                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 136741011641                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    697175034                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    697175034                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    276935678                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    276935678                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data        10003                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total        10003                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data         9985                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total         9985                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    974172539                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    974172539                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    974172539                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    974172539                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data    974110712                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    974110712                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    974110712                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    974110712                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.002803                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.002803                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.003043                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.003043                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.003015                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.003015                       # miss rate for WriteReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000300                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000300                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.002871                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.002871                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.002871                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.002871                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41151.733678                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 41151.733678                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69567.943800                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 69567.943800                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 70583.333333                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 70583.333333                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 49713.233307                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 49713.233307                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 49713.233307                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 49713.233307                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs         2265                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets          939                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                52                       # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data     0.002863                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.002863                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.002863                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.002863                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41981.375162                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 41981.375162                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65520.412942                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 65520.412942                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        75000                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        75000                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 49029.584851                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 49029.584851                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 49029.584851                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 49029.584851                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs         2327                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets          933                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                51                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets              89                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    43.557692                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    10.550562                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    45.627451                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    10.483146                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks        96313                       # number of writebacks
-system.cpu.dcache.writebacks::total             96313                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       489564                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       489564                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       765848                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       765848                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks        96321                       # number of writebacks
+system.cpu.dcache.writebacks::total             96321                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       489326                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       489326                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       758271                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       758271                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            3                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total            3                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1255412                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1255412                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1255412                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1255412                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1464551                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1464551                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data        76781                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total        76781                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1541332                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1541332                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1541332                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1541332                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  42792151524                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  42792151524                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   4993494488                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   4993494488                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  47785646012                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  47785646012                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  47785646012                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  47785646012                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_hits::cpu.data      1247597                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1247597                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1247597                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1247597                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1464538                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1464538                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data        76814                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total        76814                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1541352                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1541352                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1541352                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1541352                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  42911632024                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  42911632024                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   4684436204                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   4684436204                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  47596068228                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  47596068228                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  47596068228                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  47596068228                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002101                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002101                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000277                       # mshr miss rate for WriteReq accesses
@@ -1077,14 +1040,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.001582
 system.cpu.dcache.demand_mshr_miss_rate::total     0.001582                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.001582                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.001582                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29218.614800                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29218.614800                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 65035.549003                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65035.549003                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31002.824837                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 31002.824837                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31002.824837                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 31002.824837                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29300.456543                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29300.456543                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60984.146171                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60984.146171                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30879.428079                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 30879.428079                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30879.428079                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 30879.428079                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 391c7c37b316370ab0e3064dfd7626a016672e0a..f3edc594831d0608bcbe72ba8ea844f59b20fa39 100644 (file)
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.043690                       # Number of seconds simulated
-sim_ticks                                 43690025000                       # Number of ticks simulated
-final_tick                                43690025000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.043459                       # Number of seconds simulated
+sim_ticks                                 43458818000                       # Number of ticks simulated
+final_tick                                43458818000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 133116                       # Simulator instruction rate (inst/s)
-host_op_rate                                   133116                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               65834414                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 238716                       # Number of bytes of host memory used
-host_seconds                                   663.64                       # Real time elapsed on the host
+host_inst_rate                                 114678                       # Simulator instruction rate (inst/s)
+host_op_rate                                   114678                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               56415550                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 273516                       # Number of bytes of host memory used
+host_seconds                                   770.33                       # Real time elapsed on the host
 sim_insts                                    88340673                       # Number of instructions simulated
 sim_ops                                      88340673                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -25,27 +25,27 @@ system.physmem.num_reads::cpu.data             158412                       # Nu
 system.physmem.num_reads::total                165515                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks          113997                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total               113997                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst             10404938                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            232052236                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               242457174                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst        10404938                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total           10404938                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks         166990245                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              166990245                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks         166990245                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst            10404938                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           232052236                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              409447420                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst             10460294                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            233286787                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               243747080                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst        10460294                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total           10460294                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks         167878657                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              167878657                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks         167878657                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst            10460294                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           233286787                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              411625737                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                        165515                       # Number of read requests accepted
 system.physmem.writeReqs                       113997                       # Number of write requests accepted
 system.physmem.readBursts                      165515                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                     113997                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 10592832                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                       128                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7294912                       # Total number of bytes written to DRAM
+system.physmem.bytesReadDRAM                 10592576                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                       384                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7294400                       # Total number of bytes written to DRAM
 system.physmem.bytesReadSys                  10592960                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                7295808                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                        2                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.servicedByWrQ                        6                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
 system.physmem.perBankRdBursts::0               10379                       # Per bank write bursts
@@ -58,10 +58,10 @@ system.physmem.perBankRdBursts::6                9796                       # Pe
 system.physmem.perBankRdBursts::7               10273                       # Per bank write bursts
 system.physmem.perBankRdBursts::8               10509                       # Per bank write bursts
 system.physmem.perBankRdBursts::9               10590                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              10479                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              10477                       # Per bank write bursts
 system.physmem.perBankRdBursts::11              10188                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              10237                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              10581                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              10236                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              10580                       # Per bank write bursts
 system.physmem.perBankRdBursts::14              10468                       # Per bank write bursts
 system.physmem.perBankRdBursts::15              10593                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                7081                       # Per bank write bursts
@@ -69,20 +69,20 @@ system.physmem.perBankWrBursts::1                7259                       # Pe
 system.physmem.perBankWrBursts::2                7255                       # Per bank write bursts
 system.physmem.perBankWrBursts::3                6998                       # Per bank write bursts
 system.physmem.perBankWrBursts::4                7125                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7173                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7170                       # Per bank write bursts
 system.physmem.perBankWrBursts::6                6769                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                7091                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7219                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                7092                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7216                       # Per bank write bursts
 system.physmem.perBankWrBursts::9                6938                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7084                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7083                       # Per bank write bursts
 system.physmem.perBankWrBursts::11               6989                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               6964                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               6963                       # Per bank write bursts
 system.physmem.perBankWrBursts::13               7284                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7282                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7281                       # Per bank write bursts
 system.physmem.perBankWrBursts::15               7472                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     43690004000                       # Total gap between requests
+system.physmem.totGap                     43458797000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -97,10 +97,10 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                 113997                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     73680                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     70517                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     16364                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      4951                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                     69517                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     66164                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     19662                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     10165                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
@@ -129,195 +129,147 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                      4750                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                      4761                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                      4763                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                      4763                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                      4759                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                      4760                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                      4763                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                      4764                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                      4766                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                      4765                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                     4768                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                     4771                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                     4774                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                     4774                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                     4800                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     4848                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     4954                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5307                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     6045                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     6005                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6585                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     6557                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     1474                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                      538                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                      102                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                       52                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                       21                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                        7                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        51391                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      348.059076                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     166.605304                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     670.587406                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64-65          21918     42.65%     42.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-129         7689     14.96%     57.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192-193         4202      8.18%     65.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-257         3191      6.21%     72.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320-321         2222      4.32%     76.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-385         1690      3.29%     79.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448-449         1284      2.50%     82.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-513         1159      2.26%     84.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576-577          851      1.66%     86.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-641          652      1.27%     87.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704-705          530      1.03%     88.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-769          483      0.94%     89.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832-833          404      0.79%     90.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-897          335      0.65%     90.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960-961          260      0.51%     91.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1025          388      0.75%     91.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088-1089          222      0.43%     92.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152-1153          237      0.46%     92.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216-1217          182      0.35%     93.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280-1281          255      0.50%     93.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344-1345          215      0.42%     94.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408-1409          327      0.64%     94.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472-1473          148      0.29%     95.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536-1537          683      1.33%     96.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600-1601          243      0.47%     96.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664-1665          177      0.34%     97.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1728-1729           59      0.11%     97.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1792-1793          192      0.37%     97.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856-1857           83      0.16%     97.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1920-1921           80      0.16%     98.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984-1985           48      0.09%     98.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2048-2049           87      0.17%     98.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112-2113           58      0.11%     98.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2176-2177           48      0.09%     98.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2240-2241           18      0.04%     98.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2304-2305           40      0.08%     98.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2368-2369           31      0.06%     98.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2432-2433           31      0.06%     98.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2496-2497           14      0.03%     98.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2560-2561           34      0.07%     98.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2624-2625           27      0.05%     98.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2688-2689           26      0.05%     98.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2752-2753           13      0.03%     98.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2816-2817           18      0.04%     98.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2880-2881           10      0.02%     98.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2944-2945           16      0.03%     99.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3008-3009           12      0.02%     99.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3072-3073           26      0.05%     99.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3136-3137            7      0.01%     99.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3200-3201           17      0.03%     99.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3264-3265            6      0.01%     99.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3328-3329           16      0.03%     99.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3392-3393           10      0.02%     99.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3456-3457           11      0.02%     99.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3520-3521            2      0.00%     99.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3584-3585           13      0.03%     99.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3648-3649           10      0.02%     99.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3712-3713            3      0.01%     99.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3776-3777            6      0.01%     99.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3840-3841            3      0.01%     99.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3904-3905            7      0.01%     99.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3968-3969            8      0.02%     99.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4032-4033           20      0.04%     99.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4096-4097           11      0.02%     99.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4160-4161           15      0.03%     99.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4224-4225           14      0.03%     99.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4288-4289            1      0.00%     99.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4352-4353            7      0.01%     99.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4416-4417            1      0.00%     99.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4480-4481            5      0.01%     99.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4544-4545           13      0.03%     99.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4608-4609            7      0.01%     99.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4672-4673            2      0.00%     99.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4736-4737            6      0.01%     99.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4800-4801            6      0.01%     99.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4864-4865            7      0.01%     99.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4928-4929            5      0.01%     99.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4992-4993            5      0.01%     99.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5056-5057            5      0.01%     99.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5120-5121            7      0.01%     99.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5184-5185            5      0.01%     99.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5248-5249            1      0.00%     99.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5312-5313            3      0.01%     99.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5376-5377            2      0.00%     99.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5440-5441            8      0.02%     99.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5504-5505            5      0.01%     99.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5568-5569            4      0.01%     99.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5632-5633            3      0.01%     99.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5696-5697            2      0.00%     99.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5760-5761            5      0.01%     99.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5824-5825            4      0.01%     99.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5888-5889            5      0.01%     99.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5952-5953            2      0.00%     99.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6016-6017            4      0.01%     99.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6080-6081            4      0.01%     99.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6144-6145            2      0.00%     99.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6208-6209            4      0.01%     99.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6272-6273            3      0.01%     99.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6336-6337            2      0.00%     99.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6400-6401            5      0.01%     99.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6464-6465            2      0.00%     99.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6528-6529            4      0.01%     99.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6592-6593            6      0.01%     99.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6656-6657            6      0.01%     99.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6720-6721            1      0.00%     99.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6784-6785            1      0.00%     99.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6848-6849            1      0.00%     99.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6912-6913            2      0.00%     99.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6976-6977            1      0.00%     99.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7040-7041            2      0.00%     99.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7104-7105            2      0.00%     99.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7168-7169            2      0.00%     99.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7232-7233            1      0.00%     99.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7360-7361            2      0.00%     99.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7424-7425            1      0.00%     99.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7488-7489            1      0.00%     99.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7552-7553            2      0.00%     99.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7616-7617            1      0.00%     99.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7680-7681            2      0.00%     99.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7808-7809            2      0.00%     99.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7872-7873            1      0.00%     99.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7936-7937            1      0.00%     99.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8000-8001            1      0.00%     99.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8064-8065            2      0.00%     99.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8128-8129           24      0.05%     99.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8192-8193           73      0.14%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          51391                       # Bytes accessed per row activation
-system.physmem.totQLat                     6031819750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                8481513500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    827565000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                  1622128750                       # Total ticks spent accessing banks
-system.physmem.avgQLat                       36443.18                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                     9800.61                       # Average bank access latency per DRAM burst
+system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      573                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      585                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                      866                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     1934                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     2737                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     4571                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     5772                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     6159                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     6456                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     6714                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     7156                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     7301                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     7672                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     8033                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     8104                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     8481                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     8313                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     8308                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     5342                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                     3822                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                     2427                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      910                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      567                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      333                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      152                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      100                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                       82                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                       69                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                       58                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                       54                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                       48                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                       47                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                       44                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                       38                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                       37                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       33                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       29                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       28                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       27                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        41807                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      385.014950                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     230.118388                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     358.708548                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          12628     30.21%     30.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         8632     20.65%     50.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         4415     10.56%     61.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2749      6.58%     67.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2263      5.41%     73.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1680      4.02%     77.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1442      3.45%     80.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1629      3.90%     84.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         6369     15.23%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          41807                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6909                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        23.954842                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      351.043824                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           6907     99.97%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047            1      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::28672-29695            1      0.01%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            6909                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6909                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.496599                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.404036                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        2.150839                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               6289     91.03%     91.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 13      0.19%     91.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                 61      0.88%     92.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                166      2.40%     94.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                127      1.84%     96.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 73      1.06%     97.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 63      0.91%     98.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 29      0.42%     98.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                 18      0.26%     98.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                 12      0.17%     99.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                  7      0.10%     99.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27                  3      0.04%     99.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28                  3      0.04%     99.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29                  1      0.01%     99.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30                  2      0.03%     99.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::31                  3      0.04%     99.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32                  2      0.03%     99.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::34                  3      0.04%     99.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::35                  2      0.03%     99.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::37                  3      0.04%     99.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::38                  2      0.03%     99.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::39                 19      0.28%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40                  5      0.07%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::42                  2      0.03%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::43                  1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6909                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     5306478250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                7800537000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    827545000                       # Total ticks spent in databus transfers
+system.physmem.totBankLat                  1666513750                       # Total ticks spent accessing banks
+system.physmem.avgQLat                       32061.57                       # Average queueing delay per DRAM burst
+system.physmem.avgBankLat                    10069.02                       # Average bank access latency per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  51243.79                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         242.45                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                         166.97                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      242.46                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                      166.99                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  47130.59                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         243.74                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                         167.85                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      243.75                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                      167.88                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           3.20                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       1.89                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      1.30                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         0.19                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        10.01                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     151507                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     76598                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   91.54                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  67.19                       # Row buffer hit rate for writes
-system.physmem.avgGap                       156308.15                       # Average gap between requests
-system.physmem.pageHitRate                      81.61                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent              10.59                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                    409447420                       # Throughput (bytes/s)
+system.physmem.busUtil                           3.22                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       1.90                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      1.31                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.45                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        26.84                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     144461                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     82889                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   87.28                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  72.71                       # Row buffer hit rate for writes
+system.physmem.avgGap                       155480.97                       # Average gap between requests
+system.physmem.pageHitRate                      81.34                       # Row buffer hit rate, read and write combined
+system.physmem.prechargeAllPercent              10.25                       # Percentage of time for which DRAM has all the banks in precharge state
+system.membus.throughput                    411625737                       # Throughput (bytes/s)
 system.membus.trans_dist::ReadReq               34625                       # Transaction distribution
 system.membus.trans_dist::ReadResp              34625                       # Transaction distribution
 system.membus.trans_dist::Writeback            113997                       # Transaction distribution
@@ -329,40 +281,40 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
 system.membus.tot_pkt_size::total            17888768                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.data_through_bus               17888768                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy          1218631000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy          1219845000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               2.8                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         1521663500                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         1520840750                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              3.5                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                18742723                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          12318363                       # Number of conditional branches predicted
+system.cpu.branchPred.lookups                18742760                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          12318400                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect           4775680                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             15507309                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 4664026                       # Number of BTB hits
+system.cpu.branchPred.BTBLookups             15507492                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 4664025                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             30.076308                       # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct             30.075947                       # BTB Hit Percentage
 system.cpu.branchPred.usedRAS                 1660965                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect               1030                       # Number of incorrect RAS predictions.
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     20277713                       # DTB read hits
+system.cpu.dtb.read_hits                     20277780                       # DTB read hits
 system.cpu.dtb.read_misses                      90148                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                 20367861                       # DTB read accesses
-system.cpu.dtb.write_hits                    14728970                       # DTB write hits
+system.cpu.dtb.read_accesses                 20367928                       # DTB read accesses
+system.cpu.dtb.write_hits                    14729056                       # DTB write hits
 system.cpu.dtb.write_misses                      7252                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                14736222                       # DTB write accesses
-system.cpu.dtb.data_hits                     35006683                       # DTB hits
+system.cpu.dtb.write_accesses                14736308                       # DTB write accesses
+system.cpu.dtb.data_hits                     35006836                       # DTB hits
 system.cpu.dtb.data_misses                      97400                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                 35104083                       # DTB accesses
-system.cpu.itb.fetch_hits                    12367758                       # ITB hits
+system.cpu.dtb.data_accesses                 35104236                       # DTB accesses
+system.cpu.itb.fetch_hits                    12367757                       # ITB hits
 system.cpu.itb.fetch_misses                     11021                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                12378779                       # ITB accesses
+system.cpu.itb.fetch_accesses                12378778                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -376,18 +328,18 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                 4583                       # Number of system calls
-system.cpu.numCycles                         87380051                       # number of cpu cycles simulated
+system.cpu.numCycles                         86917637                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.branch_predictor.predictedTaken      8074237                       # Number of Branches Predicted As Taken (True).
-system.cpu.branch_predictor.predictedNotTaken     10668486                       # Number of Branches Predicted As Not Taken (False).
-system.cpu.regfile_manager.intRegFileReads     74161830                       # Number of Reads from Int. Register File
+system.cpu.branch_predictor.predictedTaken      8074236                       # Number of Branches Predicted As Taken (True).
+system.cpu.branch_predictor.predictedNotTaken     10668524                       # Number of Branches Predicted As Not Taken (False).
+system.cpu.regfile_manager.intRegFileReads     74162131                       # Number of Reads from Int. Register File
 system.cpu.regfile_manager.intRegFileWrites     52319250                       # Number of Writes to Int. Register File
-system.cpu.regfile_manager.intRegFileAccesses    126481080                       # Total Accesses (Read+Write) to the Int. Register File
+system.cpu.regfile_manager.intRegFileAccesses    126481381                       # Total Accesses (Read+Write) to the Int. Register File
 system.cpu.regfile_manager.floatRegFileReads        66044                       # Number of Reads from FP Register File
 system.cpu.regfile_manager.floatRegFileWrites       227630                       # Number of Writes to FP Register File
 system.cpu.regfile_manager.floatRegFileAccesses       293674                       # Total Accesses (Read+Write) to the FP Register File
-system.cpu.regfile_manager.regForwards       14174544                       # Number of Registers Read Through Forwarding Logic
+system.cpu.regfile_manager.regForwards       14174243                       # Number of Registers Read Through Forwarding Logic
 system.cpu.agen_unit.agens                   35060070                       # Number of Address Generations
 system.cpu.execution_unit.predictedTakenIncorrect      4449011                       # Number of Branches Incorrectly Predicted As Taken.
 system.cpu.execution_unit.predictedNotTakenIncorrect       216169                       # Number of Branches Incorrectly Predicted As Not Taken).
@@ -398,12 +350,12 @@ system.cpu.execution_unit.executions         44777932                       # Nu
 system.cpu.mult_div_unit.multiplies             41107                       # Number of Multipy Operations Executed
 system.cpu.mult_div_unit.divides                    0                       # Number of Divide Operations Executed
 system.cpu.contextSwitches                          1                       # Number of context switches
-system.cpu.threadCycles                      77196544                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles                      77191042                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
 system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled                          232942                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        17804423                       # Number of cycles cpu's stages were not processed
-system.cpu.runCycles                         69575628                       # Number of cycles cpu stages are processed.
-system.cpu.activity                         79.624156                       # Percentage of cycles cpu is active
+system.cpu.timesIdled                          229429                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        17341864                       # Number of cycles cpu's stages were not processed
+system.cpu.runCycles                         69575773                       # Number of cycles cpu stages are processed.
+system.cpu.activity                         80.047934                       # Percentage of cycles cpu is active
 system.cpu.comLoads                          20276638                       # Number of Load instructions committed
 system.cpu.comStores                         14613377                       # Number of Store instructions committed
 system.cpu.comBranches                       13754477                       # Number of Branches instructions committed
@@ -415,62 +367,62 @@ system.cpu.committedInsts                    88340673                       # Nu
 system.cpu.committedOps                      88340673                       # Number of Ops committed (Per-Thread)
 system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
 system.cpu.committedInsts_total              88340673                       # Number of Instructions committed (Total)
-system.cpu.cpi                               0.989126                       # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi                               0.983891                       # CPI: Cycles Per Instruction (Per-Thread)
 system.cpu.smt_cpi                                nan                       # CPI: Total SMT-CPI
-system.cpu.cpi_total                         0.989126                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.010994                       # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.cpi_total                         0.983891                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.016372                       # IPC: Instructions Per Cycle (Per-Thread)
 system.cpu.smt_ipc                                nan                       # IPC: Total SMT-IPC
-system.cpu.ipc_total                         1.010994                       # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles                 34724442                       # Number of cycles 0 instructions are processed.
-system.cpu.stage0.runCycles                  52655609                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization               60.260447                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles                 44924893                       # Number of cycles 0 instructions are processed.
-system.cpu.stage1.runCycles                  42455158                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization               48.586786                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles                 44349560                       # Number of cycles 0 instructions are processed.
-system.cpu.stage2.runCycles                  43030491                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization               49.245212                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage3.idleCycles                 65259184                       # Number of cycles 0 instructions are processed.
-system.cpu.stage3.runCycles                  22120867                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage3.utilization               25.315695                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles                 41338146                       # Number of cycles 0 instructions are processed.
-system.cpu.stage4.runCycles                  46041905                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization               52.691552                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.ipc_total                         1.016372                       # IPC: Total IPC of All Threads
+system.cpu.stage0.idleCycles                 34262012                       # Number of cycles 0 instructions are processed.
+system.cpu.stage0.runCycles                  52655625                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage0.utilization               60.581059                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles                 44462439                       # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles                  42455198                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization               48.845320                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles                 43887105                       # Number of cycles 0 instructions are processed.
+system.cpu.stage2.runCycles                  43030532                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage2.utilization               49.507250                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles                 64797015                       # Number of cycles 0 instructions are processed.
+system.cpu.stage3.runCycles                  22120622                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage3.utilization               25.450096                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles                 40875399                       # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles                  46042238                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization               52.972262                       # Percentage of cycles stage was utilized (processing insts).
 system.cpu.icache.tags.replacements             84371                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1906.431852                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            12250505                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse          1905.831723                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            12250503                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs             86417                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs            141.760360                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs            141.760337                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1906.431852                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.930875                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.930875                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1905.831723                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.930582                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.930582                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         2046                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           61                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          105                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           62                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          104                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3         1090                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4          790                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.999023                       # Percentage of cache occupancy per task id
 system.cpu.icache.tags.tag_accesses          24821911                       # Number of tag accesses
 system.cpu.icache.tags.data_accesses         24821911                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     12250505                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        12250505                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      12250505                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         12250505                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     12250505                       # number of overall hits
-system.cpu.icache.overall_hits::total        12250505                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       117242                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        117242                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       117242                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         117242                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       117242                       # number of overall misses
-system.cpu.icache.overall_misses::total        117242                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   2020332731                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   2020332731                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst   2020332731                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   2020332731                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst   2020332731                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   2020332731                       # number of overall miss cycles
+system.cpu.icache.ReadReq_hits::cpu.inst     12250503                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        12250503                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      12250503                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         12250503                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     12250503                       # number of overall hits
+system.cpu.icache.overall_hits::total        12250503                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       117244                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        117244                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       117244                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         117244                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       117244                       # number of overall misses
+system.cpu.icache.overall_misses::total        117244                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   1999895234                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   1999895234                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   1999895234                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   1999895234                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   1999895234                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   1999895234                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst     12367747                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total     12367747                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst     12367747                       # number of demand (read+write) accesses
@@ -483,106 +435,106 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.009480
 system.cpu.icache.demand_miss_rate::total     0.009480                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.009480                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.009480                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17232.158535                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 17232.158535                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 17232.158535                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 17232.158535                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 17232.158535                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 17232.158535                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          376                       # number of cycles access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17057.548651                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 17057.548651                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 17057.548651                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 17057.548651                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 17057.548651                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 17057.548651                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          343                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets          192                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                17                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                15                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               4                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    22.117647                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    22.866667                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets           48                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        30825                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        30825                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        30825                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        30825                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        30825                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        30825                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        30827                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        30827                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        30827                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        30827                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        30827                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        30827                       # number of overall MSHR hits
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst        86417                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total        86417                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst        86417                       # number of demand (read+write) MSHR misses
 system.cpu.icache.demand_mshr_misses::total        86417                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst        86417                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total        86417                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   1432321765                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total   1432321765                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst   1432321765                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total   1432321765                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst   1432321765                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total   1432321765                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   1419611513                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total   1419611513                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   1419611513                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total   1419611513                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst   1419611513                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total   1419611513                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.006987                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.006987                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.006987                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.006987                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.006987                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.006987                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16574.537012                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16574.537012                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16574.537012                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 16574.537012                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16574.537012                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 16574.537012                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16427.456554                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16427.456554                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16427.456554                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 16427.456554                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16427.456554                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 16427.456554                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput               672540151                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq         146994                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp        146994                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       168351                       # Transaction distribution
+system.cpu.toL2Bus.throughput               676121104                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq         146995                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp        146995                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       168352                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq       143769                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp       143769                       # Transaction distribution
 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       172834                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       577043                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total            749877                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       577046                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total            749880                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5530688                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     23852608                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total       29383296                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus          29383296                       # Total data (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     23852736                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total       29383424                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus          29383424                       # Total data (bytes)
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy      397908000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.occupancy      397910000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.9                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy     130875735                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy     130829487                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.3                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy     325637219                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy     323146469                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.7                       # Layer utilization (%)
 system.cpu.l2cache.tags.replacements           131591                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        30890.802594                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs             151432                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse        30877.243576                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs             151434                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs           163651                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.925335                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.925347                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 27098.006137                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2007.747165                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  1785.049292                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.826966                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.061272                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.054475                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.942712                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks 27092.654478                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2007.905024                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  1776.684074                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.826802                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.061276                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.054220                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.942299                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        32060                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          137                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1155                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2        17071                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3        13589                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          145                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1156                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2        17173                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        13478                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4          108                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.978394                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses          3980332                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses         3980332                       # Number of data accesses
+system.cpu.l2cache.tags.tag_accesses          3980348                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses         3980348                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst        79314                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data        33055                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total         112369                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       168351                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       168351                       # number of Writeback hits
+system.cpu.l2cache.ReadReq_hits::cpu.data        33056                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         112370                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       168352                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       168352                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data        12879                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total        12879                       # number of ReadExReq hits
 system.cpu.l2cache.demand_hits::cpu.inst        79314                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data        45934                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total          125248                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data        45935                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          125249                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.inst        79314                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data        45934                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         125248                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data        45935                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         125249                       # number of overall hits
 system.cpu.l2cache.ReadReq_misses::cpu.inst         7103                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.data        27522                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::total        34625                       # number of ReadReq misses
@@ -594,52 +546,52 @@ system.cpu.l2cache.demand_misses::total        165515                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst         7103                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data       158412                       # number of overall misses
 system.cpu.l2cache.overall_misses::total       165515                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    550125750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data   2043322000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total   2593447750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  13452980250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  13452980250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    550125750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  15496302250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  16046428000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    550125750                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  15496302250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  16046428000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    537407000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1972226500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   2509633500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  12899781250                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  12899781250                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    537407000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  14872007750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  15409414750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    537407000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  14872007750                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  15409414750                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst        86417                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data        60577                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total       146994                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       168351                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       168351                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data        60578                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       146995                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       168352                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       168352                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data       143769                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total       143769                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.inst        86417                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       204346                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       290763                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       204347                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       290764                       # number of demand (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.inst        86417                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       204346                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       290763                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       204347                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       290764                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.082194                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.454331                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.235554                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.454323                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.235552                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.910419                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total     0.910419                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.082194                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.775215                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.569244                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.775211                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.569242                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.082194                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.775215                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.569244                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77449.774743                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74243.223603                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 74901.018051                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 102780.810222                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 102780.810222                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77449.774743                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 97822.780156                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 96948.482011                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77449.774743                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 97822.780156                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 96948.482011                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.775211                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.569242                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75659.158102                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71659.999273                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 72480.389892                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 98554.368172                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 98554.368172                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75659.158102                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93881.825556                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 93099.808174                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75659.158102                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93881.825556                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 93099.808174                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -661,80 +613,80 @@ system.cpu.l2cache.demand_mshr_misses::total       165515
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         7103                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data       158412                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total       165515                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    460945750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1695556500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2156502250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  11851363750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  11851363750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    460945750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  13546920250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  14007866000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    460945750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  13546920250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  14007866000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    448296500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1624855000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2073151500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  11301062250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  11301062250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    448296500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  12925917250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  13374213750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    448296500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  12925917250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  13374213750                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.082194                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.454331                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.235554                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.454323                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.235552                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.910419                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.910419                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.082194                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.775215                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.569244                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.775211                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.569242                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.082194                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.775215                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.569244                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64894.516402                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61607.314149                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62281.653430                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 90544.455268                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 90544.455268                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64894.516402                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 85517.007866                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84632.003142                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64894.516402                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 85517.007866                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84632.003142                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.775211                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.569242                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63113.684359                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59038.405639                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59874.411552                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86340.150126                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86340.150126                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63113.684359                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81596.831364                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 80803.635622                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63113.684359                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81596.831364                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80803.635622                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements            200250                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4076.382661                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            33754883                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            204346                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            165.184946                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         297515000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4076.382661                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.995211                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.995211                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements            200251                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4076.081511                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            33755026                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            204347                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            165.184838                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         302612000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4076.081511                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.995137                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.995137                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           66                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          922                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         3118                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         3108                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          69984376                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         69984376                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     20180292                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        20180292                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     13574591                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       13574591                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      33754883                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         33754883                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     33754883                       # number of overall hits
-system.cpu.dcache.overall_hits::total        33754883                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data        96346                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total         96346                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1038786                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1038786                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      1135132                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1135132                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1135132                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1135132                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   5098666234                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   5098666234                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  85921765380                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  85921765380                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  91020431614                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  91020431614                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  91020431614                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  91020431614                       # number of overall miss cycles
+system.cpu.dcache.tags.tag_accesses          69984377                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         69984377                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     20180293                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        20180293                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     13574733                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       13574733                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      33755026                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         33755026                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     33755026                       # number of overall hits
+system.cpu.dcache.overall_hits::total        33755026                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data        96345                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total         96345                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1038644                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1038644                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      1134989                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1134989                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1134989                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1134989                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   4945314984                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   4945314984                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  82211352380                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  82211352380                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  87156667364                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  87156667364                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  87156667364                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  87156667364                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data     20276638                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total     20276638                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     14613377                       # number of WriteReq accesses(hits+misses)
@@ -745,54 +697,54 @@ system.cpu.dcache.overall_accesses::cpu.data     34890015
 system.cpu.dcache.overall_accesses::total     34890015                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.004752                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.004752                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.071085                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.071085                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.032535                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.032535                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.032535                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.032535                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52920.372761                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 52920.372761                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 82713.634358                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 82713.634358                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 80184.887409                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 80184.887409                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 80184.887409                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 80184.887409                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs      5745787                       # number of cycles access was blocked
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.071075                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.071075                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.032530                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.032530                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.032530                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.032530                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51329.233318                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 51329.233318                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79152.580076                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 79152.580076                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 76790.759526                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 76790.759526                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 76790.759526                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 76790.759526                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs      5467849                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets           77                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs            116736                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs            116872                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               1                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    49.220352                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    46.784936                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets           77                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       168351                       # number of writebacks
-system.cpu.dcache.writebacks::total            168351                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data        35580                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        35580                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       895206                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       895206                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       930786                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       930786                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       930786                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       930786                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data        60766                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total        60766                       # number of ReadReq MSHR misses
+system.cpu.dcache.writebacks::writebacks       168352                       # number of writebacks
+system.cpu.dcache.writebacks::total            168352                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        35578                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        35578                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       895064                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       895064                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       930642                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       930642                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       930642                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       930642                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data        60767                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total        60767                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data       143580                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total       143580                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       204346                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       204346                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       204346                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       204346                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   2437943016                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   2437943016                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  13723508765                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  13723508765                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  16161451781                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  16161451781                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  16161451781                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  16161451781                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data       204347                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       204347                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       204347                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       204347                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   2366861266                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   2366861266                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  13170287765                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  13170287765                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  15537149031                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  15537149031                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  15537149031                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  15537149031                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002997                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002997                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009825                       # mshr miss rate for WriteReq accesses
@@ -801,14 +753,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.005857
 system.cpu.dcache.demand_mshr_miss_rate::total     0.005857                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.005857                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.005857                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40120.182602                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40120.182602                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 95580.921890                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 95580.921890                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 79088.662274                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 79088.662274                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 79088.662274                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 79088.662274                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 38949.779749                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 38949.779749                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 91727.871326                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 91727.871326                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76033.164328                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 76033.164328                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76033.164328                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 76033.164328                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 629fb2f138a2285d892ad8fcf00ea3eb4d7f67ff..7573bf6de53961e8b86da8ccde17919453af5183 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.024877                       # Number of seconds simulated
-sim_ticks                                 24876941500                       # Number of ticks simulated
-final_tick                                24876941500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.024671                       # Number of seconds simulated
+sim_ticks                                 24670906500                       # Number of ticks simulated
+final_tick                                24670906500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 202143                       # Simulator instruction rate (inst/s)
-host_op_rate                                   202143                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               63181048                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 239772                       # Number of bytes of host memory used
-host_seconds                                   393.74                       # Real time elapsed on the host
+host_inst_rate                                 168282                       # Simulator instruction rate (inst/s)
+host_op_rate                                   168282                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               52161952                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 276592                       # Number of bytes of host memory used
+host_seconds                                   472.97                       # Real time elapsed on the host
 sim_insts                                    79591756                       # Number of instructions simulated
 sim_ops                                      79591756                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            490624                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          10154752                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             10645376                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       490624                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          490624                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7297216                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7297216                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               7666                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             158668                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                166334                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          114019                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               114019                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst             19722039                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            408199376                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               427921415                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst        19722039                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total           19722039                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks         293332522                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              293332522                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks         293332522                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst            19722039                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           408199376                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              721253937                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        166334                       # Number of read requests accepted
-system.physmem.writeReqs                       114019                       # Number of write requests accepted
-system.physmem.readBursts                      166334                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     114019                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 10645312                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                        64                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7297024                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  10645376                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7297216                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                        1                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst            489344                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          10153856                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             10643200                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       489344                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          489344                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7297088                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7297088                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               7646                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             158654                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                166300                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          114017                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               114017                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst             19834861                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            411572068                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               431406929                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst        19834861                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total           19834861                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks         295777052                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              295777052                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks         295777052                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst            19834861                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           411572068                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              727183981                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        166300                       # Number of read requests accepted
+system.physmem.writeReqs                       114017                       # Number of write requests accepted
+system.physmem.readBursts                      166300                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     114017                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 10642752                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                       448                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7295296                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  10643200                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7297088                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                        7                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               10436                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               10466                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               10310                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               10058                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               10431                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               10410                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                9846                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               10323                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               10612                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               10641                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              10552                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              10231                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              10282                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               10427                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               10465                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               10308                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               10056                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               10424                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               10403                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                9851                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               10318                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               10615                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               10643                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              10551                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              10228                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              10273                       # Per bank write bursts
 system.physmem.perBankRdBursts::13              10619                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              10489                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              10627                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                7083                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7258                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              10486                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              10626                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                7082                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7259                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                7255                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                6998                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                6997                       # Per bank write bursts
 system.physmem.perBankWrBursts::4                7126                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7177                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7170                       # Per bank write bursts
 system.physmem.perBankWrBursts::6                6771                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                7092                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7228                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                7086                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7221                       # Per bank write bursts
 system.physmem.perBankWrBursts::9                6941                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7087                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6989                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               6966                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7084                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6991                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               6963                       # Per bank write bursts
 system.physmem.perBankWrBursts::13               7287                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7286                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7284                       # Per bank write bursts
 system.physmem.perBankWrBursts::15               7472                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     24876907500                       # Total gap between requests
+system.physmem.totGap                     24670873000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  166334                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  166300                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 114019                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     71615                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     56813                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     31969                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      5926                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         8                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 114017                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     69085                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     53344                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     32724                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     11125                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        12                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
@@ -129,233 +129,193 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                      4795                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                      4808                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                      4807                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                      4805                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                      4807                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                      4811                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                      4806                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                      4810                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                      4806                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                      4815                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                     4809                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                     4814                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                     4825                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                     4821                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                     4848                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     4871                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     4925                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5346                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5647                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5867                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6542                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7048                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                      962                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                      451                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                      107                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                       49                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                       13                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        52112                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      344.289837                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     164.462354                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     671.053187                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64-65          22533     43.24%     43.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-129         7819     15.00%     58.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192-193         4221      8.10%     66.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-257         3179      6.10%     72.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320-321         2215      4.25%     76.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-385         1656      3.18%     79.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448-449         1349      2.59%     82.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-513         1165      2.24%     84.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576-577          821      1.58%     86.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-641          640      1.23%     87.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704-705          526      1.01%     88.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-769          503      0.97%     89.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832-833          384      0.74%     90.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-897          279      0.54%     90.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960-961          312      0.60%     91.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1025          436      0.84%     92.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088-1089          202      0.39%     92.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152-1153          182      0.35%     92.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216-1217          166      0.32%     93.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280-1281          352      0.68%     93.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344-1345          220      0.42%     94.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408-1409          250      0.48%     94.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472-1473          131      0.25%     95.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536-1537          818      1.57%     96.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600-1601          224      0.43%     97.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664-1665           79      0.15%     97.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1728-1729           35      0.07%     97.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1792-1793          217      0.42%     97.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856-1857          119      0.23%     97.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1920-1921           48      0.09%     98.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984-1985           34      0.07%     98.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2048-2049           83      0.16%     98.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112-2113           65      0.12%     98.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2176-2177           27      0.05%     98.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2240-2241           17      0.03%     98.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2304-2305           59      0.11%     98.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2368-2369           39      0.07%     98.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2432-2433           22      0.04%     98.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2496-2497           18      0.03%     98.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2560-2561           32      0.06%     98.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2624-2625           27      0.05%     98.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2688-2689           16      0.03%     98.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2752-2753            9      0.02%     98.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2816-2817           20      0.04%     98.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2880-2881           18      0.03%     98.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2944-2945           13      0.02%     98.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3008-3009           16      0.03%     99.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3072-3073           32      0.06%     99.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3136-3137           16      0.03%     99.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3200-3201           10      0.02%     99.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3264-3265           10      0.02%     99.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3328-3329           12      0.02%     99.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3392-3393           13      0.02%     99.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3456-3457           13      0.02%     99.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3520-3521            4      0.01%     99.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3584-3585           12      0.02%     99.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3648-3649           12      0.02%     99.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3712-3713            5      0.01%     99.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3776-3777            5      0.01%     99.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3840-3841           14      0.03%     99.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3904-3905            6      0.01%     99.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3968-3969            9      0.02%     99.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4032-4033           11      0.02%     99.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4096-4097           10      0.02%     99.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4160-4161           10      0.02%     99.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4224-4225           14      0.03%     99.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4288-4289            2      0.00%     99.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4352-4353            3      0.01%     99.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4416-4417            6      0.01%     99.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4480-4481            9      0.02%     99.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4544-4545            6      0.01%     99.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4608-4609           11      0.02%     99.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4672-4673            4      0.01%     99.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4736-4737            4      0.01%     99.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4800-4801            4      0.01%     99.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4864-4865            9      0.02%     99.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4928-4929            5      0.01%     99.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4992-4993            5      0.01%     99.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5056-5057            3      0.01%     99.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5120-5121            6      0.01%     99.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5184-5185            5      0.01%     99.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5248-5249            3      0.01%     99.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5312-5313            4      0.01%     99.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5376-5377            2      0.00%     99.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5440-5441            6      0.01%     99.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5568-5569            3      0.01%     99.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5632-5633            6      0.01%     99.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5696-5697            3      0.01%     99.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5760-5761            3      0.01%     99.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5888-5889            4      0.01%     99.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5952-5953            4      0.01%     99.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6080-6081            6      0.01%     99.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6144-6145            5      0.01%     99.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6208-6209            5      0.01%     99.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6272-6273            1      0.00%     99.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6336-6337            3      0.01%     99.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6400-6401            9      0.02%     99.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6528-6529            1      0.00%     99.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6592-6593            1      0.00%     99.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6656-6657            1      0.00%     99.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6720-6721            6      0.01%     99.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6784-6785            1      0.00%     99.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6848-6849            4      0.01%     99.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6912-6913            4      0.01%     99.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7040-7041            1      0.00%     99.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7104-7105            2      0.00%     99.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7168-7169           10      0.02%     99.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7232-7233            4      0.01%     99.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7296-7297            3      0.01%     99.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7360-7361            1      0.00%     99.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7424-7425            2      0.00%     99.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7488-7489            1      0.00%     99.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7616-7617            1      0.00%     99.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7808-7809            2      0.00%     99.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7936-7937            1      0.00%     99.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8000-8001            2      0.00%     99.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8064-8065            4      0.01%     99.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8128-8129           15      0.03%     99.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8192-8193           82      0.16%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          52112                       # Bytes accessed per row activation
-system.physmem.totQLat                     6294270000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                8641432500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    831665000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                  1515497500                       # Total ticks spent accessing banks
-system.physmem.avgQLat                       37841.38                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                     9111.23                       # Average bank access latency per DRAM burst
+system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      477                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      497                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                      834                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     2010                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     3571                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     4892                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     5900                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     6322                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     6639                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     6815                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     7340                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     7462                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     7667                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     8141                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     8256                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     8096                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     8008                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     7688                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     5156                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                     3526                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                     2094                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      889                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      544                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      347                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      222                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      108                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                       76                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                       63                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                       54                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                       46                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                       42                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                       37                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                       36                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                       35                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                       31                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       29                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       19                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       17                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       16                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        43247                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      376.488173                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     224.222062                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     355.745587                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          13435     31.07%     31.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         8988     20.78%     51.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         4626     10.70%     62.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2682      6.20%     68.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2451      5.67%     74.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1626      3.76%     78.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1548      3.58%     81.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1315      3.04%     84.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         6576     15.21%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          43247                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6943                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        23.949301                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      342.898812                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           6941     99.97%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047            1      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::27648-28671            1      0.01%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            6943                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6943                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.417831                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.341311                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.942818                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               6412     92.35%     92.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 14      0.20%     92.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                 48      0.69%     93.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                135      1.94%     95.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                111      1.60%     96.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 69      0.99%     97.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 62      0.89%     98.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 19      0.27%     98.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                 14      0.20%     99.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                  9      0.13%     99.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                  3      0.04%     99.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27                  6      0.09%     99.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28                  5      0.07%     99.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30                  4      0.06%     99.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::31                  3      0.04%     99.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32                  1      0.01%     99.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::33                  3      0.04%     99.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::35                  1      0.01%     99.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36                  4      0.06%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::37                  2      0.03%     99.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::38                  1      0.01%     99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::39                 10      0.14%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40                  2      0.03%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::41                  2      0.03%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::42                  1      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::45                  2      0.03%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6943                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     5579601250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                7987531250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    831465000                       # Total ticks spent in databus transfers
+system.physmem.totBankLat                  1576465000                       # Total ticks spent accessing banks
+system.physmem.avgQLat                       33552.83                       # Average queueing delay per DRAM burst
+system.physmem.avgBankLat                     9480.04                       # Average bank access latency per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  51952.60                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         427.92                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                         293.32                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      427.92                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                      293.33                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  48032.88                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         431.39                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                         295.70                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      431.41                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                      295.78                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           5.63                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       3.34                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      2.29                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         0.35                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                         9.70                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     152220                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     76017                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   91.52                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  66.67                       # Row buffer hit rate for writes
-system.physmem.avgGap                        88734.23                       # Average gap between requests
-system.physmem.pageHitRate                      81.41                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent              11.97                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                    721253937                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq               35533                       # Transaction distribution
-system.membus.trans_dist::ReadResp              35533                       # Transaction distribution
-system.membus.trans_dist::Writeback            114019                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            130801                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           130801                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       446687                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 446687                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     17942592                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            17942592                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus               17942592                       # Total data (bytes)
+system.physmem.busUtil                           5.68                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       3.37                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      2.31                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.68                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        26.84                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     144952                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     82533                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   87.17                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  72.39                       # Row buffer hit rate for writes
+system.physmem.avgGap                        88010.62                       # Average gap between requests
+system.physmem.pageHitRate                      81.15                       # Row buffer hit rate, read and write combined
+system.physmem.prechargeAllPercent              12.46                       # Percentage of time for which DRAM has all the banks in precharge state
+system.membus.throughput                    727183981                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq               35502                       # Transaction distribution
+system.membus.trans_dist::ReadResp              35502                       # Transaction distribution
+system.membus.trans_dist::Writeback            114017                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            130798                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           130798                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       446617                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 446617                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     17940288                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total            17940288                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               17940288                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy          1242193000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy          1242249500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               5.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         1539567000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         1535210250                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              6.2                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                16535475                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          10680150                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            413128                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             11281450                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 7332394                       # Number of BTB hits
+system.cpu.branchPred.lookups                16545461                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          10688882                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            416220                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             11528806                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 7341014                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             64.995138                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1986702                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              41528                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             63.675406                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1988101                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              40517                       # Number of incorrect RAS predictions.
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     22396974                       # DTB read hits
-system.cpu.dtb.read_misses                     220986                       # DTB read misses
-system.cpu.dtb.read_acv                            45                       # DTB read access violations
-system.cpu.dtb.read_accesses                 22617960                       # DTB read accesses
-system.cpu.dtb.write_hits                    15703419                       # DTB write hits
-system.cpu.dtb.write_misses                     41132                       # DTB write misses
-system.cpu.dtb.write_acv                            4                       # DTB write access violations
-system.cpu.dtb.write_accesses                15744551                       # DTB write accesses
-system.cpu.dtb.data_hits                     38100393                       # DTB hits
-system.cpu.dtb.data_misses                     262118                       # DTB misses
-system.cpu.dtb.data_acv                            49                       # DTB access violations
-system.cpu.dtb.data_accesses                 38362511                       # DTB accesses
-system.cpu.itb.fetch_hits                    13901400                       # ITB hits
-system.cpu.itb.fetch_misses                     35038                       # ITB misses
+system.cpu.dtb.read_hits                     22395847                       # DTB read hits
+system.cpu.dtb.read_misses                     219375                       # DTB read misses
+system.cpu.dtb.read_acv                            51                       # DTB read access violations
+system.cpu.dtb.read_accesses                 22615222                       # DTB read accesses
+system.cpu.dtb.write_hits                    15705719                       # DTB write hits
+system.cpu.dtb.write_misses                     41176                       # DTB write misses
+system.cpu.dtb.write_acv                            2                       # DTB write access violations
+system.cpu.dtb.write_accesses                15746895                       # DTB write accesses
+system.cpu.dtb.data_hits                     38101566                       # DTB hits
+system.cpu.dtb.data_misses                     260551                       # DTB misses
+system.cpu.dtb.data_acv                            53                       # DTB access violations
+system.cpu.dtb.data_accesses                 38362117                       # DTB accesses
+system.cpu.itb.fetch_hits                    13909771                       # ITB hits
+system.cpu.itb.fetch_misses                     35326                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                13936438                       # ITB accesses
+system.cpu.itb.fetch_accesses                13945097                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -369,238 +329,238 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                 4583                       # Number of system calls
-system.cpu.numCycles                         49753887                       # number of cpu cycles simulated
+system.cpu.numCycles                         49341816                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           15785706                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      105319377                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    16535475                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches            9319096                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      19535939                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 1995771                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles                7614067                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                 7763                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        310803                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles           76                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  13901400                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                208167                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples           44703895                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.355933                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.120018                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           15790710                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      105357061                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    16545461                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            9329115                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      19544756                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 1999793                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles                7570274                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                 7578                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        314157                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles           37                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  13909771                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                205601                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples           44679590                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.358058                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.120608                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 25167956     56.30%     56.30% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  1528006      3.42%     59.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  1366750      3.06%     62.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  1512499      3.38%     66.16% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  4138976      9.26%     75.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  1846420      4.13%     79.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                   671442      1.50%     81.05% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1071050      2.40%     83.44% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                  7400796     16.56%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 25134834     56.26%     56.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  1529938      3.42%     59.68% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  1370308      3.07%     62.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  1511826      3.38%     66.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  4137251      9.26%     75.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  1848058      4.14%     79.53% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                   674230      1.51%     81.04% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1068805      2.39%     83.43% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                  7404340     16.57%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total             44703895                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.332345                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.116807                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 16874554                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles               7142634                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  18558802                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                783225                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                1344680                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              3743647                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                107085                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              103596223                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                302671                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                1344680                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 17346175                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 4853031                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          85455                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  18830704                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               2243850                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              102345999                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                   509                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                   2584                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               2124299                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands            61632193                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             123331325                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        123012632                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups            318692                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total             44679590                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.335323                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.135249                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 16882265                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles               7097756                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  18571135                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                780643                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                1347791                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              3745694                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                106722                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              103639332                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                302042                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                1347791                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 17356196                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 4802628                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          85206                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  18838214                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               2249555                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              102372003                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                   486                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                   2542                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               2130672                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands            61646955                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             123349032                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        123030884                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups            318147                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps              52546881                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                  9085312                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               5523                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts           5521                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                   4830878                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             23230757                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            16269125                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1199559                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores           452349                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                   90724395                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                5268                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                  88415459                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued             94171                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        10689316                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined      4663748                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            685                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples      44703895                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.977802                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.109542                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                  9100074                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               5525                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           5523                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                   4824517                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             23234080                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            16271017                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1195142                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores           460766                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                   90738136                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                5320                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                  88425930                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued             95845                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        10681231                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined      4663960                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            737                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples      44679590                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.979112                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.109137                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            16507369     36.93%     36.93% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1             6840922     15.30%     52.23% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             5582133     12.49%     64.72% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             4775843     10.68%     75.40% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             4724672     10.57%     85.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             2622986      5.87%     91.84% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             1924028      4.30%     96.14% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             1282580      2.87%     99.01% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              443362      0.99%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            16474837     36.87%     36.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1             6839728     15.31%     52.18% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             5595634     12.52%     64.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             4775900     10.69%     75.39% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             4713198     10.55%     85.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             2628457      5.88%     91.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             1926364      4.31%     96.14% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             1289803      2.89%     99.02% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              435669      0.98%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total        44703895                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        44679590                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  126532      6.78%      6.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      6.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      6.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      6.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      6.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      6.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      6.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      6.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      6.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      6.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      6.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      6.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      6.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      6.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      6.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      6.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      6.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      6.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      6.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      6.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      6.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      6.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      6.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      6.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      6.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      6.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      6.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      6.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      6.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                 788261     42.26%     49.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                950494     50.96%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  126495      6.81%      6.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      6.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      6.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      6.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      6.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      6.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      6.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      6.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      6.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      6.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      6.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      6.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      6.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      6.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      6.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      6.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      6.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      6.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      6.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      6.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      6.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      6.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      6.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      6.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      6.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      6.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      6.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      6.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      6.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 783002     42.16%     48.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                947503     51.02%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              49348241     55.81%     55.81% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                43886      0.05%     55.86% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     55.86% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd              121319      0.14%     56.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                  88      0.00%     56.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              49357567     55.82%     55.82% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                43846      0.05%     55.87% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     55.87% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd              121254      0.14%     56.00% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                  91      0.00%     56.00% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCvt              121135      0.14%     56.14% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                 57      0.00%     56.14% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv               38977      0.04%     56.18% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     56.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     56.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     56.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     56.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     56.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     56.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     56.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     56.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     56.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     56.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     56.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     56.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     56.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     56.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     56.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     56.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     56.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     56.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     56.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     56.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     56.18% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             22847876     25.84%     82.02% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            15893880     17.98%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                 59      0.00%     56.14% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv               38967      0.04%     56.19% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     56.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     56.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     56.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     56.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     56.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     56.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     56.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     56.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     56.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     56.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     56.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     56.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     56.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     56.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     56.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     56.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     56.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     56.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     56.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     56.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     56.19% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             22848069     25.84%     82.02% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            15894942     17.98%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total               88415459                       # Type of FU issued
-system.cpu.iq.rate                           1.777056                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     1865287                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.021097                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          222890546                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         101022608                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     86533727                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads              603725                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes             414375                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses       294393                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses               89978801                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                  301945                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          1469946                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total               88425930                       # Type of FU issued
+system.cpu.iq.rate                           1.792109                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     1857000                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.021001                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          222881148                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         101028016                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     86544064                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads              603147                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes             414515                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses       294050                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses               89981281                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                  301649                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1467705                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      2954119                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         4771                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        18244                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      1655748                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      2957442                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         4633                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        18287                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      1657640                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads         3011                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked         95424                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads         2832                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked         88581                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                1344680                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 3730457                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                 74850                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           100207935                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            218697                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              23230757                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             16269125                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               5268                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  49823                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                  6563                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          18244                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         192844                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       159688                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               352532                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts              87575579                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              22621211                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts            839880                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                1347791                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 3663804                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                 77381                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           100225939                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            227298                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              23234080                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             16271017                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               5320                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  49801                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                  6534                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          18287                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         195800                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       160651                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               356451                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts              87582928                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              22618546                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            843002                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                       9478272                       # number of nop insts executed
-system.cpu.iew.exec_refs                     38366084                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 15081989                       # Number of branches executed
-system.cpu.iew.exec_stores                   15744873                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.760176                       # Inst execution rate
-system.cpu.iew.wb_sent                       87218892                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      86828120                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  33348545                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  43472168                       # num instructions consuming a value
+system.cpu.iew.exec_nop                       9482483                       # number of nop insts executed
+system.cpu.iew.exec_refs                     38365741                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 15084551                       # Number of branches executed
+system.cpu.iew.exec_stores                   15747195                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.775024                       # Inst execution rate
+system.cpu.iew.wb_sent                       87227797                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      86838114                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  33351220                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  43473707                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.745152                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.767124                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.759929                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.767158                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts         8870802                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts         8889589                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls            4583                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            308267                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples     43359215                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.037414                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.791048                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts            311933                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples     43331799                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.038703                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.791883                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     20533772     47.36%     47.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1      7032064     16.22%     63.58% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      3351851      7.73%     71.31% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      2056930      4.74%     76.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      2048633      4.72%     80.77% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1170984      2.70%     83.48% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      1108500      2.56%     86.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       718184      1.66%     87.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      5338297     12.31%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     20501224     47.31%     47.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1      7041698     16.25%     63.56% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      3356099      7.75%     71.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      2051116      4.73%     76.04% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      2049317      4.73%     80.77% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1167384      2.69%     83.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      1102119      2.54%     86.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       716210      1.65%     87.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      5346632     12.34%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total     43359215                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total     43331799                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts             88340672                       # Number of instructions committed
 system.cpu.commit.committedOps               88340672                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -611,230 +571,229 @@ system.cpu.commit.branches                   13754477                       # Nu
 system.cpu.commit.fp_insts                     267754                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                  77942044                       # Number of committed integer instructions.
 system.cpu.commit.function_calls              1661057                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events               5338297                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events               5346632                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    133915050                       # The number of ROB reads
-system.cpu.rob.rob_writes                   195770285                       # The number of ROB writes
-system.cpu.timesIdled                           83590                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         5049992                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                    133898086                       # The number of ROB reads
+system.cpu.rob.rob_writes                   195811124                       # The number of ROB writes
+system.cpu.timesIdled                           85852                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         4662226                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                    79591756                       # Number of Instructions Simulated
 system.cpu.committedOps                      79591756                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total              79591756                       # Number of Instructions Simulated
-system.cpu.cpi                               0.625114                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.625114                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.599709                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.599709                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                115901393                       # number of integer regfile reads
-system.cpu.int_regfile_writes                57502981                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                    249622                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                   240154                       # number of floating regfile writes
-system.cpu.misc_regfile_reads                   38048                       # number of misc regfile reads
+system.cpu.cpi                               0.619936                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.619936                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.613069                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.613069                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                115913702                       # number of integer regfile reads
+system.cpu.int_regfile_writes                57508814                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                    249357                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                   240037                       # number of floating regfile writes
+system.cpu.misc_regfile_reads                   38036                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput              1204366702                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq         155800                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp        155799                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       168930                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       143411                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       143411                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       187341                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       580010                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total            767351                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5994880                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     23966080                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total       29960960                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus          29960960                       # Total data (bytes)
+system.cpu.toL2Bus.throughput              1213726946                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq         155524                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp        155523                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       168929                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       143419                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       143419                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       186761                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       580053                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total            766814                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5976320                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     23967424                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total       29943744                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus          29943744                       # Total data (bytes)
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy      403000500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.occupancy      402865000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.6                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy     141888472                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy     141399227                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.6                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy     326227248                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy     324564248                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.3                       # Layer utilization (%)
-system.cpu.icache.tags.replacements             91622                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1926.124790                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            13794941                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             93670                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs            147.271709                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       20019697250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1926.124790                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.940491                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.940491                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements             91332                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1925.493490                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            13803368                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             93380                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs            147.819319                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       19891128250                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst  1925.493490                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.940182                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.940182                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         2048                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           66                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           91                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2            1                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3         1531                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          359                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           73                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           90                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3         1527                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          358                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          27896466                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         27896466                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     13794941                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        13794941                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      13794941                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         13794941                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     13794941                       # number of overall hits
-system.cpu.icache.overall_hits::total        13794941                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       106457                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        106457                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       106457                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         106457                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       106457                       # number of overall misses
-system.cpu.icache.overall_misses::total        106457                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   2019960968                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   2019960968                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst   2019960968                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   2019960968                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst   2019960968                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   2019960968                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     13901398                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     13901398                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     13901398                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     13901398                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     13901398                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     13901398                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.007658                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.007658                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.007658                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.007658                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.007658                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.007658                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18974.430690                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 18974.430690                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 18974.430690                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 18974.430690                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 18974.430690                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 18974.430690                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          691                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses          27912922                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         27912922                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     13803368                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        13803368                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      13803368                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         13803368                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     13803368                       # number of overall hits
+system.cpu.icache.overall_hits::total        13803368                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       106403                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        106403                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       106403                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         106403                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       106403                       # number of overall misses
+system.cpu.icache.overall_misses::total        106403                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   2000796974                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   2000796974                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   2000796974                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   2000796974                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   2000796974                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   2000796974                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     13909771                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     13909771                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     13909771                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     13909771                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     13909771                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     13909771                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.007650                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.007650                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.007650                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.007650                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.007650                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.007650                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18803.952652                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 18803.952652                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 18803.952652                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 18803.952652                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 18803.952652                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 18803.952652                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          263                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                16                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                12                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    43.187500                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    21.916667                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        12786                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        12786                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        12786                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        12786                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        12786                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        12786                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        93671                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        93671                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        93671                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        93671                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        93671                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        93671                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   1551735028                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total   1551735028                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst   1551735028                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total   1551735028                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst   1551735028                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total   1551735028                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.006738                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.006738                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.006738                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.006738                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.006738                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.006738                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16565.799746                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16565.799746                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16565.799746                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 16565.799746                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16565.799746                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 16565.799746                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        13022                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        13022                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        13022                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        13022                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        13022                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        13022                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        93381                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        93381                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        93381                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        93381                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        93381                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        93381                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   1534559773                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total   1534559773                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   1534559773                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total   1534559773                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst   1534559773                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total   1534559773                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.006713                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.006713                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.006713                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.006713                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.006713                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.006713                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16433.319123                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16433.319123                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16433.319123                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 16433.319123                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16433.319123                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 16433.319123                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           132428                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        30694.665852                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs             159970                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           164497                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.972480                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           132391                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        30672.416469                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs             159732                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           164458                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.971263                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 26341.005950                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2105.517354                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  2248.142548                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.803864                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.064255                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.068608                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.936727                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        32069                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          167                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1443                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2        18046                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3        12352                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_blocks::writebacks 26335.603733                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2101.899695                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  2234.913041                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.803699                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.064145                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.068204                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.936048                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        32067                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          179                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1463                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2        18089                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        12275                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4           61                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.978668                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses          4053036                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses         4053036                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst        86004                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data        34262                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total         120266                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       168930                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       168930                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data        12610                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total        12610                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        86004                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data        46872                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total          132876                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst        86004                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data        46872                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         132876                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         7667                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data        27867                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        35534                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       130801                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       130801                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         7667                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       158668                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        166335                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         7667                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       158668                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       166335                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    597389250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data   2119099250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total   2716488500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  13782092500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  13782092500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    597389250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  15901191750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  16498581000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    597389250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  15901191750                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  16498581000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst        93671                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data        62129                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total       155800                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       168930                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       168930                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       143411                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       143411                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        93671                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       205540                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       299211                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        93671                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       205540                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       299211                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.081850                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.448535                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.228074                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.912071                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.912071                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.081850                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.771957                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.555912                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.081850                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.771957                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.555912                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77916.949263                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76043.321850                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 76447.585411                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 105366.874106                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 105366.874106                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77916.949263                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 100216.752905                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 99188.871855                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77916.949263                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 100216.752905                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 99188.871855                       # average overall miss latency
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.978607                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses          4050853                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses         4050853                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst        85734                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data        34287                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         120021                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       168929                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       168929                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data        12621                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total        12621                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst        85734                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data        46908                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          132642                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst        85734                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data        46908                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         132642                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         7647                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data        27856                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        35503                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       130798                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       130798                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         7647                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       158654                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        166301                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         7647                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       158654                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       166301                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    583211250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data   2050433250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   2633644500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  13218958750                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  13218958750                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    583211250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  15269392000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  15852603250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    583211250                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  15269392000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  15852603250                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst        93381                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data        62143                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       155524                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       168929                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       168929                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       143419                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       143419                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        93381                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       205562                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       298943                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        93381                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       205562                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       298943                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.081890                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.448256                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.228280                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.911999                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.911999                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.081890                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.771806                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.556297                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.081890                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.771806                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.556297                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76266.673205                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73608.315982                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 74180.900206                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101063.921084                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101063.921084                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76266.673205                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 96243.347158                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 95324.762028                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76266.673205                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 96243.347158                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 95324.762028                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -843,171 +802,171 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       114019                       # number of writebacks
-system.cpu.l2cache.writebacks::total           114019                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         7667                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        27867                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        35534                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       130801                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       130801                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         7667                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       158668                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       166335                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         7667                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       158668                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       166335                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    500389250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1762290750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2262680000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  12178041500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  12178041500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    500389250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  13940332250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  14440721500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    500389250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  13940332250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  14440721500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.081850                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.448535                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.228074                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.912071                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.912071                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.081850                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.771957                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.555912                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.081850                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.771957                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.555912                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65265.325421                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63239.342233                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63676.478865                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 93103.581012                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 93103.581012                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65265.325421                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 87858.498563                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 86817.095019                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65265.325421                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 87858.498563                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86817.095019                       # average overall mshr miss latency
+system.cpu.l2cache.writebacks::writebacks       114017                       # number of writebacks
+system.cpu.l2cache.writebacks::total           114017                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         7647                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        27856                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        35503                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       130798                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       130798                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         7647                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       158654                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       166301                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         7647                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       158654                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       166301                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    486616750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1695026750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2181643500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  11619308250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  11619308250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    486616750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  13314335000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  13800951750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    486616750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  13314335000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  13800951750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.081890                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.448256                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.228280                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.911999                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.911999                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.081890                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.771806                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.556297                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.081890                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.771806                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.556297                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63634.987577                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60849.610497                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61449.553559                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88833.990199                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88833.990199                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63634.987577                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83920.575592                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 82987.785702                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63634.987577                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83920.575592                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 82987.785702                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements            201444                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4074.011744                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            34183901                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            205540                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            166.312645                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         220306250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4074.011744                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.994632                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.994632                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements            201466                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4073.410780                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            34191132                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            205562                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            166.330022                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         225470250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4073.410780                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.994485                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.994485                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           78                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         1078                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         2940                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           82                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         1081                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         2933                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          71186914                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         71186914                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     20609776                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        20609776                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     13574069                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       13574069                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data           56                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total           56                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data      34183845                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         34183845                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     34183845                       # number of overall hits
-system.cpu.dcache.overall_hits::total        34183845                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       267478                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        267478                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1039308                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1039308                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      1306786                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1306786                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1306786                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1306786                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  16319754498                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  16319754498                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  88798095012                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  88798095012                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 105117849510                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 105117849510                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 105117849510                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 105117849510                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     20877254                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     20877254                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses          71201646                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         71201646                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     20617040                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        20617040                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     13574040                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       13574040                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data           52                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total           52                       # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits::cpu.data      34191080                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         34191080                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     34191080                       # number of overall hits
+system.cpu.dcache.overall_hits::total        34191080                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       267573                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        267573                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1039337                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1039337                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      1306910                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1306910                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1306910                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1306910                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  15791609498                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  15791609498                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  85266584825                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  85266584825                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 101058194323                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 101058194323                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 101058194323                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 101058194323                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     20884613                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     20884613                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     14613377                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     14613377                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data           56                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total           56                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     35490631                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     35490631                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     35490631                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     35490631                       # number of overall (read+write) accesses
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data           52                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total           52                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     35497990                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     35497990                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     35497990                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     35497990                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.012812                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.012812                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.071120                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.071120                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.036821                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.036821                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.036821                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.036821                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61013.445958                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 61013.445958                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 85439.633883                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 85439.633883                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 80439.987504                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 80439.987504                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 80439.987504                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 80439.987504                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs      5138864                       # number of cycles access was blocked
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.071122                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.071122                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.036816                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.036816                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.036816                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.036816                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59017.948365                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 59017.948365                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 82039.400911                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 82039.400911                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 77326.054834                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 77326.054834                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 77326.054834                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 77326.054834                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs      4861037                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets          131                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs            112181                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs            111685                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               1                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    45.808684                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    43.524529                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          131                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       168930                       # number of writebacks
-system.cpu.dcache.writebacks::total            168930                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       205345                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       205345                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       895901                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       895901                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1101246                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1101246                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1101246                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1101246                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data        62133                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total        62133                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       143407                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       143407                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       205540                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       205540                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       205540                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       205540                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   2525887252                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   2525887252                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  14052510994                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  14052510994                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  16578398246                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  16578398246                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  16578398246                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  16578398246                       # number of overall MSHR miss cycles
+system.cpu.dcache.writebacks::writebacks       168929                       # number of writebacks
+system.cpu.dcache.writebacks::total            168929                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       205428                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       205428                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       895920                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       895920                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      1101348                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1101348                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1101348                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1101348                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data        62145                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total        62145                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       143417                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       143417                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       205562                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       205562                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       205562                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       205562                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   2457360502                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   2457360502                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  13489619744                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  13489619744                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  15946980246                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  15946980246                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  15946980246                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  15946980246                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002976                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002976                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009813                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009813                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009814                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009814                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.005791                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total     0.005791                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.005791                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.005791                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40652.909919                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40652.909919                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 97990.411863                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 97990.411863                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80657.770974                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 80657.770974                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80657.770974                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 80657.770974                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39542.368686                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39542.368686                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 94058.722076                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 94058.722076                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77577.471741                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 77577.471741                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77577.471741                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 77577.471741                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 9978094b9c40b79dc0047ff4dd91ed002b9a22d2..e2e70aeb1ab16ab02a246c0b6700121a188aa84a 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.026790                       # Number of seconds simulated
-sim_ticks                                 26790388000                       # Number of ticks simulated
-final_tick                                26790388000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.026596                       # Number of seconds simulated
+sim_ticks                                 26596403000                       # Number of ticks simulated
+final_tick                                26596403000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 134448                       # Simulator instruction rate (inst/s)
-host_op_rate                                   190799                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               50797444                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 278572                       # Number of bytes of host memory used
-host_seconds                                   527.40                       # Real time elapsed on the host
+host_inst_rate                                 110554                       # Simulator instruction rate (inst/s)
+host_op_rate                                   156889                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               41466984                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 321816                       # Number of bytes of host memory used
+host_seconds                                   641.39                       # Real time elapsed on the host
 sim_insts                                    70907629                       # Number of instructions simulated
 sim_ops                                     100626876                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            297344                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           7942912                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              8240256                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       297344                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          297344                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      5371968                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           5371968                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               4646                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             124108                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                128754                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           83937                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                83937                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst             11098906                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            296483649                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               307582555                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst        11098906                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total           11098906                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks         200518484                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              200518484                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks         200518484                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst            11098906                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           296483649                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              508101040                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        128754                       # Number of read requests accepted
-system.physmem.writeReqs                        83937                       # Number of write requests accepted
-system.physmem.readBursts                      128754                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      83937                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  8240128                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                       128                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   5371648                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   8240256                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                5371968                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                        2                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst            297984                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           7942976                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              8240960                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       297984                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          297984                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      5372480                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           5372480                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               4656                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             124109                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                128765                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           83945                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                83945                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst             11203921                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            298648505                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               309852426                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst        11203921                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total           11203921                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks         202000248                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              202000248                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks         202000248                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst            11203921                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           298648505                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              511852674                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        128766                       # Number of read requests accepted
+system.physmem.writeReqs                        83945                       # Number of write requests accepted
+system.physmem.readBursts                      128766                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      83945                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  8240704                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                       320                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   5371136                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   8241024                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                5372480                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                        5                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs            308                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                8131                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                8390                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                8247                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                8163                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                8302                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                8446                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                8088                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                7962                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                8060                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                7613                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               7786                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               7812                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               7879                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               7885                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               7978                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               8010                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                5179                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                5375                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs            300                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0                8143                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                8388                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                8255                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                8165                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                8298                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                8451                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                8084                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                7964                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                8055                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                7611                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               7782                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               7815                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               7881                       # Per bank write bursts
+system.physmem.perBankRdBursts::13               7884                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               7976                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               8009                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                5177                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                5376                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                5289                       # Per bank write bursts
 system.physmem.perBankWrBursts::3                5157                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                5265                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                5267                       # Per bank write bursts
 system.physmem.perBankWrBursts::5                5517                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                5207                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                5048                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                5029                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                5201                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                5049                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                5030                       # Per bank write bursts
 system.physmem.perBankWrBursts::9                5089                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               5251                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               5246                       # Per bank write bursts
 system.physmem.perBankWrBursts::11               5144                       # Per bank write bursts
 system.physmem.perBankWrBursts::12               5342                       # Per bank write bursts
 system.physmem.perBankWrBursts::13               5363                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               5451                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               5226                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               5452                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               5225                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     26790282500                       # Total gap between requests
+system.physmem.totGap                     26596386500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  128754                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  128766                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  83937                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     73147                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     54223                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      1319                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        57                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         6                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  83945                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     71874                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     54925                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      1900                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        55                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         7                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -129,219 +129,173 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                      3672                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                      3689                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                      3689                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                      3683                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                      3681                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                      3683                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                      3687                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                      3686                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                      3681                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                      3678                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                     3681                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                     3680                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                     3686                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                     3683                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                     3698                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     3772                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     3751                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     3941                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     3889                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     3936                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     4300                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5019                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                       63                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        37879                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      359.276222                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     174.215706                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     692.456870                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64-65          15075     39.80%     39.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-129         5750     15.18%     54.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192-193         3421      9.03%     64.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-257         2320      6.12%     70.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320-321         1668      4.40%     74.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-385         1547      4.08%     78.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448-449         1100      2.90%     81.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-513          895      2.36%     83.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576-577          687      1.81%     85.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-641          539      1.42%     87.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704-705          385      1.02%     88.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-769          594      1.57%     89.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832-833          272      0.72%     90.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-897          354      0.93%     91.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960-961          173      0.46%     91.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1025          239      0.63%     92.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088-1089          118      0.31%     92.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152-1153          247      0.65%     93.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216-1217          108      0.29%     93.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280-1281          279      0.74%     94.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344-1345          118      0.31%     94.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408-1409          446      1.18%     95.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472-1473          106      0.28%     96.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536-1537          237      0.63%     96.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600-1601           43      0.11%     96.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664-1665          118      0.31%     97.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1728-1729           42      0.11%     97.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1792-1793           85      0.22%     97.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856-1857           20      0.05%     97.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1920-1921           62      0.16%     97.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984-1985           22      0.06%     97.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2048-2049           44      0.12%     97.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112-2113           19      0.05%     98.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2176-2177           33      0.09%     98.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2240-2241           16      0.04%     98.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2304-2305           33      0.09%     98.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2368-2369            8      0.02%     98.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2432-2433           24      0.06%     98.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2496-2497           13      0.03%     98.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2560-2561           33      0.09%     98.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2624-2625           14      0.04%     98.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2688-2689           23      0.06%     98.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2752-2753           10      0.03%     98.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2816-2817           16      0.04%     98.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2880-2881            9      0.02%     98.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2944-2945           18      0.05%     98.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3008-3009            4      0.01%     98.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3072-3073           17      0.04%     98.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3136-3137           11      0.03%     98.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3200-3201           19      0.05%     98.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3264-3265           11      0.03%     98.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3328-3329           26      0.07%     98.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3392-3393            4      0.01%     98.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3456-3457            7      0.02%     98.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3520-3521           10      0.03%     98.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3584-3585            5      0.01%     98.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3648-3649            7      0.02%     99.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3712-3713           10      0.03%     99.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3776-3777            5      0.01%     99.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3840-3841            9      0.02%     99.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3904-3905            4      0.01%     99.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3968-3969           16      0.04%     99.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4032-4033            7      0.02%     99.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4096-4097            9      0.02%     99.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4160-4161            5      0.01%     99.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4224-4225           10      0.03%     99.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4288-4289           10      0.03%     99.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4352-4353           11      0.03%     99.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4416-4417            6      0.02%     99.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4480-4481           10      0.03%     99.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4544-4545            7      0.02%     99.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4608-4609            6      0.02%     99.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4672-4673            5      0.01%     99.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4736-4737            5      0.01%     99.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4800-4801            2      0.01%     99.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4864-4865           12      0.03%     99.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4928-4929            4      0.01%     99.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4992-4993            8      0.02%     99.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5056-5057            5      0.01%     99.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5120-5121            9      0.02%     99.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5184-5185            2      0.01%     99.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5248-5249            7      0.02%     99.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5312-5313            4      0.01%     99.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5376-5377            6      0.02%     99.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5440-5441            5      0.01%     99.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5504-5505            7      0.02%     99.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5568-5569            7      0.02%     99.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5632-5633           10      0.03%     99.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5696-5697            4      0.01%     99.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5760-5761            3      0.01%     99.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5824-5825            5      0.01%     99.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5888-5889            2      0.01%     99.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5952-5953            4      0.01%     99.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6016-6017            1      0.00%     99.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6080-6081            5      0.01%     99.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6144-6145            6      0.02%     99.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6208-6209            6      0.02%     99.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6272-6273            3      0.01%     99.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6336-6337            5      0.01%     99.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6400-6401            4      0.01%     99.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6464-6465            5      0.01%     99.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6528-6529            1      0.00%     99.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6592-6593            4      0.01%     99.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6656-6657            4      0.01%     99.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6720-6721            5      0.01%     99.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6784-6785            5      0.01%     99.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6848-6849            1      0.00%     99.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6912-6913            4      0.01%     99.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6976-6977            4      0.01%     99.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7040-7041            5      0.01%     99.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7104-7105            1      0.00%     99.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7168-7169            1      0.00%     99.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7232-7233            2      0.01%     99.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7296-7297            3      0.01%     99.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7424-7425            3      0.01%     99.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7552-7553            1      0.00%     99.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7680-7681            3      0.01%     99.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7744-7745            3      0.01%     99.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7872-7873            1      0.00%     99.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7936-7937            1      0.00%     99.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8064-8065            4      0.01%     99.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8128-8129            6      0.02%     99.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8192-8193           37      0.10%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          37879                       # Bytes accessed per row activation
-system.physmem.totQLat                     3022726750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                4971045500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    643760000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                  1304558750                       # Total ticks spent accessing banks
-system.physmem.avgQLat                       23477.12                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    10132.34                       # Average bank access latency per DRAM burst
+system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      478                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      495                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                      840                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     2288                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     3768                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     4393                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     4872                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     5100                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     5159                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     5216                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     5492                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     5691                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     5740                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     6272                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     6389                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     5693                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     5625                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     5394                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     2900                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      953                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      409                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      107                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                       92                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                       72                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                       63                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                       49                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                       50                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                       43                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                       37                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                       36                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                       31                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                       34                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                       26                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                       24                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                       22                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       20                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       19                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       19                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       19                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        29627                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      410.695649                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     253.351666                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     359.831379                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127           7793     26.30%     26.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         6034     20.37%     46.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         3130     10.56%     57.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2203      7.44%     64.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2053      6.93%     71.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1365      4.61%     76.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1045      3.53%     79.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1191      4.02%     83.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         4813     16.25%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          29627                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5084                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        25.322974                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      394.325536                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           5082     99.96%     99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047            1      0.02%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::27648-28671            1      0.02%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            5084                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5084                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.507474                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.421096                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        2.063173                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               4555     89.59%     89.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 21      0.41%     90.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                 58      1.14%     91.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                170      3.34%     94.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                125      2.46%     96.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 57      1.12%     98.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 23      0.45%     98.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 15      0.30%     98.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                 10      0.20%     99.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                  6      0.12%     99.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                  5      0.10%     99.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27                  5      0.10%     99.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28                  4      0.08%     99.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29                  2      0.04%     99.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30                  4      0.08%     99.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::31                  2      0.04%     99.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::33                  1      0.02%     99.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::35                  1      0.02%     99.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36                  1      0.02%     99.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::37                  1      0.02%     99.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::39                 13      0.26%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40                  3      0.06%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::42                  1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48                  1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5084                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     2537399000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                4590111500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    643805000                       # Total ticks spent in databus transfers
+system.physmem.totBankLat                  1408907500                       # Total ticks spent accessing banks
+system.physmem.avgQLat                       19706.27                       # Average queueing delay per DRAM burst
+system.physmem.avgBankLat                    10942.04                       # Average bank access latency per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  38609.46                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         307.58                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                         200.51                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      307.58                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                      200.52                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  35648.31                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         309.84                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                         201.95                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      309.85                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                      202.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           3.97                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       2.40                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      1.57                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         0.19                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                         9.70                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     117872                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     56933                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   91.55                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  67.83                       # Row buffer hit rate for writes
-system.physmem.avgGap                       125958.70                       # Average gap between requests
-system.physmem.pageHitRate                      82.19                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent              11.78                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                    508101040                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq               26500                       # Transaction distribution
-system.membus.trans_dist::ReadResp              26500                       # Transaction distribution
-system.membus.trans_dist::Writeback             83937                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              308                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp             308                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            102254                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           102254                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       342061                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 342061                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     13612224                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            13612224                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus               13612224                       # Total data (bytes)
+system.physmem.busUtil                           4.00                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       2.42                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      1.58                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.36                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        25.09                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     112537                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     62593                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   87.40                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  74.56                       # Row buffer hit rate for writes
+system.physmem.avgGap                       125035.31                       # Average gap between requests
+system.physmem.pageHitRate                      82.33                       # Row buffer hit rate, read and write combined
+system.physmem.prechargeAllPercent              11.63                       # Percentage of time for which DRAM has all the banks in precharge state
+system.membus.throughput                    511852674                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq               26511                       # Transaction distribution
+system.membus.trans_dist::ReadResp              26510                       # Transaction distribution
+system.membus.trans_dist::Writeback             83945                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq              300                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp             300                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            102255                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           102255                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       342076                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 342076                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     13613440                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total            13613440                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               13613440                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy           934459500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy           934794000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               3.5                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         1203485442                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         1201882201                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              4.5                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                16615535                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          12754556                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            602333                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             10795457                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 7770077                       # Number of BTB hits
+system.cpu.branchPred.lookups                16626299                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          12761376                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            603542                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             10553987                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 7772041                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             71.975434                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1823925                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect             112966                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             73.640805                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1823891                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             112970                       # Number of incorrect RAS predictions.
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -427,136 +381,136 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                 1946                       # Number of system calls
-system.cpu.numCycles                         53580777                       # number of cpu cycles simulated
+system.cpu.numCycles                         53192807                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           12546836                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                       85170403                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    16615535                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches            9594002                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      21183792                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 2362024                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles               10685029                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                   63                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles           557                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles           20                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  11675856                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                179932                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples           46149323                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.583841                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.333163                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           12548027                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                       85225985                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    16626299                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            9595932                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      21195811                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 2371567                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles               10764095                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                  172                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles           524                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles           23                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  11679981                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                179230                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples           46249849                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.580108                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.332376                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 24986446     54.14%     54.14% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  2137638      4.63%     58.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  1962079      4.25%     63.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  2043997      4.43%     67.46% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  1466310      3.18%     70.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  1377582      2.99%     73.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                   960310      2.08%     75.70% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1185958      2.57%     78.27% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 10029003     21.73%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 25074842     54.22%     54.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  2134843      4.62%     58.83% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  1965334      4.25%     63.08% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  2045724      4.42%     67.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  1467866      3.17%     70.68% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  1377638      2.98%     73.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                   956719      2.07%     75.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1188096      2.57%     78.29% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 10038787     21.71%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total             46149323                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.310103                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.589570                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 14635353                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles               9029918                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  19485051                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               1368887                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                1630114                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              3325603                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                104819                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              116788167                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                363460                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                1630114                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 16340014                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 2585458                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles        1028005                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  19100045                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               5465687                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              114914880                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                   172                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                  17272                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               4606354                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents              316                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           115243032                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             529540867                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        476170049                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups              2600                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total             46249849                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.312567                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.602209                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 14635842                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles               9109376                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  19493309                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               1372783                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                1638539                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              3331010                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                104505                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              116880506                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                361697                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                1638539                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 16346771                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 2652791                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles        1020533                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  19105290                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               5485925                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              114999580                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                   152                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                  17445                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               4623062                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents              183                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           115318587                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             529932404                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        476522297                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups              2751                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps              99132672                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 16110360                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts              20388                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts          20384                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  12995984                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             29602749                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            22439249                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           3932152                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          4401403                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  111507434                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded               36062                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 107242523                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            272405                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        10768427                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     25739903                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved           2276                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples      46149323                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.323816                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.990206                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                 16185915                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts              20374                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts          20369                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  13024660                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             29615928                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            22451967                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           3877153                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          4417845                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  111572377                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded               35991                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 107273861                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            274045                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        10831021                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     25918238                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           2205                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples      46249849                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.319442                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.990414                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            10919279     23.66%     23.66% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1             8079518     17.51%     41.17% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             7423472     16.09%     57.25% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             7094481     15.37%     72.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             5420902     11.75%     84.37% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             3930329      8.52%     92.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             1841974      3.99%     96.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              869423      1.88%     98.76% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              569945      1.24%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            10978806     23.74%     23.74% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1             8116860     17.55%     41.29% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             7434269     16.07%     57.36% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             7097763     15.35%     72.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             5421519     11.72%     84.43% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             3913580      8.46%     92.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             1842525      3.98%     96.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              870168      1.88%     98.76% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              574359      1.24%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total        46149323                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        46249849                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  112279      4.53%      4.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      4.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      4.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     2      0.00%      4.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      4.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      4.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      4.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      4.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      4.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      4.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      4.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      4.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      4.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      4.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      4.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      4.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      4.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      4.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      4.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      4.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      4.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      4.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      4.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      4.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      4.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      4.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      4.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      4.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      4.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                1361817     54.98%     59.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               1002641     40.48%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  113368      4.58%      4.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      4.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      4.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     2      0.00%      4.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      4.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      4.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      4.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      4.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      4.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      4.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      4.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      4.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      4.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      4.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      4.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      4.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      4.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      4.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      4.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      4.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      4.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      4.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      4.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      4.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      4.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      4.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      4.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      4.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      4.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                1353818     54.73%     59.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               1006223     40.68%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              56635396     52.81%     52.81% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                91455      0.09%     52.90% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              56655592     52.81%     52.81% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                91505      0.09%     52.90% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     52.90% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                 208      0.00%     52.90% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                 217      0.00%     52.90% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     52.90% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     52.90% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     52.90% # Type of FU issued
@@ -582,84 +536,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              7      0.00%     52.90% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     52.90% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     52.90% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     52.90% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             28883502     26.93%     79.83% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            21631955     20.17%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             28893939     26.93%     79.83% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            21632601     20.17%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              107242523                       # Type of FU issued
-system.cpu.iq.rate                           2.001511                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     2476739                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.023095                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          263382945                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         122340040                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    105564996                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 568                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                856                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses          168                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              109718975                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     287                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          2181751                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              107273861                       # Type of FU issued
+system.cpu.iq.rate                           2.016699                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2473411                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.023057                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          263544444                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         122467509                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    105589962                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 583                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                918                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses          177                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              109746981                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     291                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          2178933                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      2295641                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         6455                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        29983                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      1883511                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      2308820                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         6717                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        29962                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      1896229                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads           31                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked           679                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads           29                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked           670                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                1630114                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 1093825                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                 45147                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           111553302                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            294819                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              29602749                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             22439249                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts              20142                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                   6322                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                  5200                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          29983                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         391827                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       180696                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               572523                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             106211851                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              28585179                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           1030672                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                1638539                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 1135526                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                 46796                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           111618146                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            297287                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              29615928                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             22451967                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts              20071                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                   6522                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                  5186                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          29962                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         392730                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       181164                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               573894                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             106245086                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              28594669                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1028775                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                          9806                       # number of nop insts executed
-system.cpu.iew.exec_refs                     49926975                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 14599283                       # Number of branches executed
-system.cpu.iew.exec_stores                   21341796                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.982275                       # Inst execution rate
-system.cpu.iew.wb_sent                      105782073                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     105565164                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  53316718                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 103963305                       # num instructions consuming a value
+system.cpu.iew.exec_nop                          9778                       # number of nop insts executed
+system.cpu.iew.exec_refs                     49940992                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 14602318                       # Number of branches executed
+system.cpu.iew.exec_stores                   21346323                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.997358                       # Inst execution rate
+system.cpu.iew.wb_sent                      105809508                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     105590139                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  53305824                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 103866304                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.970206                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.512842                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.985045                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.513216                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        10921742                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts        10986690                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls           33786                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            499421                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples     44519209                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.260427                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.765009                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts            500884                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples     44611310                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.255760                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.762475                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     15470185     34.75%     34.75% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     11634994     26.13%     60.88% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      3452010      7.75%     68.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      2868846      6.44%     75.08% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1865323      4.19%     79.27% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1954753      4.39%     83.66% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       686748      1.54%     85.21% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       559469      1.26%     86.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      6026881     13.54%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     15517142     34.78%     34.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     11686207     26.20%     60.98% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      3450926      7.74%     68.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      2867812      6.43%     75.14% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1872959      4.20%     79.34% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1945129      4.36%     83.70% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       689747      1.55%     85.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       566134      1.27%     86.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      6015254     13.48%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total     44519209                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total     44611310                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts             70913181                       # Number of instructions committed
 system.cpu.commit.committedOps              100632428                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -670,243 +624,243 @@ system.cpu.commit.branches                   13741485                       # Nu
 system.cpu.commit.fp_insts                         56                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                  91472779                       # Number of committed integer instructions.
 system.cpu.commit.function_calls              1679850                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events               6026881                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events               6015254                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    150021199                       # The number of ROB reads
-system.cpu.rob.rob_writes                   224747411                       # The number of ROB writes
-system.cpu.timesIdled                           76674                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         7431454                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                    150189875                       # The number of ROB reads
+system.cpu.rob.rob_writes                   224886049                       # The number of ROB writes
+system.cpu.timesIdled                           80066                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         6942958                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                    70907629                       # Number of Instructions Simulated
 system.cpu.committedOps                     100626876                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total              70907629                       # Number of Instructions Simulated
-system.cpu.cpi                               0.755642                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.755642                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.323378                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.323378                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                511545132                       # number of integer regfile reads
-system.cpu.int_regfile_writes               103340839                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                       806                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                      694                       # number of floating regfile writes
-system.cpu.misc_regfile_reads                49339612                       # number of misc regfile reads
+system.cpu.cpi                               0.750170                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.750170                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.333030                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.333030                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                511686083                       # number of integer regfile reads
+system.cpu.int_regfile_writes               103364033                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                       870                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                      762                       # number of floating regfile writes
+system.cpu.misc_regfile_reads                49348247                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                  31840                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput               773036658                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq          87363                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp         87363                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       129182                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq          325                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp          325                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       107048                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       107048                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        63452                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       454686                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total            518138                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2013952                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     18662976                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total       20676928                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus          20676928                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus        33024                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy      291143497                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.throughput               778162370                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq          87191                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp         87190                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       129156                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq          314                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp          314                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       107034                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       107034                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        63123                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       454609                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total            517732                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2003904                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     18660352                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total       20664256                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus          20664256                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus        32064                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy      291006496                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      48712731                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      48441979                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy     260354993                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy     259878236                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.0                       # Layer utilization (%)
-system.cpu.icache.tags.replacements             29638                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1806.211071                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            11640103                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             31672                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs            367.520302                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements             29471                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1806.055358                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            11644351                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             31508                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs            369.568078                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1806.211071                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.881939                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.881939                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         2034                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           89                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           18                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3         1251                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          676                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.993164                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          23383696                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         23383696                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     11640118                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        11640118                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      11640118                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         11640118                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     11640118                       # number of overall hits
-system.cpu.icache.overall_hits::total        11640118                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        35738                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         35738                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        35738                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          35738                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        35738                       # number of overall misses
-system.cpu.icache.overall_misses::total         35738                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    828271479                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    828271479                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    828271479                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    828271479                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    828271479                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    828271479                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     11675856                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     11675856                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     11675856                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     11675856                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     11675856                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     11675856                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.003061                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.003061                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.003061                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.003061                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.003061                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.003061                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23176.212407                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 23176.212407                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 23176.212407                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 23176.212407                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 23176.212407                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 23176.212407                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          856                       # number of cycles access was blocked
+system.cpu.icache.tags.occ_blocks::cpu.inst  1806.055358                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.881863                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.881863                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         2037                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           84                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           19                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3         1253                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          681                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.994629                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          23391772                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         23391772                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     11644361                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        11644361                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      11644361                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         11644361                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     11644361                       # number of overall hits
+system.cpu.icache.overall_hits::total        11644361                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        35619                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         35619                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        35619                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          35619                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        35619                       # number of overall misses
+system.cpu.icache.overall_misses::total         35619                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    813918226                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    813918226                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    813918226                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    813918226                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    813918226                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    813918226                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     11679980                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     11679980                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     11679980                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     11679980                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     11679980                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     11679980                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.003050                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.003050                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.003050                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.003050                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.003050                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.003050                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22850.675931                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 22850.675931                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 22850.675931                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 22850.675931                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 22850.675931                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 22850.675931                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         1148                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                20                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                22                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    42.800000                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    52.181818                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         3754                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         3754                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         3754                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         3754                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         3754                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         3754                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        31984                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        31984                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        31984                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        31984                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        31984                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        31984                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    671357769                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    671357769                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    671357769                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    671357769                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    671357769                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    671357769                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.002739                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.002739                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.002739                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.002739                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.002739                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.002739                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20990.425494                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20990.425494                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20990.425494                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 20990.425494                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20990.425494                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 20990.425494                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         3807                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         3807                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         3807                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         3807                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         3807                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         3807                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        31812                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        31812                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        31812                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        31812                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        31812                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        31812                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    661574021                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    661574021                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    661574021                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    661574021                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    661574021                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    661574021                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.002724                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.002724                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.002724                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.002724                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.002724                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.002724                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20796.366811                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20796.366811                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20796.366811                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 20796.366811                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20796.366811                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 20796.366811                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements            95620                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        29882.992791                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs              89182                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           126734                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.703694                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements            95635                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        29857.974256                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs              88990                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           126748                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.702102                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 26677.610156                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  1366.039955                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  1839.342681                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.814136                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.041688                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.056132                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.911957                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        31114                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          144                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1849                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2        20244                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         8486                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4          391                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.949524                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses          2821016                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses         2821016                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst        26805                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data        33463                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total          60268                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       129182                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       129182                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data           17                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total           17                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data         4794                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total         4794                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        26805                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data        38257                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total           65062                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst        26805                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data        38257                       # number of overall hits
-system.cpu.l2cache.overall_hits::total          65062                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         4663                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data        21916                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        26579                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data          308                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total          308                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       102254                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       102254                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         4663                       # number of demand (read+write) misses
+system.cpu.l2cache.tags.occ_blocks::writebacks 26666.144476                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  1368.316766                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  1823.513014                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.813786                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.041758                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.055649                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.911193                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        31113                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          137                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1837                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2        20828                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         7917                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4          394                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.949493                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses          2819349                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses         2819349                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst        26638                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data        33464                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total          60102                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       129156                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       129156                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data           14                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total           14                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data         4779                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total         4779                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst        26638                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data        38243                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total           64881                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst        26638                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data        38243                       # number of overall hits
+system.cpu.l2cache.overall_hits::total          64881                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         4673                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data        21915                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        26588                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data          300                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total          300                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       102255                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       102255                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         4673                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.data       124170                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        128833                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         4663                       # number of overall misses
+system.cpu.l2cache.demand_misses::total        128843                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         4673                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data       124170                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       128833                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    370582250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1870540500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total   2241122750                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data        22999                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total        22999                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   8514187000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   8514187000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    370582250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  10384727500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  10755309750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    370582250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  10384727500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  10755309750                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst        31468                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.overall_misses::total       128843                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    362632500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1783611000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   2146243500                       # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data        23499                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total        23499                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   8210815250                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   8210815250                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    362632500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   9994426250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  10357058750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    362632500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   9994426250                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  10357058750                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst        31311                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data        55379                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total        86847                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       129182                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       129182                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data          325                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total          325                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       107048                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       107048                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        31468                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       162427                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       193895                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        31468                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       162427                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       193895                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.148182                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.395746                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.306044                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.947692                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.947692                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.955216                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.955216                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.148182                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.764466                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.664447                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.148182                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.764466                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.664447                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79472.925155                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85350.451725                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 84319.302833                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data    74.672078                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total    74.672078                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83265.075205                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83265.075205                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79472.925155                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83633.144077                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 83482.568519                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79472.925155                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83633.144077                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 83482.568519                       # average overall miss latency
+system.cpu.l2cache.ReadReq_accesses::total        86690                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       129156                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       129156                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data          314                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total          314                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       107034                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       107034                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        31311                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       162413                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       193724                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        31311                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       162413                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       193724                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.149245                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.395728                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.306702                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.955414                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.955414                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.955351                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.955351                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.149245                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.764532                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.665085                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.149245                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.764532                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.665085                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77601.647764                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 81387.679671                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 80722.261923                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data    78.330000                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total    78.330000                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80297.445113                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80297.445113                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77601.647764                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80489.862688                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 80385.110173                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77601.647764                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80489.862688                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 80385.110173                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -915,202 +869,202 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        83937                       # number of writebacks
-system.cpu.l2cache.writebacks::total            83937                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks        83945                       # number of writebacks
+system.cpu.l2cache.writebacks::total            83945                       # number of writebacks
 system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           17                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           62                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total           79                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           60                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total           77                       # number of ReadReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.inst           17                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data           62                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total           79                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data           60                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           77                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.inst           17                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data           62                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total           79                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         4646                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        21854                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        26500                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data          308                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total          308                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       102254                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       102254                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         4646                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       124108                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       128754                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         4646                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       124108                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       128754                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    311360750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1593475000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1904835750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      3080308                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      3080308                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7238548000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7238548000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    311360750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   8832023000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   9143383750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    311360750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8832023000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   9143383750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.147642                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.394626                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.305134                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.947692                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.947692                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.955216                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.955216                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.147642                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.764085                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.664040                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.147642                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.764085                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.664040                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67016.950065                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 72914.569415                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71880.594340                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        10001                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70789.876191                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70789.876191                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67016.950065                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71164.010378                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71014.366544                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67016.950065                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71164.010378                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71014.366544                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_hits::cpu.data           60                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total           77                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         4656                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        21855                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        26511                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data          300                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total          300                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       102255                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       102255                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         4656                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       124110                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       128766                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         4656                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       124110                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       128766                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    303015250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1507731500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1810746750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      3014299                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      3014299                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6936413750                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6936413750                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    303015250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   8444145250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   8747160500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    303015250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8444145250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   8747160500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.148702                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.394644                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.305814                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.955414                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.955414                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.955351                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.955351                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.148702                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.764163                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.664688                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.148702                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.764163                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.664688                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65080.594931                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68987.943262                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68301.714383                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10047.663333                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10047.663333                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67834.470197                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67834.470197                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65080.594931                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68037.589638                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67930.668810                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65080.594931                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68037.589638                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67930.668810                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements            158331                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4068.839586                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            44347897                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            162427                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            273.032790                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         363282250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4068.839586                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.993369                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.993369                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements            158316                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4068.473281                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            44361466                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            162412                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            273.141554                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         367394250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4068.473281                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.993280                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.993280                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           66                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         1776                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         2254                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         1757                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         2276                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          92273995                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         92273995                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     26048802                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        26048802                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     18266579                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       18266579                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data        15981                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total        15981                       # number of LoadLockedReq hits
+system.cpu.dcache.tags.tag_accesses          92298894                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         92298894                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     26061245                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        26061245                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     18267715                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       18267715                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data        15989                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total        15989                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data        15919                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total        15919                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      44315381                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         44315381                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     44315381                       # number of overall hits
-system.cpu.dcache.overall_hits::total        44315381                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       125140                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        125140                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1583322                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1583322                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data           41                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total           41                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      1708462                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1708462                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1708462                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1708462                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   5205484954                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   5205484954                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 127036653749                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 127036653749                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       856750                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total       856750                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 132242138703                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 132242138703                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 132242138703                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 132242138703                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     26173942                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     26173942                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_hits::cpu.data      44328960                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         44328960                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     44328960                       # number of overall hits
+system.cpu.dcache.overall_hits::total        44328960                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       125143                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        125143                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1582186                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1582186                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data           44                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total           44                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data      1707329                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1707329                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1707329                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1707329                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   5010352449                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   5010352449                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 122380602729                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 122380602729                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       944750                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total       944750                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 127390955178                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 127390955178                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 127390955178                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 127390955178                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     26186388                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     26186388                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     19849901                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     19849901                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data        16022                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total        16022                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data        16033                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total        16033                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data        15919                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total        15919                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     46023843                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     46023843                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     46023843                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     46023843                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.004781                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.004781                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.079765                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.079765                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.002559                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.002559                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.037121                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.037121                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.037121                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.037121                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41597.290666                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 41597.290666                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80234.250360                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 80234.250360                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20896.341463                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20896.341463                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 77404.202554                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 77404.202554                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 77404.202554                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 77404.202554                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs         4865                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets         1223                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs               137                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets              14                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    35.510949                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    87.357143                       # average number of cycles each access was blocked
+system.cpu.dcache.demand_accesses::cpu.data     46036289                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     46036289                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     46036289                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     46036289                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.004779                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.004779                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.079708                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.079708                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.002744                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.002744                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.037087                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.037087                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.037087                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.037087                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40037.017244                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 40037.017244                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77349.061823                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 77349.061823                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 21471.590909                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 21471.590909                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 74614.181085                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 74614.181085                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 74614.181085                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 74614.181085                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs         4179                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets         1300                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs               140                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets              15                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    29.850000                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    86.666667                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       129182                       # number of writebacks
-system.cpu.dcache.writebacks::total            129182                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data        69727                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        69727                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1475983                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      1475983                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           41                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total           41                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1545710                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1545710                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1545710                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1545710                       # number of overall MSHR hits
+system.cpu.dcache.writebacks::writebacks       129156                       # number of writebacks
+system.cpu.dcache.writebacks::total            129156                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        69730                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        69730                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1474872                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      1474872                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           44                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total           44                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      1544602                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1544602                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1544602                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1544602                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data        55413                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total        55413                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       107339                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       107339                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       162752                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       162752                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       162752                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       162752                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   2263243564                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   2263243564                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8680214182                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   8680214182                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  10943457746                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  10943457746                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  10943457746                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  10943457746                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002117                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002117                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005408                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.005408                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.003536                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.003536                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.003536                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.003536                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40843.187772                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40843.187772                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80867.291311                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80867.291311                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67240.081511                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 67240.081511                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67240.081511                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 67240.081511                       # average overall mshr miss latency
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       107314                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       107314                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       162727                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       162727                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       162727                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       162727                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   2176479313                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   2176479313                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8375757941                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   8375757941                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  10552237254                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  10552237254                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  10552237254                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  10552237254                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002116                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002116                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005406                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.005406                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.003535                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.003535                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.003535                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.003535                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39277.413477                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39277.413477                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78049.070401                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78049.070401                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 64846.259404                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 64846.259404                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 64846.259404                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 64846.259404                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 01fe4f8415a07e82402997f97f69d03362af674d..f20aedd289cc5ff83d7146751ea87f22598c5355 100644 (file)
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.009838                       # Number of seconds simulated
-sim_ticks                                1009838214500                       # Number of ticks simulated
-final_tick                               1009838214500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.007337                       # Number of seconds simulated
+sim_ticks                                1007336591500                       # Number of ticks simulated
+final_tick                               1007336591500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 128161                       # Simulator instruction rate (inst/s)
-host_op_rate                                   128161                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               71119760                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 230508                       # Number of bytes of host memory used
-host_seconds                                 14199.12                       # Real time elapsed on the host
+host_inst_rate                                 109896                       # Simulator instruction rate (inst/s)
+host_op_rate                                   109896                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               60832901                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 265436                       # Number of bytes of host memory used
+host_seconds                                 16559.08                       # Real time elapsed on the host
 sim_insts                                  1819780127                       # Number of instructions simulated
 sim_ops                                    1819780127                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -25,64 +25,64 @@ system.physmem.num_reads::cpu.data            1958829                       # Nu
 system.physmem.num_reads::total               1959688                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks         1018055                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total              1018055                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                54440                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            124143704                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               124198144                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           54440                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              54440                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          64520751                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               64520751                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          64520751                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               54440                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           124143704                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              188718895                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst                54576                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            124452002                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               124506578                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           54576                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              54576                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          64680982                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               64680982                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          64680982                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               54576                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           124452002                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              189187560                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                       1959688                       # Number of read requests accepted
 system.physmem.writeReqs                      1018055                       # Number of write requests accepted
 system.physmem.readBursts                     1959688                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                    1018055                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                125384704                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     35328                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  65154176                       # Total number of bytes written to DRAM
+system.physmem.bytesReadDRAM                125336064                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     83968                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  65153920                       # Total number of bytes written to DRAM
 system.physmem.bytesReadSys                 125420032                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys               65155520                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      552                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.servicedByWrQ                     1312                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              118719                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              114075                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              116210                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              117697                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              117769                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              117504                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              119870                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              124481                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              126964                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              130062                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             128627                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             130265                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             125943                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             125205                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             122569                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             123176                       # Per bank write bursts
+system.physmem.perBankRdBursts::0              118685                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              114026                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              116162                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              117671                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              117731                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              117464                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              119807                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              124441                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              126920                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              130015                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             128574                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             130216                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             125899                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             125145                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             122505                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             123115                       # Per bank write bursts
 system.physmem.perBankWrBursts::0               61223                       # Per bank write bursts
 system.physmem.perBankWrBursts::1               61467                       # Per bank write bursts
 system.physmem.perBankWrBursts::2               60558                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               61216                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               61215                       # Per bank write bursts
 system.physmem.perBankWrBursts::4               61647                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               63084                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               64137                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               63083                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               64136                       # Per bank write bursts
 system.physmem.perBankWrBursts::7               65614                       # Per bank write bursts
 system.physmem.perBankWrBursts::8               65332                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               65770                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              65297                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              65611                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              64149                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              64192                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              64551                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               65769                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              65294                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              65608                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              64146                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              64202                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              64550                       # Per bank write bursts
 system.physmem.perBankWrBursts::15              64186                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1009838141500                       # Total gap between requests
+system.physmem.totGap                    1007336518500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -97,10 +97,10 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                1018055                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1662258                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    204908                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     70586                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     21384                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                   1664981                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    198590                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     70959                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     23846                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
@@ -129,234 +129,213 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                     45504                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                     45756                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                     45744                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                     45699                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                     45701                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                     45665                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                     45697                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                     45681                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                     45686                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                     45671                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                    45688                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                    45723                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                    45729                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                    45793                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                    45986                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    46199                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    46502                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    47345                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    47567                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    47005                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    48930                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    47073                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     1504                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                      185                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                       15                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      1862398                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      102.290110                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean      79.389553                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     186.671437                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64-65        1500560     80.57%     80.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-129       201450     10.82%     91.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192-193        59792      3.21%     94.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-257        29273      1.57%     96.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320-321        16605      0.89%     97.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-385        10399      0.56%     97.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448-449         7221      0.39%     98.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-513         6896      0.37%     98.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576-577         4046      0.22%     98.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-641         3343      0.18%     98.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704-705         3041      0.16%     98.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-769         2820      0.15%     99.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832-833         1620      0.09%     99.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-897         1539      0.08%     99.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960-961         1515      0.08%     99.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1025         1490      0.08%     99.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088-1089         1330      0.07%     99.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152-1153         1307      0.07%     99.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216-1217          969      0.05%     99.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280-1281         1340      0.07%     99.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344-1345          596      0.03%     99.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408-1409         2192      0.12%     99.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472-1473          189      0.01%     99.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536-1537          700      0.04%     99.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600-1601          112      0.01%     99.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664-1665           81      0.00%     99.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1728-1729           79      0.00%     99.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1792-1793           79      0.00%     99.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856-1857           66      0.00%     99.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1920-1921           52      0.00%     99.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984-1985           55      0.00%     99.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2048-2049           71      0.00%     99.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112-2113           36      0.00%     99.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2176-2177           40      0.00%     99.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2240-2241           43      0.00%     99.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2304-2305           52      0.00%     99.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2368-2369           33      0.00%     99.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2432-2433           31      0.00%     99.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2496-2497           35      0.00%     99.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2560-2561           28      0.00%     99.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2624-2625           29      0.00%     99.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2688-2689           30      0.00%     99.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2752-2753           34      0.00%     99.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2816-2817           33      0.00%     99.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2880-2881           22      0.00%     99.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2944-2945           20      0.00%     99.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3008-3009           22      0.00%     99.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3072-3073           24      0.00%     99.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3136-3137           16      0.00%     99.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3200-3201           19      0.00%     99.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3264-3265           21      0.00%     99.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3328-3329           28      0.00%     99.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3392-3393           15      0.00%     99.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3456-3457           19      0.00%     99.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3520-3521           14      0.00%     99.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3584-3585           18      0.00%     99.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3648-3649           13      0.00%     99.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3712-3713           13      0.00%     99.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3776-3777           16      0.00%     99.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3840-3841           25      0.00%     99.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3904-3905           17      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3968-3969           18      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4032-4033           21      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4096-4097           22      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4160-4161           15      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4224-4225           12      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4288-4289           17      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4352-4353           19      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4416-4417           13      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4480-4481           14      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4544-4545            8      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4608-4609           17      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4672-4673           11      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4736-4737           11      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4800-4801           10      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4864-4865           12      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4928-4929          106      0.01%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4992-4993           10      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5056-5057            8      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5120-5121            6      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5184-5185            9      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5248-5249            6      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5312-5313            6      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5376-5377           15      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5440-5441           13      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5504-5505            6      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5568-5569           10      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5632-5633           11      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5696-5697           12      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5760-5761            7      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5824-5825            4      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5888-5889           11      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5952-5953           10      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6016-6017            6      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6080-6081            5      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6144-6145           11      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6208-6209            8      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6272-6273            5      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6336-6337            7      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6400-6401           10      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6464-6465            8      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6528-6529            5      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6592-6593            6      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6656-6657           14      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6720-6721            9      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6784-6785           13      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6848-6849           64      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6912-6913            1      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7104-7105            4      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7168-7169            4      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7424-7425            1      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7488-7489            2      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7552-7553            3      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7616-7617            2      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7680-7681            2      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7744-7745            2      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7808-7809            2      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7936-7937            5      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8000-8001            1      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8192-8193          154      0.01%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        1862398                       # Bytes accessed per row activation
-system.physmem.totQLat                    23048924250                       # Total ticks spent queuing
-system.physmem.totMemAccLat               84969451750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   9795680000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                 52124847500                       # Total ticks spent accessing banks
-system.physmem.avgQLat                       11764.84                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    26606.04                       # Average bank access latency per DRAM burst
+system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                    26939                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    28117                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    34916                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    48946                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    53936                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    56821                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    58079                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    58536                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    58949                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    59504                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    64559                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    64811                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    64584                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    72712                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    62778                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    60810                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    59834                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    59240                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                    14814                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                     4880                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                     1773                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      499                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      291                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      206                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      167                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      150                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      128                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      119                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      107                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      102                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                       98                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                       93                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                       82                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                       86                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                       80                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       76                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       72                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       69                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       67                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples      1266500                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      109.102187                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean      83.148932                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     142.836675                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         979529     77.34%     77.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       199046     15.72%     93.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        36524      2.88%     95.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        14982      1.18%     97.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         8864      0.70%     97.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         4419      0.35%     98.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         2809      0.22%     98.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         2238      0.18%     98.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        18089      1.43%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        1266500                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         58142                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        33.680816                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      161.230571                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023          58099     99.93%     99.93% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047           17      0.03%     99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-3071           10      0.02%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3072-4095            6      0.01%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::4096-5119            3      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::5120-6143            1      0.00%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::6144-7167            1      0.00%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::8192-9215            1      0.00%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::9216-10239            1      0.00%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::12288-13311            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::16384-17407            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::19456-20479            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total           58142                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         58142                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.509374                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.424358                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.849185                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16              29010     49.90%     49.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17               1046      1.80%     51.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18               6657     11.45%     63.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19              16493     28.37%     91.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20               3312      5.70%     97.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21               1061      1.82%     99.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                264      0.45%     99.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 97      0.17%     99.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                 56      0.10%     99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                 17      0.03%     99.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                 18      0.03%     99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27                 13      0.02%     99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28                  5      0.01%     99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29                  6      0.01%     99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30                  4      0.01%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::31                  5      0.01%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32                  5      0.01%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::33                  3      0.01%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::34                  3      0.01%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::35                  2      0.00%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36                  2      0.00%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::38                  1      0.00%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::39                 28      0.05%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40                  9      0.02%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::41                  6      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::42                  2      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::43                  5      0.01%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::46                  1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::47                  1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48                  2      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::49                  2      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::50                  1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::53                  1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::54                  1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::55                  1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::59                  1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::62                  1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           58142                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    19659284500                       # Total ticks spent queuing
+system.physmem.totMemAccLat               80383790750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   9791880000                       # Total ticks spent in databus transfers
+system.physmem.totBankLat                 50932626250                       # Total ticks spent accessing banks
+system.physmem.avgQLat                       10038.56                       # Average queueing delay per DRAM burst
+system.physmem.avgBankLat                    26007.58                       # Average bank access latency per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  43370.88                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         124.16                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          64.52                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      124.20                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       64.52                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  41046.15                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         124.42                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          64.68                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      124.51                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       64.68                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           1.47                       # Data bus utilization in percentage
+system.physmem.busUtil                           1.48                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.97                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.50                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         0.08                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        10.29                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     771409                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    343363                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   39.37                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  33.73                       # Row buffer hit rate for writes
-system.physmem.avgGap                       339128.71                       # Average gap between requests
-system.physmem.pageHitRate                      37.44                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent              12.16                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                    188718895                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq             1178392                       # Transaction distribution
-system.membus.trans_dist::ReadResp            1178392                       # Transaction distribution
+system.physmem.busUtilWrite                      0.51                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.04                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        25.03                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     753336                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    422191                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   38.47                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  41.47                       # Row buffer hit rate for writes
+system.physmem.avgGap                       338288.60                       # Average gap between requests
+system.physmem.pageHitRate                      39.49                       # Row buffer hit rate, read and write combined
+system.physmem.prechargeAllPercent              12.29                       # Percentage of time for which DRAM has all the banks in precharge state
+system.membus.throughput                    189187560                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq             1178393                       # Transaction distribution
+system.membus.trans_dist::ReadResp            1178393                       # Transaction distribution
 system.membus.trans_dist::Writeback           1018055                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            781296                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           781296                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            781295                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           781295                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      4937431                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count::total                4937431                       # Packet count per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    190575552                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size::total           190575552                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.data_through_bus              190575552                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy         11785228500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy         11782666500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               1.2                       # Layer utilization (%)
-system.membus.respLayer1.occupancy        18364778000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy        18347417750                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              1.8                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups               326538257                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         252572868                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect         138234365                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            220428800                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               135446379                       # Number of BTB hits
+system.cpu.branchPred.lookups               326511183                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         252559725                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect         138218265                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            220270477                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               135614039                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             61.446771                       # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct             61.567052                       # BTB Hit Percentage
 system.cpu.branchPred.usedRAS                16767439                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                  6                       # Number of incorrect RAS predictions.
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    444831817                       # DTB read hits
+system.cpu.dtb.read_hits                    444830139                       # DTB read hits
 system.cpu.dtb.read_misses                    4897078                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                449728895                       # DTB read accesses
-system.cpu.dtb.write_hits                   160846718                       # DTB write hits
+system.cpu.dtb.read_accesses                449727217                       # DTB read accesses
+system.cpu.dtb.write_hits                   160844128                       # DTB write hits
 system.cpu.dtb.write_misses                   1701304                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses               162548022                       # DTB write accesses
-system.cpu.dtb.data_hits                    605678535                       # DTB hits
+system.cpu.dtb.write_accesses               162545432                       # DTB write accesses
+system.cpu.dtb.data_hits                    605674267                       # DTB hits
 system.cpu.dtb.data_misses                    6598382                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                612276917                       # DTB accesses
-system.cpu.itb.fetch_hits                   231928870                       # ITB hits
+system.cpu.dtb.data_accesses                612272649                       # DTB accesses
+system.cpu.itb.fetch_hits                   232118114                       # ITB hits
 system.cpu.itb.fetch_misses                        22                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses               231928892                       # ITB accesses
+system.cpu.itb.fetch_accesses               232118136                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -370,34 +349,34 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   29                       # Number of system calls
-system.cpu.numCycles                       2019676430                       # number of cpu cycles simulated
+system.cpu.numCycles                       2014673184                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.branch_predictor.predictedTaken    172263299                       # Number of Branches Predicted As Taken (True).
-system.cpu.branch_predictor.predictedNotTaken    154274958                       # Number of Branches Predicted As Not Taken (False).
-system.cpu.regfile_manager.intRegFileReads   1667627607                       # Number of Reads from Int. Register File
+system.cpu.branch_predictor.predictedTaken    172428181                       # Number of Branches Predicted As Taken (True).
+system.cpu.branch_predictor.predictedNotTaken    154083002                       # Number of Branches Predicted As Not Taken (False).
+system.cpu.regfile_manager.intRegFileReads   1667622783                       # Number of Reads from Int. Register File
 system.cpu.regfile_manager.intRegFileWrites   1376202617                       # Number of Writes to Int. Register File
-system.cpu.regfile_manager.intRegFileAccesses   3043830224                       # Total Accesses (Read+Write) to the Int. Register File
-system.cpu.regfile_manager.floatRegFileReads          230                       # Number of Reads from FP Register File
+system.cpu.regfile_manager.intRegFileAccesses   3043825400                       # Total Accesses (Read+Write) to the Int. Register File
+system.cpu.regfile_manager.floatRegFileReads          231                       # Number of Reads from FP Register File
 system.cpu.regfile_manager.floatRegFileWrites          345                       # Number of Writes to FP Register File
-system.cpu.regfile_manager.floatRegFileAccesses          575                       # Total Accesses (Read+Write) to the FP Register File
-system.cpu.regfile_manager.regForwards      651720859                       # Number of Registers Read Through Forwarding Logic
-system.cpu.agen_unit.agens                  617884928                       # Number of Address Generations
-system.cpu.execution_unit.predictedTakenIncorrect    120516333                       # Number of Branches Incorrectly Predicted As Taken.
-system.cpu.execution_unit.predictedNotTakenIncorrect     11119574                       # Number of Branches Incorrectly Predicted As Not Taken).
-system.cpu.execution_unit.mispredicted      131635907                       # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.predicted          83564055                       # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.mispredictPct     61.169113                       # Percentage of Incorrect Branches Predicts
-system.cpu.execution_unit.executions       1139356886                       # Number of Instructions Executed.
+system.cpu.regfile_manager.floatRegFileAccesses          576                       # Total Accesses (Read+Write) to the FP Register File
+system.cpu.regfile_manager.regForwards      651695392                       # Number of Registers Read Through Forwarding Logic
+system.cpu.agen_unit.agens                  617886274                       # Number of Address Generations
+system.cpu.execution_unit.predictedTakenIncorrect    120493688                       # Number of Branches Incorrectly Predicted As Taken.
+system.cpu.execution_unit.predictedNotTakenIncorrect     11126119                       # Number of Branches Incorrectly Predicted As Not Taken).
+system.cpu.execution_unit.mispredicted      131619807                       # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.predicted          83580161                       # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.mispredictPct     61.161629                       # Percentage of Incorrect Branches Predicts
+system.cpu.execution_unit.executions       1139354623                       # Number of Instructions Executed.
 system.cpu.mult_div_unit.multiplies                75                       # Number of Multipy Operations Executed
 system.cpu.mult_div_unit.divides                    0                       # Number of Divide Operations Executed
 system.cpu.contextSwitches                          1                       # Number of context switches
-system.cpu.threadCycles                    1742060649                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles                    1742144730                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
 system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled                         7515544                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                       447943086                       # Number of cycles cpu's stages were not processed
-system.cpu.runCycles                       1571733344                       # Number of cycles cpu stages are processed.
-system.cpu.activity                         77.821047                       # Percentage of cycles cpu is active
+system.cpu.timesIdled                         7512368                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                       442846963                       # Number of cycles cpu's stages were not processed
+system.cpu.runCycles                       1571826221                       # Number of cycles cpu stages are processed.
+system.cpu.activity                         78.018918                       # Percentage of cycles cpu is active
 system.cpu.comLoads                         444595663                       # Number of Load instructions committed
 system.cpu.comStores                        160728502                       # Number of Store instructions committed
 system.cpu.comBranches                      214632552                       # Number of Branches instructions committed
@@ -409,78 +388,78 @@ system.cpu.committedInsts                  1819780127                       # Nu
 system.cpu.committedOps                    1819780127                       # Number of Ops committed (Per-Thread)
 system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
 system.cpu.committedInsts_total            1819780127                       # Number of Instructions committed (Total)
-system.cpu.cpi                               1.109846                       # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi                               1.107097                       # CPI: Cycles Per Instruction (Per-Thread)
 system.cpu.smt_cpi                                nan                       # CPI: Total SMT-CPI
-system.cpu.cpi_total                         1.109846                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.901026                       # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.cpi_total                         1.107097                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.903263                       # IPC: Instructions Per Cycle (Per-Thread)
 system.cpu.smt_ipc                                nan                       # IPC: Total SMT-IPC
-system.cpu.ipc_total                         0.901026                       # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles                833031386                       # Number of cycles 0 instructions are processed.
-system.cpu.stage0.runCycles                1186645044                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization               58.754216                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles               1085876271                       # Number of cycles 0 instructions are processed.
-system.cpu.stage1.runCycles                 933800159                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization               46.235137                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles               1047285367                       # Number of cycles 0 instructions are processed.
-system.cpu.stage2.runCycles                 972391063                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization               48.145884                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage3.idleCycles               1610051904                       # Number of cycles 0 instructions are processed.
-system.cpu.stage3.runCycles                 409624526                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage3.utilization               20.281691                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles                998329594                       # Number of cycles 0 instructions are processed.
-system.cpu.stage4.runCycles                1021346836                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization               50.569825                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.ipc_total                         0.903263                       # IPC: Total IPC of All Threads
+system.cpu.stage0.idleCycles                827756857                       # Number of cycles 0 instructions are processed.
+system.cpu.stage0.runCycles                1186916327                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage0.utilization               58.913591                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles               1081059316                       # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles                 933613868                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization               46.340711                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles               1042290381                       # Number of cycles 0 instructions are processed.
+system.cpu.stage2.runCycles                 972382803                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage2.utilization               48.265039                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles               1605047974                       # Number of cycles 0 instructions are processed.
+system.cpu.stage3.runCycles                 409625210                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage3.utilization               20.332092                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles                993337465                       # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles                1021335719                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization               50.694858                       # Percentage of cycles stage was utilized (processing insts).
 system.cpu.icache.tags.replacements                 1                       # number of replacements
-system.cpu.icache.tags.tagsinuse           668.332859                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           231927731                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           668.288600                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           232116975                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               859                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          269997.358556                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs          270217.665891                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   668.332859                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.326334                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.326334                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   668.288600                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.326313                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.326313                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          858                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           73                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4          785                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.418945                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         463858599                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        463858599                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    231927731                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       231927731                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     231927731                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        231927731                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    231927731                       # number of overall hits
-system.cpu.icache.overall_hits::total       231927731                       # number of overall hits
+system.cpu.icache.tags.tag_accesses         464237087                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        464237087                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    232116975                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       232116975                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     232116975                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        232116975                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    232116975                       # number of overall hits
+system.cpu.icache.overall_hits::total       232116975                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst         1139                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total          1139                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst         1139                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total           1139                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst         1139                       # number of overall misses
 system.cpu.icache.overall_misses::total          1139                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     82716500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     82716500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     82716500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     82716500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     82716500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     82716500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    231928870                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    231928870                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    231928870                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    231928870                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    231928870                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    231928870                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     81449500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     81449500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     81449500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     81449500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     81449500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     81449500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    232118114                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    232118114                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    232118114                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    232118114                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    232118114                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    232118114                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000005                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000005                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000005                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000005                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000005                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000005                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72622.036874                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 72622.036874                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 72622.036874                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 72622.036874                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 72622.036874                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 72622.036874                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71509.657594                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 71509.657594                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 71509.657594                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 71509.657594                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 71509.657594                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 71509.657594                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs          162                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 1                       # number of cycles access was blocked
@@ -501,134 +480,134 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          859
 system.cpu.icache.demand_mshr_misses::total          859                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          859                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          859                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     65136250                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     65136250                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     65136250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     65136250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     65136250                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     65136250                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     63326500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     63326500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     63326500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     63326500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     63326500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     63326500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000004                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000004                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000004                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000004                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000004                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000004                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75827.997672                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75827.997672                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75827.997672                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 75827.997672                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75827.997672                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 75827.997672                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73721.187427                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73721.187427                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73721.187427                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 73721.187427                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73721.187427                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 73721.187427                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput               811573074                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq        7222683                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       7222683                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      3693280                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      1889623                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      1889623                       # Transaction distribution
+system.cpu.toL2Bus.throughput               813589109                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq        7222688                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       7222688                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      3693283                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      1889624                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      1889624                       # Transaction distribution
 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1718                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     21916174                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          21917892                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     21916189                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          21917907                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        54976                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    819502528                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      819557504                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus         819557504                       # Total data (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    819503104                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      819558080                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         819558080                       # Total data (bytes)
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy    10096073000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.occupancy    10096080500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1445250                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       1443000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   13991718500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy   13971303500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.4                       # Layer utilization (%)
 system.cpu.l2cache.tags.replacements          1926957                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        30919.698369                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            8958682                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse        30916.680897                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            8958690                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs          1956750                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             4.578348                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle      67892812750                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 14931.951876                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    34.659960                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 15953.086532                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.455687                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001058                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.486850                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.943594                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.avg_refs             4.578352                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle      67897094750                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 14926.990701                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    34.739406                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 15954.950790                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.455536                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001060                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.486906                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.943502                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        29793                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          158                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          613                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          725                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          586                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          752                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3        12815                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4        15482                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.909210                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        106291061                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       106291061                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.data      6044291                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        6044291                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      3693280                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      3693280                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1108327                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1108327                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.data      7152618                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         7152618                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.data      7152618                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        7152618                       # number of overall hits
+system.cpu.l2cache.tags.tag_accesses        106291134                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       106291134                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.data      6044295                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        6044295                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      3693283                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      3693283                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data      1108329                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total      1108329                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.data      7152624                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         7152624                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.data      7152624                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        7152624                       # number of overall hits
 system.cpu.l2cache.ReadReq_misses::cpu.inst          859                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data      1177533                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total      1178392                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       781296                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       781296                       # number of ReadExReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data      1177534                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total      1178393                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       781295                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       781295                       # number of ReadExReq misses
 system.cpu.l2cache.demand_misses::cpu.inst          859                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.data      1958829                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::total       1959688                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst          859                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data      1958829                       # number of overall misses
 system.cpu.l2cache.overall_misses::total      1959688                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     64273250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data  98166669000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total  98230942250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  71141350250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  71141350250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     64273250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 169308019250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 169372292500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     64273250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 169308019250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 169372292500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     62463500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data  95853275750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total  95915739250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  68840007000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  68840007000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     62463500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 164693282750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 164755746250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     62463500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 164693282750                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 164755746250                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst          859                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      7221824                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      7222683                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      3693280                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      3693280                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data      1889623                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total      1889623                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      7221829                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      7222688                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      3693283                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      3693283                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data      1889624                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total      1889624                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.inst          859                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      9111447                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      9112306                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      9111453                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      9112312                       # number of demand (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.inst          859                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      9111447                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      9112306                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      9111453                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      9112312                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst            1                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.163052                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::total     0.163152                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.413467                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.413467                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.413466                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.413466                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst            1                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.214986                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.215060                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.214985                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.215059                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.214986                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.215060                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74823.341094                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83366.384636                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 83360.157104                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 91055.566968                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 91055.566968                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74823.341094                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86433.281951                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 86428.192906                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74823.341094                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86433.281951                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 86428.192906                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.214985                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.215059                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72716.530850                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 81401.705386                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 81395.374251                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88110.133816                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88110.133816                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72716.530850                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84077.417044                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 84072.437169                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72716.530850                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84077.417044                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 84072.437169                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -640,91 +619,91 @@ system.cpu.l2cache.cache_copies                     0                       # nu
 system.cpu.l2cache.writebacks::writebacks      1018055                       # number of writebacks
 system.cpu.l2cache.writebacks::total          1018055                       # number of writebacks
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          859                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data      1177533                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total      1178392                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       781296                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       781296                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data      1177534                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total      1178393                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       781295                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       781295                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.inst          859                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data      1958829                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::total      1959688                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          859                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data      1958829                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total      1959688                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     53491750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  83391618000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  83445109750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  61355946750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  61355946750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     53491750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 144747564750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 144801056500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     53491750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 144747564750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 144801056500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     51686000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  81095366750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  81147052750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  59075528500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  59075528500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     51686000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 140170895250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 140222581250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     51686000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 140170895250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 140222581250                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.163052                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.163152                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.413467                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.413467                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.413466                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.413466                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.214986                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.215060                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.214985                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.215059                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.214986                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.215060                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62272.118743                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70818.922272                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70812.691999                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78530.987935                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78530.987935                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62272.118743                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73894.946802                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73889.852109                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62272.118743                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73894.946802                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73889.852109                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.214985                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.215059                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60169.965076                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68868.811219                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68862.470118                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75612.321210                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75612.321210                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60169.965076                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71558.515445                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71553.523444                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60169.965076                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71558.515445                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71553.523444                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements           9107351                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4082.357931                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           593283202                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           9111447                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             65.114049                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle       12709353000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4082.357931                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.996669                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.996669                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements           9107357                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4082.325879                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           593298406                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           9111453                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             65.115674                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle       12706876000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4082.325879                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.996662                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.996662                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          590                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         2876                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          593                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3           37                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          560                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         2879                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          619                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3           38                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1219759777                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1219759777                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    437268777                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       437268777                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    156014425                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      156014425                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data     593283202                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        593283202                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    593283202                       # number of overall hits
-system.cpu.dcache.overall_hits::total       593283202                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      7326886                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       7326886                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      4714077                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      4714077                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data     12040963                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total       12040963                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data     12040963                       # number of overall misses
-system.cpu.dcache.overall_misses::total      12040963                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 183066004000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 183066004000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 258278135000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 258278135000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 441344139000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 441344139000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 441344139000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 441344139000                       # number of overall miss cycles
+system.cpu.dcache.tags.tag_accesses        1219759783                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1219759783                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    437268768                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       437268768                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    156029638                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      156029638                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     593298406                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        593298406                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    593298406                       # number of overall hits
+system.cpu.dcache.overall_hits::total       593298406                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      7326895                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       7326895                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      4698864                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      4698864                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data     12025759                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total       12025759                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data     12025759                       # number of overall misses
+system.cpu.dcache.overall_misses::total      12025759                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 180765205750                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 180765205750                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 250221551250                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 250221551250                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 430986757000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 430986757000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 430986757000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 430986757000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data    444595663                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total    444595663                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    160728502                       # number of WriteReq accesses(hits+misses)
@@ -735,54 +714,54 @@ system.cpu.dcache.overall_accesses::cpu.data    605324165
 system.cpu.dcache.overall_accesses::total    605324165                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.016480                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.016480                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.029329                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.029329                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.019892                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.019892                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.019892                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.019892                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24985.512809                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 24985.512809                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54788.696706                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 54788.696706                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 36653.558274                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 36653.558274                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 36653.558274                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 36653.558274                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs     12098433                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets      7855784                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs            422647                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets           73423                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    28.625385                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets   106.993503                       # average number of cycles each access was blocked
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.029235                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.029235                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.019867                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.019867                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.019867                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.019867                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24671.461206                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 24671.461206                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53251.498926                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 53251.498926                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 35838.632472                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 35838.632472                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 35838.632472                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 35838.632472                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs     11447989                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets      7764770                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs            416735                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets           73422                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    27.470668                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets   105.755359                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      3693280                       # number of writebacks
-system.cpu.dcache.writebacks::total           3693280                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       104620                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       104620                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      2824896                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      2824896                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      2929516                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      2929516                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      2929516                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      2929516                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7222266                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      7222266                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1889181                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      1889181                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      9111447                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      9111447                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      9111447                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      9111447                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 165959957500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 165959957500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  84276720000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  84276720000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 250236677500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 250236677500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 250236677500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 250236677500                       # number of overall MSHR miss cycles
+system.cpu.dcache.writebacks::writebacks      3693283                       # number of writebacks
+system.cpu.dcache.writebacks::total           3693283                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       104624                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       104624                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      2809682                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      2809682                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      2914306                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      2914306                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      2914306                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      2914306                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7222271                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      7222271                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1889182                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      1889182                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      9111453                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      9111453                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      9111453                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      9111453                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 163647011750                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 163647011750                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  81975016250                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  81975016250                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 245622028000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 245622028000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 245622028000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 245622028000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.016245                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.016245                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.011754                       # mshr miss rate for WriteReq accesses
@@ -791,14 +770,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.015052
 system.cpu.dcache.demand_mshr_miss_rate::total     0.015052                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.015052                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.015052                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22978.931751                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22978.931751                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44610.188224                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44610.188224                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27463.988706                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 27463.988706                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27463.988706                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 27463.988706                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22658.663978                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22658.663978                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43391.804628                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43391.804628                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26957.503704                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 26957.503704                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26957.503704                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 26957.503704                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 09d12ecbaa2fc515d6ea18e9b795c90ed6432266..2f4d3475f13cde02b4e637ae1e2d652bbb4a8e24 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.685387                       # Number of seconds simulated
-sim_ticks                                685386545000                       # Number of ticks simulated
-final_tick                               685386545000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.682192                       # Number of seconds simulated
+sim_ticks                                682191807000                       # Number of ticks simulated
+final_tick                               682191807000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 166100                       # Simulator instruction rate (inst/s)
-host_op_rate                                   166100                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               65575812                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 231660                       # Number of bytes of host memory used
-host_seconds                                 10451.82                       # Real time elapsed on the host
+host_inst_rate                                 139307                       # Simulator instruction rate (inst/s)
+host_op_rate                                   139307                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               54741914                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 268504                       # Number of bytes of host memory used
+host_seconds                                 12461.96                       # Real time elapsed on the host
 sim_insts                                  1736043781                       # Number of instructions simulated
 sim_ops                                    1736043781                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             61760                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         125792064                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            125853824                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        61760                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           61760                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     65263104                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          65263104                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst                965                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            1965501                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1966466                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1019736                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1019736                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                90110                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            183534481                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               183624591                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           90110                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              90110                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          95220871                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               95220871                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          95220871                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               90110                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           183534481                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              278845462                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1966466                       # Number of read requests accepted
-system.physmem.writeReqs                      1019736                       # Number of write requests accepted
-system.physmem.readBursts                     1966466                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1019736                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                125817344                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     36480                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  65263104                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 125853824                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               65263104                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      570                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst             61696                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         125800064                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            125861760                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        61696                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           61696                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     65265984                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          65265984                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst                964                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            1965626                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1966590                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1019781                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1019781                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst                90438                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            184405709                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               184496147                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           90438                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              90438                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          95671017                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               95671017                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          95671017                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               90438                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           184405709                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              280167164                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1966590                       # Number of read requests accepted
+system.physmem.writeReqs                      1019781                       # Number of write requests accepted
+system.physmem.readBursts                     1966590                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1019781                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                125780416                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     81344                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  65264896                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 125861760                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               65265984                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                     1271                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              119017                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              114428                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              116569                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              118023                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              118127                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              117816                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              120202                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              124913                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              127544                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              130446                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             129104                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             130773                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             126663                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             125636                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             122981                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             123654                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               61274                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               61571                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               60654                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               61312                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               61747                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               63190                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               64213                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               65700                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               65483                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               65878                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              65419                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              65720                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              64327                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              64305                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              64649                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              64294                       # Per bank write bursts
+system.physmem.perBankRdBursts::0              118991                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              114394                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              116519                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              118029                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              118142                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              117777                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              120156                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              124892                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              127514                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              130376                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             129025                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             130742                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             126628                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             125605                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             122932                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             123597                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               61284                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               61572                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               60658                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               61323                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               61765                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               63192                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               64214                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               65706                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               65482                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               65855                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              65405                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              65740                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              64329                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              64310                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              64647                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              64282                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           4                       # Number of times write queue was full causing retry
-system.physmem.totGap                    685386422500                       # Total gap between requests
+system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
+system.physmem.totGap                    682191684500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1966466                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1966590                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1019736                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1645035                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    231982                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     68923                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     19945                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        10                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1019781                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1642976                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    230548                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     69552                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     22230                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        12                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -129,235 +129,203 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                     45483                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                     45666                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                     45709                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                     45692                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                     45696                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                     45650                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                     45681                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                     45674                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                     45697                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                     45708                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                    45706                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                    45762                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                    45739                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                    45791                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                    45957                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    46127                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    46326                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    47316                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    47486                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    47499                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    49473                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    48655                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                      974                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                      190                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                       31                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                        7                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                        7                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                       12                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      1821867                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      104.857955                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean      80.098310                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     197.882118                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64-65        1460616     80.17%     80.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-129       186071     10.21%     90.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192-193        71892      3.95%     94.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-257        32365      1.78%     96.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320-321        16766      0.92%     97.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-385        10653      0.58%     97.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448-449         7007      0.38%     98.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-513         6870      0.38%     98.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576-577         3886      0.21%     98.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-641         3166      0.17%     98.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704-705         2723      0.15%     98.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-769         1980      0.11%     99.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832-833         1594      0.09%     99.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-897         1502      0.08%     99.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960-961         1242      0.07%     99.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1025         1240      0.07%     99.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088-1089         1003      0.06%     99.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152-1153         1017      0.06%     99.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216-1217          831      0.05%     99.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280-1281          807      0.04%     99.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344-1345          751      0.04%     99.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408-1409         2873      0.16%     99.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472-1473          389      0.02%     99.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536-1537          742      0.04%     99.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600-1601          289      0.02%     99.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664-1665          237      0.01%     99.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1728-1729          196      0.01%     99.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1792-1793          198      0.01%     99.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856-1857          161      0.01%     99.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1920-1921          147      0.01%     99.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984-1985          132      0.01%     99.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2048-2049          165      0.01%     99.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112-2113          370      0.02%     99.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2176-2177          134      0.01%     99.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2240-2241          101      0.01%     99.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2304-2305           83      0.00%     99.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2368-2369           73      0.00%     99.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2432-2433           67      0.00%     99.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2496-2497           51      0.00%     99.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2560-2561           72      0.00%     99.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2624-2625           49      0.00%     99.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2688-2689           40      0.00%     99.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2752-2753           35      0.00%     99.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2816-2817           42      0.00%     99.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2880-2881           36      0.00%     99.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2944-2945           34      0.00%     99.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3008-3009           27      0.00%     99.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3072-3073           45      0.00%     99.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3136-3137           32      0.00%     99.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3200-3201           23      0.00%     99.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3264-3265           19      0.00%     99.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3328-3329           28      0.00%     99.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3392-3393           20      0.00%     99.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3456-3457           15      0.00%     99.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3520-3521           21      0.00%     99.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3584-3585           35      0.00%     99.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3648-3649           14      0.00%     99.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3712-3713            9      0.00%     99.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3776-3777           10      0.00%     99.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3840-3841           15      0.00%     99.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3904-3905           20      0.00%     99.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3968-3969            9      0.00%     99.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4032-4033           19      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4096-4097           21      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4160-4161           16      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4224-4225           11      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4288-4289           15      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4352-4353           12      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4416-4417            9      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4480-4481           10      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4544-4545           16      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4608-4609           24      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4672-4673           17      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4736-4737            8      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4800-4801           15      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4864-4865           14      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4928-4929           12      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4992-4993           12      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5056-5057           18      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5120-5121           22      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5184-5185           17      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5248-5249           11      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5312-5313            8      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5376-5377           12      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5440-5441           14      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5504-5505            6      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5568-5569           17      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5632-5633           26      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5696-5697           14      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5760-5761            4      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5824-5825           11      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5888-5889           10      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5952-5953            9      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6016-6017            6      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6080-6081           14      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6144-6145           22      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6208-6209           13      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6272-6273           10      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6336-6337            9      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6400-6401            9      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6464-6465           10      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6528-6529            7      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6592-6593           17      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6656-6657           89      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6720-6721            2      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6784-6785            5      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6848-6849           28      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6912-6913            4      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7040-7041            1      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7104-7105            1      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7168-7169            7      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7296-7297            3      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7424-7425            1      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7552-7553            1      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7680-7681            3      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7744-7745            1      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7808-7809            2      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7936-7937            7      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8000-8001            1      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8064-8065            1      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8192-8193          123      0.01%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        1821867                       # Bytes accessed per row activation
-system.physmem.totQLat                    24443368500                       # Total ticks spent queuing
-system.physmem.totMemAccLat               84807426000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   9829480000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                 50534577500                       # Total ticks spent accessing banks
-system.physmem.avgQLat                       12433.70                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    25705.62                       # Average bank access latency per DRAM burst
+system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                    23411                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    24830                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    31804                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    47471                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    54150                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    57221                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    58425                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    59086                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    59586                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    60134                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    64812                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    65271                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    65616                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    73465                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    64939                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    61899                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    60584                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    59687                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                    17452                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                     5357                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                     1832                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      647                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      358                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      230                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      171                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      145                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                      136                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                      117                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                      108                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                      111                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                       92                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                       90                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                       83                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                       92                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                       80                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       82                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       70                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       59                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       58                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples      1251998                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      113.111439                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean      84.586325                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     150.844327                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         955672     76.33%     76.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       201584     16.10%     92.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        38062      3.04%     95.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        16101      1.29%     96.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         9606      0.77%     97.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         4835      0.39%     97.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         3234      0.26%     98.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         2576      0.21%     98.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        20328      1.62%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        1251998                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         58888                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        33.373692                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      161.339848                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023          58850     99.94%     99.94% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047           11      0.02%     99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-3071           10      0.02%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3072-4095            7      0.01%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::4096-5119            3      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::5120-6143            1      0.00%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::6144-7167            1      0.00%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::8192-9215            1      0.00%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::9216-10239            1      0.00%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::12288-13311            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::16384-17407            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::19456-20479            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total           58888                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         58888                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.317009                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.233410                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.918536                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-17           34047     57.82%     57.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18-19           20086     34.11%     91.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-21            4266      7.24%     99.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22-23             290      0.49%     99.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-25              84      0.14%     99.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26-27              30      0.05%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-29              14      0.02%     99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30-31               5      0.01%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-33               4      0.01%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::34-35               3      0.01%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-37               2      0.00%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::38-39              12      0.02%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-41              19      0.03%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::42-43               9      0.02%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-45               1      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::46-47               4      0.01%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-49               2      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::50-51               1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-53               1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::54-55               1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-61               1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-65               1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::78-79               1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::86-87               1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-89               1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-105             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::106-107             1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           58888                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    20653307250                       # Total ticks spent queuing
+system.physmem.totMemAccLat               80037239750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   9826595000                       # Total ticks spent in databus transfers
+system.physmem.totBankLat                 49557337500                       # Total ticks spent accessing banks
+system.physmem.avgQLat                       10508.88                       # Average queueing delay per DRAM burst
+system.physmem.avgBankLat                    25215.93                       # Average bank access latency per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  43139.32                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         183.57                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          95.22                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      183.62                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       95.22                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  40724.81                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         184.38                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          95.67                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      184.50                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       95.67                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           2.18                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       1.43                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.74                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         0.12                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        10.01                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     819101                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    344664                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   41.67                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  33.80                       # Row buffer hit rate for writes
-system.physmem.avgGap                       229517.77                       # Average gap between requests
-system.physmem.pageHitRate                      38.98                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               7.14                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                    278845462                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq             1191273                       # Transaction distribution
-system.membus.trans_dist::ReadResp            1191273                       # Transaction distribution
-system.membus.trans_dist::Writeback           1019736                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            775193                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           775193                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      4952668                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                4952668                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    191116928                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total           191116928                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus              191116928                       # Total data (bytes)
+system.physmem.busUtil                           2.19                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       1.44                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.75                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.09                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        25.29                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     797879                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    422825                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   40.60                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  41.46                       # Row buffer hit rate for writes
+system.physmem.avgGap                       228435.01                       # Average gap between requests
+system.physmem.pageHitRate                      40.89                       # Row buffer hit rate, read and write combined
+system.physmem.prechargeAllPercent               7.23                       # Percentage of time for which DRAM has all the banks in precharge state
+system.membus.throughput                    280167164                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq             1191439                       # Transaction distribution
+system.membus.trans_dist::ReadResp            1191439                       # Transaction distribution
+system.membus.trans_dist::Writeback           1019781                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            775151                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           775151                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      4952961                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                4952961                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    191127744                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total           191127744                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus              191127744                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy         11873404000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy         11872683000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               1.7                       # Layer utilization (%)
-system.membus.respLayer1.occupancy        18493738500                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy        18474077250                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              2.7                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups               381642976                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         296606399                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          16082111                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            262443817                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               259723367                       # Number of BTB hits
+system.cpu.branchPred.lookups               381618384                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         296575373                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          16092188                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            262164042                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               259697812                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             98.963416                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                24699577                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect               3003                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             99.059280                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                24705469                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect               3069                       # Number of incorrect RAS predictions.
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    613972689                       # DTB read hits
-system.cpu.dtb.read_misses                   11257711                       # DTB read misses
+system.cpu.dtb.read_hits                    613976008                       # DTB read hits
+system.cpu.dtb.read_misses                   11261750                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                625230400                       # DTB read accesses
-system.cpu.dtb.write_hits                   212364531                       # DTB write hits
-system.cpu.dtb.write_misses                   7123508                       # DTB write misses
+system.cpu.dtb.read_accesses                625237758                       # DTB read accesses
+system.cpu.dtb.write_hits                   212363538                       # DTB write hits
+system.cpu.dtb.write_misses                   7134748                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses               219488039                       # DTB write accesses
-system.cpu.dtb.data_hits                    826337220                       # DTB hits
-system.cpu.dtb.data_misses                   18381219                       # DTB misses
+system.cpu.dtb.write_accesses               219498286                       # DTB write accesses
+system.cpu.dtb.data_hits                    826339546                       # DTB hits
+system.cpu.dtb.data_misses                   18396498                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                844718439                       # DTB accesses
-system.cpu.itb.fetch_hits                   391054896                       # ITB hits
-system.cpu.itb.fetch_misses                        42                       # ITB misses
+system.cpu.dtb.data_accesses                844736044                       # DTB accesses
+system.cpu.itb.fetch_hits                   391110222                       # ITB hits
+system.cpu.itb.fetch_misses                        44                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses               391054938                       # ITB accesses
+system.cpu.itb.fetch_accesses               391110266                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -371,138 +339,139 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   29                       # Number of system calls
-system.cpu.numCycles                       1370773091                       # number of cpu cycles simulated
+system.cpu.numCycles                       1364383615                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          402523002                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     3161115412                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   381642976                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          284422944                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     574525052                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles               140645567                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles              190952168                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                   27                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          1444                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                 391054896                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               8064214                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples         1284797805                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.460399                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.144459                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          402585287                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     3161125101                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   381618384                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          284403281                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     574536383                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles               140665925                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles              188120516                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                  124                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles          1448                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles            4                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 391110222                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               8062763                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples         1282059246                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.465662                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.145744                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                710272753     55.28%     55.28% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 42667609      3.32%     58.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 21782496      1.70%     60.30% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 39699327      3.09%     63.39% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                129330544     10.07%     73.46% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 61540269      4.79%     78.25% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 38580495      3.00%     81.25% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 28116157      2.19%     83.44% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                212808155     16.56%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                707522863     55.19%     55.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 42675531      3.33%     58.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 21787283      1.70%     60.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 39707555      3.10%     63.31% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                129310443     10.09%     73.40% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 61549431      4.80%     78.20% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 38571496      3.01%     81.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 28142716      2.20%     83.40% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                212791928     16.60%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1284797805                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.278414                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.306082                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                434521910                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             172167391                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 542471492                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              18841651                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles              116795361                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             58349498                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                   879                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             3088463521                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                  2045                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles              116795361                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                457475867                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles               116907635                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           7798                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 535572514                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              58038630                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             3006337354                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                608843                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                1808950                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents              51752219                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands          2247576032                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            3898866654                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       3898722180                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups            144473                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total           1282059246                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.279700                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.316889                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                434597074                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             169317553                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 542454813                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              18875119                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles              116814687                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             58354170                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                   898                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             3088496267                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                  2037                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles              116814687                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                457547940                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles               113953082                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           6967                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 535589228                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              58147342                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             3006454755                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                609106                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                1833248                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents              51828481                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands          2247677853                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            3898974365                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       3898830865                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups            143499                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps            1376202963                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                871373069                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                157                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            156                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 123546719                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            679659315                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           255464076                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          67507479                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         36716823                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 2724801247                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                 120                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                2509489521                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           3207288                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       979575578                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    416138423                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved             91                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples    1284797805                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.953217                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.971436                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                871474890                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                178                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            177                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 123676155                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            679702242                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           255475560                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          67614908                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         37053481                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 2724914461                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                 131                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                2509610552                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           3196332                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       979670705                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    416123894                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            102                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    1282059246                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.957484                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.971278                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           442944970     34.48%     34.48% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           203642722     15.85%     50.33% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           185470521     14.44%     64.76% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           153370563     11.94%     76.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4           133097213     10.36%     87.06% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            80758631      6.29%     93.34% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            65098641      5.07%     98.41% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7            15296137      1.19%     99.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             5118407      0.40%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           440049739     34.32%     34.32% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           203670606     15.89%     50.21% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           185671301     14.48%     64.69% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           153363283     11.96%     76.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4           133052268     10.38%     87.03% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            80767651      6.30%     93.33% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            65047769      5.07%     98.41% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7            15319478      1.19%     99.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             5117151      0.40%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      1284797805                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1282059246                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 2193136     11.83%     11.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     11.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     11.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     11.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     11.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     11.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     11.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     11.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     11.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     11.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     11.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     11.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     11.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     11.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     11.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     11.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     11.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     11.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     11.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     11.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     11.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     11.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     11.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     11.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     11.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     11.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     11.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     11.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     11.83% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               11923525     64.32%     76.15% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               4420966     23.85%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 2188252     11.81%     11.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     11.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     11.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     11.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     11.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     11.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     11.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     11.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     11.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     11.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     11.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     11.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     11.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     11.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     11.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     11.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     11.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     11.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     11.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     11.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     11.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     11.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     11.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     11.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     11.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     11.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     11.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     11.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     11.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               11925862     64.39%     76.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               4407339     23.80%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1643778581     65.50%     65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                  107      0.00%     65.50% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1643881644     65.50%     65.50% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                   99      0.00%     65.50% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                 275      0.00%     65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                  16      0.00%     65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                 160      0.00%     65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                 33      0.00%     65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                  24      0.00%     65.50% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                 265      0.00%     65.50% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                  15      0.00%     65.50% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                 161      0.00%     65.50% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                 23      0.00%     65.50% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                  25      0.00%     65.50% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     65.50% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     65.50% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     65.50% # Type of FU issued
@@ -524,84 +493,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     65.50% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     65.50% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     65.50% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            641602507     25.57%     91.07% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           224107818      8.93%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            641614566     25.57%     91.07% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           224113754      8.93%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             2509489521                       # Type of FU issued
-system.cpu.iq.rate                           1.830711                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    18537627                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.007387                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         6323623582                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        3703265011                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   2413078875                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads             1898180                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes            1217876                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses       850894                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             2527088869                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                  938279                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         62595515                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             2509610552                       # Type of FU issued
+system.cpu.iq.rate                           1.839373                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    18521453                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.007380                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         6321098058                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        3703474382                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   2413201675                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             1900077                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes            1218284                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses       852187                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             2527192648                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                  939357                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         62588107                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    235063652                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses       262733                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       107683                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     94735574                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads    235106579                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       263309                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       109146                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     94747058                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads          113                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked       1541249                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads          184                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked       1530387                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles              116795361                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                56591518                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               1298088                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          2866959659                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts           8943399                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             679659315                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            255464076                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                120                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 282702                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 18018                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         107683                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect       10360004                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      8558145                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             18918149                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            2462143246                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             625230973                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          47346275                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles              116814687                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                54760955                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               1302145                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          2867095326                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           8936600                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             679702242                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            255475560                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                131                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 285836                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 18373                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         109146                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect       10363389                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      8561306                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             18924695                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            2462265598                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             625238282                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          47344954                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                     142158292                       # number of nop insts executed
-system.cpu.iew.exec_refs                    844719037                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                300873221                       # Number of branches executed
-system.cpu.iew.exec_stores                  219488064                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.796171                       # Inst execution rate
-system.cpu.iew.wb_sent                     2441862108                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    2413929769                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1388272639                       # num instructions producing a value
-system.cpu.iew.wb_consumers                1764258225                       # num instructions consuming a value
+system.cpu.iew.exec_nop                     142180734                       # number of nop insts executed
+system.cpu.iew.exec_refs                    844736593                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                300891924                       # Number of branches executed
+system.cpu.iew.exec_stores                  219498311                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.804673                       # Inst execution rate
+system.cpu.iew.wb_sent                     2442007403                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    2414053862                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1388335082                       # num instructions producing a value
+system.cpu.iew.wb_consumers                1764294016                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.760999                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.786887                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.769337                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.786907                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts       826504574                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       826637792                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              29                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts          16081360                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples   1168002444                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.558028                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.499439                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts          16091391                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples   1165244559                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.561715                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.500982                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    654033697     56.00%     56.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    174911016     14.98%     70.97% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     86140681      7.38%     78.35% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     53576194      4.59%     82.93% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     34697975      2.97%     85.90% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     25994339      2.23%     88.13% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6     21604457      1.85%     89.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     22883851      1.96%     91.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     94160234      8.06%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    651170378     55.88%     55.88% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    175014835     15.02%     70.90% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     86149099      7.39%     78.30% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     53527990      4.59%     82.89% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     34710349      2.98%     85.87% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     26102733      2.24%     88.11% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     21568948      1.85%     89.96% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     22887442      1.96%     91.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     94112785      8.08%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total   1168002444                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total   1165244559                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts           1819780126                       # Number of instructions committed
 system.cpu.commit.committedOps             1819780126                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -612,225 +581,224 @@ system.cpu.commit.branches                  214632552                       # Nu
 system.cpu.commit.fp_insts                     805525                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                1718967519                       # Number of committed integer instructions.
 system.cpu.commit.function_calls             16767440                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events              94160234                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events              94112785                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   3634347710                       # The number of ROB reads
-system.cpu.rob.rob_writes                  5409463480                       # The number of ROB writes
-system.cpu.timesIdled                          947782                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        85975286                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                   3631770492                       # The number of ROB reads
+system.cpu.rob.rob_writes                  5409749589                       # The number of ROB writes
+system.cpu.timesIdled                          953701                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        82324369                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                  1736043781                       # Number of Instructions Simulated
 system.cpu.committedOps                    1736043781                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total            1736043781                       # Number of Instructions Simulated
-system.cpu.cpi                               0.789596                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.789596                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.266471                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.266471                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               3318031256                       # number of integer regfile reads
-system.cpu.int_regfile_writes              1931984794                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                     30556                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                      536                       # number of floating regfile writes
+system.cpu.cpi                               0.785915                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.785915                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.272402                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.272402                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               3318200326                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1932098427                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                     30699                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                      520                       # number of floating regfile writes
 system.cpu.misc_regfile_reads                      25                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput              1205179048                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq        7297603                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       7297603                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      3725230                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      1883628                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      1883628                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1930                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     22085762                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          22087692                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        61760                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    825951744                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      826013504                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus         826013504                       # Total data (bytes)
+system.cpu.toL2Bus.throughput              1210780745                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq        7297678                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       7297678                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      3724768                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      1883565                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      1883565                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1928                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     22085326                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          22087254                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        61696                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    825923008                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      825984704                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         825984704                       # Total data (bytes)
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy    10178550909                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.occupancy    10177843430                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.5                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1610000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       1605500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   14084464250                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy   14065476499                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          2.1                       # Layer utilization (%)
 system.cpu.icache.tags.replacements                 1                       # number of replacements
-system.cpu.icache.tags.tagsinuse           773.100738                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           391053395                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               965                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          405236.678756                       # Average number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           773.695817                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           391108717                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               964                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          405714.436722                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   773.100738                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.377491                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.377491                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          964                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          907                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.470703                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         782110757                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        782110757                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    391053395                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       391053395                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     391053395                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        391053395                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    391053395                       # number of overall hits
-system.cpu.icache.overall_hits::total       391053395                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         1501                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          1501                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         1501                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           1501                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         1501                       # number of overall misses
-system.cpu.icache.overall_misses::total          1501                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    108152500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    108152500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    108152500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    108152500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    108152500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    108152500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    391054896                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    391054896                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    391054896                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    391054896                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    391054896                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    391054896                       # number of overall (read+write) accesses
+system.cpu.icache.tags.occ_blocks::cpu.inst   773.695817                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.377781                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.377781                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          963                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           57                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          906                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.470215                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         782221404                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        782221404                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    391108717                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       391108717                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     391108717                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        391108717                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    391108717                       # number of overall hits
+system.cpu.icache.overall_hits::total       391108717                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1503                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1503                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1503                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1503                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1503                       # number of overall misses
+system.cpu.icache.overall_misses::total          1503                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    108284500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    108284500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    108284500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    108284500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    108284500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    108284500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    391110220                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    391110220                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    391110220                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    391110220                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    391110220                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    391110220                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000004                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000004                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000004                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000004                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000004                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000004                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72053.630913                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 72053.630913                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 72053.630913                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 72053.630913                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 72053.630913                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 72053.630913                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          156                       # number of cycles access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72045.575516                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 72045.575516                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 72045.575516                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 72045.575516                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 72045.575516                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 72045.575516                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          349                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 2                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 5                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs           78                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    69.800000                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          536                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          536                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          536                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          536                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          536                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          536                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          965                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          965                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          965                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          965                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          965                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          965                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     75095000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     75095000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     75095000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     75095000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     75095000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     75095000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          539                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          539                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          539                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          539                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          539                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          539                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          964                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          964                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          964                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          964                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          964                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          964                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     75722000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     75722000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     75722000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     75722000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     75722000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     75722000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000002                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77818.652850                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77818.652850                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77818.652850                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 77818.652850                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77818.652850                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 77818.652850                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78549.792531                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78549.792531                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78549.792531                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 78549.792531                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78549.792531                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 78549.792531                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements          1933762                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        31423.393947                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            9058762                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1963540                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             4.613485                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle      28354220250                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 14586.517425                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    26.834239                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 16810.042284                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.445145                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000819                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.513002                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.958966                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        29778                       # Occupied blocks per task id
+system.cpu.l2cache.tags.replacements          1933885                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        31421.269549                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            9058254                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          1963664                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             4.612935                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle      28359986250                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 14571.956791                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    26.815575                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 16822.497182                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.444701                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000818                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.513382                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.958901                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        29779                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          146                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          978                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          594                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3        17297                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        10763                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.908752                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        107098856                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       107098856                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.data      6106330                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        6106330                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      3725230                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      3725230                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1108435                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1108435                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.data      7214765                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         7214765                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.data      7214765                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        7214765                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          965                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data      1190308                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total      1191273                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       775193                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       775193                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          965                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data      1965501                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total       1966466                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          965                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data      1965501                       # number of overall misses
-system.cpu.l2cache.overall_misses::total      1966466                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     74125000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 102633894750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 102708019750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  67309627250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  67309627250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     74125000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 169943522000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 170017647000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     74125000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 169943522000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 170017647000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          965                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      7296638                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      7297603                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      3725230                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      3725230                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data      1883628                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total      1883628                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          965                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      9180266                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      9181231                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          965                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      9180266                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      9181231                       # number of overall (read+write) accesses
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          974                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          593                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        17299                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        10767                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.908783                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        107095317                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       107095317                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.data      6106239                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        6106239                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      3724768                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      3724768                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data      1108414                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total      1108414                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.data      7214653                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         7214653                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.data      7214653                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        7214653                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          964                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data      1190475                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total      1191439                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       775151                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       775151                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          964                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data      1965626                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total       1966590                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          964                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data      1965626                       # number of overall misses
+system.cpu.l2cache.overall_misses::total      1966590                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     74752000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data  99906666750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total  99981418750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  65179640000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  65179640000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     74752000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 165086306750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 165161058750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     74752000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 165086306750                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 165161058750                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          964                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      7296714                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      7297678                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      3724768                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      3724768                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data      1883565                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total      1883565                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          964                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      9180279                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      9181243                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          964                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      9180279                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      9181243                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst            1                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.163131                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.163242                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.411543                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.411543                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.163152                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.163263                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.411534                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.411534                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst            1                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.214101                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.214183                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.214114                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.214196                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.214101                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.214183                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76813.471503                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 86224.653409                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 86217.029808                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 86829.508587                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 86829.508587                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76813.471503                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86463.208108                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 86458.472712                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76813.471503                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86463.208108                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 86458.472712                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.214114                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.214196                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77543.568465                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83921.683992                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 83916.523423                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 84086.378009                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 84086.378009                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77543.568465                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83986.631613                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 83983.473296                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77543.568465                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83986.631613                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 83983.473296                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -839,188 +807,188 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks      1019736                       # number of writebacks
-system.cpu.l2cache.writebacks::total          1019736                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          965                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data      1190308                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total      1191273                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       775193                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       775193                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          965                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data      1965501                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total      1966466                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          965                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data      1965501                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total      1966466                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     61971000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  87692417750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  87754388750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  57554177250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  57554177250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     61971000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 145246595000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 145308566000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     61971000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 145246595000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 145308566000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.writebacks::writebacks      1019781                       # number of writebacks
+system.cpu.l2cache.writebacks::total          1019781                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          964                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data      1190475                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total      1191439                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       775151                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       775151                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          964                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data      1965626                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total      1966590                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          964                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data      1965626                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total      1966590                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     62625000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  84983280750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  85045905750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  55444498500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  55444498500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     62625000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 140427779250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 140490404250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     62625000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 140427779250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 140490404250                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.163131                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.163242                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.411543                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.411543                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.163152                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.163263                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.411534                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.411534                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.214101                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.214183                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.214114                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.214196                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.214101                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.214183                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64218.652850                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73672.039296                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 73664.381506                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 74244.965125                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 74244.965125                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64218.652850                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73898.001069                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73893.251142                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64218.652850                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73898.001069                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73893.251142                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.214114                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.214196                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64963.692946                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71386.027216                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71380.830869                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71527.352090                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71527.352090                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64963.692946                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71441.759139                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71438.583665                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64963.692946                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71441.759139                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71438.583665                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements           9176170                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4087.561673                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           694256138                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           9180266                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             75.624839                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.replacements           9176183                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4087.522150                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           694277633                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           9180279                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             75.627073                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle        5178034250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4087.561673                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.997940                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.997940                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data  4087.522150                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.997930                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.997930                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          690                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         2994                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          408                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          705                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         2966                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          421                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3            4                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1430860164                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1430860164                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    538716411                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       538716411                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    155539725                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      155539725                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data            2                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total            2                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data     694256136                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        694256136                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    694256136                       # number of overall hits
-system.cpu.dcache.overall_hits::total       694256136                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data     11395033                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total      11395033                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      5188777                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      5188777                       # number of WriteReq misses
+system.cpu.dcache.tags.tag_accesses        1430905565                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1430905565                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    538740047                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       538740047                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    155537583                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      155537583                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data            3                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total            3                       # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits::cpu.data     694277630                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        694277630                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    694277630                       # number of overall hits
+system.cpu.dcache.overall_hits::total       694277630                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data     11394090                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total      11394090                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      5190919                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      5190919                       # number of WriteReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            1                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            1                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data     16583810                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total       16583810                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data     16583810                       # number of overall misses
-system.cpu.dcache.overall_misses::total      16583810                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 343354515500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 343354515500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 296317441834                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 296317441834                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        92250                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total        92250                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 639671957334                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 639671957334                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 639671957334                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 639671957334                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    550111444                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    550111444                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data     16585009                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total       16585009                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data     16585009                       # number of overall misses
+system.cpu.dcache.overall_misses::total      16585009                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 335805939499                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 335805939499                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 289123962439                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 289123962439                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       201500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total       201500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 624929901938                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 624929901938                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 624929901938                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 624929901938                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    550134137                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    550134137                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    160728502                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    160728502                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data            3                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total            3                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    710839946                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    710839946                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    710839946                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    710839946                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.020714                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.020714                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.032283                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.032283                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.333333                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.333333                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.023330                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.023330                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.023330                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.023330                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30131.945691                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 30131.945691                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57107.376523                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 57107.376523                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        92250                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        92250                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 38572.074652                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 38572.074652                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 38572.074652                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 38572.074652                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs     12375504                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets      8646342                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs            745563                       # number of cycles access was blocked
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data            4                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total            4                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    710862639                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    710862639                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    710862639                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    710862639                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.020711                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.020711                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.032296                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.032296                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.250000                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.250000                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.023331                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.023331                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.023331                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.023331                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 29471.940234                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 29471.940234                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55698.030048                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 55698.030048                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data       201500                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total       201500                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 37680.407767                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 37680.407767                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 37680.407767                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 37680.407767                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs     11880802                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets      8587513                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs            745209                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets           65135                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    16.598871                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets   132.744945                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    15.942913                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets   131.841759                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      3725230                       # number of writebacks
-system.cpu.dcache.writebacks::total           3725230                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      4098384                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      4098384                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3305161                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      3305161                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      7403545                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      7403545                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      7403545                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      7403545                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7296649                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      7296649                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1883616                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      1883616                       # number of WriteReq MSHR misses
+system.cpu.dcache.writebacks::writebacks      3724768                       # number of writebacks
+system.cpu.dcache.writebacks::total           3724768                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      4097367                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      4097367                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3307364                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      3307364                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      7404731                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      7404731                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      7404731                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      7404731                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7296723                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      7296723                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1883555                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      1883555                       # number of WriteReq MSHR misses
 system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data            1                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.LoadLockedReq_mshr_misses::total            1                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      9180265                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      9180265                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      9180265                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      9180265                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 171833895250                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 171833895250                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  80710616128                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  80710616128                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data        89750                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total        89750                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 252544511378                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 252544511378                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 252544511378                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 252544511378                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data      9180278                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      9180278                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      9180278                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      9180278                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 169103281751                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 169103281751                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  78582140948                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  78582140948                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data       199500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total       199500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 247685422699                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 247685422699                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 247685422699                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 247685422699                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.013264                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.013264                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.011719                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.011719                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.333333                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.333333                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.012915                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.012915                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.012915                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.012915                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23549.700040                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23549.700040                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42848.763298                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42848.763298                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data        89750                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total        89750                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27509.501237                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 27509.501237                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27509.501237                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 27509.501237                       # average overall mshr miss latency
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.250000                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.250000                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.012914                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.012914                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.012914                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.012914                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23175.236576                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23175.236576                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41720.120171                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41720.120171                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data       199500                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total       199500                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26980.165818                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 26980.165818                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26980.165818                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 26980.165818                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 8c6f8359fc3081400d1f6d7c5d4c75631a343ef3..06e7873ee11d080377d5039bbff1957fe3905b70 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.533762                       # Number of seconds simulated
-sim_ticks                                533761922000                       # Number of ticks simulated
-final_tick                               533761922000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.530994                       # Number of seconds simulated
+sim_ticks                                530994193500                       # Number of ticks simulated
+final_tick                               530994193500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 155948                       # Simulator instruction rate (inst/s)
-host_op_rate                                   173972                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               53891847                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 269768                       # Number of bytes of host memory used
-host_seconds                                  9904.32                       # Real time elapsed on the host
+host_inst_rate                                 125227                       # Simulator instruction rate (inst/s)
+host_op_rate                                   139700                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               43051016                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 313040                       # Number of bytes of host memory used
+host_seconds                                 12334.07                       # Real time elapsed on the host
 sim_insts                                  1544563023                       # Number of instructions simulated
 sim_ops                                    1723073835                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             47616                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         143740736                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            143788352                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        47616                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           47616                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     70437056                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          70437056                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst                744                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            2245949                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               2246693                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1100579                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1100579                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                89208                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            269297472                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               269386680                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           89208                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              89208                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks         131963434                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              131963434                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks         131963434                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               89208                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           269297472                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              401350114                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       2246694                       # Number of read requests accepted
-system.physmem.writeReqs                      1100579                       # Number of write requests accepted
-system.physmem.readBursts                     2246694                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1100579                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                143750848                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     37568                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  70435904                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 143788416                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               70437056                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      587                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst             47488                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         143709888                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            143757376                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        47488                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           47488                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     70419456                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          70419456                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst                742                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            2245467                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               2246209                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1100304                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1100304                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst                89432                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            270643050                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               270732482                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           89432                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              89432                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks         132618128                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              132618128                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks         132618128                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               89432                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           270643050                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              403350610                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       2246209                       # Number of read requests accepted
+system.physmem.writeReqs                      1100304                       # Number of write requests accepted
+system.physmem.readBursts                     2246209                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1100304                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                143663936                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     93440                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  70418368                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 143757376                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               70419456                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                     1460                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              139629                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              136292                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              133828                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              136435                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              134766                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              135151                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              136244                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              136309                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              143829                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              146501                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             144298                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             146295                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             145712                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             146106                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             142241                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             142471                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               69077                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               67426                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               65726                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               66343                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               66130                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               66357                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               67984                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               68878                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               70373                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               70997                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              70493                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              70981                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              70269                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              70812                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              69646                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              69069                       # Per bank write bursts
+system.physmem.perBankRdBursts::0              139551                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              136202                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              133682                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              136207                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              134706                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              135350                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              136147                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              135992                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              143786                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              146457                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             144536                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             146082                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             145807                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             145943                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             141988                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             142313                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               69095                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               67437                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               65633                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               66265                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               66084                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               66429                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               67953                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               68751                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               70388                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               70973                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              70609                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              70934                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              70330                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              70711                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              69591                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              69104                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           2                       # Number of times write queue was full causing retry
-system.physmem.totGap                    533761847000                       # Total gap between requests
+system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
+system.physmem.totGap                    530994124500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 2246694                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 2246209                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1100579                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1621644                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    445219                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                    135704                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     43528                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        11                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1100304                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1619262                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    446010                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                    134777                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     44683                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        15                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
@@ -129,216 +129,178 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                     48877                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                     49060                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                     49089                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                     49071                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                     49076                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                     49104                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                     49085                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                     49081                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                     49079                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                     49128                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                    49123                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                    49158                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                    49172                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                    49261                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                    49504                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    49899                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    50373                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    52060                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    52016                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    51492                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    52976                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    52139                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     2343                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                      326                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                       39                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                       16                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                        6                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                        6                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                        5                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                        5                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                        6                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      2078319                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      103.049035                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean      79.954808                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     184.695982                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64-65        1660986     79.92%     79.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-129       227336     10.94%     90.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192-193        68882      3.31%     94.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-257        37662      1.81%     95.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320-321        25035      1.20%     97.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-385        12093      0.58%     97.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448-449         8438      0.41%     98.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-513         8141      0.39%     98.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576-577         4391      0.21%     98.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-641         3442      0.17%     98.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704-705         2829      0.14%     99.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-769         1974      0.09%     99.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832-833         1676      0.08%     99.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-897         1442      0.07%     99.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960-961         1174      0.06%     99.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1025         1106      0.05%     99.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088-1089          969      0.05%     99.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152-1153          858      0.04%     99.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216-1217          735      0.04%     99.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280-1281          673      0.03%     99.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344-1345          651      0.03%     99.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408-1409         3128      0.15%     99.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472-1473          421      0.02%     99.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536-1537          240      0.01%     99.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600-1601          179      0.01%     99.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664-1665          200      0.01%     99.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1728-1729          207      0.01%     99.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1792-1793          498      0.02%     99.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856-1857          133      0.01%     99.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1920-1921          147      0.01%     99.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984-1985          136      0.01%     99.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2048-2049          128      0.01%     99.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112-2113           89      0.00%     99.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2176-2177          121      0.01%     99.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2240-2241          102      0.00%     99.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2304-2305          117      0.01%     99.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2368-2369           77      0.00%     99.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2432-2433           74      0.00%     99.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2496-2497           59      0.00%     99.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2560-2561           70      0.00%     99.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2624-2625           60      0.00%     99.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2688-2689           54      0.00%     99.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2752-2753           55      0.00%     99.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2816-2817           76      0.00%     99.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2880-2881           49      0.00%     99.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2944-2945           45      0.00%     99.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3008-3009           33      0.00%     99.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3072-3073           66      0.00%     99.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3136-3137           39      0.00%     99.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3200-3201           33      0.00%     99.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3264-3265           36      0.00%     99.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3328-3329           47      0.00%     99.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3392-3393           27      0.00%     99.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3456-3457           23      0.00%     99.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3520-3521           22      0.00%     99.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3584-3585           27      0.00%     99.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3648-3649           21      0.00%     99.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3712-3713           25      0.00%     99.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3776-3777           26      0.00%     99.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3840-3841           40      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3904-3905           20      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3968-3969           18      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4032-4033           16      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4096-4097           30      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4160-4161           10      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4224-4225           21      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4288-4289           16      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4352-4353           36      0.00%     99.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4416-4417           15      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4480-4481           15      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4544-4545           13      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4608-4609           17      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4672-4673           11      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4736-4737           17      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4800-4801           17      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4864-4865           32      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4928-4929           10      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4992-4993           14      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5056-5057           15      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5120-5121           31      0.00%     99.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5184-5185           15      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5248-5249           10      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5312-5313            9      0.00%     99.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5376-5377          206      0.01%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5440-5441            4      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5504-5505            6      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5568-5569            4      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5632-5633            3      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5696-5697            3      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5824-5825            2      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5888-5889           22      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5952-5953            6      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6016-6017            4      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6080-6081            3      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6144-6145            5      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6208-6209            4      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6272-6273            3      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6336-6337            1      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6400-6401           20      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6464-6465            2      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6592-6593            3      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6656-6657           37      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6720-6721            2      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6784-6785            4      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6848-6849            1      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6912-6913            5      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6976-6977            3      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7040-7041            2      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7104-7105            3      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7168-7169           13      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7232-7233            1      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7296-7297            1      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7360-7361            6      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7488-7489            1      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7552-7553            1      0.00%     99.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7616-7617            4      0.00%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7680-7681            3      0.00%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7872-7873            1      0.00%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7936-7937            6      0.00%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8000-8001            1      0.00%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8064-8065            4      0.00%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8192-8193           88      0.00%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        2078319                       # Bytes accessed per row activation
-system.physmem.totQLat                    32815970750                       # Total ticks spent queuing
-system.physmem.totMemAccLat              104054627000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                  11230535000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                 60008121250                       # Total ticks spent accessing banks
-system.physmem.avgQLat                       14610.15                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    26716.50                       # Average bank access latency per DRAM burst
+system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                    17958                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    19185                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    29573                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    48522                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    58770                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    63067                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    64531                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    65202                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    65713                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    66239                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    70263                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    71854                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    72330                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    80202                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    72456                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    68391                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    66809                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    65859                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                    22753                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                     6508                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                     1933                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      609                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      277                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                      176                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                      132                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                      105                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                       91                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                       84                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                       74                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                       70                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                       70                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                       67                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                       67                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                       70                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                       60                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       59                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       49                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       42                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       44                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples      1604351                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      105.964762                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean      82.430314                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     134.227606                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127        1240784     77.34%     77.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       261404     16.29%     93.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        44793      2.79%     96.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        17157      1.07%     97.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        10128      0.63%     98.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         4810      0.30%     98.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         3056      0.19%     98.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         2546      0.16%     98.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        19673      1.23%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        1604351                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         64945                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        34.562861                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      155.173168                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023          64902     99.93%     99.93% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047           18      0.03%     99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-3071           12      0.02%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3072-4095            6      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::4096-5119            2      0.00%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::10240-11263            1      0.00%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::12288-13311            2      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::14336-15359            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::22528-23551            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total           64945                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         64945                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.941828                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.872806                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.740981                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-17           45649     70.29%     70.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18-19           15339     23.62%     93.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-21            3628      5.59%     99.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22-23             219      0.34%     99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-25              37      0.06%     99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26-27              12      0.02%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-29              13      0.02%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30-31               7      0.01%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-37               2      0.00%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::38-39               4      0.01%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-41              17      0.03%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::42-43               3      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-45               2      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-53               1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::54-55               1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-57               1      0.00%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-61               1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::66-67               1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-69               1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-77               1      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-81               2      0.00%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::82-83               1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-85               1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-89               1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::90-91               1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           64945                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    28406230500                       # Total ticks spent queuing
+system.physmem.totMemAccLat               98095071750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                  11223745000                       # Total ticks spent in databus transfers
+system.physmem.totBankLat                 58465096250                       # Total ticks spent accessing banks
+system.physmem.avgQLat                       12654.52                       # Average queueing delay per DRAM burst
+system.physmem.avgBankLat                    26045.27                       # Average bank access latency per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  46326.66                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         269.32                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                         131.96                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      269.39                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                      131.96                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  43699.80                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         270.56                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                         132.62                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      270.73                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                      132.62                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           3.13                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       2.10                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      1.03                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         0.19                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        10.33                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     932061                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    336288                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   41.50                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  30.56                       # Row buffer hit rate for writes
-system.physmem.avgGap                       159461.70                       # Average gap between requests
-system.physmem.pageHitRate                      37.90                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               5.96                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                    401350114                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq             1420099                       # Transaction distribution
-system.membus.trans_dist::ReadResp            1420098                       # Transaction distribution
-system.membus.trans_dist::Writeback           1100579                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            826595                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           826595                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5593966                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                5593966                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    214225408                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total           214225408                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus              214225408                       # Total data (bytes)
+system.physmem.busUtil                           3.15                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       2.11                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      1.04                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.18                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        25.38                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     908698                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    419053                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   40.48                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  38.09                       # Row buffer hit rate for writes
+system.physmem.avgGap                       158670.87                       # Average gap between requests
+system.physmem.pageHitRate                      39.69                       # Row buffer hit rate, read and write combined
+system.physmem.prechargeAllPercent               6.04                       # Percentage of time for which DRAM has all the banks in precharge state
+system.membus.throughput                    403350610                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq             1419771                       # Transaction distribution
+system.membus.trans_dist::ReadResp            1419771                       # Transaction distribution
+system.membus.trans_dist::Writeback           1100304                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            826438                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           826438                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5592722                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                5592722                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    214176832                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total           214176832                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus              214176832                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy         12926034750                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy         12918660500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               2.4                       # Layer utilization (%)
-system.membus.respLayer1.occupancy        21084340000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy        21056537500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              4.0                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups               303426723                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         249665263                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          15197446                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            174885075                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               161766496                       # Number of BTB hits
+system.cpu.branchPred.lookups               303422540                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         249650550                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          15218950                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            174790549                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               161666933                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             92.498743                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                17552924                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                181                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             92.491805                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                17552768                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                208                       # Number of incorrect RAS predictions.
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -424,132 +386,133 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                   46                       # Number of system calls
-system.cpu.numCycles                       1067523845                       # number of cpu cycles simulated
+system.cpu.numCycles                       1061988388                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          299169160                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     2189552617                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   303426723                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          179319420                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     435766349                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                88088140                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles              164108706                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.PendingTrapStallCycles           249                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                 289578845                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               5989031                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          969003000                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.499478                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.206212                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          298972523                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     2188716520                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   303422540                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          179219701                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     435616214                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                87982008                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles              163592873                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                    1                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles            98                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                 289402821                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               5967581                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          968083151                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.501232                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.206704                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                533236766     55.03%     55.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 25461427      2.63%     57.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 39064672      4.03%     61.69% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 48308848      4.99%     66.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 43759414      4.52%     71.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 46393042      4.79%     75.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 38404129      3.96%     79.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 18940871      1.95%     81.90% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                175433831     18.10%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                532467013     55.00%     55.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 25400980      2.62%     57.63% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 39071584      4.04%     61.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 48282365      4.99%     66.65% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 43747142      4.52%     71.17% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 46387901      4.79%     75.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 38401401      3.97%     79.93% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 18925667      1.95%     81.88% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                175399098     18.12%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            969003000                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.284234                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.051057                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                331406137                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             141956827                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 405364012                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              20318148                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               69957876                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             46020737                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                   686                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             2369052643                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                  2441                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles               69957876                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                354906744                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                70525275                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          17150                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 400533325                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              73062630                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             2306235389                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                151230                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                5013278                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents              60135849                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents               19                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands          2282078057                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups           10649208068                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       9763247621                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups               332                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            968083151                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.285712                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.060961                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                331186258                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             141449476                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 405224090                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              20322579                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               69900748                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             46031045                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                   725                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             2368410495                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                  2465                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles               69900748                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                354622933                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                70003752                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          18690                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 400463677                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              73073351                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             2305921736                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                149865                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                5017686                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents              60142463                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents               10                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands          2281817078                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups           10647699630                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       9761875654                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups               372                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps            1706319930                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                575758127                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                542                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            539                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 160926093                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            624728249                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           220785157                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          86065935                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         71218939                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 2202289570                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                 584                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                2018746767                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           4010968                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       474628449                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined   1127376318                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            414                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     969003000                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.083324                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.906240                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                575497148                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                824                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            821                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 160915749                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            624658588                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           220783882                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          86055084                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         71680407                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 2202175358                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                 849                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                2018579412                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           4016690                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       474511400                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined   1127247409                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            679                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     968083151                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.085130                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.905910                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           286111139     29.53%     29.53% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           153618591     15.85%     45.38% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           160911412     16.61%     61.99% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           120366979     12.42%     74.41% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4           123454210     12.74%     87.15% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            73801369      7.62%     94.76% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            38320646      3.95%     98.72% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             9892378      1.02%     99.74% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             2526276      0.26%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           285219249     29.46%     29.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           153603913     15.87%     45.33% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           160908478     16.62%     61.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           120369215     12.43%     74.38% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4           123515877     12.76%     87.14% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            73725483      7.62%     94.76% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            38349194      3.96%     98.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             9869125      1.02%     99.74% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             2522617      0.26%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       969003000                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       968083151                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  901909      3.77%      3.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                   5511      0.02%      3.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      3.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               18267438     76.34%     80.13% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               4754077     19.87%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  891948      3.74%      3.74% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                   5659      0.02%      3.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      3.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      3.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      3.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      3.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      3.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      3.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      3.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      3.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      3.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      3.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      3.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      3.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      3.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      3.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      3.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      3.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      3.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      3.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      3.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      3.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      3.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      3.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      3.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      3.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      3.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      3.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      3.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               18285123     76.74%     80.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               4644794     19.49%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1236913920     61.27%     61.27% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               925199      0.05%     61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1236892590     61.28%     61.28% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               924644      0.05%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   2      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     61.32% # Type of FU issued
@@ -571,90 +534,90 @@ system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     61.32% # Ty
 system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt              31      0.00%     61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt              35      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatDiv               1      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMisc             20      0.00%     61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              6      0.00%     61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              5      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            587869811     29.12%     90.44% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           193037777      9.56%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            587766580     29.12%     90.44% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           192995535      9.56%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             2018746767                       # Type of FU issued
-system.cpu.iq.rate                           1.891055                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    23928935                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.011853                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         5034436167                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        2677107941                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1957305969                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 270                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                526                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses          103                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             2042675566                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     136                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         64599963                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             2018579412                       # Type of FU issued
+system.cpu.iq.rate                           1.900755                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    23827524                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.011804                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         5033085915                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        2676877502                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1957286875                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 274                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                546                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses          114                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             2042406797                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     139                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         64607409                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    138801480                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses       270727                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       192405                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     45938112                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads    138731819                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       269264                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       192926                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     45936837                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            5                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked       4771665                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked       4636852                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               69957876                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                33460674                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               1602950                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          2202290297                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts           7880065                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             624728249                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            220785157                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                522                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 477902                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 97314                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         192405                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        8143338                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      9598007                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             17741345                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            1988017569                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             574014855                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          30729198                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles               69900748                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                32985264                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               1607893                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          2202176322                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           7875030                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             624658588                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            220783882                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                787                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 480489                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 97297                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         192926                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        8154150                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      9614096                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             17768246                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1987907812                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             573917969                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          30671600                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                           143                       # number of nop insts executed
-system.cpu.iew.exec_refs                    764181270                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                238318975                       # Number of branches executed
-system.cpu.iew.exec_stores                  190166415                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.862270                       # Inst execution rate
-system.cpu.iew.wb_sent                     1965726867                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    1957306072                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1295394361                       # num instructions producing a value
-system.cpu.iew.wb_consumers                2059160488                       # num instructions consuming a value
+system.cpu.iew.exec_nop                           115                       # number of nop insts executed
+system.cpu.iew.exec_refs                    764035004                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                238344765                       # Number of branches executed
+system.cpu.iew.exec_stores                  190117035                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.871873                       # Inst execution rate
+system.cpu.iew.wb_sent                     1965721385                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1957286989                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1295353169                       # num instructions producing a value
+system.cpu.iew.wb_consumers                2059124619                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.833501                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.629089                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.843040                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.629080                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts       479315418                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       479201419                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             170                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts          15196786                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    899045124                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.916560                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.718243                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts          15218256                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    898182403                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.918401                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.718632                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    410462230     45.66%     45.66% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    193303811     21.50%     67.16% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     72810970      8.10%     75.26% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     35275316      3.92%     79.18% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     18883906      2.10%     81.28% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     30780783      3.42%     84.70% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6     19963318      2.22%     86.92% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     11415613      1.27%     88.19% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8    106149177     11.81%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    409520932     45.59%     45.59% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    193341126     21.53%     67.12% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     72856392      8.11%     75.23% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     35266381      3.93%     79.16% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     18923261      2.11%     81.27% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     30757515      3.42%     84.69% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     19970325      2.22%     86.91% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     11453537      1.28%     88.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8    106092934     11.81%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    899045124                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    898182403                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts           1544563041                       # Number of instructions committed
 system.cpu.commit.committedOps             1723073853                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -665,98 +628,99 @@ system.cpu.commit.branches                  213462426                       # Nu
 system.cpu.commit.fp_insts                         36                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                1536941841                       # Number of committed integer instructions.
 system.cpu.commit.function_calls             13665177                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events             106149177                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events             106092934                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   2995284619                       # The number of ROB reads
-system.cpu.rob.rob_writes                  4474886700                       # The number of ROB writes
-system.cpu.timesIdled                         1153694                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        98520845                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                   2994364142                       # The number of ROB reads
+system.cpu.rob.rob_writes                  4474601624                       # The number of ROB writes
+system.cpu.timesIdled                         1160522                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        93905237                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                  1544563023                       # Number of Instructions Simulated
 system.cpu.committedOps                    1723073835                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total            1544563023                       # Number of Instructions Simulated
-system.cpu.cpi                               0.691149                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.691149                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.446865                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.446865                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               9956057659                       # number of integer regfile reads
-system.cpu.int_regfile_writes              1937206435                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                        98                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                       94                       # number of floating regfile writes
-system.cpu.misc_regfile_reads               737611057                       # number of misc regfile reads
+system.cpu.cpi                               0.687566                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.687566                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.454407                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.454407                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               9955508978                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1937309574                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                       108                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                      108                       # number of floating regfile writes
+system.cpu.misc_regfile_reads               737568033                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                    124                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput              1604912326                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq        7709455                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       7709454                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      3782070                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      1893493                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      1893493                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1550                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     22986415                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          22987965                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        49600                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    856591488                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      856641088                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus         856641088                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy    10474747083                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.throughput              1613255878                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq        7708873                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       7708872                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      3782409                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq            3                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp            3                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      1893555                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      1893555                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1549                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     22985720                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          22987269                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        49536                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    856579904                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      856629440                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         856629440                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus           64                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy    10474986844                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          2.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1295998                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       1289999                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   14769977492                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy   14746367742                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          2.8                       # Layer utilization (%)
-system.cpu.icache.tags.replacements                19                       # number of replacements
-system.cpu.icache.tags.tagsinuse           628.273269                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           289577640                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               775                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          373648.567742                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements                17                       # number of replacements
+system.cpu.icache.tags.tagsinuse           631.201883                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           289401615                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               772                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          374872.558290                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   628.273269                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.306774                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.306774                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          756                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst   631.201883                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.308204                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.308204                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          755                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           23                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2            4                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          727                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.369141                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         579158465                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        579158465                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    289577640                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       289577640                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     289577640                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        289577640                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    289577640                       # number of overall hits
-system.cpu.icache.overall_hits::total       289577640                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         1205                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          1205                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         1205                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           1205                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         1205                       # number of overall misses
-system.cpu.icache.overall_misses::total          1205                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     81284498                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     81284498                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     81284498                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     81284498                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     81284498                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     81284498                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    289578845                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    289578845                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    289578845                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    289578845                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    289578845                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    289578845                       # number of overall (read+write) accesses
+system.cpu.icache.tags.age_task_id_blocks_1024::2            3                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          729                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.368652                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         578806417                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        578806417                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    289401622                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       289401622                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     289401622                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        289401622                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    289401622                       # number of overall hits
+system.cpu.icache.overall_hits::total       289401622                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1199                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1199                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1199                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1199                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1199                       # number of overall misses
+system.cpu.icache.overall_misses::total          1199                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     84823499                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     84823499                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     84823499                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     84823499                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     84823499                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     84823499                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    289402821                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    289402821                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    289402821                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    289402821                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    289402821                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    289402821                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000004                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000004                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000004                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000004                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000004                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000004                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67456.014938                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 67456.014938                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 67456.014938                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 67456.014938                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 67456.014938                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 67456.014938                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70745.203503                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 70745.203503                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 70745.203503                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 70745.203503                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 70745.203503                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 70745.203503                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs          202                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 4                       # number of cycles access was blocked
@@ -765,129 +729,133 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs    50.500000
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          430                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          430                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          430                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          430                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          430                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          430                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          424                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          424                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          424                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          424                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          424                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          424                       # number of overall MSHR hits
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          775                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total          775                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst          775                       # number of demand (read+write) MSHR misses
 system.cpu.icache.demand_mshr_misses::total          775                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          775                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          775                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     55854002                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     55854002                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     55854002                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     55854002                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     55854002                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     55854002                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     56494501                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     56494501                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     56494501                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     56494501                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     56494501                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     56494501                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000003                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000003                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000003                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000003                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000003                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000003                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72069.680000                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72069.680000                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72069.680000                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 72069.680000                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72069.680000                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 72069.680000                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72896.130323                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72896.130323                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72896.130323                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 72896.130323                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72896.130323                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 72896.130323                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements          2214011                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        31532.870200                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            9247003                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          2243785                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             4.121163                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle      21623958250                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 14303.376165                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    20.256077                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 17209.237958                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.436504                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000618                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.525184                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.962307                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.replacements          2213521                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        31530.649727                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            9247246                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          2243295                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             4.122171                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle      21629133000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 14295.824986                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    20.209231                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 17214.615510                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.436274                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000617                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.525348                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.962239                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        29774                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           92                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           97                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1           79                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1894                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3        23751                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         3958                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1889                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        23754                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         3955                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.908630                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        111217422                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       111217422                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst           29                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data      6289318                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        6289347                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      3782070                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      3782070                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1066898                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1066898                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst           29                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      7356216                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         7356245                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst           29                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      7356216                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        7356245                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          746                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data      1419362                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total      1420108                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       826595                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       826595                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          746                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data      2245957                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total       2246703                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          746                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data      2245957                       # number of overall misses
-system.cpu.l2cache.overall_misses::total      2246703                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     54783500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 125692113250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 125746896750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  76318094500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  76318094500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     54783500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 202010207750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 202064991250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     54783500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 202010207750                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 202064991250                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          775                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      7708680                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      7709455                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      3782070                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      3782070                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data      1893493                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total      1893493                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          775                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      9602173                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      9602948                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          775                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      9602173                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      9602948                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.962581                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.184125                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.184203                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.436545                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.436545                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.962581                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.233901                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.233960                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.962581                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.233901                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.233960                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73436.327078                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 88555.360260                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 88547.418048                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92328.279871                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92328.279871                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73436.327078                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89943.933811                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 89938.452590                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73436.327078                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89943.933811                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 89938.452590                       # average overall miss latency
+system.cpu.l2cache.tags.tag_accesses        111215565                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       111215565                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst           31                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data      6289061                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        6289092                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      3782409                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      3782409                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data            3                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total            3                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data      1067117                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total      1067117                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst           31                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      7356178                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         7356209                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst           31                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      7356178                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        7356209                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          743                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data      1419037                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total      1419780                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       826438                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       826438                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          743                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data      2245475                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total       2246218                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          743                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data      2245475                       # number of overall misses
+system.cpu.l2cache.overall_misses::total      2246218                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     55398500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 122091721000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 122147119500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  73834470750                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  73834470750                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     55398500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 195926191750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 195981590250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     55398500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 195926191750                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 195981590250                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          774                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      7708098                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      7708872                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      3782409                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      3782409                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data            3                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total            3                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data      1893555                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total      1893555                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          774                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      9601653                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      9602427                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          774                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      9601653                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      9602427                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.959948                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.184097                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.184175                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.436448                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.436448                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.959948                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.233863                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.233922                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.959948                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.233863                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.233922                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74560.565276                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 86038.433811                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 86032.427207                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89340.604800                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89340.604800                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74560.565276                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87253.784500                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 87249.585859                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74560.565276                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87253.784500                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 87249.585859                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -896,195 +864,195 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks      1100579                       # number of writebacks
-system.cpu.l2cache.writebacks::total          1100579                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            2                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data            7                       # number of ReadReq MSHR hits
+system.cpu.l2cache.writebacks::writebacks      1100304                       # number of writebacks
+system.cpu.l2cache.writebacks::total          1100304                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            1                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data            8                       # number of ReadReq MSHR hits
 system.cpu.l2cache.ReadReq_mshr_hits::total            9                       # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst            2                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data            7                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data            8                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::total            9                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst            2                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data            7                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data            8                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total            9                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          744                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data      1419355                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total      1420099                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       826595                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       826595                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          744                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data      2245950                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total      2246694                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          744                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data      2245950                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total      2246694                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     45263000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 107889512500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 107934775500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  65933341000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  65933341000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     45263000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 173822853500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 173868116500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     45263000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 173822853500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 173868116500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.960000                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.184124                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.184202                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.436545                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.436545                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.960000                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.233900                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.233959                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.960000                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.233900                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.233959                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60837.365591                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 76013.056987                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 76005.106334                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79764.988900                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79764.988900                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60837.365591                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77393.910595                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77388.427841                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60837.365591                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77393.910595                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77388.427841                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          742                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data      1419029                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total      1419771                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       826438                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       826438                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          742                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data      2245467                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total      2246209                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          742                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data      2245467                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total      2246209                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     45997000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 104316352250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 104362349250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  63474835750                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  63474835750                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     45997000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 167791188000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 167837185000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     45997000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 167791188000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 167837185000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.958656                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.184096                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.184174                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.436448                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.436448                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.958656                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.233863                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.233921                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.958656                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.233863                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.233921                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61990.566038                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73512.487941                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 73506.466360                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76805.320847                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76805.320847                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61990.566038                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74724.406103                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 74720.199679                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61990.566038                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74724.406103                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 74720.199679                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements           9598076                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4088.041397                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           656012597                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           9602172                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             68.319188                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        3547188250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4088.041397                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.998057                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.998057                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements           9597556                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4088.017894                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           656035033                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           9601652                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             68.325225                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        3543401250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4088.017894                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.998051                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.998051                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          635                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         2403                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         1057                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          619                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         2366                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         1110                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1355899932                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1355899932                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    489056209                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       489056209                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    166956265                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      166956265                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data           62                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total           62                       # number of LoadLockedReq hits
+system.cpu.dcache.tags.tag_accesses        1355956994                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1355956994                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    489079777                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       489079777                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    166955126                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      166955126                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data           64                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total           64                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data           61                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total           61                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     656012474                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        656012474                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    656012474                       # number of overall hits
-system.cpu.dcache.overall_hits::total       656012474                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data     11506498                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total      11506498                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      5629782                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      5629782                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data     656034903                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        656034903                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    656034903                       # number of overall hits
+system.cpu.dcache.overall_hits::total       656034903                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data     11511719                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total      11511719                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      5630921                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      5630921                       # number of WriteReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            3                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            3                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data     17136280                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total       17136280                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data     17136280                       # number of overall misses
-system.cpu.dcache.overall_misses::total      17136280                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 363307841237                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 363307841237                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 307618244019                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 307618244019                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       233500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total       233500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 670926085256                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 670926085256                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 670926085256                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 670926085256                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    500562707                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    500562707                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data     17142640                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total       17142640                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data     17142640                       # number of overall misses
+system.cpu.dcache.overall_misses::total      17142640                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 356637028987                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 356637028987                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 299385068793                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 299385068793                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       231500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total       231500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 656022097780                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 656022097780                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 656022097780                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 656022097780                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    500591496                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    500591496                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    172586047                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    172586047                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data           65                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total           65                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data           67                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total           67                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data           61                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total           61                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    673148754                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    673148754                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    673148754                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    673148754                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.022987                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.022987                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.032620                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.032620                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.046154                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.046154                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.025457                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.025457                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.025457                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.025457                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31574.145430                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 31574.145430                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54641.235490                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 54641.235490                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 77833.333333                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 77833.333333                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 39152.376435                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 39152.376435                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 39152.376435                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 39152.376435                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs     24574937                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets      3988182                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs           1212192                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets           65130                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    20.273139                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    61.234178                       # average number of cycles each access was blocked
+system.cpu.dcache.demand_accesses::cpu.data    673177543                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    673177543                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    673177543                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    673177543                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.022996                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.022996                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.032627                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.032627                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.044776                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.044776                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.025465                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.025465                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.025465                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.025465                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30980.345245                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 30980.345245                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53168.046363                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 53168.046363                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 77166.666667                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 77166.666667                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 38268.440437                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 38268.440437                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 38268.440437                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 38268.440437                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs     23433940                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets      3966170                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs           1210564                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets           65132                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    19.357870                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    60.894338                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      3782070                       # number of writebacks
-system.cpu.dcache.writebacks::total           3782070                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      3797817                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      3797817                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3736290                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      3736290                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks      3782409                       # number of writebacks
+system.cpu.dcache.writebacks::total           3782409                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      3803620                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      3803620                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3737364                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      3737364                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            3                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total            3                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      7534107                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      7534107                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      7534107                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      7534107                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7708681                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      7708681                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1893492                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      1893492                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      9602173                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      9602173                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      9602173                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      9602173                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 198180916008                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 198180916008                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  89373429339                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  89373429339                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 287554345347                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 287554345347                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 287554345347                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 287554345347                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.015400                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.015400                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.010971                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.010971                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.014265                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.014265                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.014265                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.014265                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25708.797135                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25708.797135                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47200.320540                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47200.320540                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29946.799058                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 29946.799058                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29946.799058                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 29946.799058                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_hits::cpu.data      7540984                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      7540984                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      7540984                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      7540984                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7708099                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      7708099                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1893557                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      1893557                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      9601656                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      9601656                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      9601656                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      9601656                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 194575797258                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 194575797258                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  86895396246                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  86895396246                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 281471193504                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 281471193504                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 281471193504                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 281471193504                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.015398                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.015398                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.010972                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.010972                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.014263                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.014263                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.014263                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.014263                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25243.032978                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25243.032978                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45890.034599                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45890.034599                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29314.859177                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 29314.859177                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29314.859177                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 29314.859177                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 3f6e9d455a1c7e78288e65637fcb2a261f97a48e..17c346b699a9b4c00c329182a5b8e63cd66664bc 100644 (file)
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.041680                       # Number of seconds simulated
-sim_ticks                                 41680207000                       # Number of ticks simulated
-final_tick                                41680207000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.041684                       # Number of seconds simulated
+sim_ticks                                 41683573000                       # Number of ticks simulated
+final_tick                                41683573000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 131207                       # Simulator instruction rate (inst/s)
-host_op_rate                                   131207                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               59505524                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 234284                       # Number of bytes of host memory used
-host_seconds                                   700.44                       # Real time elapsed on the host
+host_inst_rate                                 119929                       # Simulator instruction rate (inst/s)
+host_op_rate                                   119929                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               54395175                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 269084                       # Number of bytes of host memory used
+host_seconds                                   766.31                       # Real time elapsed on the host
 sim_insts                                    91903056                       # Number of instructions simulated
 sim_ops                                      91903056                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total          178816                       # Nu
 system.physmem.num_reads::cpu.inst               2794                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data               2144                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                  4938                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              4290190                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3292114                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 7582304                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         4290190                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            4290190                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             4290190                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             3292114                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                7582304                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst              4289843                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3291848                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 7581692                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         4289843                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            4289843                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             4289843                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             3291848                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                7581692                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                          4938                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                        4938                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     41680133000                       # Total gap between requests
+system.physmem.totGap                     41683192000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -90,10 +90,10 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      3403                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      1090                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       402                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        39                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      3265                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      1157                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       435                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        77                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         4                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
@@ -154,65 +154,60 @@ system.physmem.wrQLenPdf::28                        0                       # Wh
 system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          743                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      421.641992                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     209.527903                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     761.351186                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64-65            254     34.19%     34.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-129           96     12.92%     47.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192-193           62      8.34%     55.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-257           50      6.73%     62.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320-321           29      3.90%     66.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-385           32      4.31%     70.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448-449           22      2.96%     73.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-513           25      3.36%     76.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576-577           15      2.02%     78.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-641           12      1.62%     80.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704-705           14      1.88%     82.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-769           16      2.15%     84.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832-833           32      4.31%     88.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-897           17      2.29%     90.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960-961            5      0.67%     91.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1025            5      0.67%     92.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088-1089            8      1.08%     93.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152-1153            5      0.67%     94.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216-1217            6      0.81%     94.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280-1281            6      0.81%     95.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344-1345            2      0.27%     95.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408-1409            1      0.13%     96.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472-1473            1      0.13%     96.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536-1537            3      0.40%     96.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600-1601            2      0.27%     96.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664-1665            1      0.13%     97.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1792-1793            2      0.27%     97.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856-1857            2      0.27%     97.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1920-1921            1      0.13%     97.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984-1985            1      0.13%     97.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2048-2049            1      0.13%     97.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112-2113            1      0.13%     98.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2240-2241            1      0.13%     98.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2432-2433            1      0.13%     98.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2624-2625            1      0.13%     98.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2880-2881            1      0.13%     98.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2944-2945            1      0.13%     98.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3328-3329            1      0.13%     98.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3520-3521            1      0.13%     99.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4032-4033            1      0.13%     99.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4608-4609            1      0.13%     99.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5568-5569            1      0.13%     99.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7168-7169            1      0.13%     99.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8064-8065            1      0.13%     99.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8128-8129            1      0.13%     99.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8192-8193            1      0.13%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            743                       # Bytes accessed per row activation
-system.physmem.totQLat                       34070750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 126424500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples          284                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      541.521127                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     335.427822                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     417.351632                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             58     20.42%     20.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           54     19.01%     39.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           24      8.45%     47.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           12      4.23%     52.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           10      3.52%     55.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            9      3.17%     58.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            5      1.76%     60.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            5      1.76%     62.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          107     37.68%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total            284                       # Bytes accessed per row activation
+system.physmem.totQLat                       37971250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 131493750                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                     24690000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                    67663750                       # Total ticks spent accessing banks
-system.physmem.avgQLat                        6899.71                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    13702.66                       # Average bank access latency per DRAM burst
+system.physmem.totBankLat                    68832500                       # Total ticks spent accessing banks
+system.physmem.avgQLat                        7689.60                       # Average queueing delay per DRAM burst
+system.physmem.avgBankLat                    13939.35                       # Average bank access latency per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  25602.37                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  26628.95                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           7.58                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        7.58                       # Average system read bandwidth in MiByte/s
@@ -221,16 +216,16 @@ system.physmem.peakBW                        12800.00                       # Th
 system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.06                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         0.00                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       4195                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       4086                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   84.95                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   82.75                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                      8440691.17                       # Average gap between requests
-system.physmem.pageHitRate                      84.95                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               0.90                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                      7582304                       # Throughput (bytes/s)
+system.physmem.avgGap                      8441310.65                       # Average gap between requests
+system.physmem.pageHitRate                      82.75                       # Row buffer hit rate, read and write combined
+system.physmem.prechargeAllPercent               1.04                       # Percentage of time for which DRAM has all the banks in precharge state
+system.membus.throughput                      7581692                       # Throughput (bytes/s)
 system.membus.trans_dist::ReadReq                3216                       # Transaction distribution
 system.membus.trans_dist::ReadResp               3216                       # Transaction distribution
 system.membus.trans_dist::ReadExReq              1722                       # Transaction distribution
@@ -241,9 +236,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
 system.membus.tot_pkt_size::total              316032                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.data_through_bus                 316032                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy             5775000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy             5776500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           45973500                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           45941000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                13412627                       # Number of BP lookups
@@ -259,18 +254,18 @@ system.cpu.dtb.fetch_hits                           0                       # IT
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     19996265                       # DTB read hits
+system.cpu.dtb.read_hits                     19996264                       # DTB read hits
 system.cpu.dtb.read_misses                         10                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                 19996275                       # DTB read accesses
-system.cpu.dtb.write_hits                     6501862                       # DTB write hits
+system.cpu.dtb.read_accesses                 19996274                       # DTB read accesses
+system.cpu.dtb.write_hits                     6501866                       # DTB write hits
 system.cpu.dtb.write_misses                        23                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                 6501885                       # DTB write accesses
-system.cpu.dtb.data_hits                     26498127                       # DTB hits
+system.cpu.dtb.write_accesses                 6501889                       # DTB write accesses
+system.cpu.dtb.data_hits                     26498130                       # DTB hits
 system.cpu.dtb.data_misses                         33                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                 26498160                       # DTB accesses
+system.cpu.dtb.data_accesses                 26498163                       # DTB accesses
 system.cpu.itb.fetch_hits                     9956950                       # ITB hits
 system.cpu.itb.fetch_misses                        49                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
@@ -288,18 +283,18 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                  389                       # Number of system calls
-system.cpu.numCycles                         83360415                       # number of cpu cycles simulated
+system.cpu.numCycles                         83367147                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.branch_predictor.predictedTaken      5905662                       # Number of Branches Predicted As Taken (True).
 system.cpu.branch_predictor.predictedNotTaken      7506965                       # Number of Branches Predicted As Not Taken (False).
-system.cpu.regfile_manager.intRegFileReads     73570552                       # Number of Reads from Int. Register File
+system.cpu.regfile_manager.intRegFileReads     73570553                       # Number of Reads from Int. Register File
 system.cpu.regfile_manager.intRegFileWrites     62575472                       # Number of Writes to Int. Register File
-system.cpu.regfile_manager.intRegFileAccesses    136146024                       # Total Accesses (Read+Write) to the Int. Register File
+system.cpu.regfile_manager.intRegFileAccesses    136146025                       # Total Accesses (Read+Write) to the Int. Register File
 system.cpu.regfile_manager.floatRegFileReads      2206128                       # Number of Reads from FP Register File
 system.cpu.regfile_manager.floatRegFileWrites      5851888                       # Number of Writes to FP Register File
 system.cpu.regfile_manager.floatRegFileAccesses      8058016                       # Total Accesses (Read+Write) to the FP Register File
-system.cpu.regfile_manager.regForwards       38521866                       # Number of Registers Read Through Forwarding Logic
+system.cpu.regfile_manager.regForwards       38521865                       # Number of Registers Read Through Forwarding Logic
 system.cpu.agen_unit.agens                   26722393                       # Number of Address Generations
 system.cpu.execution_unit.predictedTakenIncorrect      3469296                       # Number of Branches Incorrectly Predicted As Taken.
 system.cpu.execution_unit.predictedNotTakenIncorrect       799060                       # Number of Branches Incorrectly Predicted As Not Taken).
@@ -310,12 +305,12 @@ system.cpu.execution_unit.executions         57404027                       # Nu
 system.cpu.mult_div_unit.multiplies            458253                       # Number of Multipy Operations Executed
 system.cpu.mult_div_unit.divides                    0                       # Number of Divide Operations Executed
 system.cpu.contextSwitches                          1                       # Number of context switches
-system.cpu.threadCycles                      82971123                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles                      82970332                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
 system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled                           10519                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         7752655                       # Number of cycles cpu's stages were not processed
-system.cpu.runCycles                         75607760                       # Number of cycles cpu stages are processed.
-system.cpu.activity                         90.699836                       # Percentage of cycles cpu is active
+system.cpu.timesIdled                           10410                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         7759392                       # Number of cycles cpu's stages were not processed
+system.cpu.runCycles                         75607755                       # Number of cycles cpu stages are processed.
+system.cpu.activity                         90.692506                       # Percentage of cycles cpu is active
 system.cpu.comLoads                          19996198                       # Number of Load instructions committed
 system.cpu.comStores                          6501103                       # Number of Store instructions committed
 system.cpu.comBranches                       10240685                       # Number of Branches instructions committed
@@ -327,36 +322,36 @@ system.cpu.committedInsts                    91903056                       # Nu
 system.cpu.committedOps                      91903056                       # Number of Ops committed (Per-Thread)
 system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
 system.cpu.committedInsts_total              91903056                       # Number of Instructions committed (Total)
-system.cpu.cpi                               0.907047                       # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi                               0.907121                       # CPI: Cycles Per Instruction (Per-Thread)
 system.cpu.smt_cpi                                nan                       # CPI: Total SMT-CPI
-system.cpu.cpi_total                         0.907047                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.102478                       # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.cpi_total                         0.907121                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.102389                       # IPC: Instructions Per Cycle (Per-Thread)
 system.cpu.smt_ipc                                nan                       # IPC: Total SMT-IPC
-system.cpu.ipc_total                         1.102478                       # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles                 27680069                       # Number of cycles 0 instructions are processed.
-system.cpu.stage0.runCycles                  55680346                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization               66.794708                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles                 34108732                       # Number of cycles 0 instructions are processed.
-system.cpu.stage1.runCycles                  49251683                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization               59.082819                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles                 33509067                       # Number of cycles 0 instructions are processed.
-system.cpu.stage2.runCycles                  49851348                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization               59.802183                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage3.idleCycles                 65333914                       # Number of cycles 0 instructions are processed.
-system.cpu.stage3.runCycles                  18026501                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage3.utilization               21.624774                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles                 29500658                       # Number of cycles 0 instructions are processed.
-system.cpu.stage4.runCycles                  53859757                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization               64.610711                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.ipc_total                         1.102389                       # IPC: Total IPC of All Threads
+system.cpu.stage0.idleCycles                 27686803                       # Number of cycles 0 instructions are processed.
+system.cpu.stage0.runCycles                  55680344                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage0.utilization               66.789312                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles                 34115467                       # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles                  49251680                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization               59.078044                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles                 33515800                       # Number of cycles 0 instructions are processed.
+system.cpu.stage2.runCycles                  49851347                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage2.utilization               59.797353                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles                 65340657                       # Number of cycles 0 instructions are processed.
+system.cpu.stage3.runCycles                  18026490                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage3.utilization               21.623014                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles                 29507392                       # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles                  53859755                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization               64.605491                       # Percentage of cycles stage was utilized (processing insts).
 system.cpu.icache.tags.replacements              7635                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1492.182806                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse          1492.188372                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs             9945551                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs              9520                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs           1044.700735                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1492.182806                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.728605                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.728605                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1492.188372                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.728608                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.728608                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1885                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          122                       # Occupied blocks per task id
@@ -378,12 +373,12 @@ system.cpu.icache.demand_misses::cpu.inst        11399                       # n
 system.cpu.icache.demand_misses::total          11399                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst        11399                       # number of overall misses
 system.cpu.icache.overall_misses::total         11399                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    325866750                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    325866750                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    325866750                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    325866750                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    325866750                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    325866750                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    329283500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    329283500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    329283500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    329283500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    329283500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    329283500                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst      9956950                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total      9956950                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst      9956950                       # number of demand (read+write) accesses
@@ -396,12 +391,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.001145
 system.cpu.icache.demand_miss_rate::total     0.001145                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.001145                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.001145                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28587.310290                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 28587.310290                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 28587.310290                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 28587.310290                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 28587.310290                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 28587.310290                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28887.051496                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 28887.051496                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 28887.051496                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 28887.051496                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 28887.051496                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 28887.051496                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            7                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 1                       # number of cycles access was blocked
@@ -422,26 +417,26 @@ system.cpu.icache.demand_mshr_misses::cpu.inst         9520
 system.cpu.icache.demand_mshr_misses::total         9520                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst         9520                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total         9520                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    266339500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    266339500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    266339500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    266339500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    266339500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    266339500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    268822750                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    268822750                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    268822750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    268822750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    268822750                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    268822750                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000956                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000956                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000956                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000956                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000956                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000956                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27976.838235                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27976.838235                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27976.838235                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 27976.838235                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27976.838235                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 27976.838235                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28237.683824                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28237.683824                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28237.683824                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 28237.683824                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28237.683824                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 28237.683824                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput                18195687                       # Throughput (bytes/s)
+system.cpu.toL2Bus.throughput                18194218                       # Throughput (bytes/s)
 system.cpu.toL2Bus.trans_dist::ReadReq           9995                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp          9995                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::Writeback          107                       # Transaction distribution
@@ -457,19 +452,19 @@ system.cpu.toL2Bus.data_through_bus            758400                       # To
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
 system.cpu.toL2Bus.reqLayer0.occupancy        6032000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      14812000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      14800250                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy       3559500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy       3515750                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         2189.577948                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse         2189.597840                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs               6793                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs             3282                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             2.069775                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks    17.842967                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  1820.748644                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   350.986337                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks    17.844631                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  1820.766792                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   350.986416                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.000545                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.055565                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.010711                       # Average percentage of cache occupancy
@@ -507,17 +502,17 @@ system.cpu.l2cache.demand_misses::total          4938                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst         2794                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data         2144                       # number of overall misses
 system.cpu.l2cache.overall_misses::total         4938                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    189282000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     32395250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    221677250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    122425750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    122425750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    189282000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    154821000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    344103000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    189282000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    154821000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    344103000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    191765250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     32319750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    224085000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    125611500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    125611500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    191765250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    157931250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    349696500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    191765250                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    157931250                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    349696500                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst         9520                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data          475                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total         9995                       # number of ReadReq accesses(hits+misses)
@@ -542,17 +537,17 @@ system.cpu.l2cache.demand_miss_rate::total     0.420506                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.293487                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.964462                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.420506                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67745.884037                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76765.995261                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 68929.493159                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71095.092915                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71095.092915                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67745.884037                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72211.287313                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 69684.690158                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67745.884037                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72211.287313                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 69684.690158                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68634.663565                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76587.085308                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 69678.171642                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72945.121951                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72945.121951                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68634.663565                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73661.963619                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 70817.436209                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68634.663565                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73661.963619                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 70817.436209                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -572,17 +567,17 @@ system.cpu.l2cache.demand_mshr_misses::total         4938
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         2794                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data         2144                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total         4938                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    154136500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     27132250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    181268750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    101289750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    101289750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    154136500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    128422000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    282558500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    154136500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    128422000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    282558500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    156642750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     27057250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    183700000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    104540000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    104540000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    156642750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    131597250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    288240000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    156642750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    131597250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    288240000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.293487                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.888421                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.321761                       # mshr miss rate for ReadReq accesses
@@ -594,31 +589,31 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.420506
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.293487                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.964462                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.420506                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55166.964925                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64294.431280                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56364.661070                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58820.993031                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58820.993031                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55166.964925                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59898.320896                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57221.243418                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55166.964925                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59898.320896                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57221.243418                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56063.976378                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64116.706161                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57120.646766                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60708.478513                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60708.478513                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56063.976378                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61379.314366                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58371.810450                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56063.976378                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61379.314366                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58371.810450                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.dcache.tags.replacements               157                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          1441.367780                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            26488450                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          1441.382253                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            26488456                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs              2223                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          11915.632029                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          11915.634728                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  1441.367780                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.351896                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.351896                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data  1441.382253                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.351900                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.351900                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         2066                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           22                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           58                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          211                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           57                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          212                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3          403                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4         1372                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.504395                       # Percentage of cache occupancy per task id
@@ -626,28 +621,28 @@ system.cpu.dcache.tags.tag_accesses          52996825                       # Nu
 system.cpu.dcache.tags.data_accesses         52996825                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data     19995621                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        19995621                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      6492829                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        6492829                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      26488450                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         26488450                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     26488450                       # number of overall hits
-system.cpu.dcache.overall_hits::total        26488450                       # number of overall hits
+system.cpu.dcache.WriteReq_hits::cpu.data      6492835                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        6492835                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      26488456                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         26488456                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     26488456                       # number of overall hits
+system.cpu.dcache.overall_hits::total        26488456                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data          577                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total           577                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data         8274                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         8274                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data         8851                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           8851                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         8851                       # number of overall misses
-system.cpu.dcache.overall_misses::total          8851                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     41023250                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     41023250                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    492650500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    492650500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    533673750                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    533673750                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    533673750                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    533673750                       # number of overall miss cycles
+system.cpu.dcache.WriteReq_misses::cpu.data         8268                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         8268                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data         8845                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           8845                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         8845                       # number of overall misses
+system.cpu.dcache.overall_misses::total          8845                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     40979500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     40979500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    507652000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    507652000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    548631500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    548631500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    548631500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    548631500                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data     19996198                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total     19996198                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data      6501103                       # number of WriteReq accesses(hits+misses)
@@ -658,25 +653,25 @@ system.cpu.dcache.overall_accesses::cpu.data     26497301
 system.cpu.dcache.overall_accesses::total     26497301                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000029                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.000029                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001273                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.001273                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001272                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.001272                       # miss rate for WriteReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.000334                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     0.000334                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.000334                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.000334                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71097.487002                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 71097.487002                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59541.999033                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 59541.999033                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 60295.305615                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 60295.305615                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 60295.305615                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 60295.305615                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs        23884                       # number of cycles access was blocked
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71021.663778                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 71021.663778                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61399.612966                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 61399.612966                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 62027.303561                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 62027.303561                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 62027.303561                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 62027.303561                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs        25755                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs               841                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs               844                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    28.399524                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    30.515403                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
@@ -684,12 +679,12 @@ system.cpu.dcache.writebacks::writebacks          107                       # nu
 system.cpu.dcache.writebacks::total               107                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data          102                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total          102                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data         6526                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total         6526                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data         6628                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total         6628                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data         6628                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total         6628                       # number of overall MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data         6520                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total         6520                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data         6622                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total         6622                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data         6622                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total         6622                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data          475                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total          475                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1748                       # number of WriteReq MSHR misses
@@ -698,14 +693,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data         2223
 system.cpu.dcache.demand_mshr_misses::total         2223                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data         2223                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total         2223                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     33418750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     33418750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    124443250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    124443250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    157862000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    157862000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    157862000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    157862000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     33343250                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     33343250                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    127629000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    127629000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    160972250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    160972250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    160972250                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    160972250                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000024                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000024                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000269                       # mshr miss rate for WriteReq accesses
@@ -714,14 +709,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000084
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000084                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000084                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000084                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70355.263158                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70355.263158                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71191.790618                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71191.790618                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71013.045434                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 71013.045434                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71013.045434                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 71013.045434                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70196.315789                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70196.315789                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73014.302059                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73014.302059                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72412.168241                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 72412.168241                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72412.168241                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 72412.168241                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index b0acaf58e56608a8c2e8caf61e0453f597d7398b..c3a9e9ab97e6e0ffc468a018c21c90d5b9bd1692 100644 (file)
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.023462                       # Number of seconds simulated
-sim_ticks                                 23461709500                       # Number of ticks simulated
-final_tick                                23461709500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.023455                       # Number of seconds simulated
+sim_ticks                                 23455364500                       # Number of ticks simulated
+final_tick                                23455364500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 186682                       # Simulator instruction rate (inst/s)
-host_op_rate                                   186682                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               52030153                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 235304                       # Number of bytes of host memory used
-host_seconds                                   450.93                       # Real time elapsed on the host
+host_inst_rate                                 164985                       # Simulator instruction rate (inst/s)
+host_op_rate                                   164985                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               45970553                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 272156                       # Number of bytes of host memory used
+host_seconds                                   510.23                       # Real time elapsed on the host
 sim_insts                                    84179709                       # Number of instructions simulated
 sim_ops                                      84179709                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total          195968                       # Nu
 system.physmem.num_reads::cpu.inst               3062                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data               2166                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                  5228                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              8352674                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              5908521                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                14261194                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         8352674                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            8352674                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             8352674                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             5908521                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               14261194                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst              8354933                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              5910119                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                14265052                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         8354933                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            8354933                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             8354933                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             5910119                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               14265052                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                          5228                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                        5228                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -41,20 +41,20 @@ system.physmem.bytesWrittenSys                      0                       # To
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                 466                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                 469                       # Per bank write bursts
 system.physmem.perBankRdBursts::1                 290                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                 300                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                 524                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                 301                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                 519                       # Per bank write bursts
 system.physmem.perBankRdBursts::4                 220                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                 226                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                 219                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                 227                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                 220                       # Per bank write bursts
 system.physmem.perBankRdBursts::7                 288                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                 240                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                 279                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                 236                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                 278                       # Per bank write bursts
 system.physmem.perBankRdBursts::10                248                       # Per bank write bursts
-system.physmem.perBankRdBursts::11                254                       # Per bank write bursts
-system.physmem.perBankRdBursts::12                400                       # Per bank write bursts
-system.physmem.perBankRdBursts::13                336                       # Per bank write bursts
+system.physmem.perBankRdBursts::11                255                       # Per bank write bursts
+system.physmem.perBankRdBursts::12                401                       # Per bank write bursts
+system.physmem.perBankRdBursts::13                338                       # Per bank write bursts
 system.physmem.perBankRdBursts::14                491                       # Per bank write bursts
 system.physmem.perBankRdBursts::15                447                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     23461582500                       # Total gap between requests
+system.physmem.totGap                     23455237500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -90,11 +90,11 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      3259                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      1363                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       513                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        84                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         8                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      3268                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      1321                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       517                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       112                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         9                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -154,84 +154,78 @@ system.physmem.wrQLenPdf::28                        0                       # Wh
 system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          750                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      442.026667                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     206.409345                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     807.667918                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64-65            266     35.47%     35.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-129          111     14.80%     50.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192-193           59      7.87%     58.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-257           40      5.33%     63.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320-321           26      3.47%     66.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-385           30      4.00%     70.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448-449           24      3.20%     74.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-513           16      2.13%     76.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576-577            9      1.20%     77.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-641           13      1.73%     79.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704-705           15      2.00%     81.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-769           13      1.73%     82.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832-833           37      4.93%     87.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-897           11      1.47%     89.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960-961            6      0.80%     90.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1025            3      0.40%     90.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088-1089            7      0.93%     91.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152-1153            7      0.93%     92.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216-1217            3      0.40%     92.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280-1281            3      0.40%     93.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344-1345            8      1.07%     94.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408-1409            1      0.13%     94.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472-1473            3      0.40%     94.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536-1537            2      0.27%     95.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600-1601            4      0.53%     95.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664-1665            2      0.27%     95.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1728-1729            1      0.13%     96.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1792-1793            1      0.13%     96.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856-1857            3      0.40%     96.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984-1985            3      0.40%     96.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2048-2049            1      0.13%     97.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112-2113            3      0.40%     97.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2176-2177            1      0.13%     97.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2240-2241            1      0.13%     97.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2304-2305            3      0.40%     98.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2752-2753            1      0.13%     98.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2944-2945            1      0.13%     98.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3072-3073            2      0.27%     98.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3520-3521            1      0.13%     98.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3584-3585            1      0.13%     98.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3904-3905            1      0.13%     99.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4288-4289            1      0.13%     99.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4480-4481            1      0.13%     99.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5056-5057            1      0.13%     99.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8000-8001            1      0.13%     99.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8128-8129            2      0.27%     99.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8192-8193            1      0.13%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            750                       # Bytes accessed per row activation
-system.physmem.totQLat                       37518750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 134402500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples          339                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      526.348083                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     311.933424                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     425.197716                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             81     23.89%     23.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           64     18.88%     42.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           21      6.19%     48.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           17      5.01%     53.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            9      2.65%     56.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            8      2.36%     59.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            7      2.06%     61.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            3      0.88%     61.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          129     38.05%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total            339                       # Bytes accessed per row activation
+system.physmem.totQLat                       42838250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 141220750                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                     26140000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                    70743750                       # Total ticks spent accessing banks
-system.physmem.avgQLat                        7176.50                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    13531.70                       # Average bank access latency per DRAM burst
+system.physmem.totBankLat                    72242500                       # Total ticks spent accessing banks
+system.physmem.avgQLat                        8194.00                       # Average queueing delay per DRAM burst
+system.physmem.avgBankLat                    13818.38                       # Average bank access latency per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  25708.21                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          14.26                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  27012.39                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          14.27                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       14.26                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       14.27                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.11                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.11                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         0.01                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       4478                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       4346                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   85.65                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   83.13                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                      4487678.37                       # Average gap between requests
-system.physmem.pageHitRate                      85.65                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               1.19                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                     14261194                       # Throughput (bytes/s)
+system.physmem.avgGap                      4486464.71                       # Average gap between requests
+system.physmem.pageHitRate                      83.13                       # Row buffer hit rate, read and write combined
+system.physmem.prechargeAllPercent               1.10                       # Percentage of time for which DRAM has all the banks in precharge state
+system.membus.throughput                     14265052                       # Throughput (bytes/s)
 system.membus.trans_dist::ReadReq                3523                       # Transaction distribution
 system.membus.trans_dist::ReadResp               3523                       # Transaction distribution
 system.membus.trans_dist::ReadExReq              1705                       # Transaction distribution
@@ -242,40 +236,40 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
 system.membus.tot_pkt_size::total              334592                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.data_through_bus                 334592                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy             6831000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy             6760500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           49012250                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           48963750                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                14847721                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          10774921                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            922205                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              8301784                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 6957680                       # Number of BTB hits
+system.cpu.branchPred.lookups                14848335                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          10770516                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            922016                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              8296689                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 6955595                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             83.809456                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1467978                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect               3097                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             83.835793                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1468520                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect               3112                       # Number of incorrect RAS predictions.
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     23117785                       # DTB read hits
-system.cpu.dtb.read_misses                     192281                       # DTB read misses
+system.cpu.dtb.read_hits                     23116922                       # DTB read hits
+system.cpu.dtb.read_misses                     193562                       # DTB read misses
 system.cpu.dtb.read_acv                             4                       # DTB read access violations
-system.cpu.dtb.read_accesses                 23310066                       # DTB read accesses
-system.cpu.dtb.write_hits                     7068175                       # DTB write hits
-system.cpu.dtb.write_misses                      1137                       # DTB write misses
-system.cpu.dtb.write_acv                            4                       # DTB write access violations
-system.cpu.dtb.write_accesses                 7069312                       # DTB write accesses
-system.cpu.dtb.data_hits                     30185960                       # DTB hits
-system.cpu.dtb.data_misses                     193418                       # DTB misses
-system.cpu.dtb.data_acv                             8                       # DTB access violations
-system.cpu.dtb.data_accesses                 30379378                       # DTB accesses
-system.cpu.itb.fetch_hits                    14734161                       # ITB hits
-system.cpu.itb.fetch_misses                       103                       # ITB misses
+system.cpu.dtb.read_accesses                 23310484                       # DTB read accesses
+system.cpu.dtb.write_hits                     7068693                       # DTB write hits
+system.cpu.dtb.write_misses                      1118                       # DTB write misses
+system.cpu.dtb.write_acv                            2                       # DTB write access violations
+system.cpu.dtb.write_accesses                 7069811                       # DTB write accesses
+system.cpu.dtb.data_hits                     30185615                       # DTB hits
+system.cpu.dtb.data_misses                     194680                       # DTB misses
+system.cpu.dtb.data_acv                             6                       # DTB access violations
+system.cpu.dtb.data_accesses                 30380295                       # DTB accesses
+system.cpu.itb.fetch_hits                    14732180                       # ITB hits
+system.cpu.itb.fetch_misses                       100                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                14734264                       # ITB accesses
+system.cpu.itb.fetch_accesses                14732280                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -289,139 +283,139 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                  389                       # Number of system calls
-system.cpu.numCycles                         46923420                       # number of cpu cycles simulated
+system.cpu.numCycles                         46910730                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           15463381                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      126961894                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    14847721                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches            8425658                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      22130056                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 4473003                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles                5559398                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                   52                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          2205                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles           25                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  14734161                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                324644                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples           46671603                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.720324                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.376096                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           15458006                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      126949517                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    14848335                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            8424115                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      22129467                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 4471319                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles                5547804                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                  111                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles          2176                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles            8                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  14732180                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                325492                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples           46652781                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.721156                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.376288                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 24541547     52.58%     52.58% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  2361252      5.06%     57.64% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  1192515      2.56%     60.20% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  1742111      3.73%     63.93% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  2755701      5.90%     69.84% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  1149393      2.46%     72.30% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  1220691      2.62%     74.91% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                   771780      1.65%     76.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 10936613     23.43%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 24523314     52.57%     52.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  2362460      5.06%     57.63% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  1191709      2.55%     60.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  1744531      3.74%     63.92% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  2756035      5.91%     69.83% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  1149513      2.46%     72.29% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  1216156      2.61%     74.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                   771099      1.65%     76.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 10937964     23.45%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total             46671603                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.316425                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.705725                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 17289395                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles               4257221                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  20524693                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               1095542                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                3504752                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              2511898                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 12167                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              123979126                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                 31595                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                3504752                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 18431780                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                  963421                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           7928                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  20455398                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               3308324                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              121154570                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                    87                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 400162                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               2430153                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands            88974225                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             157440425                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        150394655                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups           7045769                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total             46652781                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.316523                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.706194                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 17279755                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles               4249359                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  20525557                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               1094653                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                3503457                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              2516236                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 12079                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              123971467                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                 32460                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                3503457                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 18421615                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                  960025                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           8092                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  20456033                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               3303559                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              121144333                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                    76                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 398869                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               2427038                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands            88958437                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             157404324                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        150359413                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups           7044910                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps              68427361                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 20546864                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                749                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            744                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                   8783261                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             25363133                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores             8241349                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           2569635                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores           893782                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  105438334                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                 961                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                  96565072                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            178504                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        20784578                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     15622466                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            572                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples      46671603                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.069033                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.876517                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                 20531076                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                753                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            746                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                   8762869                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             25364686                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores             8245053                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           2579677                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores           916866                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  105436349                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                1901                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                  96572685                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            177506                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        20788885                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     15603704                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           1512                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples      46652781                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.070031                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.877189                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            12133902     26.00%     26.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1             9340972     20.01%     46.01% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             8404137     18.01%     64.02% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             6285068     13.47%     77.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             4921137     10.54%     88.03% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             2853571      6.11%     94.14% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             1727806      3.70%     97.85% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              798697      1.71%     99.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              206313      0.44%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            12130850     26.00%     26.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1             9330795     20.00%     46.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             8389374     17.98%     63.99% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             6281972     13.47%     77.45% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             4924466     10.56%     88.01% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             2864469      6.14%     94.15% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             1724344      3.70%     97.84% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              801135      1.72%     99.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              205376      0.44%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total        46671603                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        46652781                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  187905     11.99%     11.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  187827     11.99%     11.99% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                      0      0.00%     11.99% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%     11.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                   198      0.01%     12.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     12.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                  7114      0.45%     12.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                 5683      0.36%     12.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                843073     53.81%     66.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     66.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     66.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     66.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     66.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     66.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     66.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     66.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     66.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     66.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     66.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     66.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     66.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     66.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     66.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     66.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     66.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     66.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     66.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     66.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     66.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     66.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                 444038     28.34%     94.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                 78699      5.02%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                   195      0.01%     12.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     12.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                  7087      0.45%     12.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                 5615      0.36%     12.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                842803     53.78%     66.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     66.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     66.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     66.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     66.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     66.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     66.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     66.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     66.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     66.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     66.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     66.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     66.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     66.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     66.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     66.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     66.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     66.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     66.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     66.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     66.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     66.59% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 445934     28.46%     95.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                 77665      4.96%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 7      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              58732393     60.82%     60.82% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               479878      0.50%     61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              58739096     60.82%     60.82% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               479860      0.50%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd             2798409      2.90%     64.22% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp              115272      0.12%     64.34% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt             2387143      2.47%     66.81% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult             310920      0.32%     67.13% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv              760028      0.79%     67.92% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd             2798014      2.90%     64.22% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp              115391      0.12%     64.34% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt             2386555      2.47%     66.81% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult             310970      0.32%     67.13% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv              759904      0.79%     67.92% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatSqrt                319      0.00%     67.92% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.92% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.92% # Type of FU issued
@@ -443,84 +437,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.92% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.92% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.92% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.92% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             23829441     24.68%     92.59% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             7151262      7.41%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             23830824     24.68%     92.59% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             7151745      7.41%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total               96565072                       # Type of FU issued
-system.cpu.iq.rate                           2.057929                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     1566710                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.016224                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          226434513                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         117518300                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     87069210                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads            15112448                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes            8740080                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses      7062492                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses               90145382                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                 7986393                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          1518186                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total               96572685                       # Type of FU issued
+system.cpu.iq.rate                           2.058648                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     1567126                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.016227                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          226432918                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         117523015                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     87074868                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads            15109865                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes            8738386                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses      7061397                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses               90154911                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 7984893                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1517468                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      5366935                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        18425                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        34629                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      1740246                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      5368488                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        18513                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        34393                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      1743950                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        10551                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          2023                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        10556                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          2089                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                3504752                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                  133474                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                 18356                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           115674265                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            366324                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              25363133                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts              8241349                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                961                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                   2994                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles                3503457                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                  134155                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                 17977                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           115673905                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            371989                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              25364686                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts              8245053                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               1901                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                   2671                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewLSQFullEvents                    35                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          34629                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         535207                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       494157                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1029364                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts              95337689                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              23310553                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           1227383                       # Number of squashed instructions skipped in execute
+system.cpu.iew.memOrderViolationEvents          34393                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         533358                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       495038                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              1028396                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts              95341973                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              23310954                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1230712                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                      10234970                       # number of nop insts executed
-system.cpu.iew.exec_refs                     30380075                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 12022158                       # Number of branches executed
-system.cpu.iew.exec_stores                    7069522                       # Number of stores executed
-system.cpu.iew.exec_rate                     2.031772                       # Inst execution rate
-system.cpu.iew.wb_sent                       94652012                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      94131702                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  64474346                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  89850691                       # num instructions consuming a value
+system.cpu.iew.exec_nop                      10235655                       # number of nop insts executed
+system.cpu.iew.exec_refs                     30380968                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 12023807                       # Number of branches executed
+system.cpu.iew.exec_stores                    7070014                       # Number of stores executed
+system.cpu.iew.exec_rate                     2.032413                       # Inst execution rate
+system.cpu.iew.wb_sent                       94656410                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      94136265                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  64475750                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  89852391                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       2.006071                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.717572                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       2.006711                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.717574                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts        23772316                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts        23771863                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             389                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            910471                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples     43166851                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.129019                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.746086                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts            910264                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples     43149324                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.129884                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.746526                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     16723468     38.74%     38.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1      9908468     22.95%     61.70% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      4486822     10.39%     72.09% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      2263317      5.24%     77.33% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1605459      3.72%     81.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1122723      2.60%     83.65% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       719573      1.67%     85.32% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       818065      1.90%     87.21% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      5518956     12.79%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     16704227     38.71%     38.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1      9920088     22.99%     61.70% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      4481212     10.39%     72.09% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      2253745      5.22%     77.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1606057      3.72%     81.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1123881      2.60%     83.64% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       722151      1.67%     85.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       820935      1.90%     87.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      5517028     12.79%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total     43166851                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total     43149324                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts             91903055                       # Number of instructions committed
 system.cpu.commit.committedOps               91903055                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -531,173 +525,173 @@ system.cpu.commit.branches                   10240685                       # Nu
 system.cpu.commit.fp_insts                    6862061                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                  79581076                       # Number of committed integer instructions.
 system.cpu.commit.function_calls              1029620                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events               5518956                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events               5517028                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    153322226                       # The number of ROB reads
-system.cpu.rob.rob_writes                   234879469                       # The number of ROB writes
-system.cpu.timesIdled                            5401                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          251817                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                    153306174                       # The number of ROB reads
+system.cpu.rob.rob_writes                   234877097                       # The number of ROB writes
+system.cpu.timesIdled                            5272                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          257949                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                    84179709                       # Number of Instructions Simulated
 system.cpu.committedOps                      84179709                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total              84179709                       # Number of Instructions Simulated
-system.cpu.cpi                               0.557420                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.557420                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.793981                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.793981                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                129048096                       # number of integer regfile reads
-system.cpu.int_regfile_writes                70519803                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                   6188545                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                  6044303                       # number of floating regfile writes
-system.cpu.misc_regfile_reads                  714547                       # number of misc regfile reads
+system.cpu.cpi                               0.557269                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.557269                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.794466                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.794466                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                129050731                       # number of integer regfile reads
+system.cpu.int_regfile_writes                70522819                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                   6187407                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                  6043154                       # number of floating regfile writes
+system.cpu.misc_regfile_reads                  714454                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput                37824354                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq          12026                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp         12026                       # Transaction distribution
+system.cpu.toL2Bus.throughput                37351626                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq          11849                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp         11849                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::Writeback          109                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq         1731                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp         1731                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        23020                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        22666                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         4603                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             27623                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       736640                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             27269                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       725312                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       150784                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total         887424                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus            887424                       # Total data (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total         876096                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus            876096                       # Total data (bytes)
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy        7042000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.occupancy        6953500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      17847250                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      17562000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy       3547000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy       3539750                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.icache.tags.replacements              9576                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1596.482984                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            14719872                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             11510                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           1278.876803                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements              9398                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1599.250917                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            14718111                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             11333                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           1298.695050                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1596.482984                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.779533                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.779533                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1934                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           54                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          184                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          766                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst  1599.250917                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.780884                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.780884                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1935                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           58                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          181                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          761                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3            6                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          924                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.944336                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          29479830                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         29479830                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     14719872                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        14719872                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      14719872                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         14719872                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     14719872                       # number of overall hits
-system.cpu.icache.overall_hits::total        14719872                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        14288                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         14288                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        14288                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          14288                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        14288                       # number of overall misses
-system.cpu.icache.overall_misses::total         14288                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    413271500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    413271500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    413271500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    413271500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    413271500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    413271500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     14734160                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     14734160                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     14734160                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     14734160                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     14734160                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     14734160                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000970                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000970                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000970                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000970                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000970                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000970                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28924.377100                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 28924.377100                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 28924.377100                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 28924.377100                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 28924.377100                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 28924.377100                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          548                       # number of cycles access was blocked
+system.cpu.icache.tags.age_task_id_blocks_1024::4          929                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.944824                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          29475691                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         29475691                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     14718111                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        14718111                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      14718111                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         14718111                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     14718111                       # number of overall hits
+system.cpu.icache.overall_hits::total        14718111                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        14068                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         14068                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        14068                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          14068                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        14068                       # number of overall misses
+system.cpu.icache.overall_misses::total         14068                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    413989500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    413989500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    413989500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    413989500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    413989500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    413989500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     14732179                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     14732179                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     14732179                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     14732179                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     14732179                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     14732179                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000955                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000955                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000955                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000955                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000955                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000955                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29427.743816                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 29427.743816                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 29427.743816                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 29427.743816                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 29427.743816                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 29427.743816                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          165                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 8                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 4                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    68.500000                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    41.250000                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2778                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         2778                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         2778                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         2778                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         2778                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         2778                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        11510                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        11510                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        11510                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        11510                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        11510                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        11510                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    303668250                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    303668250                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    303668250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    303668250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    303668250                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    303668250                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000781                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000781                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000781                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000781                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000781                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000781                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26382.993050                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26382.993050                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26382.993050                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 26382.993050                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26382.993050                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 26382.993050                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2735                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         2735                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         2735                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         2735                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         2735                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         2735                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        11333                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        11333                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        11333                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        11333                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        11333                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        11333                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    305304500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    305304500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    305304500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    305304500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    305304500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    305304500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000769                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000769                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000769                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000769                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000769                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000769                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26939.424689                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26939.424689                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26939.424689                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 26939.424689                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26939.424689                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 26939.424689                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         2409.583505                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs               8517                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         2413.657208                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs               8341                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs             3590                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             2.372423                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             2.323398                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks    17.678720                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2010.447963                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   381.456822                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.000540                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.061354                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.011641                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.073535                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks    17.675331                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2012.279201                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   383.702676                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.000539                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.061410                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.011710                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.073659                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024         3590                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           70                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          178                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          910                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2431                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           72                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          177                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          904                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2435                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.109558                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses           116249                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses          116249                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst         8448                       # number of ReadReq hits
+system.cpu.l2cache.tags.tag_accesses           114833                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses          114833                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst         8271                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data           55                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total           8503                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total           8326                       # number of ReadReq hits
 system.cpu.l2cache.Writeback_hits::writebacks          109                       # number of Writeback hits
 system.cpu.l2cache.Writeback_hits::total          109                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data           26                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total           26                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         8448                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst         8271                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.data           81                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total            8529                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         8448                       # number of overall hits
+system.cpu.l2cache.demand_hits::total            8352                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         8271                       # number of overall hits
 system.cpu.l2cache.overall_hits::cpu.data           81                       # number of overall hits
-system.cpu.l2cache.overall_hits::total           8529                       # number of overall hits
+system.cpu.l2cache.overall_hits::total           8352                       # number of overall hits
 system.cpu.l2cache.ReadReq_misses::cpu.inst         3062                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.data          461                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::total         3523                       # number of ReadReq misses
@@ -709,52 +703,52 @@ system.cpu.l2cache.demand_misses::total          5228                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst         3062                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data         2166                       # number of overall misses
 system.cpu.l2cache.overall_misses::total         5228                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    207668250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     34560750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    242229000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    124310250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    124310250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    207668250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    158871000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    366539250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    207668250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    158871000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    366539250                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst        11510                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    211253500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     36622500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    247876000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    125606750                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    125606750                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    211253500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    162229250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    373482750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    211253500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    162229250                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    373482750                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst        11333                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data          516                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total        12026                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total        11849                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::writebacks          109                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::total          109                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data         1731                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total         1731                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        11510                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst        11333                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data         2247                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total        13757                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        11510                       # number of overall (read+write) accesses
+system.cpu.l2cache.demand_accesses::total        13580                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        11333                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data         2247                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total        13757                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.266030                       # miss rate for ReadReq accesses
+system.cpu.l2cache.overall_accesses::total        13580                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.270184                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.893411                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.292949                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.297325                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.984980                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total     0.984980                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.266030                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.270184                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.963952                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.380025                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.266030                       # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::total     0.384978                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.270184                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.963952                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.380025                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67821.113651                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74969.088937                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 68756.457565                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72909.237537                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72909.237537                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67821.113651                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73347.645429                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 70110.797628                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67821.113651                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73347.645429                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 70110.797628                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total     0.384978                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68991.998694                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79441.431670                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 70359.352824                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73669.648094                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73669.648094                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68991.998694                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74898.084026                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 71438.934583                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68991.998694                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74898.084026                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 71438.934583                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -774,135 +768,136 @@ system.cpu.l2cache.demand_mshr_misses::total         5228
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         3062                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data         2166                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total         5228                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    168834750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     28858250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    197693000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    103390750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    103390750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    168834750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    132249000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    301083750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    168834750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    132249000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    301083750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.266030                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    172480500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     30915000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    203395500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    104707750                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    104707750                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    172480500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    135622750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    308103250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    172480500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    135622750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    308103250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.270184                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.893411                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.292949                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.297325                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.984980                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.984980                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.266030                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.270184                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.963952                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.380025                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.266030                       # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.384978                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.270184                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.963952                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.380025                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55138.716525                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62599.240781                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56114.958842                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60639.736070                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60639.736070                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55138.716525                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61056.786704                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57590.617827                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55138.716525                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61056.786704                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57590.617827                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.384978                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56329.359895                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67060.737527                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57733.607721                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61412.170088                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61412.170088                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56329.359895                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62614.381348                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58933.291890                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56329.359895                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62614.381348                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58933.291890                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.dcache.tags.replacements               159                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          1459.152638                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            28079168                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          1460.308394                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            28078942                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs              2247                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          12496.291945                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          12496.191366                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  1459.152638                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.356238                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.356238                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data  1460.308394                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.356521                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.356521                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         2088                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           25                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          131                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          542                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         1390                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          130                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          541                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         1391                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.509766                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          56179001                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         56179001                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     21586035                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        21586035                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      6492869                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        6492869                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data          264                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total          264                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data      28078904                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         28078904                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     28078904                       # number of overall hits
-system.cpu.dcache.overall_hits::total        28078904                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          974                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           974                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data         8234                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         8234                       # number of WriteReq misses
+system.cpu.dcache.tags.tag_accesses          56178581                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         56178581                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     21585827                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        21585827                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      6492868                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        6492868                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data          247                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total          247                       # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits::cpu.data      28078695                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         28078695                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     28078695                       # number of overall hits
+system.cpu.dcache.overall_hits::total        28078695                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          989                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           989                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data         8235                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         8235                       # number of WriteReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            1                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            1                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data         9208                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           9208                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         9208                       # number of overall misses
-system.cpu.dcache.overall_misses::total          9208                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     58289250                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     58289250                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    505816795                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    505816795                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data         9224                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           9224                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         9224                       # number of overall misses
+system.cpu.dcache.overall_misses::total          9224                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     64012750                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     64012750                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    517866286                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    517866286                       # number of WriteReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        92750                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::total        92750                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    564106045                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    564106045                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    564106045                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    564106045                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     21587009                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     21587009                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data    581879036                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    581879036                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    581879036                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    581879036                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     21586816                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     21586816                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data      6501103                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total      6501103                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data          265                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total          265                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     28088112                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     28088112                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     28088112                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     28088112                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000045                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.000045                       # miss rate for ReadReq accesses
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data          248                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total          248                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     28087919                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     28087919                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     28087919                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     28087919                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000046                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.000046                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001267                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.001267                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.003774                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.003774                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.004032                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.004032                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.000328                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     0.000328                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.000328                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.000328                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59845.225873                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 59845.225873                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61430.264149                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 61430.264149                       # average WriteReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64724.721941                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 64724.721941                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62886.009229                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 62886.009229                       # average WriteReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        92750                       # average LoadLockedReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        92750                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 61262.602628                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 61262.602628                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 61262.602628                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 61262.602628                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs        24052                       # number of cycles access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 63083.156548                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 63083.156548                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 63083.156548                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 63083.156548                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs        24818                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs               336                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs               346                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    71.583333                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    71.728324                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks          109                       # number of writebacks
 system.cpu.dcache.writebacks::total               109                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          459                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          459                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data         6503                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total         6503                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data         6962                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total         6962                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data         6962                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total         6962                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          474                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          474                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data         6504                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total         6504                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data         6978                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total         6978                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data         6978                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total         6978                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data          515                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total          515                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1731                       # number of WriteReq MSHR misses
@@ -913,36 +908,36 @@ system.cpu.dcache.demand_mshr_misses::cpu.data         2246
 system.cpu.dcache.demand_mshr_misses::total         2246                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data         2246                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total         2246                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     35552000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     35552000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    126441497                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    126441497                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     37612750                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     37612750                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    127737997                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    127737997                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data        90250                       # number of LoadLockedReq MSHR miss cycles
 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total        90250                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    161993497                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    161993497                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    161993497                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    161993497                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    165350747                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    165350747                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    165350747                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    165350747                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000024                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000024                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000266                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000266                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.003774                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.003774                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.004032                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.004032                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000080                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000080                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000080                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000080                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 69033.009709                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69033.009709                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73045.347776                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73045.347776                       # average WriteReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73034.466019                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73034.466019                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73794.336800                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73794.336800                       # average WriteReq mshr miss latency
 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data        90250                       # average LoadLockedReq mshr miss latency
 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total        90250                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72125.332591                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 72125.332591                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72125.332591                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 72125.332591                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73620.101069                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 73620.101069                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73620.101069                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 73620.101069                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index a1592fc7b071a53d947cf561e2bb946013d9a417..97565511190db863edfd145b85d23736a75ed05b 100644 (file)
@@ -1,61 +1,61 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.074220                       # Number of seconds simulated
-sim_ticks                                 74219931000                       # Number of ticks simulated
-final_tick                                74219931000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.074212                       # Number of seconds simulated
+sim_ticks                                 74211770500                       # Number of ticks simulated
+final_tick                                74211770500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 128899                       # Simulator instruction rate (inst/s)
-host_op_rate                                   141133                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               55523526                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 273064                       # Number of bytes of host memory used
-host_seconds                                  1336.73                       # Real time elapsed on the host
+host_inst_rate                                 109728                       # Simulator instruction rate (inst/s)
+host_op_rate                                   120142                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               47260193                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 316324                       # Number of bytes of host memory used
+host_seconds                                  1570.28                       # Real time elapsed on the host
 sim_insts                                   172303021                       # Number of instructions simulated
 sim_ops                                     188656503                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst            131072                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data            111680                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               242752                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data            112000                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               243072                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read::cpu.inst       131072                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total          131072                       # Number of instructions bytes read from this memory
 system.physmem.num_reads::cpu.inst               2048                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               1745                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  3793                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              1765995                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1504717                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 3270712                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         1765995                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            1765995                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             1765995                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1504717                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3270712                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                          3794                       # Number of read requests accepted
+system.physmem.num_reads::cpu.data               1750                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  3798                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              1766189                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1509195                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 3275383                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1766189                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1766189                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             1766189                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1509195                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3275383                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                          3799                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                        3794                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                        3799                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                   242816                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                   243136                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                    242816                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                    243136                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
 system.physmem.perBankRdBursts::0                 306                       # Per bank write bursts
 system.physmem.perBankRdBursts::1                 215                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                 133                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                 132                       # Per bank write bursts
 system.physmem.perBankRdBursts::3                 308                       # Per bank write bursts
 system.physmem.perBankRdBursts::4                 298                       # Per bank write bursts
 system.physmem.perBankRdBursts::5                 299                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                 264                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                 216                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                 265                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                 218                       # Per bank write bursts
 system.physmem.perBankRdBursts::8                 246                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                 215                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                 214                       # Per bank write bursts
 system.physmem.perBankRdBursts::10                289                       # Per bank write bursts
-system.physmem.perBankRdBursts::11                193                       # Per bank write bursts
-system.physmem.perBankRdBursts::12                189                       # Per bank write bursts
-system.physmem.perBankRdBursts::13                206                       # Per bank write bursts
-system.physmem.perBankRdBursts::14                217                       # Per bank write bursts
+system.physmem.perBankRdBursts::11                192                       # Per bank write bursts
+system.physmem.perBankRdBursts::12                190                       # Per bank write bursts
+system.physmem.perBankRdBursts::13                208                       # Per bank write bursts
+system.physmem.perBankRdBursts::14                219                       # Per bank write bursts
 system.physmem.perBankRdBursts::15                200                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     74219912500                       # Total gap between requests
+system.physmem.totGap                     74211752000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                    3794                       # Read request sizes (log2)
+system.physmem.readPktSize::6                    3799                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -90,9 +90,9 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      2825                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       784                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       142                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      2838                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       780                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       138                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                        36                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         6                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
@@ -154,101 +154,102 @@ system.physmem.wrQLenPdf::28                        0                       # Wh
 system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          717                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      334.192469                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     180.652659                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     576.534776                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64-65            257     35.84%     35.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-129          120     16.74%     52.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192-193           71      9.90%     62.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-257           49      6.83%     69.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320-321           19      2.65%     71.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-385           26      3.63%     75.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448-449           20      2.79%     78.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-513           17      2.37%     80.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576-577           17      2.37%     83.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-641           40      5.58%     88.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704-705           17      2.37%     91.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-769            6      0.84%     91.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832-833            6      0.84%     92.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-897            8      1.12%     93.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960-961            6      0.84%     94.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1025            5      0.70%     95.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088-1089            4      0.56%     95.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152-1153            1      0.14%     96.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216-1217            2      0.28%     96.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280-1281            2      0.28%     96.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344-1345            2      0.28%     96.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408-1409            2      0.28%     97.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472-1473            1      0.14%     97.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536-1537            1      0.14%     97.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600-1601            1      0.14%     97.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664-1665            1      0.14%     97.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1728-1729            1      0.14%     97.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1792-1793            2      0.28%     98.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856-1857            1      0.14%     98.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984-1985            2      0.28%     98.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2176-2177            1      0.14%     98.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2688-2689            1      0.14%     98.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2816-2817            1      0.14%     99.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3008-3009            1      0.14%     99.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3200-3201            1      0.14%     99.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3392-3393            1      0.14%     99.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3648-3649            1      0.14%     99.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3712-3713            1      0.14%     99.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6656-6657            1      0.14%     99.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8192-8193            1      0.14%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            717                       # Bytes accessed per row activation
-system.physmem.totQLat                       25208000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 100718000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     18970000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                    56540000                       # Total ticks spent accessing banks
-system.physmem.avgQLat                        6644.18                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    14902.48                       # Average bank access latency per DRAM burst
+system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples          252                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      398.476190                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     217.440190                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     401.372897                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             87     34.52%     34.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           58     23.02%     57.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           17      6.75%     64.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            5      1.98%     66.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            7      2.78%     69.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            8      3.17%     72.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            4      1.59%     73.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            3      1.19%     75.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151           63     25.00%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total            252                       # Bytes accessed per row activation
+system.physmem.totQLat                       23847500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 100702500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     18995000                       # Total ticks spent in databus transfers
+system.physmem.totBankLat                    57860000                       # Total ticks spent accessing banks
+system.physmem.avgQLat                        6277.31                       # Average queueing delay per DRAM burst
+system.physmem.avgBankLat                    15230.32                       # Average bank access latency per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  26546.65                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           3.27                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  26507.63                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           3.28                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        3.27                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        3.28                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         0.00                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       3077                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       3018                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   81.10                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   79.44                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                     19562443.99                       # Average gap between requests
-system.physmem.pageHitRate                      81.10                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               0.24                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                      3270712                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq                2723                       # Transaction distribution
-system.membus.trans_dist::ReadResp               2722                       # Transaction distribution
+system.physmem.avgGap                     19534549.09                       # Average gap between requests
+system.physmem.pageHitRate                      79.44                       # Row buffer hit rate, read and write combined
+system.physmem.prechargeAllPercent               0.21                       # Percentage of time for which DRAM has all the banks in precharge state
+system.membus.throughput                      3275383                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq                2728                       # Transaction distribution
+system.membus.trans_dist::ReadResp               2727                       # Transaction distribution
 system.membus.trans_dist::ReadExReq              1071                       # Transaction distribution
 system.membus.trans_dist::ReadExResp             1071                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         7587                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                   7587                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       242752                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total              242752                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus                 242752                       # Total data (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         7597                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                   7597                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       243072                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total              243072                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus                 243072                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy             4681000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy             4687500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           35532250                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           35592500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                94784239                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          74783977                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           6281559                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             44678373                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                43049971                       # Number of BTB hits
+system.cpu.branchPred.lookups                94795806                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          74795654                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           6279989                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             44691885                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                43051051                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             96.355279                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 4356641                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              88400                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             96.328564                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 4354918                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              88426                       # Number of incorrect RAS predictions.
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -334,135 +335,135 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  400                       # Number of system calls
-system.cpu.numCycles                        148439863                       # number of cpu cycles simulated
+system.cpu.numCycles                        148423542                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           39656875                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      380179667                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    94784239                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           47406612                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      80370607                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                27283097                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles                7220794                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                   45                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          6206                       # Number of stall cycles due to pending traps
+system.cpu.fetch.icacheStallCycles           39654967                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      380195915                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    94795806                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           47405969                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      80368300                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                27279262                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles                7212539                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                    9                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles          5988                       # Number of stall cycles due to pending traps
 system.cpu.fetch.PendingQuiesceStallCycles            1                       # Number of stall cycles due to pending quiesce instructions
 system.cpu.fetch.IcacheWaitRetryStallCycles           50                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  36850851                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               1831977                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          148240291                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.801605                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.152871                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines                  36848695                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               1833193                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          148225221                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.802047                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.153051                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 68038529     45.90%     45.90% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  5265458      3.55%     49.45% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 10540663      7.11%     56.56% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 10285699      6.94%     63.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  8660453      5.84%     69.34% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  6545120      4.42%     73.76% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  6246377      4.21%     77.97% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  8002820      5.40%     83.37% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 24655172     16.63%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 68026374     45.89%     45.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  5263091      3.55%     49.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 10536182      7.11%     56.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 10285653      6.94%     63.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  8660137      5.84%     69.33% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  6544581      4.42%     73.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  6243734      4.21%     77.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  8007959      5.40%     83.36% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 24657510     16.64%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            148240291                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.638536                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.561170                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 45513767                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles               5886575                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  74804066                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               1203498                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               20832385                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             14327909                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                164350                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              392779624                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                733803                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles               20832385                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 50900716                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                  730751                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         603183                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  70558259                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               4614997                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              371307860                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                    42                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 339068                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               3661204                       # Number of times rename has blocked due to LSQ full
+system.cpu.fetch.rateDist::total            148225221                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.638684                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.561561                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 45510679                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles               5881311                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  74801618                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               1201370                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               20830243                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             14327753                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                164034                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              392767808                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                749358                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles               20830243                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 50895494                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                  723680                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         602483                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  70555782                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               4617539                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              371309891                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                    37                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 338990                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               3664355                       # Number of times rename has blocked due to LSQ full
 system.cpu.rename.FullRegisterEvents               25                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           631703204                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            1588513521                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1506815662                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups           3203425                       # Number of floating rename lookups
+system.cpu.rename.RenamedOperands           631718613                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1588504211                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1506839397                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups           3198087                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             298044139                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                333659065                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts              25072                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts          25068                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  13010227                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             43012674                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            16416368                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           5733538                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          3666489                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  329189946                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded               47154                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 249456447                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            789359                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       139503196                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    362394637                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved           1938                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     148240291                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.682784                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.761427                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                333674474                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts              25005                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts          25002                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  13030816                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             43005440                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            16429294                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           5701095                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          3639070                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  329189812                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded               47090                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 249460239                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            787524                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       139505237                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    362363758                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           1874                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     148225221                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.682981                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.761692                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            56059626     37.82%     37.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            22638758     15.27%     53.09% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            24824129     16.75%     69.83% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            20343397     13.72%     83.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            12534810      8.46%     92.01% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             6516110      4.40%     96.41% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             4026087      2.72%     99.12% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             1116064      0.75%     99.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              181310      0.12%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            56054819     37.82%     37.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            22642547     15.28%     53.09% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            24806201     16.74%     69.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            20327492     13.71%     83.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            12550892      8.47%     92.01% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             6518173      4.40%     96.41% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             4029511      2.72%     99.13% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             1113373      0.75%     99.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              182213      0.12%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       148240291                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       148225221                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  965209     38.57%     38.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                   5593      0.22%     38.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     38.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     38.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     38.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     38.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     38.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     38.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     38.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     38.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     38.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     38.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     38.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     38.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     38.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     38.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     38.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     38.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     38.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     38.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd               101      0.00%     38.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     38.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     38.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     38.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     38.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc               48      0.00%     38.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     38.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     38.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     38.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                1158969     46.31%     85.11% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                372730     14.89%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  964965     38.34%     38.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                   5593      0.22%     38.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     38.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     38.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     38.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     38.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     38.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     38.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     38.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     38.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     38.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     38.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     38.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     38.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     38.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     38.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     38.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     38.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     38.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     38.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                99      0.00%     38.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     38.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     38.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     38.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     38.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc               49      0.00%     38.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     38.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     38.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     38.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                1170821     46.51%     85.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                375623     14.92%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             194899827     78.13%     78.13% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               979613      0.39%     78.52% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             194894311     78.13%     78.13% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               979316      0.39%     78.52% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     78.52% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     78.52% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     78.52% # Type of FU issued
@@ -481,93 +482,93 @@ system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     78.52% # Ty
 system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     78.52% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     78.52% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     78.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd           33082      0.01%     78.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     78.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp          164367      0.07%     78.60% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt          255141      0.10%     78.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv           76420      0.03%     78.73% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc         466123      0.19%     78.92% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult         206380      0.08%     79.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc        71866      0.03%     79.03% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd           33075      0.01%     78.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     78.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp          164356      0.07%     78.60% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt          254647      0.10%     78.70% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv           76432      0.03%     78.73% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc         465549      0.19%     78.92% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult         206388      0.08%     79.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc        71859      0.03%     79.03% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt            321      0.00%     79.03% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             38355265     15.38%     94.41% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            13948042      5.59%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             38358541     15.38%     94.41% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            13955444      5.59%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              249456447                       # Type of FU issued
-system.cpu.iq.rate                           1.680522                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     2502650                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.010032                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          646705187                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         466563017                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    237885267                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads             3740007                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes            2195697                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses      1842613                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              250082678                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                 1876419                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          2013206                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              249460239                       # Type of FU issued
+system.cpu.iq.rate                           1.680732                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2517150                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.010090                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          646712991                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         466571759                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    237891174                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             3737382                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes            2188885                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses      1841279                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              250102160                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 1875229                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          2007089                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     13163190                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        11604                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        18881                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      3771734                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     13155956                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        11631                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        18977                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      3784660                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads           18                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked           107                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads           11                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked           100                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               20832385                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                   18544                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                   886                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           329254297                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            785292                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              43012674                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             16416368                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts              24746                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                    181                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                   276                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          18881                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        3889950                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      3760088                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              7650038                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewSquashCycles               20830243                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                   18508                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                   911                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           329253924                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            785902                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              43005440                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             16429294                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts              24682                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                    206                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                   274                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          18977                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        3891616                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      3758665                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              7650281                       # Number of branch mispredicts detected at execute
 system.cpu.iew.iewExecutedInsts             242960344                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              36851914                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           6496103                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecLoadInsts              36855491                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           6499895                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                         17197                       # number of nop insts executed
-system.cpu.iew.exec_refs                     50500351                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 53426054                       # Number of branches executed
-system.cpu.iew.exec_stores                   13648437                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.636759                       # Inst execution rate
-system.cpu.iew.wb_sent                      240785488                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     239727880                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 148473973                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 267261246                       # num instructions consuming a value
+system.cpu.iew.exec_nop                         17022                       # number of nop insts executed
+system.cpu.iew.exec_refs                     50506525                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 53424421                       # Number of branches executed
+system.cpu.iew.exec_stores                   13651034                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.636939                       # Inst execution rate
+system.cpu.iew.wb_sent                      240787816                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     239732453                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 148473522                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 267271209                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.614983                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.555539                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.615192                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.555516                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts       140583409                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       140583033                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls           45216                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           6128231                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    127407906                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.480841                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.185453                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           6126865                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    127394978                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.480992                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.186196                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     57701601     45.29%     45.29% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     31696921     24.88%     70.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     13777775     10.81%     80.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      7640604      6.00%     86.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      4387783      3.44%     90.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1321955      1.04%     91.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      1703214      1.34%     92.80% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      1308007      1.03%     93.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      7870046      6.18%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     57713917     45.30%     45.30% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     31674198     24.86%     70.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     13788488     10.82%     80.99% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      7625423      5.99%     86.98% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      4380329      3.44%     90.41% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1321262      1.04%     91.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      1701589      1.34%     92.79% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      1311888      1.03%     93.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      7877884      6.18%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    127407906                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    127394978                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            172317409                       # Number of instructions committed
 system.cpu.commit.committedOps              188670891                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -578,230 +579,230 @@ system.cpu.commit.branches                   40300311                       # Nu
 system.cpu.commit.fp_insts                    1752310                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                 150106217                       # Number of committed integer instructions.
 system.cpu.commit.function_calls              1848934                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events               7870046                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events               7877884                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    448786959                       # The number of ROB reads
-system.cpu.rob.rob_writes                   679450685                       # The number of ROB writes
-system.cpu.timesIdled                            2806                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          199572                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                    448765817                       # The number of ROB reads
+system.cpu.rob.rob_writes                   679447245                       # The number of ROB writes
+system.cpu.timesIdled                            2831                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          198321                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   172303021                       # Number of Instructions Simulated
 system.cpu.committedOps                     188656503                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total             172303021                       # Number of Instructions Simulated
-system.cpu.cpi                               0.861505                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.861505                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.160760                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.160760                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               1079416198                       # number of integer regfile reads
-system.cpu.int_regfile_writes               384871537                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                   2913086                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                  2499105                       # number of floating regfile writes
-system.cpu.misc_regfile_reads                64870078                       # number of misc regfile reads
+system.cpu.cpi                               0.861410                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.861410                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.160887                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.160887                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               1079439987                       # number of integer regfile reads
+system.cpu.int_regfile_writes               384873432                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                   2912671                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                  2497165                       # number of floating regfile writes
+system.cpu.misc_regfile_reads                64868455                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                 820036                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput                 5170363                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq           4900                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp          4899                       # Transaction distribution
+system.cpu.toL2Bus.throughput                 5152821                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq           4879                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp          4878                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::Writeback           18                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq         1079                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp         1079                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         8253                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         3722                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             11975                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       264064                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       119680                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total         383744                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus            383744                       # Total data (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         8203                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         3730                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             11933                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       262464                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       119936                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total         382400                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus            382400                       # Total data (bytes)
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy        3016500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.occupancy        3006000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       6553746                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       6511747                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy       3047989                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy       3051239                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.icache.tags.replacements              2395                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1347.740461                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            36845513                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              4126                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           8930.080708                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements              2374                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1347.666302                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            36843383                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              4101                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           8983.999756                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1347.740461                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.658076                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.658076                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1731                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           41                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           82                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          544                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3           27                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1037                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.845215                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          73705828                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         73705828                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     36845513                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        36845513                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      36845513                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         36845513                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     36845513                       # number of overall hits
-system.cpu.icache.overall_hits::total        36845513                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         5338                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          5338                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         5338                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           5338                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         5338                       # number of overall misses
-system.cpu.icache.overall_misses::total          5338                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    225943745                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    225943745                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    225943745                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    225943745                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    225943745                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    225943745                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     36850851                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     36850851                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     36850851                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     36850851                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     36850851                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     36850851                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000145                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000145                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000145                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000145                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000145                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000145                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42327.415699                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 42327.415699                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 42327.415699                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 42327.415699                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 42327.415699                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 42327.415699                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         1128                       # number of cycles access was blocked
+system.cpu.icache.tags.occ_blocks::cpu.inst  1347.666302                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.658040                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.658040                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1727                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           42                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           83                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          534                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3           28                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1040                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.843262                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          73701491                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         73701491                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     36843383                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        36843383                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      36843383                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         36843383                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     36843383                       # number of overall hits
+system.cpu.icache.overall_hits::total        36843383                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         5312                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          5312                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         5312                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           5312                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         5312                       # number of overall misses
+system.cpu.icache.overall_misses::total          5312                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    224724996                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    224724996                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    224724996                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    224724996                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    224724996                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    224724996                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     36848695                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     36848695                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     36848695                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     36848695                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     36848695                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     36848695                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000144                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000144                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000144                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000144                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000144                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000144                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42305.157380                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 42305.157380                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 42305.157380                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 42305.157380                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 42305.157380                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 42305.157380                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         1646                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                19                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    59.368421                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    86.631579                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1211                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         1211                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         1211                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         1211                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         1211                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         1211                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4127                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         4127                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         4127                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         4127                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         4127                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         4127                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    168102254                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    168102254                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    168102254                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    168102254                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    168102254                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    168102254                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000112                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000112                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000112                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000112                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000112                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000112                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40732.312576                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40732.312576                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40732.312576                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 40732.312576                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40732.312576                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 40732.312576                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1210                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         1210                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         1210                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         1210                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         1210                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         1210                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4102                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         4102                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         4102                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         4102                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         4102                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         4102                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    167739253                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    167739253                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    167739253                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    167739253                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    167739253                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    167739253                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000111                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000111                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000111                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000111                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000111                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000111                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40892.065578                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40892.065578                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40892.065578                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 40892.065578                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40892.065578                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 40892.065578                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         1967.449595                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs               2163                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             2732                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.791728                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         1968.326603                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs               2138                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs             2737                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.781147                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks     4.994097                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  1425.569547                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   536.885951                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks     4.994032                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  1425.493487                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   537.839084                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.000152                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.043505                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.016384                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.060042                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024         2732                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           39                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1           91                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          604                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.043503                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.016414                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.060069                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         2737                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           41                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           95                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          602                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3           28                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         1970                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.083374                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses            51787                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses           51787                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst         2074                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data           88                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total           2162                       # number of ReadReq hits
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         1971                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.083527                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses            51624                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses           51624                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst         2050                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data           87                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total           2137                       # number of ReadReq hits
 system.cpu.l2cache.Writeback_hits::writebacks           18                       # number of Writeback hits
 system.cpu.l2cache.Writeback_hits::total           18                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data            8                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total            8                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         2074                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data           96                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total            2170                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         2074                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data           96                       # number of overall hits
-system.cpu.l2cache.overall_hits::total           2170                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         2053                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data          685                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         2738                       # number of ReadReq misses
+system.cpu.l2cache.demand_hits::cpu.inst         2050                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data           95                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total            2145                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         2050                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data           95                       # number of overall hits
+system.cpu.l2cache.overall_hits::total           2145                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         2052                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data          690                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total         2742                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data         1071                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total         1071                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         2053                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data         1756                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total          3809                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         2053                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data         1756                       # number of overall misses
-system.cpu.l2cache.overall_misses::total         3809                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    143228250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     51387250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    194615500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     72292250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total     72292250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    143228250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    123679500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    266907750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    143228250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    123679500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    266907750                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst         4127                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data          773                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total         4900                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.demand_misses::cpu.inst         2052                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data         1761                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total          3813                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         2052                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data         1761                       # number of overall misses
+system.cpu.l2cache.overall_misses::total         3813                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    143127750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     50855750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    193983500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     72887500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total     72887500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    143127750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    123743250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    266871000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    143127750                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    123743250                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    266871000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst         4102                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data          777                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total         4879                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::writebacks           18                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::total           18                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data         1079                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total         1079                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         4127                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data         1852                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total         5979                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         4127                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data         1852                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total         5979                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.497456                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.886158                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.558776                       # miss rate for ReadReq accesses
+system.cpu.l2cache.demand_accesses::cpu.inst         4102                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data         1856                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total         5958                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         4102                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data         1856                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total         5958                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.500244                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.888031                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.562000                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.992586                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total     0.992586                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.497456                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.948164                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.637063                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.497456                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.948164                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.637063                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69765.343400                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75017.883212                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 71079.437546                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67499.766573                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67499.766573                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69765.343400                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70432.517084                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 70072.919401                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69765.343400                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70432.517084                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 70072.919401                       # average overall miss latency
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.500244                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.948815                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.639980                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.500244                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.948815                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.639980                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69750.365497                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73703.985507                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 70745.258935                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68055.555556                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68055.555556                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69750.365497                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70268.739353                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 69989.771833                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69750.365497                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70268.739353                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 69989.771833                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -810,178 +811,178 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            4                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            3                       # number of ReadReq MSHR hits
 system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           11                       # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total           15                       # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst            4                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total           14                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst            3                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.data           11                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total           15                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst            4                       # number of overall MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           14                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst            3                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.data           11                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total           15                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total           14                       # number of overall MSHR hits
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2049                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          674                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         2723                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          679                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         2728                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1071                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total         1071                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.inst         2049                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data         1745                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         3794                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data         1750                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         3799                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         2049                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data         1745                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total         3794                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    117257250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     42300250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    159557500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     58841750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     58841750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    117257250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    101142000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    218399250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    117257250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    101142000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    218399250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.496487                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.871928                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.555714                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.overall_mshr_misses::cpu.data         1750                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total         3799                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    117223750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     41708750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    158932500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     59427500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     59427500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    117223750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    101136250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    218360000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    117223750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    101136250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    218360000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.499512                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.873874                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.559131                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.992586                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.992586                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.496487                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.942225                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.634554                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.496487                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.942225                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.634554                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57226.573939                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62760.014837                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58596.217407                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54940.943044                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54940.943044                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57226.573939                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57961.031519                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57564.377965                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57226.573939                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57961.031519                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57564.377965                       # average overall mshr miss latency
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.499512                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.942888                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.637630                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.499512                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.942888                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.637630                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57210.224500                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61426.730486                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58259.714076                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55487.861811                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55487.861811                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57210.224500                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57792.142857                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57478.283759                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57210.224500                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57792.142857                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57478.283759                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements                57                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          1406.103051                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            46786126                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs              1852                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          25262.487041                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.replacements                59                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          1407.038554                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            46795712                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs              1856                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          25213.206897                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  1406.103051                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.343287                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.343287                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         1795                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           24                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           38                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_blocks::cpu.data  1407.038554                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.343515                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.343515                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         1797                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           25                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           39                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2          353                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4         1378                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.438232                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          93593354                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         93593354                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     34384681                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        34384681                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     12356564                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       12356564                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data        22474                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total        22474                       # number of LoadLockedReq hits
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.438721                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses          93612504                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         93612504                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     34394263                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        34394263                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     12356566                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       12356566                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data        22476                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total        22476                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data        22407                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total        22407                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      46741245                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         46741245                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     46741245                       # number of overall hits
-system.cpu.dcache.overall_hits::total        46741245                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data         1900                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total          1900                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data         7723                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         7723                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data      46750829                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         46750829                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     46750829                       # number of overall hits
+system.cpu.dcache.overall_hits::total        46750829                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data         1889                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total          1889                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data         7721                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         7721                       # number of WriteReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            2                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            2                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data         9623                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           9623                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         9623                       # number of overall misses
-system.cpu.dcache.overall_misses::total          9623                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data    121712227                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total    121712227                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    465623746                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    465623746                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data         9610                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           9610                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         9610                       # number of overall misses
+system.cpu.dcache.overall_misses::total          9610                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data    119060977                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total    119060977                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    479134996                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    479134996                       # number of WriteReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       142500                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::total       142500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    587335973                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    587335973                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    587335973                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    587335973                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     34386581                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     34386581                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data    598195973                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    598195973                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    598195973                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    598195973                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     34396152                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     34396152                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     12364287                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     12364287                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data        22476                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total        22476                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data        22478                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total        22478                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data        22407                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total        22407                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     46750868                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     46750868                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     46750868                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     46750868                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data     46760439                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     46760439                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     46760439                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     46760439                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000055                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.000055                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000625                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.000625                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000624                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.000624                       # miss rate for WriteReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000089                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000089                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.000206                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     0.000206                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.000206                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.000206                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64059.066842                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 64059.066842                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60290.527774                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 60290.527774                       # average WriteReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63028.574378                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 63028.574378                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62056.080300                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 62056.080300                       # average WriteReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        71250                       # average LoadLockedReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        71250                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 61034.601787                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 61034.601787                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 61034.601787                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 61034.601787                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs          592                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets          314                       # number of cycles access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 62247.239646                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 62247.239646                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 62247.239646                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 62247.239646                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs          566                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets          318                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                11                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               4                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    53.818182                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    78.500000                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    51.454545                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    79.500000                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks           18                       # number of writebacks
 system.cpu.dcache.writebacks::total                18                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data         1126                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total         1126                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data         6645                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total         6645                       # number of WriteReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data         1111                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total         1111                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data         6643                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total         6643                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            2                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total            2                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data         7771                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total         7771                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data         7771                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total         7771                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data          774                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          774                       # number of ReadReq MSHR misses
+system.cpu.dcache.demand_mshr_hits::cpu.data         7754                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total         7754                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data         7754                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total         7754                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          778                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          778                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1078                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total         1078                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data         1852                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total         1852                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data         1852                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total         1852                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     53118011                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     53118011                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     73393498                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total     73393498                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    126511509                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    126511509                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    126511509                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    126511509                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data         1856                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         1856                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data         1856                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         1856                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     52580511                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     52580511                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     73988748                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total     73988748                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    126569259                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    126569259                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    126569259                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    126569259                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000023                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000023                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000087                       # mshr miss rate for WriteReq accesses
@@ -990,14 +991,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000040
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000040                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000040                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000040                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68627.921189                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68627.921189                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68083.022263                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68083.022263                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68310.750000                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 68310.750000                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68310.750000                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 68310.750000                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67584.204370                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67584.204370                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68635.202226                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68635.202226                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68194.643858                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 68194.643858                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68194.643858                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 68194.643858                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 1427887bb9ceffe1cfe3701ce9cee1c3e6673894..cc1011ed37717a23f84e64e3241cdc85e48909a3 100644 (file)
@@ -1,61 +1,61 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.144463                       # Number of seconds simulated
-sim_ticks                                144463317000                       # Number of ticks simulated
-final_tick                               144463317000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.144377                       # Number of seconds simulated
+sim_ticks                                144377116000                       # Number of ticks simulated
+final_tick                               144377116000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  81167                       # Simulator instruction rate (inst/s)
-host_op_rate                                   136043                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               88782348                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 282908                       # Number of bytes of host memory used
-host_seconds                                  1627.16                       # Real time elapsed on the host
+host_inst_rate                                  66784                       # Simulator instruction rate (inst/s)
+host_op_rate                                   111936                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               73006862                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 319660                       # Number of bytes of host memory used
+host_seconds                                  1977.58                       # Real time elapsed on the host
 sim_insts                                   132071192                       # Number of instructions simulated
 sim_ops                                     221363384                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            217088                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data            125568                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               342656                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       217088                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          217088                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               3392                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               1962                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  5354                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              1502721                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data               869203                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2371924                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         1502721                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            1502721                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             1502721                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data              869203                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2371924                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                          5354                       # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst            217984                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data            125056                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               343040                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       217984                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          217984                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               3406                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               1954                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  5360                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              1509824                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data               866176                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2376000                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1509824                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1509824                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             1509824                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data              866176                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2376000                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                          5361                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                        5354                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                        5361                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                   342656                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                   343104                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                    342656                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                    343104                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs            163                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                 289                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                 357                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                 453                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                 356                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                 332                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                 326                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                 402                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                 377                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                 341                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                 276                       # Per bank write bursts
-system.physmem.perBankRdBursts::10                232                       # Per bank write bursts
-system.physmem.perBankRdBursts::11                277                       # Per bank write bursts
-system.physmem.perBankRdBursts::12                205                       # Per bank write bursts
-system.physmem.perBankRdBursts::13                465                       # Per bank write bursts
-system.physmem.perBankRdBursts::14                384                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs            150                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0                 281                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                 346                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                 449                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                 351                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                 335                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                 328                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                 398                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                 381                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                 343                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                 292                       # Per bank write bursts
+system.physmem.perBankRdBursts::10                228                       # Per bank write bursts
+system.physmem.perBankRdBursts::11                284                       # Per bank write bursts
+system.physmem.perBankRdBursts::12                208                       # Per bank write bursts
+system.physmem.perBankRdBursts::13                469                       # Per bank write bursts
+system.physmem.perBankRdBursts::14                386                       # Per bank write bursts
 system.physmem.perBankRdBursts::15                282                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    144463266500                       # Total gap between requests
+system.physmem.totGap                    144377080000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                    5354                       # Read request sizes (log2)
+system.physmem.readPktSize::6                    5361                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -90,11 +90,11 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      4302                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       874                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       155                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      4312                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       880                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       145                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                        20                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -154,346 +154,337 @@ system.physmem.wrQLenPdf::28                        0                       # Wh
 system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          957                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      353.103448                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     172.307957                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     612.115437                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64               385     40.23%     40.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128              164     17.14%     57.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192               81      8.46%     65.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256               46      4.81%     70.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320               43      4.49%     75.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384               20      2.09%     77.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448               26      2.72%     79.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512               19      1.99%     81.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576               17      1.78%     83.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640               26      2.72%     86.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704               27      2.82%     89.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768                7      0.73%     89.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832                7      0.73%     90.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896                7      0.73%     91.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960                3      0.31%     91.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024               5      0.52%     92.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088               6      0.63%     92.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152               6      0.63%     93.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216               4      0.42%     93.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280               2      0.21%     94.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344               2      0.21%     94.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408               3      0.31%     94.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472               7      0.73%     95.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536               1      0.10%     95.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600               5      0.52%     96.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664               4      0.42%     96.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1728               2      0.21%     96.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1792               2      0.21%     96.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856               2      0.21%     97.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1920               3      0.31%     97.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984               2      0.21%     97.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112               1      0.10%     97.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2176               1      0.10%     97.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2240               1      0.10%     97.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2304               1      0.10%     98.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2368               1      0.10%     98.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2432               2      0.21%     98.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2496               1      0.10%     98.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2816               2      0.21%     98.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2880               3      0.31%     98.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3072               1      0.10%     99.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3328               1      0.10%     99.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3456               1      0.10%     99.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3584               1      0.10%     99.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4160               1      0.10%     99.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4352               1      0.10%     99.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4736               1      0.10%     99.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5312               1      0.10%     99.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5696               1      0.10%     99.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5952               1      0.10%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            957                       # Bytes accessed per row activation
-system.physmem.totQLat                       28783000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 137846750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     26770000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                    82293750                       # Total ticks spent accessing banks
-system.physmem.avgQLat                        5375.98                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    15370.52                       # Average bank access latency per DRAM burst
+system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples          327                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      508.672783                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     294.998238                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     425.682375                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             88     26.91%     26.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           53     16.21%     43.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           28      8.56%     51.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           16      4.89%     56.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            9      2.75%     59.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            6      1.83%     61.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            3      0.92%     62.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            3      0.92%     63.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          121     37.00%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total            327                       # Bytes accessed per row activation
+system.physmem.totQLat                       28551000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 139987250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     26805000                       # Total ticks spent in databus transfers
+system.physmem.totBankLat                    84631250                       # Total ticks spent accessing banks
+system.physmem.avgQLat                        5325.69                       # Average queueing delay per DRAM burst
+system.physmem.avgBankLat                    15786.47                       # Average bank access latency per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  25746.50                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           2.37                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  26112.15                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           2.38                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        2.37                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        2.38                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         0.00                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.13                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       4397                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       4274                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.13                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   79.72                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                     26982306.03                       # Average gap between requests
-system.physmem.pageHitRate                      82.13                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               0.41                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                      2371924                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq                3822                       # Transaction distribution
-system.membus.trans_dist::ReadResp               3822                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              163                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp             163                       # Transaction distribution
-system.membus.trans_dist::ReadExReq              1532                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             1532                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        11034                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total        11034                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  11034                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       342656                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total       342656                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total              342656                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus                 342656                       # Total data (bytes)
+system.physmem.avgGap                     26930997.95                       # Average gap between requests
+system.physmem.pageHitRate                      79.72                       # Row buffer hit rate, read and write combined
+system.physmem.prechargeAllPercent               0.40                       # Percentage of time for which DRAM has all the banks in precharge state
+system.membus.throughput                      2375113                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq                3828                       # Transaction distribution
+system.membus.trans_dist::ReadResp               3825                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq              150                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp             150                       # Transaction distribution
+system.membus.trans_dist::ReadExReq              1533                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             1533                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        11019                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total        11019                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  11019                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       342912                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total       342912                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total              342912                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus                 342912                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy             6950000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy             6993500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           50662837                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           50706850                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                18648233                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          18648233                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           1490176                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             11407549                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                10790529                       # Number of BTB hits
+system.cpu.branchPred.lookups                18662333                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          18662333                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           1490477                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             11407057                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                10802916                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             94.591126                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1320367                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              22841                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             94.703796                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1319575                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              23217                       # Number of incorrect RAS predictions.
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                  400                       # Number of system calls
-system.cpu.numCycles                        289221873                       # number of cpu cycles simulated
+system.cpu.numCycles                        289035036                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           23458043                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      206724218                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    18648233                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           12110896                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      54209097                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                15518774                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles              178161359                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                 1571                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          9111                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles           38                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  22353211                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                224061                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          269612469                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.268180                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.756310                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           23466628                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      206674196                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    18662333                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           12122491                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      54224578                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                15529649                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles              177872737                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                 1739                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles          9780                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles           23                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  22363082                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                227556                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          269352720                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.269654                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.757498                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                216842563     80.43%     80.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  2848142      1.06%     81.48% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  2312055      0.86%     82.34% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  2633842      0.98%     83.32% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  3218714      1.19%     84.51% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  3388946      1.26%     85.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  3831195      1.42%     87.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  2559437      0.95%     88.14% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 31977575     11.86%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                216567147     80.40%     80.40% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  2849140      1.06%     81.46% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  2312743      0.86%     82.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  2640443      0.98%     83.30% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  3223496      1.20%     84.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  3388678      1.26%     85.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  3828931      1.42%     87.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  2559342      0.95%     88.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 31982800     11.87%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            269612469                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.064477                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.714760                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 36899359                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             167130004                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  41545229                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              10264627                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               13773250                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts              336001462                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles               13773250                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 44972487                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles               116686698                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          32545                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  42701689                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              51445800                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              329633775                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                 10827                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents               26123597                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents              22730549                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands           382342090                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             917586713                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        605878272                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups           4127660                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            269352720                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.064568                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.715049                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 36872291                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             166882879                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  41583049                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              10237266                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               13777235                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts              336030589                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles               13777235                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 44927552                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles               116592006                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          33482                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  42725844                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              51296601                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              329644603                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                 10793                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               25973281                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents              22738118                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands           382392326                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             917644681                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        605892364                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups           4122807                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             259429450                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                122912640                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               2051                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts           2042                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 105140052                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             84507276                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            30107186                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          58355212                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         18979888                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  322730905                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                4069                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 260501994                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            116055                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       100987191                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    210203655                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved           2824                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     269612469                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.966209                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.343680                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                122962876                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               2119                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           2126                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 104910685                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             84442386                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            30099715                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          58118082                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         18905602                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  322699954                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                4280                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 260615725                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            114961                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       100953398                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    209924725                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           3035                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     269352720                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.967563                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.344835                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           143429912     53.20%     53.20% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            55567346     20.61%     73.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            34108148     12.65%     86.46% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            19044980      7.06%     93.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            10887634      4.04%     97.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             4152283      1.54%     99.10% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             1816697      0.67%     99.78% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              472473      0.18%     99.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              132996      0.05%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           143250903     53.18%     53.18% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            55370436     20.56%     73.74% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            34176648     12.69%     86.43% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            19094867      7.09%     93.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            10869897      4.04%     97.55% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             4155062      1.54%     99.10% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             1825131      0.68%     99.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              476500      0.18%     99.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              133276      0.05%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       269612469                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       269352720                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  130605      4.82%      4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      4.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                2279077     84.03%     88.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                302412     11.15%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  130941      4.84%      4.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      4.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      4.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      4.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      4.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      4.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      4.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      4.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      4.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      4.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      4.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      4.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      4.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      4.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      4.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      4.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      4.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      4.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      4.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      4.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      4.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      4.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      4.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      4.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      4.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      4.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      4.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      4.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      4.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                2275620     84.10%     88.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                299199     11.06%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass           1210810      0.46%      0.46% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             162055944     62.21%     62.67% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               789191      0.30%     62.98% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv               7035649      2.70%     65.68% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd             1445882      0.56%     66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             65414513     25.11%     91.34% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            22550005      8.66%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass           1210799      0.46%      0.46% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             162097443     62.20%     62.66% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               790400      0.30%     62.97% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv               7035783      2.70%     65.67% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd             1447528      0.56%     66.22% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.22% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     66.22% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     66.22% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     66.22% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     66.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     66.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     66.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     66.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     66.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     66.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     66.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     66.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     66.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     66.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     66.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     66.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     66.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     66.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     66.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     66.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     66.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.22% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             65478586     25.12%     91.35% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            22555186      8.65%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              260501994                       # Type of FU issued
-system.cpu.iq.rate                           0.900699                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     2712094                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.010411                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          788557578                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         420384868                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    255147075                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads             4887028                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes            3615221                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses      2349564                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              259544026                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                 2459252                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         18903382                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              260615725                       # Type of FU issued
+system.cpu.iq.rate                           0.901675                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2705760                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.010382                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          788512519                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         420334227                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    255242293                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             4892372                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes            3608187                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses      2352192                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              259648600                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 2462086                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         18920241                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     27857689                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        25992                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       283319                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      9591469                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     27792799                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        26588                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       290410                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      9583998                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        49752                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked            16                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        49921                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked            17                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               13773250                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                85040639                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               5471570                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           322734974                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            133239                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              84507276                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             30107186                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               1979                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                2708196                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 13910                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         283319                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         639398                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       901242                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1540640                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             258732431                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              64645019                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           1769563                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles               13777235                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                85064772                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               5446513                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           322704234                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            135340                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              84442386                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             30099715                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               2049                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                2678194                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 12950                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         290410                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         639185                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       902051                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              1541236                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             258833919                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              64703526                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1781806                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                     86992194                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 14265859                       # Number of branches executed
-system.cpu.iew.exec_stores                   22347175                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.894581                       # Inst execution rate
-system.cpu.iew.wb_sent                      258096693                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     257496639                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 205928299                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 369130530                       # num instructions consuming a value
+system.cpu.iew.exec_refs                     87053484                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 14272898                       # Number of branches executed
+system.cpu.iew.exec_stores                   22349958                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.895511                       # Inst execution rate
+system.cpu.iew.wb_sent                      258192676                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     257594485                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 206043233                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 369200904                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.890308                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.557874                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.891222                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.558079                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts       101448840                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts       101415579                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls            1245                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           1491529                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    255839219                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.865244                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.654327                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           1491917                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    255575485                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.866137                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.656618                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    156486617     61.17%     61.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     57197635     22.36%     83.52% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     14067876      5.50%     89.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     12054068      4.71%     93.73% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      4176261      1.63%     95.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      2944387      1.15%     96.52% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       904564      0.35%     96.87% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      1049058      0.41%     97.28% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      6958753      2.72%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    156360594     61.18%     61.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     57109316     22.35%     83.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     13985683      5.47%     89.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     12037857      4.71%     93.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      4182593      1.64%     95.34% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      2963821      1.16%     96.50% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       909345      0.36%     96.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      1046624      0.41%     97.27% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      6979652      2.73%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    255839219                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    255575485                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            132071192                       # Number of instructions committed
 system.cpu.commit.committedOps              221363384                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -504,240 +495,240 @@ system.cpu.commit.branches                   12326938                       # Nu
 system.cpu.commit.fp_insts                    2162459                       # Number of committed floating point instructions.
 system.cpu.commit.int_insts                 219019985                       # Number of committed integer instructions.
 system.cpu.commit.function_calls               797818                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events               6958753                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events               6979652                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    571692690                       # The number of ROB reads
-system.cpu.rob.rob_writes                   659422914                       # The number of ROB writes
-system.cpu.timesIdled                         5933064                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        19609404                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                    571374796                       # The number of ROB reads
+system.cpu.rob.rob_writes                   659361249                       # The number of ROB writes
+system.cpu.timesIdled                         5927783                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        19682316                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   132071192                       # Number of Instructions Simulated
 system.cpu.committedOps                     221363384                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total             132071192                       # Number of Instructions Simulated
-system.cpu.cpi                               2.189894                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         2.189894                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.456643                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.456643                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                451224153                       # number of integer regfile reads
-system.cpu.int_regfile_writes               233957254                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                   3215586                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                  2009211                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 102809513                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                 59799383                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               133324417                       # number of misc regfile reads
+system.cpu.cpi                               2.188479                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         2.188479                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.456938                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.456938                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                451403378                       # number of integer regfile reads
+system.cpu.int_regfile_writes               234040975                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                   3219859                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                  2011879                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 102824885                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                 59817361                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               133392985                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                   1689                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput                 3898568                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq           7250                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp          7248                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback           13                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq          163                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp          163                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq         1539                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp         1539                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        13403                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         4348                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             17751                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       423616                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       129088                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total         552704                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus            552704                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus        10496                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy        4495500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.throughput                 3846371                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq           7125                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp          7121                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback           15                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq          150                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp          150                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq         1541                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp         1541                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        13184                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         4308                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             17492                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       417024                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       128640                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total         545664                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus            545664                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus         9664                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy        4430500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      10760250                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      10573999                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy       3467413                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy       3437150                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.cpu.icache.tags.replacements              4653                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1619.938452                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            22344300                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              6620                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           3375.271903                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements              4547                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1629.451963                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            22354297                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              6517                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           3430.151450                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1619.938452                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.790986                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.790986                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1967                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           96                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          185                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          767                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          122                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          797                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.960449                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          44713203                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         44713203                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     22344300                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        22344300                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      22344300                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         22344300                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     22344300                       # number of overall hits
-system.cpu.icache.overall_hits::total        22344300                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         8910                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          8910                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         8910                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           8910                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         8910                       # number of overall misses
-system.cpu.icache.overall_misses::total          8910                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    368144999                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    368144999                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    368144999                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    368144999                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    368144999                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    368144999                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     22353210                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     22353210                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     22353210                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     22353210                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     22353210                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     22353210                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000399                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000399                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000399                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000399                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000399                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000399                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41318.181706                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 41318.181706                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 41318.181706                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 41318.181706                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 41318.181706                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 41318.181706                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          877                       # number of cycles access was blocked
+system.cpu.icache.tags.occ_blocks::cpu.inst  1629.451963                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.795631                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.795631                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1970                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           94                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          187                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          757                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          125                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          807                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.961914                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          44732829                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         44732829                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     22354297                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        22354297                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      22354297                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         22354297                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     22354297                       # number of overall hits
+system.cpu.icache.overall_hits::total        22354297                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         8784                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          8784                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         8784                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           8784                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         8784                       # number of overall misses
+system.cpu.icache.overall_misses::total          8784                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    365846249                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    365846249                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    365846249                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    365846249                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    365846249                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    365846249                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     22363081                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     22363081                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     22363081                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     22363081                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     22363081                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     22363081                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000393                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000393                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000393                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000393                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000393                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000393                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41649.163138                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 41649.163138                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 41649.163138                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 41649.163138                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 41649.163138                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 41649.163138                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          800                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                20                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                14                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    43.850000                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    57.142857                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2126                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         2126                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         2126                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         2126                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         2126                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         2126                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         6784                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         6784                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         6784                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         6784                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         6784                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         6784                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    271638749                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    271638749                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    271638749                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    271638749                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    271638749                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    271638749                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000303                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000303                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000303                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000303                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000303                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000303                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40041.089180                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40041.089180                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40041.089180                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 40041.089180                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40041.089180                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 40041.089180                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2116                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         2116                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         2116                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         2116                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         2116                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         2116                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         6668                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         6668                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         6668                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         6668                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         6668                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         6668                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    272166001                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    272166001                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    272166001                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    272166001                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    272166001                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    272166001                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000298                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000298                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000298                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000298                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000298                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000298                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40816.736803                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40816.736803                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40816.736803                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 40816.736803                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40816.736803                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 40816.736803                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         2543.926920                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs               3266                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             3826                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.853633                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         2545.733703                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs               3149                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs             3831                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.821979                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks     1.725256                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2230.334814                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   311.866849                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.000053                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.068064                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.009517                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.077634                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024         3826                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           51                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          194                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          876                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3          145                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2560                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.116760                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses            75773                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses           75773                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst         3227                       # number of ReadReq hits
+system.cpu.l2cache.tags.occ_blocks::writebacks     1.666971                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2237.371026                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   306.695706                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.000051                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.068279                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.009360                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.077690                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         3831                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           49                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          190                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          881                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3          143                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2568                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.116913                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses            74812                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses           74812                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst         3110                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data           36                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total           3263                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks           13                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total           13                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data            7                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total            7                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         3227                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data           43                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total            3270                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         3227                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data           43                       # number of overall hits
-system.cpu.l2cache.overall_hits::total           3270                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         3393                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data          430                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         3823                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data          163                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total          163                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data         1532                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total         1532                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         3393                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data         1962                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total          5355                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         3393                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data         1962                       # number of overall misses
-system.cpu.l2cache.overall_misses::total         5355                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    232417000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     32755500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    265172500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    104434000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    104434000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    232417000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    137189500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    369606500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    232417000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    137189500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    369606500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst         6620                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data          466                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total         7086                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks           13                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total           13                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data          163                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total          163                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data         1539                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total         1539                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         6620                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data         2005                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total         8625                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         6620                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data         2005                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total         8625                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.512538                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.922747                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.539515                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_hits::total           3146                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks           15                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total           15                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data            8                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total            8                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst         3110                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data           44                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total            3154                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         3110                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data           44                       # number of overall hits
+system.cpu.l2cache.overall_hits::total           3154                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         3407                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data          421                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total         3828                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data          150                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total          150                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data         1533                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total         1533                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         3407                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data         1954                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total          5361                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         3407                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data         1954                       # number of overall misses
+system.cpu.l2cache.overall_misses::total         5361                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    234241000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     32796500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    267037500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    104661000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    104661000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    234241000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    137457500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    371698500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    234241000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    137457500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    371698500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst         6517                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data          457                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total         6974                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks           15                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total           15                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data          150                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total          150                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data         1541                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total         1541                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         6517                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data         1998                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total         8515                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         6517                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data         1998                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total         8515                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.522787                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.921225                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.548896                       # miss rate for ReadReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data            1                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.995452                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.995452                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.512538                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.978554                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.620870                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.512538                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.978554                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.620870                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68498.968464                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76175.581395                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 69362.411719                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68168.407311                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68168.407311                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68498.968464                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69923.292559                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 69020.821662                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68498.968464                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69923.292559                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 69020.821662                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.994809                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.994809                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.522787                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.977978                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.629595                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.522787                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.977978                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.629595                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68752.861755                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77901.425178                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 69759.012539                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68272.015656                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68272.015656                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68752.861755                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70346.724667                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 69333.799664                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68752.861755                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70346.724667                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 69333.799664                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -746,175 +737,175 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3393                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          430                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         3823                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data          163                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total          163                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1532                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total         1532                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3393                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data         1962                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         5355                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3393                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data         1962                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total         5355                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    189899500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     27426500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    217326000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      1630163                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      1630163                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     84874000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     84874000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    189899500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    112300500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    302200000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    189899500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    112300500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    302200000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.512538                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.922747                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.539515                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3407                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          421                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         3828                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data          150                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total          150                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1533                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         1533                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3407                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data         1954                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         5361                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3407                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data         1954                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total         5361                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    191583500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     27592500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    219176000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      1500150                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      1500150                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     85063500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     85063500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    191583500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    112656000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    304239500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    191583500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    112656000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    304239500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.522787                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.921225                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.548896                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.995452                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.995452                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.512538                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.978554                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.620870                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.512538                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.978554                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.620870                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55968.022399                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63782.558140                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56846.978812                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.994809                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.994809                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.522787                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.977978                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.629595                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.522787                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.977978                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.629595                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56232.315820                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65540.380048                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57256.008359                       # average ReadReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        10001                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55400.783290                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55400.783290                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55968.022399                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57237.767584                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56433.239963                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55968.022399                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57237.767584                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56433.239963                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55488.258317                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55488.258317                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56232.315820                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57654.042989                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56750.512964                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56232.315820                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57654.042989                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56750.512964                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.dcache.tags.replacements                57                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          1438.861304                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            66102356                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs              2004                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          32985.207585                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          1432.023881                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            66143701                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs              1995                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          33154.737343                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  1438.861304                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.351284                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.351284                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         1947                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_blocks::cpu.data  1432.023881                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.349615                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.349615                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         1938                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           17                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           33                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           70                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3          432                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         1395                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.475342                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         132211530                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        132211530                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     45588097                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        45588097                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     20514029                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       20514029                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      66102126                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         66102126                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     66102126                       # number of overall hits
-system.cpu.dcache.overall_hits::total        66102126                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          935                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           935                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data         1702                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         1702                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data         2637                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           2637                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         2637                       # number of overall misses
-system.cpu.dcache.overall_misses::total          2637                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     62763567                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     62763567                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    113907163                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    113907163                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    176670730                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    176670730                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    176670730                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    176670730                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     45589032                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     45589032                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           34                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           67                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3          427                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         1393                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.473145                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         132294203                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        132294203                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     45629460                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        45629460                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     20514040                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       20514040                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      66143500                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         66143500                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     66143500                       # number of overall hits
+system.cpu.dcache.overall_hits::total        66143500                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          913                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           913                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data         1691                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         1691                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data         2604                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           2604                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         2604                       # number of overall misses
+system.cpu.dcache.overall_misses::total          2604                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     59632801                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     59632801                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    113805150                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    113805150                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    173437951                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    173437951                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    173437951                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    173437951                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     45630373                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     45630373                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     20515731                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     20515731                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     66104763                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     66104763                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     66104763                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     66104763                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000021                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.000021                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000083                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.000083                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.000040                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.000040                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.000040                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.000040                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67126.809626                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 67126.809626                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66925.477673                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 66925.477673                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 66996.863860                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 66996.863860                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 66996.863860                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 66996.863860                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs          308                       # number of cycles access was blocked
+system.cpu.dcache.demand_accesses::cpu.data     66146104                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     66146104                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     66146104                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     66146104                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000020                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.000020                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000082                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.000082                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.000039                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.000039                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.000039                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.000039                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 65315.225630                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 65315.225630                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67300.502661                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 67300.502661                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 66604.435868                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 66604.435868                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 66604.435868                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 66604.435868                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs          319                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 4                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs           77                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    79.750000                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks           13                       # number of writebacks
-system.cpu.dcache.writebacks::total                13                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          468                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          468                       # number of ReadReq MSHR hits
+system.cpu.dcache.writebacks::writebacks           15                       # number of writebacks
+system.cpu.dcache.writebacks::total                15                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          455                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          455                       # number of ReadReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::cpu.data            1                       # number of WriteReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::total            1                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          469                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          469                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          469                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          469                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data          467                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          467                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1701                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total         1701                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data         2168                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total         2168                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data         2168                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total         2168                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     33590500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     33590500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    109769587                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    109769587                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    143360087                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    143360087                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    143360087                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    143360087                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_hits::cpu.data          456                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          456                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          456                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          456                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          458                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          458                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1690                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         1690                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data         2148                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         2148                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data         2148                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         2148                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     33615250                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     33615250                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    109709600                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    109709600                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    143324850                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    143324850                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    143324850                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    143324850                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000010                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000010                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000083                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000083                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000033                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.000033                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000033                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.000033                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71928.265525                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71928.265525                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64532.385068                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64532.385068                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66125.501384                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 66125.501384                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66125.501384                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 66125.501384                       # average overall mshr miss latency
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000082                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000082                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000032                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.000032                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000032                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.000032                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73395.742358                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73395.742358                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64916.923077                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64916.923077                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66724.790503                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 66724.790503                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66724.790503                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 66724.790503                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 14efebcaaa3cdb2906d82447e5d3083575f1bf50..85845c2fe0d040d8c10044a292fe54ee442d3c49 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.960910                       # Number of seconds simulated
-sim_ticks                                1960909874500                       # Number of ticks simulated
-final_tick                               1960909874500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.961814                       # Number of seconds simulated
+sim_ticks                                1961813569500                       # Number of ticks simulated
+final_tick                               1961813569500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1305982                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1305981                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            42027651646                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 309852                       # Number of bytes of host memory used
-host_seconds                                    46.66                       # Real time elapsed on the host
-sim_insts                                    60933947                       # Number of instructions simulated
-sim_ops                                      60933947                       # Number of ops (including micro ops) simulated
+host_inst_rate                                1769979                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1769979                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            57024152249                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 311592                       # Number of bytes of host memory used
+host_seconds                                    34.40                       # Real time elapsed on the host
+sim_insts                                    60892925                       # Number of instructions simulated
+sim_ops                                      60892925                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu0.inst           833472                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         24887104                       # Number of bytes read from this memory
-system.physmem.bytes_read::tsunami.ide        2650688                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst            31680                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data           338304                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             28741248                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       833472                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst        31680                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          865152                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7743680                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7743680                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst             13023                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            388861                       # Number of read requests responded to by this memory
-system.physmem.num_reads::tsunami.ide           41417                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst               495                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data              5286                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                449082                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          120995                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               120995                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst              425044                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            12691610                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide           1351764                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               16156                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              172524                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                14657098                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         425044                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          16156                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             441199                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3949024                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3949024                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3949024                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             425044                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           12691610                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide          1351764                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              16156                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             172524                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               18606122                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        449082                       # Number of read requests accepted
-system.physmem.writeReqs                       120995                       # Number of write requests accepted
-system.physmem.readBursts                      449082                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     120995                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 28737664                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      3584                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7742592                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  28741248                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7743680                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                       56                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu0.inst           833088                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         24884096                       # Number of bytes read from this memory
+system.physmem.bytes_read::tsunami.ide        2650880                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst            31936                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data           337152                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             28737152                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       833088                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst        31936                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          865024                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7735232                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7735232                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst             13017                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            388814                       # Number of read requests responded to by this memory
+system.physmem.num_reads::tsunami.ide           41420                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst               499                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data              5268                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                449018                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          120863                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               120863                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst              424652                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data            12684231                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide           1351240                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               16279                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              171857                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                14648258                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         424652                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          16279                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             440931                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3942899                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                3942899                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3942899                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             424652                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           12684231                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide          1351240                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              16279                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             171857                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               18591157                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        449018                       # Number of read requests accepted
+system.physmem.writeReqs                       120863                       # Number of write requests accepted
+system.physmem.readBursts                      449018                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     120863                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 28729600                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      7552                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7733952                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  28737152                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7735232                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      118                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           7094                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               28167                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               28459                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               28057                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               27664                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               27762                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               27793                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               28259                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               27872                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               28083                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               27730                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              27672                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              28135                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              28179                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              28505                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              28654                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              28035                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                7928                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7868                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                7543                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                7157                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7275                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7314                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                7747                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                7251                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7322                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                7110                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7099                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               7523                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7681                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8141                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               8335                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7684                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs           6983                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               28166                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               28350                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               28054                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               27500                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               27615                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               27605                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               28127                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               27851                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               28176                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               27723                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              27750                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              28018                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              28330                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              28694                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              28891                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              28050                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                7929                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7797                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                7545                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                7029                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7135                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7129                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                7643                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                7252                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7395                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                7084                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7104                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               7401                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7833                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8315                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               8551                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7701                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          11                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1960902862500                       # Total gap between requests
+system.physmem.numWrRetry                          12                       # Number of times write queue was full causing retry
+system.physmem.totGap                    1961806557500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  449082                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  449018                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 120995                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    409890                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     10611                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      5423                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      2684                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      2293                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      2304                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      1349                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      1329                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      1317                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      1416                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                     1284                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                     1243                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                     1099                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      987                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      972                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      967                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      966                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                      958                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                      963                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                      962                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        9                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 120863                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    407987                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      1708                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      1544                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      1052                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      1160                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      4326                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      3779                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      3770                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      3964                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                      2524                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                     2113                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                     2058                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                     1914                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                     1871                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                     1569                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                     1543                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                     1513                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                     1527                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                     1719                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                     1248                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                       11                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
@@ -143,456 +143,370 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                      4882                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                      4921                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                      4932                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                      5600                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                      6306                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                      5669                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                      5682                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                      5778                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                      5861                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                      5196                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                     5200                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                     5185                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                     5982                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                     6055                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                     6054                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     6099                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     6134                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5025                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4983                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     4966                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     4953                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     4920                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                      232                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                      193                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                       43                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                       28                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                       22                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                       20                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                       17                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                       15                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                       16                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                       26                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        49380                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      738.726934                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     222.746795                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev    1735.319745                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64-67          17723     35.89%     35.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-131         7354     14.89%     50.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192-195         4892      9.91%     60.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-259         2955      5.98%     66.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320-323         1860      3.77%     70.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-387         1462      2.96%     73.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448-451         1143      2.31%     75.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-515          851      1.72%     77.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576-579          746      1.51%     78.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-643          676      1.37%     80.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704-707          661      1.34%     81.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-771          443      0.90%     82.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832-835          337      0.68%     83.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-899          276      0.56%     83.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960-963          300      0.61%     84.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1027          399      0.81%     85.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088-1091          192      0.39%     85.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152-1155          178      0.36%     85.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216-1219          196      0.40%     86.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280-1283          170      0.34%     86.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344-1347          202      0.41%     87.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408-1411          873      1.77%     88.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472-1475          184      0.37%     89.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536-1539          168      0.34%     89.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600-1603           96      0.19%     89.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664-1667           82      0.17%     89.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1728-1731          107      0.22%     90.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1792-1795           72      0.15%     90.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856-1859           81      0.16%     90.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1920-1923           51      0.10%     90.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984-1987           64      0.13%     90.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2048-2051           84      0.17%     90.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112-2115           51      0.10%     90.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2176-2179           54      0.11%     91.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2240-2243           70      0.14%     91.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2304-2307           45      0.09%     91.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2368-2371           72      0.15%     91.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2432-2435           49      0.10%     91.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2496-2499           40      0.08%     91.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2560-2563           72      0.15%     91.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2624-2627           42      0.09%     91.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2688-2691           45      0.09%     91.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2752-2755           69      0.14%     92.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2816-2819           44      0.09%     92.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2880-2883           64      0.13%     92.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2944-2947           43      0.09%     92.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3008-3011           42      0.09%     92.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3072-3075           76      0.15%     92.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3136-3139           39      0.08%     92.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3200-3203           46      0.09%     92.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3264-3267           67      0.14%     92.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3328-3331           46      0.09%     93.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3392-3395           66      0.13%     93.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3456-3459           46      0.09%     93.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3520-3523           37      0.07%     93.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3584-3587           72      0.15%     93.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3648-3651           38      0.08%     93.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3712-3715           42      0.09%     93.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3776-3779           69      0.14%     93.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3840-3843           43      0.09%     93.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3904-3907           64      0.13%     94.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3968-3971           42      0.09%     94.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4032-4035           41      0.08%     94.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4096-4099           74      0.15%     94.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4160-4163           37      0.07%     94.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4224-4227           43      0.09%     94.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4288-4291           66      0.13%     94.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4352-4355           46      0.09%     94.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4416-4419           64      0.13%     94.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4480-4483           43      0.09%     94.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4544-4547           37      0.07%     95.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4608-4611          404      0.82%     95.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4672-4675           34      0.07%     95.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4736-4739           44      0.09%     96.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4800-4803           36      0.07%     96.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4864-4867           44      0.09%     96.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4928-4931           34      0.07%     96.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4992-4995           44      0.09%     96.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5056-5059           33      0.07%     96.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5120-5123           41      0.08%     96.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5184-5187           51      0.10%     96.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5248-5251           44      0.09%     96.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5312-5315           32      0.06%     96.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5376-5379           40      0.08%     96.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5440-5443           37      0.07%     96.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5504-5507           43      0.09%     96.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5568-5571           35      0.07%     97.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5632-5635           40      0.08%     97.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5696-5699           33      0.07%     97.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5760-5763           47      0.10%     97.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5824-5827           34      0.07%     97.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5888-5891           43      0.09%     97.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5952-5955           35      0.07%     97.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6016-6019           44      0.09%     97.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6080-6083           34      0.07%     97.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6144-6147           44      0.09%     97.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6208-6211           38      0.08%     97.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6272-6275           42      0.09%     97.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6336-6339           35      0.07%     97.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6400-6403           43      0.09%     98.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6464-6467           32      0.06%     98.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6528-6531           40      0.08%     98.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6592-6595           37      0.07%     98.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6656-6659           41      0.08%     98.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6720-6723           32      0.06%     98.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6784-6787          431      0.87%     99.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6912-6915            1      0.00%     99.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7040-7043            1      0.00%     99.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7104-7107            1      0.00%     99.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7168-7171           10      0.02%     99.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7232-7235            1      0.00%     99.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7296-7299            1      0.00%     99.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7488-7491            1      0.00%     99.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7552-7555            1      0.00%     99.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7616-7619            3      0.01%     99.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7808-7811            1      0.00%     99.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7872-7875            1      0.00%     99.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7936-7939            2      0.00%     99.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8000-8003            1      0.00%     99.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8128-8131            1      0.00%     99.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8192-8195            8      0.02%     99.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8384-8387            2      0.00%     99.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8448-8451            2      0.00%     99.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8576-8579            1      0.00%     99.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8768-8771            2      0.00%     99.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8832-8835            1      0.00%     99.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8896-8899            1      0.00%     99.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8960-8963            1      0.00%     99.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9088-9091            3      0.01%     99.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9152-9155            1      0.00%     99.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9216-9219            1      0.00%     99.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9280-9283            1      0.00%     99.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9344-9347            1      0.00%     99.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9472-9475            1      0.00%     99.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9600-9603            1      0.00%     99.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9856-9859            1      0.00%     99.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10368-10371            1      0.00%     99.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10688-10691            1      0.00%     99.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10752-10755            1      0.00%     99.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10880-10883            3      0.01%     99.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10944-10947            1      0.00%     99.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11136-11139            2      0.00%     99.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11520-11523            2      0.00%     99.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11776-11779            1      0.00%     99.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11840-11843            2      0.00%     99.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11904-11907            1      0.00%     99.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12032-12035            1      0.00%     99.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12288-12291            2      0.00%     99.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12352-12355            3      0.01%     99.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12416-12419            1      0.00%     99.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12608-12611            1      0.00%     99.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12672-12675            3      0.01%     99.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12800-12803            1      0.00%     99.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13056-13059            2      0.00%     99.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13120-13123            1      0.00%     99.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13248-13251            1      0.00%     99.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13312-13315            1      0.00%     99.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13376-13379            2      0.00%     99.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13440-13443            1      0.00%     99.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13504-13507            1      0.00%     99.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13696-13699            3      0.01%     99.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14016-14019            1      0.00%     99.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14208-14211            3      0.01%     99.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14272-14275            2      0.00%     99.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14336-14339            1      0.00%     99.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14592-14595            1      0.00%     99.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14656-14659            2      0.00%     99.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14912-14915            2      0.00%     99.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15040-15043            1      0.00%     99.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15104-15107            3      0.01%     99.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15168-15171            1      0.00%     99.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15232-15235            2      0.00%     99.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15296-15299            1      0.00%     99.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15360-15363           36      0.07%     99.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15424-15427            1      0.00%     99.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15488-15491            2      0.00%     99.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15616-15619            1      0.00%     99.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16000-16003            1      0.00%     99.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16064-16067            1      0.00%     99.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16384-16387          180      0.36%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          49380                       # Bytes accessed per row activation
-system.physmem.totQLat                     6346588750                       # Total ticks spent queuing
-system.physmem.totMemAccLat               14721193750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2245130000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                  6129475000                       # Total ticks spent accessing banks
-system.physmem.avgQLat                       14134.12                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    13650.60                       # Average bank access latency per DRAM burst
+system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     1574                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     1864                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     2356                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     4659                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     4706                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     4719                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     4730                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     4812                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     4815                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     4859                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     6368                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     5252                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     5405                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     6934                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     5634                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     5860                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     5888                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     5671                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     1159                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                     1116                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                     1056                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                     1045                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                     1090                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                     1047                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                     1031                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                     1187                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                     1318                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                     1508                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                     1614                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                     1739                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                     1832                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                     1868                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                     1782                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                     1877                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                     1859                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                     1827                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                     1847                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                     1717                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                     1501                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                     1291                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      876                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      631                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      437                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                      293                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       71                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       45                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       25                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       23                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       30                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        48187                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      641.951066                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     418.430190                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     422.843508                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127           8213     17.04%     17.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         7073     14.68%     31.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         2891      6.00%     37.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         1720      3.57%     41.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         1328      2.76%     44.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          906      1.88%     45.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          669      1.39%     47.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          536      1.11%     48.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        24851     51.57%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          48187                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6896                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        65.095418                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     2542.617511                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-8191           6893     99.96%     99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::40960-49151            1      0.01%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::57344-65535            1      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::196608-204799            1      0.01%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            6896                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6896                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.523637                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.253710                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        3.981541                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               4466     64.76%     64.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                342      4.96%     69.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                377      5.47%     75.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19               1323     19.19%     94.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                 32      0.46%     94.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 16      0.23%     95.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 12      0.17%     95.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 22      0.32%     95.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                 43      0.62%     96.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                 30      0.44%     96.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                 27      0.39%     97.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27                 32      0.46%     97.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28                 29      0.42%     97.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29                 31      0.45%     98.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30                  6      0.09%     98.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::31                  8      0.12%     98.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32                 10      0.15%     98.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::33                  3      0.04%     98.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::34                  4      0.06%     98.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::35                  4      0.06%     98.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::37                  3      0.04%     98.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::38                  3      0.04%     98.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::39                  5      0.07%     99.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40                  3      0.04%     99.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::41                  2      0.03%     99.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::42                  2      0.03%     99.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::43                  3      0.04%     99.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::45                  3      0.04%     99.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::46                  6      0.09%     99.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::47                 12      0.17%     99.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48                  5      0.07%     99.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::49                  7      0.10%     99.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::50                  4      0.06%     99.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::51                  3      0.04%     99.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52                  5      0.07%     99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::53                  6      0.09%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::55                  1      0.01%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56                  2      0.03%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::57                  1      0.01%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::58                  3      0.04%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6896                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     7845433250                       # Total ticks spent queuing
+system.physmem.totMemAccLat               16453873250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2244500000                       # Total ticks spent in databus transfers
+system.physmem.totBankLat                  6363940000                       # Total ticks spent accessing banks
+system.physmem.avgQLat                       17477.02                       # Average queueing delay per DRAM burst
+system.physmem.avgBankLat                    14176.74                       # Average bank access latency per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  32784.72                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          14.66                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           3.95                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       14.66                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        3.95                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  36653.76                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          14.64                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           3.94                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       14.65                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        3.94                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.15                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.11                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         0.01                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        10.65                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     424775                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     95849                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   94.60                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  79.22                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3439715.80                       # Average gap between requests
-system.physmem.pageHitRate                      91.33                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               0.53                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                     18666756                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq              292805                       # Transaction distribution
-system.membus.trans_dist::ReadResp             292805                       # Transaction distribution
-system.membus.trans_dist::WriteReq              14109                       # Transaction distribution
-system.membus.trans_dist::WriteResp             14109                       # Transaction distribution
-system.membus.trans_dist::Writeback            120995                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            16488                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq          11559                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            7097                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            164894                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           164048                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        42616                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       931055                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total       973671                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124663                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       124663                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1098334                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave        82290                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     31176960                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::total     31259250                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      5307968                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::total      5307968                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            36567218                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus               36567218                       # Total data (bytes)
-system.membus.snoop_data_through_bus            36608                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy            43251000                       # Layer occupancy (ticks)
+system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        26.52                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     403422                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     97436                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   89.87                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  80.62                       # Row buffer hit rate for writes
+system.physmem.avgGap                      3442484.58                       # Average gap between requests
+system.physmem.pageHitRate                      87.91                       # Row buffer hit rate, read and write combined
+system.physmem.prechargeAllPercent               0.55                       # Percentage of time for which DRAM has all the banks in precharge state
+system.membus.throughput                     18651494                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq              292756                       # Transaction distribution
+system.membus.trans_dist::ReadResp             292756                       # Transaction distribution
+system.membus.trans_dist::WriteReq              14067                       # Transaction distribution
+system.membus.trans_dist::WriteResp             14067                       # Transaction distribution
+system.membus.trans_dist::Writeback            120863                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            16150                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq          11271                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            6986                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            164854                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           164030                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave        42532                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       930030                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total       972562                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124666                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       124666                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1097228                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave        81954                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     31164224                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::total     31246178                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      5308160                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::total      5308160                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total            36554338                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               36554338                       # Total data (bytes)
+system.membus.snoop_data_through_bus            36416                       # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy            43154000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy          1579578000                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy          1578633000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         3830990646                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         3834132000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
-system.membus.respLayer2.occupancy          376315500                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy          376702000                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.l2c.tags.replacements                   342160                       # number of replacements
-system.l2c.tags.tagsinuse                65219.945305                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    2443226                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   407347                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     5.997899                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle               8615385750                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   55312.026017                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     4807.093964                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     4897.564051                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst      159.017352                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data       44.243921                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.843995                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.073350                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.074731                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.002426                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.000675                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.995177                       # Average percentage of cache occupancy
+system.l2c.tags.replacements                   342098                       # number of replacements
+system.l2c.tags.tagsinuse                65220.106735                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    2445213                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   407285                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     6.003690                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle               8658635750                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks   55273.758884                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     4807.212496                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     4935.163888                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst      160.761256                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data       43.210211                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.843411                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.073352                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.075305                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.002453                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.000659                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.995180                       # Average percentage of cache occupancy
 system.l2c.tags.occ_task_id_blocks::1024        65187                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1024::0          117                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          761                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         5186                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         7242                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        51881                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          784                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         5254                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         7171                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        51861                       # Occupied blocks per task id
 system.l2c.tags.occ_task_id_percent::1024     0.994675                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 25932224                       # Number of tag accesses
-system.l2c.tags.data_accesses                25932224                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.inst             684719                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             664525                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             317383                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data             107430                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1774057                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          791641                       # number of Writeback hits
-system.l2c.Writeback_hits::total               791641                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data             180                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data             539                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                 719                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data            38                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data            21                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total                59                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           129054                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            42974                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               172028                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.inst              684719                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              793579                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              317383                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              150404                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1946085                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst             684719                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             793579                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             317383                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             150404                       # number of overall hits
-system.l2c.overall_hits::total                1946085                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.inst            13026                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data           271672                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst              503                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data              242                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total               285443                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data          2949                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data          1793                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              4742                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data          919                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data          927                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total            1846                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data         117950                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data           5055                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             123005                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.inst             13026                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            389622                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst               503                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data              5297                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                408448                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst            13026                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           389622                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst              503                       # number of overall misses
-system.l2c.overall_misses::cpu1.data             5297                       # number of overall misses
-system.l2c.overall_misses::total               408448                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.inst    997409492                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data  17552881248                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst     35450000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data     19470500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total    18605211240                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0.data      1291954                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data     10252557                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total     11544511                       # number of UpgradeReq miss cycles
+system.l2c.tags.tag_accesses                 25954090                       # Number of tag accesses
+system.l2c.tags.data_accesses                25954090                       # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.inst             690864                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data             668298                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst             311515                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data             104210                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1774887                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          792911                       # number of Writeback hits
+system.l2c.Writeback_hits::total               792911                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data             184                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data             529                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                 713                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data            40                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data            24                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total                64                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data           130516                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            42247                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               172763                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.inst              690864                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              798814                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              311515                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              146457                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 1947650                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.inst             690864                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             798814                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             311515                       # number of overall hits
+system.l2c.overall_hits::cpu1.data             146457                       # number of overall hits
+system.l2c.overall_hits::total                1947650                       # number of overall hits
+system.l2c.ReadReq_misses::cpu0.inst            13020                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data           271630                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst              507                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data              237                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total               285394                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data          2952                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data          1737                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              4689                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data          888                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data          909                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total            1797                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data         117936                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data           5042                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             122978                       # number of ReadExReq misses
+system.l2c.demand_misses::cpu0.inst             13020                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data            389566                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst               507                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data              5279                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                408372                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.inst            13020                       # number of overall misses
+system.l2c.overall_misses::cpu0.data           389566                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst              507                       # number of overall misses
+system.l2c.overall_misses::cpu1.data             5279                       # number of overall misses
+system.l2c.overall_misses::total               408372                       # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu0.inst    958908741                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.data  17698605243                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst     37880750                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data     17386000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total    18712780734                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu0.data      1103962                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data      9942571                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total     11046533                       # number of UpgradeReq miss cycles
 system.l2c.SCUpgradeReq_miss_latency::cpu0.data       835964                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data       163493                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total       999457                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data   8264985252                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data    387201489                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   8652186741                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.inst    997409492                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data  25817866500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst     35450000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data    406671989                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total     27257397981                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.inst    997409492                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data  25817866500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst     35450000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data    406671989                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    27257397981                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.inst         697745                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data         936197                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst         317886                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data         107672                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2059500                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       791641                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           791641                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data         3129                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data         2332                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            5461                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data          957                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data          948                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total          1905                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       247004                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data        48029                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           295033                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst          697745                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data         1183201                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          317886                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          155701                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2354533                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         697745                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data        1183201                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         317886                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         155701                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2354533                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.018669                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.290187                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.001582                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.002248                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.138598                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.942474                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.768868                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.868339                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.960293                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.977848                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.969029                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.477523                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.105249                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.416919                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.018669                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.329295                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.001582                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.034020                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.173473                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.018669                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.329295                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.001582                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.034020                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.173473                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 76570.665745                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 64610.564386                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 70477.137177                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 80456.611570                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 65180.127871                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   438.099017                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  5718.102064                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  2434.523619                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data   909.645267                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data   176.367853                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total   541.417660                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 70071.939398                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 76597.722849                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 70340.122280                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 76570.665745                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 66263.882686                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 70477.137177                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 76774.020955                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 66734.071365                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 76570.665745                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 66263.882686                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 70477.137177                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 76774.020955                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 66734.071365                       # average overall miss latency
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data       161993                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total       997957                       # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data   8071982510                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data    364247989                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   8436230499                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu0.inst    958908741                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data  25770587753                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst     37880750                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data    381633989                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total     27149011233                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.inst    958908741                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data  25770587753                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst     37880750                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data    381633989                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total    27149011233                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.inst         703884                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data         939928                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst         312022                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data         104447                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            2060281                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       792911                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           792911                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data         3136                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data         2266                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            5402                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data          928                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data          933                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total          1861                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       248452                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data        47289                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           295741                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.inst          703884                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data         1188380                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          312022                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data          151736                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             2356022                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         703884                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data        1188380                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         312022                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data         151736                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            2356022                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.018497                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.288990                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst      0.001625                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data      0.002269                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.138522                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.941327                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.766549                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.868012                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.956897                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.974277                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.965610                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.474683                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.106621                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.415830                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.018497                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.327813                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.001625                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.034791                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.173331                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.018497                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.327813                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.001625                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.034791                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.173331                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu0.inst 73648.904839                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.data 65157.034359                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 74715.483235                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 73358.649789                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 65568.234560                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   373.970867                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  5723.990213                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  2355.839838                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data   941.400901                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data   178.210121                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total   555.346132                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 68443.753476                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 72242.758628                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 68599.509660                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 73648.904839                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 66152.045489                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 74715.483235                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 72292.856412                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 66481.079097                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 73648.904839                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 66152.045489                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 74715.483235                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 72292.856412                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 66481.079097                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -601,8 +515,8 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               79475                       # number of writebacks
-system.l2c.writebacks::total                    79475                       # number of writebacks
+system.l2c.writebacks::writebacks               79343                       # number of writebacks
+system.l2c.writebacks::total                    79343                       # number of writebacks
 system.l2c.ReadReq_mshr_hits::cpu0.inst             3                       # number of ReadReq MSHR hits
 system.l2c.ReadReq_mshr_hits::cpu1.inst             8                       # number of ReadReq MSHR hits
 system.l2c.ReadReq_mshr_hits::total                11                       # number of ReadReq MSHR hits
@@ -612,111 +526,111 @@ system.l2c.demand_mshr_hits::total                 11                       # nu
 system.l2c.overall_mshr_hits::cpu0.inst             3                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::cpu1.inst             8                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::total                11                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu0.inst        13023                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.data       271672                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst          495                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data          242                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total          285432                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data         2949                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data         1793                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total         4742                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          919                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          927                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total         1846                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data       117950                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data         5055                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        123005                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst        13023                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data       389622                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst          495                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data         5297                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           408437                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst        13023                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data       389622                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst          495                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data         5297                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          408437                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    831386758                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.data  14156096752                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst     28603000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data     16450000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total  15032536510                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     29642946                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     17939793                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total     47582739                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      9190919                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      9270927                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total     18461846                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   6783022748                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    323366011                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   7106388759                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst    831386758                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data  20939119500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst     28603000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data    339816011                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total  22138925269                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst    831386758                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data  20939119500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst     28603000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data    339816011                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  22138925269                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   1373164500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data     17619000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total   1390783500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2154378500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    679235000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   2833613500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   3527543000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data    696854000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   4224397000                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.018664                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.290187                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.001557                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.002248                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.138593                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.942474                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.768868                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.868339                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.960293                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.977848                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.969029                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.477523                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.105249                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.416919                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.018664                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.329295                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.001557                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.034020                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.173468                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.018664                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.329295                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.001557                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.034020                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.173468                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 63839.880058                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52107.308637                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 57783.838384                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 67975.206612                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 52665.911706                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10051.863683                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10005.461796                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10034.318642                       # average UpgradeReq mshr miss latency
+system.l2c.ReadReq_mshr_misses::cpu0.inst        13017                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.data       271630                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.inst          499                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.data          237                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total          285383                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data         2952                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data         1737                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total         4689                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          888                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          909                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total         1797                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data       117936                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data         5042                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        122978                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst        13017                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data       389566                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst          499                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data         5279                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           408361                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst        13017                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data       389566                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst          499                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data         5279                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          408361                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    793128009                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.data  14302134757                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst     30990750                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data     14431500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total  15140685016                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     29678448                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     17371737                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total     47050185                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      8880888                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      9090909                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total     17971797                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   6590771990                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    300610511                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   6891382501                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst    793128009                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data  20892906747                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst     30990750                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data    315042011                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  22032067517                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst    793128009                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data  20892906747                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst     30990750                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data    315042011                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  22032067517                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   1373162000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data     17619500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   1390781500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   2149958500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    674822000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   2824780500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   3523120500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data    692441500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   4215562000                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.018493                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.288990                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.001599                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.002269                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.138517                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.941327                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.766549                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.868012                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.956897                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.974277                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.965610                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.474683                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.106621                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.415830                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.018493                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.327813                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.001599                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.034791                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.173326                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.018493                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.327813                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.001599                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.034791                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.173326                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60930.168933                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52653.001351                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62105.711423                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 60892.405063                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 53053.913569                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10053.674797                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data        10001                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10034.161868                       # average UpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        10001                       # average SCUpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        10001                       # average SCUpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        10001                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 57507.611259                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 63969.537290                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 57773.169863                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 63839.880058                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53742.138534                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 57783.838384                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 64152.541250                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 54204.014986                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 63839.880058                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53742.138534                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 57783.838384                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 64152.541250                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 54204.014986                       # average overall mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 55884.310050                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59621.283419                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 56037.522980                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60930.168933                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53631.237703                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62105.711423                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59678.350256                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 53952.428163                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60930.168933                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53631.237703                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62105.711423                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59678.350256                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 53952.428163                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -728,14 +642,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf
 system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.iocache.tags.replacements                41694                       # number of replacements
-system.iocache.tags.tagsinuse                0.570482                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                0.569649                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                41710                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1754531382000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     0.570482                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.035655                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.035655                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         1755503918000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide     0.569649                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide     0.035603                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.035603                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -749,14 +663,14 @@ system.iocache.demand_misses::tsunami.ide        41726                       # n
 system.iocache.demand_misses::total             41726                       # number of demand (read+write) misses
 system.iocache.overall_misses::tsunami.ide        41726                       # number of overall misses
 system.iocache.overall_misses::total            41726                       # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide     21249133                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     21249133                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::tsunami.ide  12966402814                       # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total  12966402814                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide  12987651947                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total  12987651947                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide  12987651947                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total  12987651947                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::tsunami.ide     21248883                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     21248883                       # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::tsunami.ide  13129991411                       # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total  13129991411                       # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide  13151240294                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total  13151240294                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide  13151240294                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total  13151240294                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::tsunami.ide          174                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            174                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
@@ -773,19 +687,19 @@ system.iocache.demand_miss_rate::tsunami.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122121.454023                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 122121.454023                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::tsunami.ide 312052.435839                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 312052.435839                       # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 311260.411901                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 311260.411901                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 311260.411901                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 311260.411901                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs        401197                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122120.017241                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 122120.017241                       # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::tsunami.ide 315989.396684                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 315989.396684                       # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 315180.949384                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 315180.949384                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 315180.949384                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 315180.949384                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs        388544                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                28980                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                28481                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs    13.843927                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs    13.642218                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -799,14 +713,14 @@ system.iocache.demand_mshr_misses::tsunami.ide        41726
 system.iocache.demand_mshr_misses::total        41726                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::tsunami.ide        41726                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total        41726                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12200133                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     12200133                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::tsunami.ide  10804136814                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total  10804136814                       # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide  10816336947                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total  10816336947                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide  10816336947                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total  10816336947                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12199883                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     12199883                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::tsunami.ide  10966952411                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total  10966952411                       # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide  10979152294                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total  10979152294                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide  10979152294                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total  10979152294                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
@@ -815,14 +729,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70115.706897                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 70115.706897                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 260014.844388                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 260014.844388                       # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 259222.953243                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 259222.953243                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 259222.953243                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 259222.953243                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70114.270115                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 70114.270115                       # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 263933.202036                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 263933.202036                       # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 263124.965106                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 263124.965106                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 263124.965106                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 263124.965106                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -840,22 +754,22 @@ system.cpu0.dtb.fetch_hits                          0                       # IT
 system.cpu0.dtb.fetch_misses                        0                       # ITB misses
 system.cpu0.dtb.fetch_acv                           0                       # ITB acv
 system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu0.dtb.read_hits                     7532654                       # DTB read hits
-system.cpu0.dtb.read_misses                      7812                       # DTB read misses
+system.cpu0.dtb.read_hits                     7562587                       # DTB read hits
+system.cpu0.dtb.read_misses                      7765                       # DTB read misses
 system.cpu0.dtb.read_acv                          210                       # DTB read access violations
-system.cpu0.dtb.read_accesses                  524694                       # DTB read accesses
-system.cpu0.dtb.write_hits                    5120278                       # DTB write hits
-system.cpu0.dtb.write_misses                      919                       # DTB write misses
-system.cpu0.dtb.write_acv                         139                       # DTB write access violations
-system.cpu0.dtb.write_accesses                 202960                       # DTB write accesses
-system.cpu0.dtb.data_hits                    12652932                       # DTB hits
-system.cpu0.dtb.data_misses                      8731                       # DTB misses
-system.cpu0.dtb.data_acv                          349                       # DTB access violations
-system.cpu0.dtb.data_accesses                  727654                       # DTB accesses
-system.cpu0.itb.fetch_hits                    3655515                       # ITB hits
-system.cpu0.itb.fetch_misses                     4023                       # ITB misses
+system.cpu0.dtb.read_accesses                  524069                       # DTB read accesses
+system.cpu0.dtb.write_hits                    5147352                       # DTB write hits
+system.cpu0.dtb.write_misses                      910                       # DTB write misses
+system.cpu0.dtb.write_acv                         133                       # DTB write access violations
+system.cpu0.dtb.write_accesses                 202595                       # DTB write accesses
+system.cpu0.dtb.data_hits                    12709939                       # DTB hits
+system.cpu0.dtb.data_misses                      8675                       # DTB misses
+system.cpu0.dtb.data_acv                          343                       # DTB access violations
+system.cpu0.dtb.data_accesses                  726664                       # DTB accesses
+system.cpu0.itb.fetch_hits                    3660806                       # ITB hits
+system.cpu0.itb.fetch_misses                     3984                       # ITB misses
 system.cpu0.itb.fetch_acv                         184                       # ITB acv
-system.cpu0.itb.fetch_accesses                3659538                       # ITB accesses
+system.cpu0.itb.fetch_accesses                3664790                       # ITB accesses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.read_acv                            0                       # DTB read access violations
@@ -868,56 +782,56 @@ system.cpu0.itb.data_hits                           0                       # DT
 system.cpu0.itb.data_misses                         0                       # DTB misses
 system.cpu0.itb.data_acv                            0                       # DTB access violations
 system.cpu0.itb.data_accesses                       0                       # DTB accesses
-system.cpu0.numCycles                      3921819749                       # number of cpu cycles simulated
+system.cpu0.numCycles                      3923627139                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   47983654                       # Number of instructions committed
-system.cpu0.committedOps                     47983654                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             44515044                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                211401                       # Number of float alu accesses
-system.cpu0.num_func_calls                    1203620                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      5635723                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    44515044                       # number of integer instructions
-system.cpu0.num_fp_insts                       211401                       # number of float instructions
-system.cpu0.num_int_register_reads           61226145                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          33154260                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads              103282                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes             105080                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                     12694028                       # number of memory refs
-system.cpu0.num_load_insts                    7560495                       # Number of load instructions
-system.cpu0.num_store_insts                   5133533                       # Number of store instructions
-system.cpu0.num_idle_cycles              3698209766.998114                       # Number of idle cycles
-system.cpu0.num_busy_cycles              223609982.001886                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.057017                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.942983                       # Percentage of idle cycles
-system.cpu0.Branches                          7227606                       # Number of branches fetched
+system.cpu0.committedInsts                   48127942                       # Number of instructions committed
+system.cpu0.committedOps                     48127942                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses             44644072                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                213646                       # Number of float alu accesses
+system.cpu0.num_func_calls                    1209779                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      5646914                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    44644072                       # number of integer instructions
+system.cpu0.num_fp_insts                       213646                       # number of float instructions
+system.cpu0.num_int_register_reads           61387929                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          33243119                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads              104403                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes             106204                       # number of times the floating registers were written
+system.cpu0.num_mem_refs                     12751056                       # number of memory refs
+system.cpu0.num_load_insts                    7590434                       # Number of load instructions
+system.cpu0.num_store_insts                   5160622                       # Number of store instructions
+system.cpu0.num_idle_cycles              3699531471.998114                       # Number of idle cycles
+system.cpu0.num_busy_cycles              224095667.001886                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.057114                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.942886                       # Percentage of idle cycles
+system.cpu0.Branches                          7246727                       # Number of branches fetched
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    6813                       # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei                    165343                       # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0                   56789     40.24%     40.24% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::21                    131      0.09%     40.33% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::22                   1973      1.40%     41.73% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::30                    435      0.31%     42.04% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31                  81806     57.96%    100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total              141134                       # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0                    56279     49.08%     49.08% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.inst.quiesce                    6803                       # number of quiesce instructions executed
+system.cpu0.kern.inst.hwrei                    166332                       # number of hwrei instructions executed
+system.cpu0.kern.ipl_count::0                   57240     40.25%     40.25% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::21                    131      0.09%     40.34% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::22                   1974      1.39%     41.73% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::30                    424      0.30%     42.03% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31                  82451     57.97%    100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total              142220                       # number of times we switched to this ipl
+system.cpu0.kern.ipl_good::0                    56707     49.09%     49.09% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good::21                     131      0.11%     49.20% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22                    1973      1.72%     50.92% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::30                     435      0.38%     51.30% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31                   55844     48.70%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total               114662                       # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0            1901501471500     96.97%     96.97% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21               95150500      0.00%     96.98% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22              767153500      0.04%     97.01% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::30              322241000      0.02%     97.03% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31            58223100500      2.97%    100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total        1960909117000                       # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0                 0.991019                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_good::22                    1974      1.71%     50.91% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::30                     424      0.37%     51.28% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::31                   56283     48.72%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::total               115519                       # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks::0            1902164041000     96.96%     96.96% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21               95225000      0.00%     96.96% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22              767277500      0.04%     97.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::30              314374500      0.02%     97.02% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31            58471894000      2.98%    100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total        1961812812000                       # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used::0                 0.990688                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31                0.682639                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total             0.812434                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::31                0.682624                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::total             0.812256                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.syscall::2                         8      3.42%      3.42% # number of syscalls executed
 system.cpu0.kern.syscall::3                        20      8.55%     11.97% # number of syscalls executed
 system.cpu0.kern.syscall::4                         4      1.71%     13.68% # number of syscalls executed
@@ -949,37 +863,37 @@ system.cpu0.kern.syscall::144                       2      0.85%     99.15% # nu
 system.cpu0.kern.syscall::147                       2      0.85%    100.00% # number of syscalls executed
 system.cpu0.kern.syscall::total                   234                       # number of syscalls executed
 system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
-system.cpu0.kern.callpal::wripir                  517      0.35%      0.35% # number of callpals executed
-system.cpu0.kern.callpal::wrmces                    1      0.00%      0.35% # number of callpals executed
-system.cpu0.kern.callpal::wrfen                     1      0.00%      0.35% # number of callpals executed
-system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.35% # number of callpals executed
-system.cpu0.kern.callpal::swpctx                 3090      2.07%      2.42% # number of callpals executed
-system.cpu0.kern.callpal::tbi                      52      0.03%      2.45% # number of callpals executed
-system.cpu0.kern.callpal::wrent                     7      0.00%      2.45% # number of callpals executed
-system.cpu0.kern.callpal::swpipl               134176     89.74%     92.20% # number of callpals executed
-system.cpu0.kern.callpal::rdps                   6700      4.48%     96.68% # number of callpals executed
-system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.68% # number of callpals executed
-system.cpu0.kern.callpal::wrusp                     4      0.00%     96.68% # number of callpals executed
-system.cpu0.kern.callpal::rdusp                     9      0.01%     96.69% # number of callpals executed
-system.cpu0.kern.callpal::whami                     2      0.00%     96.69% # number of callpals executed
-system.cpu0.kern.callpal::rti                    4418      2.95%     99.64% # number of callpals executed
-system.cpu0.kern.callpal::callsys                 396      0.26%     99.91% # number of callpals executed
+system.cpu0.kern.callpal::wripir                  506      0.34%      0.34% # number of callpals executed
+system.cpu0.kern.callpal::wrmces                    1      0.00%      0.34% # number of callpals executed
+system.cpu0.kern.callpal::wrfen                     1      0.00%      0.34% # number of callpals executed
+system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.34% # number of callpals executed
+system.cpu0.kern.callpal::swpctx                 3107      2.06%      2.40% # number of callpals executed
+system.cpu0.kern.callpal::tbi                      51      0.03%      2.44% # number of callpals executed
+system.cpu0.kern.callpal::wrent                     7      0.00%      2.44% # number of callpals executed
+system.cpu0.kern.callpal::swpipl               135267     89.81%     92.25% # number of callpals executed
+system.cpu0.kern.callpal::rdps                   6701      4.45%     96.70% # number of callpals executed
+system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.70% # number of callpals executed
+system.cpu0.kern.callpal::wrusp                     4      0.00%     96.70% # number of callpals executed
+system.cpu0.kern.callpal::rdusp                     9      0.01%     96.71% # number of callpals executed
+system.cpu0.kern.callpal::whami                     2      0.00%     96.71% # number of callpals executed
+system.cpu0.kern.callpal::rti                    4423      2.94%     99.65% # number of callpals executed
+system.cpu0.kern.callpal::callsys                 394      0.26%     99.91% # number of callpals executed
 system.cpu0.kern.callpal::imb                     139      0.09%    100.00% # number of callpals executed
-system.cpu0.kern.callpal::total                149515                       # number of callpals executed
-system.cpu0.kern.mode_switch::kernel             7023                       # number of protection mode switches
-system.cpu0.kern.mode_switch::user               1378                       # number of protection mode switches
+system.cpu0.kern.callpal::total                150615                       # number of callpals executed
+system.cpu0.kern.mode_switch::kernel             7022                       # number of protection mode switches
+system.cpu0.kern.mode_switch::user               1372                       # number of protection mode switches
 system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
-system.cpu0.kern.mode_good::kernel               1377                      
-system.cpu0.kern.mode_good::user                 1378                      
+system.cpu0.kern.mode_good::kernel               1371                      
+system.cpu0.kern.mode_good::user                 1372                      
 system.cpu0.kern.mode_good::idle                    0                      
-system.cpu0.kern.mode_switch_good::kernel     0.196070                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::kernel     0.195244                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total     0.327937                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel      1957102433500     99.81%     99.81% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user          3806679000      0.19%    100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_switch_good::total     0.326781                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel      1958041026500     99.81%     99.81% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user          3771781000      0.19%    100.00% # number of ticks spent at the given mode
 system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context                    3091                       # number of times the context was actually changed
+system.cpu0.kern.swap_context                    3108                       # number of times the context was actually changed
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
 system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
@@ -1011,47 +925,47 @@ system.tsunami.ethernet.totalRxOrn                  0                       # to
 system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
 system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.toL2Bus.throughput                   103937669                       # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq            2101927                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2101912                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq             14109                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp            14109                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           791641                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           16698                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq         11618                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          28316                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           338479                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          296929                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1395511                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      3121357                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       635773                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side       463473                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               5616114                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     44655680                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    119473096                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     20344704                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     16974250                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size::total          201447730                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus             201437426                       # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus         2374976                       # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy         4790041400                       # Layer occupancy (ticks)
+system.toL2Bus.throughput                   103965077                       # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq            2102306                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2102291                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq             14067                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp            14067                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           792911                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           16363                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq         11335                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp          27698                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           339143                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          297593                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side      1407788                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      3134857                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       624045                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side       452421                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               5619111                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     45048576                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side    120057312                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     19969408                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     16548674                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size::total          201623970                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus             201613666                       # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus         2346432                       # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy         4795947858                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.2                       # Layer utilization (%)
 system.toL2Bus.snoopLayer0.occupancy           724500                       # Layer occupancy (ticks)
 system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        3142512505                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        3170057255                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             0.2                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        5519878863                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy        5536383084                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.3                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy        1430590492                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy        1404201241                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy         794307231                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy         776393157                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
-system.iobus.throughput                       1399302                       # Throughput (bytes/s)
+system.iobus.throughput                       1398487                       # Throughput (bytes/s)
 system.iobus.trans_dist::ReadReq                 7373                       # Transaction distribution
 system.iobus.trans_dist::ReadResp                7373                       # Transaction distribution
-system.iobus.trans_dist::WriteReq               55661                       # Transaction distribution
-system.iobus.trans_dist::WriteResp              55661                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio        14006                       # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::WriteReq               55619                       # Transaction distribution
+system.iobus.trans_dist::WriteResp              55619                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio        13922                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio          480                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
@@ -1063,11 +977,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf          180                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total        42616                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total        42532                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83452                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.tsunami.ide.dma::total        83452                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  126068                       # Packet count per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio        56024                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                  125984                       # Packet count per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio        55688                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio         1920                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
@@ -1079,12 +993,12 @@ system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf          299                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total        82290                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::total        81954                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661616                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.tsunami.ide.dma::total      2661616                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total              2743906                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus                 2743906                       # Total data (bytes)
-system.iobus.reqLayer0.occupancy             13361000                       # Layer occupancy (ticks)
+system.iobus.tot_pkt_size::total              2743570                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus                 2743570                       # Total data (bytes)
+system.iobus.reqLayer0.occupancy             13277000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy               359000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
@@ -1106,67 +1020,67 @@ system.iobus.reqLayer27.occupancy               76000                       # La
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy              110000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer29.occupancy           377744447                       # Layer occupancy (ticks)
+system.iobus.reqLayer29.occupancy           380082294                       # Layer occupancy (ticks)
 system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer30.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer30.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy            28507000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy            28465000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            42681500                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            43185000                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.cpu0.icache.tags.replacements           697136                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          508.398756                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           47294969                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           697648                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            67.792023                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      40091069250                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   508.398756                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.992966                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.992966                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements           703274                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          508.380970                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           47433057                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           703786                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            67.396989                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      40278267250                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   508.380970                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.992932                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.992932                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::0           54                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          447                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::3           10                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          444                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::3           13                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         48690501                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        48690501                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     47294969                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       47294969                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     47294969                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        47294969                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     47294969                       # number of overall hits
-system.cpu0.icache.overall_hits::total       47294969                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       697766                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       697766                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       697766                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        697766                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       697766                       # number of overall misses
-system.cpu0.icache.overall_misses::total       697766                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   9984385005                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total   9984385005                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst   9984385005                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total   9984385005                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst   9984385005                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total   9984385005                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     47992735                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     47992735                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     47992735                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     47992735                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     47992735                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     47992735                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014539                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.014539                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014539                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.014539                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014539                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.014539                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14309.073536                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 14309.073536                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14309.073536                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 14309.073536                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14309.073536                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 14309.073536                       # average overall miss latency
+system.cpu0.icache.tags.tag_accesses         48840865                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        48840865                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     47433057                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       47433057                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     47433057                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        47433057                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     47433057                       # number of overall hits
+system.cpu0.icache.overall_hits::total       47433057                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       703904                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       703904                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       703904                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        703904                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       703904                       # number of overall misses
+system.cpu0.icache.overall_misses::total       703904                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  10025783755                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  10025783755                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  10025783755                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  10025783755                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  10025783755                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  10025783755                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     48136961                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     48136961                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     48136961                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     48136961                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     48136961                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     48136961                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014623                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.014623                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014623                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.014623                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014623                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.014623                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14243.112349                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 14243.112349                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14243.112349                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 14243.112349                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14243.112349                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 14243.112349                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1175,119 +1089,119 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       697766                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       697766                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       697766                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       697766                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       697766                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       697766                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   8583721995                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total   8583721995                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   8583721995                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total   8583721995                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   8583721995                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total   8583721995                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.014539                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.014539                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.014539                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.014539                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.014539                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.014539                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12301.720054                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12301.720054                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12301.720054                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12301.720054                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12301.720054                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12301.720054                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       703904                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       703904                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       703904                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       703904                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       703904                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       703904                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   8612997245                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total   8612997245                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   8612997245                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total   8612997245                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   8612997245                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total   8612997245                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.014623                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.014623                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.014623                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.014623                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.014623                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.014623                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12236.039638                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12236.039638                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12236.039638                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12236.039638                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12236.039638                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12236.039638                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements          1186229                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          505.271614                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           11460994                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs          1186741                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs             9.657536                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle        107902250                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   505.271614                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.986859                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.986859                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.replacements          1191290                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          505.228160                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           11513399                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          1191802                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs             9.660496                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle        108508250                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   505.228160                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.986774                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.986774                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::0          125                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::1          318                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::2           69                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         51851796                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        51851796                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data      6451735                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        6451735                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      4706856                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       4706856                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       140512                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       140512                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       148003                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       148003                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     11158591                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        11158591                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     11158591                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       11158591                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       939483                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       939483                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       256736                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       256736                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        13633                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        13633                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data         5600                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total         5600                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      1196219                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       1196219                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      1196219                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      1196219                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  27076055500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  27076055500                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  10459807694                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  10459807694                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    148332750                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    148332750                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     43345419                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total     43345419                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  37535863194                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  37535863194                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  37535863194                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  37535863194                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      7391218                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      7391218                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      4963592                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      4963592                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       154145                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       154145                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       153603                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       153603                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     12354810                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     12354810                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     12354810                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     12354810                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.127108                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.127108                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.051724                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.051724                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.088443                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.088443                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.036458                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.036458                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.096822                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.096822                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.096822                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.096822                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28820.165453                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 28820.165453                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40741.492015                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 40741.492015                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10880.418837                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10880.418837                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  7740.253393                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  7740.253393                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31378.755223                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 31378.755223                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31378.755223                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 31378.755223                       # average overall miss latency
+system.cpu0.dcache.tags.tag_accesses         52084916                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        52084916                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data      6477391                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        6477391                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      4731575                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       4731575                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       141550                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       141550                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       149263                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       149263                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     11208966                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        11208966                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     11208966                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       11208966                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       942691                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       942691                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       258024                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       258024                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        13717                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        13717                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data         5452                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total         5452                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      1200715                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       1200715                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      1200715                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      1200715                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  27259981257                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  27259981257                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  10282729939                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  10282729939                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    150891500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    150891500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     41989388                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total     41989388                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  37542711196                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  37542711196                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  37542711196                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  37542711196                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      7420082                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      7420082                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      4989599                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      4989599                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       155267                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       155267                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       154715                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       154715                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     12409681                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     12409681                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     12409681                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     12409681                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.127046                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.127046                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.051712                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.051712                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.088345                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.088345                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.035239                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.035239                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.096756                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.096756                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.096756                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.096756                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28917.196894                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 28917.196894                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39851.835252                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 39851.835252                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11000.328060                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11000.328060                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  7701.648569                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  7701.648569                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31266.962765                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 31266.962765                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31266.962765                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 31266.962765                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1296,66 +1210,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       682519                       # number of writebacks
-system.cpu0.dcache.writebacks::total           682519                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       939483                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       939483                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       256736                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       256736                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        13633                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total        13633                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         5600                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total         5600                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      1196219                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      1196219                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      1196219                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      1196219                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  25065202500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  25065202500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   9891526306                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   9891526306                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    121052250                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    121052250                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     32145581                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     32145581                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data         1000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total         1000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  34956728806                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  34956728806                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  34956728806                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  34956728806                       # number of overall MSHR miss cycles
+system.cpu0.dcache.writebacks::writebacks       686471                       # number of writebacks
+system.cpu0.dcache.writebacks::total           686471                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       942691                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       942691                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       258024                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       258024                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        13717                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total        13717                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         5452                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total         5452                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      1200715                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      1200715                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      1200715                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      1200715                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  25249299743                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  25249299743                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   9714288061                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   9714288061                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    123443500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    123443500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     31083612                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     31083612                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  34963587804                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  34963587804                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  34963587804                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  34963587804                       # number of overall MSHR miss cycles
 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   1465602000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   1465602000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2284723500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2284723500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3750325500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   3750325500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.127108                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.127108                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.051724                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.051724                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.088443                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.088443                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.036458                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.036458                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.096822                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.096822                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.096822                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.096822                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26679.782923                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26679.782923                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 38528.006614                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 38528.006614                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data  8879.355241                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8879.355241                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  5740.282321                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  5740.282321                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29222.683142                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29222.683142                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29222.683142                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29222.683142                       # average overall mshr miss latency
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2280051500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2280051500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3745653500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   3745653500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.127046                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.127046                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.051712                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.051712                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.088345                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.088345                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.035239                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.035239                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.096756                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.096756                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.096756                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.096756                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26784.280048                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26784.280048                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37648.777094                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37648.777094                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data  8999.307429                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8999.307429                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  5701.322817                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  5701.322817                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29118.973115                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29118.973115                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29118.973115                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29118.973115                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1367,22 +1277,22 @@ system.cpu1.dtb.fetch_hits                          0                       # IT
 system.cpu1.dtb.fetch_misses                        0                       # ITB misses
 system.cpu1.dtb.fetch_acv                           0                       # ITB acv
 system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu1.dtb.read_hits                     2383442                       # DTB read hits
+system.cpu1.dtb.read_hits                     2348422                       # DTB read hits
 system.cpu1.dtb.read_misses                      2620                       # DTB read misses
 system.cpu1.dtb.read_acv                            0                       # DTB read access violations
 system.cpu1.dtb.read_accesses                  205337                       # DTB read accesses
-system.cpu1.dtb.write_hits                    1706844                       # DTB write hits
+system.cpu1.dtb.write_hits                    1677006                       # DTB write hits
 system.cpu1.dtb.write_misses                      235                       # DTB write misses
 system.cpu1.dtb.write_acv                          24                       # DTB write access violations
 system.cpu1.dtb.write_accesses                  89739                       # DTB write accesses
-system.cpu1.dtb.data_hits                     4090286                       # DTB hits
+system.cpu1.dtb.data_hits                     4025428                       # DTB hits
 system.cpu1.dtb.data_misses                      2855                       # DTB misses
 system.cpu1.dtb.data_acv                           24                       # DTB access violations
 system.cpu1.dtb.data_accesses                  295076                       # DTB accesses
-system.cpu1.itb.fetch_hits                    1814139                       # ITB hits
+system.cpu1.itb.fetch_hits                    1801062                       # ITB hits
 system.cpu1.itb.fetch_misses                     1064                       # ITB misses
 system.cpu1.itb.fetch_acv                           0                       # ITB acv
-system.cpu1.itb.fetch_accesses                1815203                       # ITB accesses
+system.cpu1.itb.fetch_accesses                1802126                       # ITB accesses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.read_acv                            0                       # DTB read access violations
@@ -1395,52 +1305,52 @@ system.cpu1.itb.data_hits                           0                       # DT
 system.cpu1.itb.data_misses                         0                       # DTB misses
 system.cpu1.itb.data_acv                            0                       # DTB access violations
 system.cpu1.itb.data_accesses                       0                       # DTB accesses
-system.cpu1.numCycles                      3919927793                       # number of cpu cycles simulated
+system.cpu1.numCycles                      3921881188                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   12950293                       # Number of instructions committed
-system.cpu1.committedOps                     12950293                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             11929999                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                174217                       # Number of float alu accesses
-system.cpu1.num_func_calls                     410658                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      1281658                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    11929999                       # number of integer instructions
-system.cpu1.num_fp_insts                       174217                       # number of float instructions
-system.cpu1.num_int_register_reads           16394755                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes           8774296                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads               90513                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes              92474                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                      4113222                       # number of memory refs
-system.cpu1.num_load_insts                    2397194                       # Number of load instructions
-system.cpu1.num_store_insts                   1716028                       # Number of store instructions
-system.cpu1.num_idle_cycles              3870487590.349789                       # Number of idle cycles
-system.cpu1.num_busy_cycles              49440202.650211                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.012613                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.987387                       # Percentage of idle cycles
-system.cpu1.Branches                          1846576                       # Number of branches fetched
+system.cpu1.committedInsts                   12764983                       # Number of instructions committed
+system.cpu1.committedOps                     12764983                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             11763372                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                170364                       # Number of float alu accesses
+system.cpu1.num_func_calls                     404056                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      1265589                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    11763372                       # number of integer instructions
+system.cpu1.num_fp_insts                       170364                       # number of float instructions
+system.cpu1.num_int_register_reads           16177579                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes           8656447                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads               88600                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes              90534                       # number of times the floating registers were written
+system.cpu1.num_mem_refs                      4047975                       # number of memory refs
+system.cpu1.num_load_insts                    2361944                       # Number of load instructions
+system.cpu1.num_store_insts                   1686031                       # Number of store instructions
+system.cpu1.num_idle_cycles              3873256564.808130                       # Number of idle cycles
+system.cpu1.num_busy_cycles              48624623.191870                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.012398                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.987602                       # Percentage of idle cycles
+system.cpu1.Branches                          1821589                       # Number of branches fetched
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    2744                       # number of quiesce instructions executed
-system.cpu1.kern.inst.hwrei                     78268                       # number of hwrei instructions executed
-system.cpu1.kern.ipl_count::0                   26619     38.27%     38.27% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::22                   1969      2.83%     41.10% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::30                    517      0.74%     41.84% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::31                  40454     58.16%    100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::total               69559                       # number of times we switched to this ipl
-system.cpu1.kern.ipl_good::0                    25752     48.16%     48.16% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::22                    1969      3.68%     51.84% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::30                     517      0.97%     52.81% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::31                   25236     47.19%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::total                53474                       # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0            1908686801000     97.38%     97.38% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22              700508000      0.04%     97.42% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30              362068000      0.02%     97.44% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31            50214489500      2.56%    100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total        1959963866500                       # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used::0                 0.967429                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.inst.quiesce                    2741                       # number of quiesce instructions executed
+system.cpu1.kern.inst.hwrei                     77081                       # number of hwrei instructions executed
+system.cpu1.kern.ipl_count::0                   26132     38.19%     38.19% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::22                   1969      2.88%     41.07% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::30                    506      0.74%     41.81% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::31                  39821     58.19%    100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::total               68428                       # number of times we switched to this ipl
+system.cpu1.kern.ipl_good::0                    25288     48.13%     48.13% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::22                    1969      3.75%     51.87% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::30                     506      0.96%     52.84% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::31                   24782     47.16%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::total                52545                       # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks::0            1909614205500     97.38%     97.38% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::22              700881500      0.04%     97.42% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::30              353850000      0.02%     97.44% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::31            50271627000      2.56%    100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total        1960940564000                       # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used::0                 0.967702                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::31                0.623820                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::total             0.768757                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::31                0.622335                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::total             0.767887                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.syscall::3                        10     10.87%     10.87% # number of syscalls executed
 system.cpu1.kern.syscall::6                         9      9.78%     20.65% # number of syscalls executed
 system.cpu1.kern.syscall::15                        1      1.09%     21.74% # number of syscalls executed
@@ -1456,87 +1366,87 @@ system.cpu1.kern.syscall::74                        9      9.78%     96.74% # nu
 system.cpu1.kern.syscall::132                       3      3.26%    100.00% # number of syscalls executed
 system.cpu1.kern.syscall::total                    92                       # number of syscalls executed
 system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
-system.cpu1.kern.callpal::wripir                  435      0.61%      0.61% # number of callpals executed
-system.cpu1.kern.callpal::wrmces                    1      0.00%      0.61% # number of callpals executed
-system.cpu1.kern.callpal::wrfen                     1      0.00%      0.61% # number of callpals executed
-system.cpu1.kern.callpal::swpctx                 2001      2.79%      3.40% # number of callpals executed
-system.cpu1.kern.callpal::tbi                       3      0.00%      3.40% # number of callpals executed
-system.cpu1.kern.callpal::wrent                     7      0.01%      3.41% # number of callpals executed
-system.cpu1.kern.callpal::swpipl                63355     88.19%     91.60% # number of callpals executed
-system.cpu1.kern.callpal::rdps                   2145      2.99%     94.59% # number of callpals executed
-system.cpu1.kern.callpal::wrkgp                     1      0.00%     94.59% # number of callpals executed
-system.cpu1.kern.callpal::wrusp                     3      0.00%     94.59% # number of callpals executed
-system.cpu1.kern.callpal::whami                     3      0.00%     94.60% # number of callpals executed
-system.cpu1.kern.callpal::rti                    3718      5.18%     99.77% # number of callpals executed
+system.cpu1.kern.callpal::wripir                  424      0.60%      0.60% # number of callpals executed
+system.cpu1.kern.callpal::wrmces                    1      0.00%      0.60% # number of callpals executed
+system.cpu1.kern.callpal::wrfen                     1      0.00%      0.60% # number of callpals executed
+system.cpu1.kern.callpal::swpctx                 1955      2.77%      3.37% # number of callpals executed
+system.cpu1.kern.callpal::tbi                       3      0.00%      3.38% # number of callpals executed
+system.cpu1.kern.callpal::wrent                     7      0.01%      3.39% # number of callpals executed
+system.cpu1.kern.callpal::swpipl                62267     88.12%     91.51% # number of callpals executed
+system.cpu1.kern.callpal::rdps                   2146      3.04%     94.54% # number of callpals executed
+system.cpu1.kern.callpal::wrkgp                     1      0.00%     94.54% # number of callpals executed
+system.cpu1.kern.callpal::wrusp                     3      0.00%     94.55% # number of callpals executed
+system.cpu1.kern.callpal::whami                     3      0.00%     94.55% # number of callpals executed
+system.cpu1.kern.callpal::rti                    3685      5.22%     99.77% # number of callpals executed
 system.cpu1.kern.callpal::callsys                 121      0.17%     99.94% # number of callpals executed
 system.cpu1.kern.callpal::imb                      42      0.06%    100.00% # number of callpals executed
 system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
-system.cpu1.kern.callpal::total                 71838                       # number of callpals executed
-system.cpu1.kern.mode_switch::kernel             1956                       # number of protection mode switches
+system.cpu1.kern.callpal::total                 70661                       # number of callpals executed
+system.cpu1.kern.mode_switch::kernel             1917                       # number of protection mode switches
 system.cpu1.kern.mode_switch::user                368                       # number of protection mode switches
-system.cpu1.kern.mode_switch::idle               2906                       # number of protection mode switches
-system.cpu1.kern.mode_good::kernel                809                      
+system.cpu1.kern.mode_switch::idle               2889                       # number of protection mode switches
+system.cpu1.kern.mode_good::kernel                798                      
 system.cpu1.kern.mode_good::user                  368                      
-system.cpu1.kern.mode_good::idle                  441                      
-system.cpu1.kern.mode_switch_good::kernel     0.413599                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_good::idle                  430                      
+system.cpu1.kern.mode_switch_good::kernel     0.416275                       # fraction of useful protection mode switches
 system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::idle      0.151755                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::total     0.309369                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel       17986814000      0.92%      0.92% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user          1484472500      0.08%      0.99% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle        1939632240000     99.01%    100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context                    2002                       # number of times the context was actually changed
-system.cpu1.icache.tags.replacements           317336                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          446.450379                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs           12635285                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs           317847                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            39.752727                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle     1958987590000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   446.450379                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.871973                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.871973                       # Average percentage of cache occupancy
+system.cpu1.kern.mode_switch_good::idle      0.148840                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good::total     0.308465                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_ticks::kernel       17543884000      0.90%      0.90% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::user          1484004500      0.08%      0.97% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::idle        1941017048000     99.03%    100.00% # number of ticks spent at the given mode
+system.cpu1.kern.swap_context                    1956                       # number of times the context was actually changed
+system.cpu1.icache.tags.replacements           311472                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          449.263709                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs           12455839                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs           311983                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            39.924736                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle     1960006992500                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   449.263709                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.877468                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.877468                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2           72                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::3          439                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2           74                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::3          437                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses         13271059                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses        13271059                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst     12635285                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total       12635285                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst     12635285                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total        12635285                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst     12635285                       # number of overall hits
-system.cpu1.icache.overall_hits::total       12635285                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       317887                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       317887                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       317887                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        317887                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       317887                       # number of overall misses
-system.cpu1.icache.overall_misses::total       317887                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   4180819492                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   4180819492                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   4180819492                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   4180819492                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   4180819492                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   4180819492                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst     12953172                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total     12953172                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst     12953172                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total     12953172                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst     12953172                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total     12953172                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.024541                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.024541                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.024541                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.024541                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.024541                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.024541                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13151.904582                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 13151.904582                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13151.904582                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 13151.904582                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13151.904582                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 13151.904582                       # average overall miss latency
+system.cpu1.icache.tags.tag_accesses         13079885                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses        13079885                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst     12455839                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total       12455839                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst     12455839                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total        12455839                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst     12455839                       # number of overall hits
+system.cpu1.icache.overall_hits::total       12455839                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       312023                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       312023                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       312023                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        312023                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       312023                       # number of overall misses
+system.cpu1.icache.overall_misses::total       312023                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   4106650741                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   4106650741                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   4106650741                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   4106650741                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   4106650741                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   4106650741                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst     12767862                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total     12767862                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst     12767862                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total     12767862                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst     12767862                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total     12767862                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.024438                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.024438                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.024438                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.024438                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.024438                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.024438                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13161.371889                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 13161.371889                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13161.371889                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 13161.371889                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13161.371889                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 13161.371889                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1545,118 +1455,118 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       317887                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       317887                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       317887                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       317887                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       317887                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       317887                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   3544847508                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   3544847508                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   3544847508                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   3544847508                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   3544847508                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   3544847508                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.024541                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.024541                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.024541                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.024541                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.024541                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.024541                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11151.281770                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11151.281770                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11151.281770                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 11151.281770                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11151.281770                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 11151.281770                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       312023                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       312023                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       312023                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       312023                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       312023                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       312023                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   3482409259                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   3482409259                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   3482409259                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   3482409259                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   3482409259                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   3482409259                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.024438                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.024438                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.024438                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.024438                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.024438                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.024438                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11160.745391                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11160.745391                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11160.745391                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 11160.745391                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11160.745391                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 11160.745391                       # average overall mshr miss latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.tags.replacements           158764                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          485.752776                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs            3916687                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs           159090                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            24.619316                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle      67802253000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   485.752776                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.948736                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.948736                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          326                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2           31                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::3          295                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.636719                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses         16587420                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses        16587420                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data      2220669                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        2220669                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      1595283                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       1595283                       # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        48031                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        48031                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        50613                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        50613                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data      3815952                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total         3815952                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data      3815952                       # number of overall hits
-system.cpu1.dcache.overall_hits::total        3815952                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       116704                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       116704                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data        56889                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total        56889                       # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         9081                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total         9081                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data         6019                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total         6019                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       173593                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        173593                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       173593                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       173593                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   1411486000                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   1411486000                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   1044020804                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total   1044020804                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     82357000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total     82357000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     44184927                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total     44184927                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data   2455506804                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total   2455506804                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data   2455506804                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total   2455506804                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      2337373                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      2337373                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      1652172                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      1652172                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        57112                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        57112                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        56632                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        56632                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data      3989545                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total      3989545                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data      3989545                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total      3989545                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.049930                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.049930                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.034433                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.034433                       # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.159003                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.159003                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.106283                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.106283                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.043512                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.043512                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.043512                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.043512                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12094.581163                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 12094.581163                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18351.892352                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 18351.892352                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  9069.155379                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  9069.155379                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  7340.908290                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  7340.908290                       # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14145.194818                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 14145.194818                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14145.194818                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 14145.194818                       # average overall miss latency
+system.cpu1.dcache.tags.replacements           155135                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          486.308895                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs            3855441                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs           155464                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            24.799574                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle     1048852146500                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   486.308895                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.949822                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.949822                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          329                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2           32                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::3          297                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.642578                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses         16322717                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        16322717                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data      2189668                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        2189668                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      1567568                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       1567568                       # number of WriteReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        46969                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        46969                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        49480                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        49480                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data      3757236                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total         3757236                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data      3757236                       # number of overall hits
+system.cpu1.dcache.overall_hits::total        3757236                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       113735                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       113735                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data        55930                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total        55930                       # number of WriteReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         8863                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total         8863                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data         5883                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total         5883                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data       169665                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        169665                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       169665                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       169665                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   1371834000                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   1371834000                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   1009197248                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total   1009197248                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     80472000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total     80472000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     43306909                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total     43306909                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data   2381031248                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total   2381031248                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data   2381031248                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total   2381031248                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      2303403                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      2303403                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      1623498                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      1623498                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        55832                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        55832                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        55363                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        55363                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data      3926901                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total      3926901                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data      3926901                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total      3926901                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.049377                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.049377                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.034450                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.034450                       # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.158744                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.158744                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.106262                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.106262                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.043206                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.043206                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.043206                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.043206                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12061.669671                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 12061.669671                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18043.934347                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 18043.934347                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  9079.544172                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  9079.544172                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  7361.364780                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  7361.364780                       # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14033.720850                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 14033.720850                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14033.720850                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 14033.720850                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1665,62 +1575,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks       109122                       # number of writebacks
-system.cpu1.dcache.writebacks::total           109122                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       116704                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total       116704                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        56889                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total        56889                       # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         9081                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total         9081                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data         6019                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total         6019                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       173593                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       173593                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       173593                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       173593                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1178000000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1178000000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data    927938196                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total    927938196                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     64195000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     64195000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     32145073                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     32145073                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   2105938196                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   2105938196                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   2105938196                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   2105938196                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     18776000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     18776000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    718207000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    718207000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    736983000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total    736983000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.049930                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.049930                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.034433                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.034433                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.159003                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.159003                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.106283                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.106283                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.043512                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.043512                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.043512                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.043512                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10093.912805                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10093.912805                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16311.381743                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16311.381743                       # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  7069.155379                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  7069.155379                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  5340.600266                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  5340.600266                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12131.469564                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12131.469564                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12131.469564                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12131.469564                       # average overall mshr miss latency
+system.cpu1.dcache.writebacks::writebacks       106440                       # number of writebacks
+system.cpu1.dcache.writebacks::total           106440                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       113735                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total       113735                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        55930                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total        55930                       # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         8863                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total         8863                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data         5883                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total         5883                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       169665                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       169665                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       169665                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       169665                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1144290000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1144290000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data    895105752                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total    895105752                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     62746000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     62746000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     31539091                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     31539091                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   2039395752                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   2039395752                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   2039395752                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   2039395752                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     18776500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     18776500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    713537000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    713537000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    732313500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total    732313500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.049377                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.049377                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.034450                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.034450                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.158744                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.158744                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.106262                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.106262                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.043206                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.043206                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.043206                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.043206                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10061.019035                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10061.019035                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16004.036331                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16004.036331                       # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  7079.544172                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  7079.544172                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  5361.055754                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  5361.055754                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12020.132331                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12020.132331                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12020.132331                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12020.132331                       # average overall mshr miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
index 1efa023f67a10ab049e0261c479fbd77ad914950..5b0dc7b9948122828ad710e01864486f75eac742 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.920428                       # Number of seconds simulated
-sim_ticks                                1920428041000                       # Number of ticks simulated
-final_tick                               1920428041000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.920416                       # Number of seconds simulated
+sim_ticks                                1920416181000                       # Number of ticks simulated
+final_tick                               1920416181000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1405906                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1405905                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            48056353161                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 307800                       # Number of bytes of host memory used
-host_seconds                                    39.96                       # Real time elapsed on the host
-sim_insts                                    56182750                       # Number of instructions simulated
-sim_ops                                      56182750                       # Number of ops (including micro ops) simulated
+host_inst_rate                                1752736                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1752735                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            59896862792                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 308520                       # Number of bytes of host memory used
+host_seconds                                    32.06                       # Real time elapsed on the host
+sim_insts                                    56196255                       # Number of instructions simulated
+sim_ops                                      56196255                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            850688                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          24846912                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst            850752                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          24860224                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide        2652352                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             28349952                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       850688                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          850688                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7389824                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7389824                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst              13292                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             388233                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total             28363328                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       850752                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          850752                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7405888                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7405888                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst              13293                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             388441                       # Number of read requests responded to by this memory
 system.physmem.num_reads::tsunami.ide           41443                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                442968                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          115466                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               115466                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               442968                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             12938216                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide           1381125                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                14762309                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          442968                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             442968                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3848009                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3848009                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3848009                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              442968                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            12938216                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide          1381125                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               18610318                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        442968                       # Number of read requests accepted
-system.physmem.writeReqs                       115466                       # Number of write requests accepted
-system.physmem.readBursts                      442968                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     115466                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 28346688                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      3264                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7389440                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  28349952                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7389824                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                       51                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.num_reads::total                443177                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          115717                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               115717                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               443004                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             12945227                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide           1381134                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                14769365                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          443004                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             443004                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3856397                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                3856397                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3856397                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              443004                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            12945227                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide          1381134                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               18625763                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        443177                       # Number of read requests accepted
+system.physmem.writeReqs                       115717                       # Number of write requests accepted
+system.physmem.readBursts                      443177                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     115717                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 28355584                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      7744                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7404416                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  28363328                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7405888                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      121                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs            130                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               27966                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               28089                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               28297                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               28053                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               27407                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               27545                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               26911                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               26762                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               27807                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               27255                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              27714                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              27327                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              27431                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              28073                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              28024                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              28256                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                7722                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7593                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                7833                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                7543                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7010                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                6982                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6469                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                6223                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7224                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                6661                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7099                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6780                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               7009                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               7722                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7773                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7817                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               27851                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               28132                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               28319                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               28010                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               27531                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               27552                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               26732                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               26855                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               27890                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               27110                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              27744                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              27465                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              27482                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              28199                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              28116                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              28068                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                7630                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7636                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                7854                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                7535                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7127                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                6994                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6317                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                6319                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7309                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                6529                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7110                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6915                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               7060                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               7819                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7860                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7680                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                          12                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1920416169000                       # Total gap between requests
+system.physmem.numWrRetry                          11                       # Number of times write queue was full causing retry
+system.physmem.totGap                    1920404309000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  442968                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  443177                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 115466                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    403787                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     10503                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      5396                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      2702                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      2330                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      2324                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      1381                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      1352                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      1335                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      1436                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                     1304                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                     1247                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                     1080                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      967                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      965                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      961                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      958                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                      953                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                      964                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                      963                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                        9                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 115717                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    402196                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      1714                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      1586                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      1056                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      1122                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      4268                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      3790                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      3793                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      3969                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                      2575                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                     2119                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                     2033                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                     1897                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                     1793                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                     1556                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                     1515                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                     1524                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                     1560                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                     1710                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                     1268                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                       12                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
@@ -133,289 +133,205 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                      4636                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                      4662                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                      4672                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                      5362                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                      6093                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                      5438                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                      5429                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                      5533                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                      5593                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                      4916                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                     4913                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                     4899                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                     5734                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                     5836                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                     5819                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     5861                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     5900                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4775                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4734                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     4717                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     4698                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     4676                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                      213                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                      175                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                       49                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                       26                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                       21                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                       17                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                       16                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                       15                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                       16                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                       22                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        46254                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      772.575777                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     229.901205                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev    1785.674907                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64-67          16351     35.35%     35.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-131         6669     14.42%     49.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192-195         4598      9.94%     59.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-259         2705      5.85%     65.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320-323         1760      3.81%     69.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-387         1480      3.20%     72.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448-451         1070      2.31%     74.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-515          848      1.83%     76.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576-579          733      1.58%     78.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-643          614      1.33%     79.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704-707          629      1.36%     80.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-771          417      0.90%     81.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832-835          327      0.71%     82.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-899          305      0.66%     83.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960-963          281      0.61%     83.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1027          335      0.72%     84.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088-1091          208      0.45%     85.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152-1155          173      0.37%     85.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216-1219          157      0.34%     85.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280-1283          138      0.30%     86.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344-1347          163      0.35%     86.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408-1411          903      1.95%     88.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472-1475          167      0.36%     88.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536-1539           98      0.21%     88.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600-1603          103      0.22%     89.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664-1667           86      0.19%     89.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1728-1731           86      0.19%     89.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1792-1795           55      0.12%     89.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856-1859           76      0.16%     89.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1920-1923           70      0.15%     89.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984-1987           69      0.15%     90.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2048-2051           49      0.11%     90.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112-2115           76      0.16%     90.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2176-2179           62      0.13%     90.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2240-2243           63      0.14%     90.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2304-2307           35      0.08%     90.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2368-2371           62      0.13%     90.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2432-2435           58      0.13%     90.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2496-2499           65      0.14%     91.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2560-2563           35      0.08%     91.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2624-2627           74      0.16%     91.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2688-2691           59      0.13%     91.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2752-2755           59      0.13%     91.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2816-2819           26      0.06%     91.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2880-2883           59      0.13%     91.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2944-2947           60      0.13%     91.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3008-3011           63      0.14%     92.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3072-3075           34      0.07%     92.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3136-3139           64      0.14%     92.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3200-3203           58      0.13%     92.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3264-3267           54      0.12%     92.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3328-3331           33      0.07%     92.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3392-3395           54      0.12%     92.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3456-3459           58      0.13%     92.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3520-3523           64      0.14%     92.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3584-3587           34      0.07%     93.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3648-3651           65      0.14%     93.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3712-3715           57      0.12%     93.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3776-3779           56      0.12%     93.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3840-3843           28      0.06%     93.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3904-3907           54      0.12%     93.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3968-3971           53      0.11%     93.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4032-4035           65      0.14%     93.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4096-4099           31      0.07%     93.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4160-4163           67      0.14%     94.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4224-4227           53      0.11%     94.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4288-4291           55      0.12%     94.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4352-4355           27      0.06%     94.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4416-4419           54      0.12%     94.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4480-4483           56      0.12%     94.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4544-4547           66      0.14%     94.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4608-4611          372      0.80%     95.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4672-4675           49      0.11%     95.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4736-4739           28      0.06%     95.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4800-4803           48      0.10%     95.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4864-4867           28      0.06%     95.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4928-4931           51      0.11%     95.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4992-4995           28      0.06%     96.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5056-5059           52      0.11%     96.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5120-5123           28      0.06%     96.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5184-5187           51      0.11%     96.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5248-5251           40      0.09%     96.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5312-5315           53      0.11%     96.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5376-5379           25      0.05%     96.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5440-5443           51      0.11%     96.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5504-5507           26      0.06%     96.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5568-5571           51      0.11%     96.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5632-5635           24      0.05%     96.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5696-5699           50      0.11%     97.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5760-5763           28      0.06%     97.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5824-5827           50      0.11%     97.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5888-5891           26      0.06%     97.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5952-5955           50      0.11%     97.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6016-6019           27      0.06%     97.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6080-6083           51      0.11%     97.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6144-6147           28      0.06%     97.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6208-6211           50      0.11%     97.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6272-6275           26      0.06%     97.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6336-6339           49      0.11%     97.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6400-6403           26      0.06%     97.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6464-6467           52      0.11%     98.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6528-6531           25      0.05%     98.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6592-6595           52      0.11%     98.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6656-6659           25      0.05%     98.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6720-6723           52      0.11%     98.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6784-6787          425      0.92%     99.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7040-7043            1      0.00%     99.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7168-7171           13      0.03%     99.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7232-7235            1      0.00%     99.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7296-7299            1      0.00%     99.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7424-7427            1      0.00%     99.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7680-7683            4      0.01%     99.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7872-7875            1      0.00%     99.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8000-8003            1      0.00%     99.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8064-8067            2      0.00%     99.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8128-8131            1      0.00%     99.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8192-8195            8      0.02%     99.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8256-8259            1      0.00%     99.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8320-8323            1      0.00%     99.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8384-8387            1      0.00%     99.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8512-8515            1      0.00%     99.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8704-8707            3      0.01%     99.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8960-8963            2      0.00%     99.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9152-9155            1      0.00%     99.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9216-9219            5      0.01%     99.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9344-9347            2      0.00%     99.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9536-9539            1      0.00%     99.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9600-9603            1      0.00%     99.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9792-9795            1      0.00%     99.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9856-9859            1      0.00%     99.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9920-9923            1      0.00%     99.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10112-10115            1      0.00%     99.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10176-10179            2      0.00%     99.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10240-10243            1      0.00%     99.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10304-10307            1      0.00%     99.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10624-10627            1      0.00%     99.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10688-10691            1      0.00%     99.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10880-10883            2      0.00%     99.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11072-11075            2      0.00%     99.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11200-11203            1      0.00%     99.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11328-11331            1      0.00%     99.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11392-11395            2      0.00%     99.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11456-11459            2      0.00%     99.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11520-11523            1      0.00%     99.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11584-11587            1      0.00%     99.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11776-11779            1      0.00%     99.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12160-12163            1      0.00%     99.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12224-12227            1      0.00%     99.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12288-12291            3      0.01%     99.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12416-12419            1      0.00%     99.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12672-12675            1      0.00%     99.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13056-13059            3      0.01%     99.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13184-13187            1      0.00%     99.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13248-13251            1      0.00%     99.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13312-13315            1      0.00%     99.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13440-13443            1      0.00%     99.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13504-13507            3      0.01%     99.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13632-13635            1      0.00%     99.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13696-13699            4      0.01%     99.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13760-13763            1      0.00%     99.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13824-13827            1      0.00%     99.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14016-14019            1      0.00%     99.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14208-14211            3      0.01%     99.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14272-14275            1      0.00%     99.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14336-14339            2      0.00%     99.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14656-14659            2      0.00%     99.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14720-14723            1      0.00%     99.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14848-14851            2      0.00%     99.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14976-14979            1      0.00%     99.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15104-15107            1      0.00%     99.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15168-15171            1      0.00%     99.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15296-15299            1      0.00%     99.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15360-15363           35      0.08%     99.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15424-15427            1      0.00%     99.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15552-15555            1      0.00%     99.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15616-15619            2      0.00%     99.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16064-16067            1      0.00%     99.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16192-16195            1      0.00%     99.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16320-16323            1      0.00%     99.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16384-16387          180      0.39%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          46254                       # Bytes accessed per row activation
-system.physmem.totQLat                     6257775000                       # Total ticks spent queuing
-system.physmem.totMemAccLat               14505282500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2214585000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                  6032922500                       # Total ticks spent accessing banks
-system.physmem.avgQLat                       14128.55                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    13620.89                       # Average bank access latency per DRAM burst
+system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     1547                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     1870                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     2302                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     4388                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     4414                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     4425                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     4435                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     4520                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     4492                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     4550                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     6087                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     4874                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     5074                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     6417                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     5284                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     5514                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     5555                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     5389                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     1180                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                     1138                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                     1092                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                     1057                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                     1105                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                     1067                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                     1057                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                     1183                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                     1357                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                     1517                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                     1561                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                     1644                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                     1709                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                     1772                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                     1718                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                     1911                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                     1872                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                     1806                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                     1830                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                     1705                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                     1482                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                     1269                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                      917                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                      667                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                      461                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                      286                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       66                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       49                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                       33                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                       25                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                       29                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        46117                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      658.429646                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     435.074403                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     420.347464                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127           7559     16.39%     16.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         6338     13.74%     30.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         2663      5.77%     35.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         1600      3.47%     39.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         1319      2.86%     42.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          861      1.87%     44.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          594      1.29%     45.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          461      1.00%     46.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        24722     53.61%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          46117                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6598                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        67.149288                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     2598.278449                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-8191           6595     99.95%     99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::40960-49151            1      0.02%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::57344-65535            1      0.02%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::196608-204799            1      0.02%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            6598                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6598                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.534707                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.278859                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        3.820387                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               4179     63.34%     63.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                322      4.88%     68.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                428      6.49%     74.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19               1303     19.75%     94.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                 22      0.33%     94.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 17      0.26%     95.04% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 11      0.17%     95.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 27      0.41%     95.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                 43      0.65%     96.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                 28      0.42%     96.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                 21      0.32%     97.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27                 25      0.38%     97.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28                 19      0.29%     97.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29                 43      0.65%     98.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30                  4      0.06%     98.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::31                 12      0.18%     98.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32                 10      0.15%     98.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::33                  1      0.02%     98.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::34                  5      0.08%     98.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::35                  4      0.06%     98.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36                  4      0.06%     98.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::37                  5      0.08%     99.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::38                  2      0.03%     99.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::39                  9      0.14%     99.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40                  4      0.06%     99.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::41                  4      0.06%     99.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::42                  1      0.02%     99.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::43                  2      0.03%     99.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44                  3      0.05%     99.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::45                  1      0.02%     99.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::46                  1      0.02%     99.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::47                  6      0.09%     99.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48                  8      0.12%     99.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::49                  5      0.08%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::50                  6      0.09%     99.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52                  3      0.05%     99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::53                  1      0.02%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::54                  4      0.06%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::55                  2      0.03%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56                  1      0.02%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::57                  1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::58                  1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6598                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     7790286250                       # Total ticks spent queuing
+system.physmem.totMemAccLat               16274878750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2215280000                       # Total ticks spent in databus transfers
+system.physmem.totBankLat                  6269312500                       # Total ticks spent accessing banks
+system.physmem.avgQLat                       17583.07                       # Average queueing delay per DRAM burst
+system.physmem.avgBankLat                    14150.16                       # Average bank access latency per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  32749.44                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          14.76                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           3.85                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       14.76                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        3.85                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  36733.23                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          14.77                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           3.86                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       14.77                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        3.86                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.15                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.12                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.03                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         0.01                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        14.25                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     419360                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     92763                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   94.68                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  80.34                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3438931.31                       # Average gap between requests
-system.physmem.pageHitRate                      91.72                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               0.52                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                     18651952                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq              292310                       # Transaction distribution
-system.membus.trans_dist::ReadResp             292310                       # Transaction distribution
+system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        24.59                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     398457                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     94179                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   89.93                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  81.39                       # Row buffer hit rate for writes
+system.physmem.avgGap                      3436079.67                       # Average gap between requests
+system.physmem.pageHitRate                      88.16                       # Row buffer hit rate, read and write combined
+system.physmem.prechargeAllPercent               0.57                       # Percentage of time for which DRAM has all the banks in precharge state
+system.membus.throughput                     18667397                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq              292363                       # Transaction distribution
+system.membus.trans_dist::ReadResp             292363                       # Transaction distribution
 system.membus.trans_dist::WriteReq               9650                       # Transaction distribution
 system.membus.trans_dist::WriteResp              9650                       # Transaction distribution
-system.membus.trans_dist::Writeback            115466                       # Transaction distribution
+system.membus.trans_dist::Writeback            115717                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq              132                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp             132                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            158141                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           158141                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            158297                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           158297                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        33160                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       877537                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total       910697                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       878206                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total       911366                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       124680                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total       124680                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1035377                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1036046                       # Packet count per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        44564                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30430656                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     30475220                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     30460096                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     30504660                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      5309120                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.iocache.mem_side::total      5309120                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            35784340                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus               35784340                       # Total data (bytes)
+system.membus.tot_pkt_size::total            35813780                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               35813780                       # Total data (bytes)
 system.membus.snoop_data_through_bus            35392                       # Total snoop data (bytes)
 system.membus.reqLayer0.occupancy            32377500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy          1489694250                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy          1492987250                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         3746415596                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         3752965347                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
-system.membus.respLayer2.occupancy          376299750                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy          376688000                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                41685                       # number of replacements
-system.iocache.tags.tagsinuse                1.352288                       # Cycle average of tags in use
+system.iocache.tags.tagsinuse                1.344147                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
 system.iocache.tags.sampled_refs                41701                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         1753529489000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide     1.352288                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide     0.084518                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.084518                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         1754500427000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide     1.344147                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide     0.084009                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.084009                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
@@ -429,14 +345,14 @@ system.iocache.demand_misses::tsunami.ide        41725                       # n
 system.iocache.demand_misses::total             41725                       # number of demand (read+write) misses
 system.iocache.overall_misses::tsunami.ide        41725                       # number of overall misses
 system.iocache.overall_misses::total            41725                       # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide     21134383                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     21134383                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::tsunami.ide  12989922573                       # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total  12989922573                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide  13011056956                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total  13011056956                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide  13011056956                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total  13011056956                       # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::tsunami.ide     21134633                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     21134633                       # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::tsunami.ide  13148459442                       # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total  13148459442                       # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide  13169594075                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total  13169594075                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide  13169594075                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total  13169594075                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
@@ -453,19 +369,19 @@ system.iocache.demand_miss_rate::tsunami.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122164.063584                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 122164.063584                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::tsunami.ide 312618.467775                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 312618.467775                       # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 311828.806615                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 311828.806615                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 311828.806615                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 311828.806615                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs        403484                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122165.508671                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 122165.508671                       # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::tsunami.ide 316433.852570                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 316433.852570                       # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 315628.378071                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 315628.378071                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 315628.378071                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 315628.378071                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs        393896                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                29141                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                28296                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs    13.845922                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs    13.920554                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -479,14 +395,14 @@ system.iocache.demand_mshr_misses::tsunami.ide        41725
 system.iocache.demand_mshr_misses::total        41725                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::tsunami.ide        41725                       # number of overall MSHR misses
 system.iocache.overall_mshr_misses::total        41725                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12137383                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     12137383                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::tsunami.ide  10827670073                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total  10827670073                       # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide  10839807456                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total  10839807456                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide  10839807456                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total  10839807456                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     12137633                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     12137633                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::tsunami.ide  10985430442                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total  10985430442                       # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide  10997568075                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total  10997568075                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide  10997568075                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total  10997568075                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
@@ -495,14 +411,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70158.283237                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 70158.283237                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 260581.201218                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 260581.201218                       # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 259791.670605                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 259791.670605                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 259791.670605                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 259791.670605                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70159.728324                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 70159.728324                       # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 264377.898585                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 264377.898585                       # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 263572.632115                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 263572.632115                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 263572.632115                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 263572.632115                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -521,22 +437,22 @@ system.cpu.dtb.fetch_hits                           0                       # IT
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                      9064966                       # DTB read hits
-system.cpu.dtb.read_misses                      10312                       # DTB read misses
+system.cpu.dtb.read_hits                      9066711                       # DTB read hits
+system.cpu.dtb.read_misses                      10324                       # DTB read misses
 system.cpu.dtb.read_acv                           210                       # DTB read access violations
-system.cpu.dtb.read_accesses                   728817                       # DTB read accesses
-system.cpu.dtb.write_hits                     6356267                       # DTB write hits
-system.cpu.dtb.write_misses                      1140                       # DTB write misses
+system.cpu.dtb.read_accesses                   728853                       # DTB read accesses
+system.cpu.dtb.write_hits                     6357503                       # DTB write hits
+system.cpu.dtb.write_misses                      1142                       # DTB write misses
 system.cpu.dtb.write_acv                          157                       # DTB write access violations
-system.cpu.dtb.write_accesses                  291929                       # DTB write accesses
-system.cpu.dtb.data_hits                     15421233                       # DTB hits
-system.cpu.dtb.data_misses                      11452                       # DTB misses
+system.cpu.dtb.write_accesses                  291931                       # DTB write accesses
+system.cpu.dtb.data_hits                     15424214                       # DTB hits
+system.cpu.dtb.data_misses                      11466                       # DTB misses
 system.cpu.dtb.data_acv                           367                       # DTB access violations
-system.cpu.dtb.data_accesses                  1020746                       # DTB accesses
-system.cpu.itb.fetch_hits                     4973920                       # ITB hits
-system.cpu.itb.fetch_misses                      4997                       # ITB misses
+system.cpu.dtb.data_accesses                  1020784                       # DTB accesses
+system.cpu.itb.fetch_hits                     4974520                       # ITB hits
+system.cpu.itb.fetch_misses                      5010                       # ITB misses
 system.cpu.itb.fetch_acv                          184                       # ITB acv
-system.cpu.itb.fetch_accesses                 4978917                       # ITB accesses
+system.cpu.itb.fetch_accesses                 4979530                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -549,52 +465,52 @@ system.cpu.itb.data_hits                            0                       # DT
 system.cpu.itb.data_misses                          0                       # DTB misses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.numCycles                       3840856082                       # number of cpu cycles simulated
+system.cpu.numCycles                       3840832362                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                    56182750                       # Number of instructions committed
-system.cpu.committedOps                      56182750                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses              52054772                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                 324326                       # Number of float alu accesses
-system.cpu.num_func_calls                     1483342                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts      6468084                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                     52054772                       # number of integer instructions
-system.cpu.num_fp_insts                        324326                       # number of float instructions
-system.cpu.num_int_register_reads            71321847                       # number of times the integer registers were read
-system.cpu.num_int_register_writes           38521555                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads               163576                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes              166452                       # number of times the floating registers were written
-system.cpu.num_mem_refs                      15473812                       # number of memory refs
-system.cpu.num_load_insts                     9101789                       # Number of load instructions
-system.cpu.num_store_insts                    6372023                       # Number of store instructions
-system.cpu.num_idle_cycles               3588896828.998131                       # Number of idle cycles
-system.cpu.num_busy_cycles               251959253.001869                       # Number of busy cycles
-system.cpu.not_idle_fraction                 0.065600                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.934400                       # Percentage of idle cycles
-system.cpu.Branches                           8421946                       # Number of branches fetched
+system.cpu.committedInsts                    56196255                       # Number of instructions committed
+system.cpu.committedOps                      56196255                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses              52067788                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                 324393                       # Number of float alu accesses
+system.cpu.num_func_calls                     1483738                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts      6469789                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                     52067788                       # number of integer instructions
+system.cpu.num_fp_insts                        324393                       # number of float instructions
+system.cpu.num_int_register_reads            71342399                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           38531411                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads               163609                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes              166486                       # number of times the floating registers were written
+system.cpu.num_mem_refs                      15476821                       # number of memory refs
+system.cpu.num_load_insts                     9103557                       # Number of load instructions
+system.cpu.num_store_insts                    6373264                       # Number of store instructions
+system.cpu.num_idle_cycles               3589010980.998131                       # Number of idle cycles
+system.cpu.num_busy_cycles               251821381.001869                       # Number of busy cycles
+system.cpu.not_idle_fraction                 0.065564                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.934436                       # Percentage of idle cycles
+system.cpu.Branches                           8424076                       # Number of branches fetched
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                     6376                       # number of quiesce instructions executed
-system.cpu.kern.inst.hwrei                     211963                       # number of hwrei instructions executed
-system.cpu.kern.ipl_count::0                    74895     40.89%     40.89% # number of times we switched to this ipl
+system.cpu.kern.inst.quiesce                     6378                       # number of quiesce instructions executed
+system.cpu.kern.inst.hwrei                     212001                       # number of hwrei instructions executed
+system.cpu.kern.ipl_count::0                    74899     40.89%     40.89% # number of times we switched to this ipl
 system.cpu.kern.ipl_count::21                     131      0.07%     40.96% # number of times we switched to this ipl
 system.cpu.kern.ipl_count::22                    1932      1.05%     42.01% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31                  106216     57.99%    100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total               183174                       # number of times we switched to this ipl
-system.cpu.kern.ipl_good::0                     73528     49.31%     49.31% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_count::31                  106222     57.99%    100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::total               183184                       # number of times we switched to this ipl
+system.cpu.kern.ipl_good::0                     73532     49.31%     49.31% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::21                      131      0.09%     49.40% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::22                     1932      1.30%     50.69% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::31                    73528     49.31%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::total                149119                       # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0             1858257404500     96.76%     96.76% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21                91623500      0.00%     96.77% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22               737068500      0.04%     96.81% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31             61341210500      3.19%    100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total         1920427307000                       # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used::0                  0.981748                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_good::31                    73532     49.31%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::total                149127                       # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks::0             1858066400000     96.75%     96.75% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::21                91407000      0.00%     96.76% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::22               737349500      0.04%     96.80% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31             61520290500      3.20%    100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total         1920415447000                       # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used::0                  0.981749                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31                 0.692250                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::total              0.814084                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::31                 0.692248                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::total              0.814083                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
 system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
 system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
@@ -630,10 +546,10 @@ system.cpu.kern.callpal::cserve                     1      0.00%      0.00% # nu
 system.cpu.kern.callpal::wrmces                     1      0.00%      0.00% # number of callpals executed
 system.cpu.kern.callpal::wrfen                      1      0.00%      0.00% # number of callpals executed
 system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # number of callpals executed
-system.cpu.kern.callpal::swpctx                  4175      2.16%      2.17% # number of callpals executed
+system.cpu.kern.callpal::swpctx                  4176      2.16%      2.17% # number of callpals executed
 system.cpu.kern.callpal::tbi                       54      0.03%      2.19% # number of callpals executed
 system.cpu.kern.callpal::wrent                      7      0.00%      2.20% # number of callpals executed
-system.cpu.kern.callpal::swpipl                175953     91.22%     93.41% # number of callpals executed
+system.cpu.kern.callpal::swpipl                175963     91.22%     93.41% # number of callpals executed
 system.cpu.kern.callpal::rdps                    6833      3.54%     96.96% # number of callpals executed
 system.cpu.kern.callpal::wrkgp                      1      0.00%     96.96% # number of callpals executed
 system.cpu.kern.callpal::wrusp                      7      0.00%     96.96% # number of callpals executed
@@ -642,21 +558,21 @@ system.cpu.kern.callpal::whami                      2      0.00%     96.97% # nu
 system.cpu.kern.callpal::rti                     5157      2.67%     99.64% # number of callpals executed
 system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
 system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
-system.cpu.kern.callpal::total                 192898                       # number of callpals executed
-system.cpu.kern.mode_switch::kernel              5903                       # number of protection mode switches
-system.cpu.kern.mode_switch::user                1739                       # number of protection mode switches
+system.cpu.kern.callpal::total                 192909                       # number of callpals executed
+system.cpu.kern.mode_switch::kernel              5904                       # number of protection mode switches
+system.cpu.kern.mode_switch::user                1741                       # number of protection mode switches
 system.cpu.kern.mode_switch::idle                2095                       # number of protection mode switches
-system.cpu.kern.mode_good::kernel                1908                      
-system.cpu.kern.mode_good::user                  1739                      
-system.cpu.kern.mode_good::idle                   169                      
-system.cpu.kern.mode_switch_good::kernel     0.323225                       # fraction of useful protection mode switches
+system.cpu.kern.mode_good::kernel                1911                      
+system.cpu.kern.mode_good::user                  1741                      
+system.cpu.kern.mode_good::idle                   170                      
+system.cpu.kern.mode_switch_good::kernel     0.323679                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::idle       0.080668                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total      0.391907                       # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel        46222890000      2.41%      2.41% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user           5212630500      0.27%      2.68% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle         1868991784500     97.32%    100.00% # number of ticks spent at the given mode
-system.cpu.kern.swap_context                     4176                       # number of times the context was actually changed
+system.cpu.kern.mode_switch_good::idle       0.081146                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::total      0.392402                       # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks::kernel        46067941500      2.40%      2.40% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user           5182686000      0.27%      2.67% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle         1869164817500     97.33%    100.00% # number of ticks spent at the given mode
+system.cpu.kern.swap_context                     4177                       # number of times the context was actually changed
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
 system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
@@ -688,7 +604,7 @@ system.tsunami.ethernet.totalRxOrn                  0                       # to
 system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
 system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.iobus.throughput                       1409150                       # Throughput (bytes/s)
+system.iobus.throughput                       1409159                       # Throughput (bytes/s)
 system.iobus.trans_dist::ReadReq                 7103                       # Transaction distribution
 system.iobus.trans_dist::ReadResp                7103                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               51202                       # Transaction distribution
@@ -748,67 +664,67 @@ system.iobus.reqLayer27.occupancy               76000                       # La
 system.iobus.reqLayer27.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer28.occupancy              110000                       # Layer occupancy (ticks)
 system.iobus.reqLayer28.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer29.occupancy           377727206                       # Layer occupancy (ticks)
+system.iobus.reqLayer29.occupancy           380034075                       # Layer occupancy (ticks)
 system.iobus.reqLayer29.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer30.occupancy               30000                       # Layer occupancy (ticks)
 system.iobus.reqLayer30.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy            23510000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            42674250                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            43162000                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.cpu.icache.tags.replacements            928358                       # number of replacements
-system.cpu.icache.tags.tagsinuse           508.321671                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            55265541                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            928869                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             59.497670                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       39723654250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   508.321671                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.992816                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.992816                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements            928494                       # number of replacements
+system.cpu.icache.tags.tagsinuse           508.301721                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            55278924                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            929005                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             59.503365                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       39895254250                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   508.301721                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.992777                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.992777                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          438                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1            3                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          436                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3            9                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          57123599                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         57123599                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     55265541                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        55265541                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      55265541                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         55265541                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     55265541                       # number of overall hits
-system.cpu.icache.overall_hits::total        55265541                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       929029                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        929029                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       929029                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         929029                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       929029                       # number of overall misses
-system.cpu.icache.overall_misses::total        929029                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  12961853258                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  12961853258                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  12961853258                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  12961853258                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  12961853258                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  12961853258                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     56194570                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     56194570                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     56194570                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     56194570                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     56194570                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     56194570                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.016532                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.016532                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.016532                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.016532                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.016532                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.016532                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13952.043755                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13952.043755                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13952.043755                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13952.043755                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13952.043755                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13952.043755                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses          57137254                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         57137254                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     55278924                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        55278924                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      55278924                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         55278924                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     55278924                       # number of overall hits
+system.cpu.icache.overall_hits::total        55278924                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       929165                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        929165                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       929165                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         929165                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       929165                       # number of overall misses
+system.cpu.icache.overall_misses::total        929165                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  12919006759                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  12919006759                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  12919006759                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  12919006759                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  12919006759                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  12919006759                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     56208089                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     56208089                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     56208089                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     56208089                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     56208089                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     56208089                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.016531                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.016531                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.016531                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.016531                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.016531                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.016531                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13903.888716                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13903.888716                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13903.888716                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13903.888716                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13903.888716                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13903.888716                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -817,135 +733,135 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       929029                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       929029                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       929029                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       929029                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       929029                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       929029                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  11098555742                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  11098555742                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  11098555742                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  11098555742                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  11098555742                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  11098555742                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.016532                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.016532                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.016532                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.016532                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.016532                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.016532                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11946.403979                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11946.403979                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11946.403979                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11946.403979                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11946.403979                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11946.403979                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       929165                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       929165                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       929165                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       929165                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       929165                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       929165                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  11055577241                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  11055577241                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  11055577241                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  11055577241                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  11055577241                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  11055577241                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.016531                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.016531                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.016531                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.016531                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.016531                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.016531                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11898.400436                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11898.400436                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11898.400436                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11898.400436                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11898.400436                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11898.400436                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           336056                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        65296.863719                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            2447536                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           401218                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             6.100265                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle       6747777750                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 55582.845445                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  4758.900638                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  4955.117636                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.848127                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.072615                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.075609                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.996351                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.replacements           336265                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65295.577509                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            2447728                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           401427                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             6.097567                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle       6793166750                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 55588.679267                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  4757.001179                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  4949.897063                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.848216                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.072586                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.075529                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.996331                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        65162                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          178                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1050                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         4896                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         3257                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55781                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1074                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         4882                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         3251                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        55777                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.994293                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         25947571                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        25947571                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst       915717                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data       814814                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1730531                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       835114                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       835114                       # number of Writeback hits
+system.cpu.l2cache.tags.tag_accesses         25952661                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        25952661                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.inst       915852                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data       814775                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        1730627                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       835359                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       835359                       # number of Writeback hits
 system.cpu.l2cache.UpgradeReq_hits::cpu.data            4                       # number of UpgradeReq hits
 system.cpu.l2cache.UpgradeReq_hits::total            4                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       187645                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       187645                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst       915717                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      1002459                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         1918176                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst       915717                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      1002459                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        1918176                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst        13292                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data       271915                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total       285207                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_hits::cpu.data       187681                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       187681                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst       915852                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      1002456                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         1918308                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst       915852                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      1002456                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        1918308                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst        13293                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data       271967                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total       285260                       # number of ReadReq misses
 system.cpu.l2cache.UpgradeReq_misses::cpu.data           13                       # number of UpgradeReq misses
 system.cpu.l2cache.UpgradeReq_misses::total           13                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       116708                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       116708                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst        13292                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       388623                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        401915                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst        13292                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       388623                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       401915                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   1012336742                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data  17564329991                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total  18576666733                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_misses::cpu.data       116864                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       116864                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst        13293                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       388831                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        402124                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst        13293                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       388831                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       402124                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    967872241                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data  17714808491                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total  18682680732                       # number of ReadReq miss cycles
 system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       190498                       # number of UpgradeReq miss cycles
 system.cpu.l2cache.UpgradeReq_miss_latency::total       190498                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   8190852374                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   8190852374                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst   1012336742                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  25755182365                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  26767519107                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst   1012336742                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  25755182365                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  26767519107                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst       929009                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      1086729                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      2015738                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       835114                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       835114                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   8011039626                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   8011039626                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    967872241                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  25725848117                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  26693720358                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    967872241                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  25725848117                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  26693720358                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst       929145                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      1086742                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      2015887                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       835359                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       835359                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::cpu.data           17                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::total           17                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       304353                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       304353                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst       929009                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      1391082                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2320091                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst       929009                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      1391082                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2320091                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.014308                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.250214                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.141490                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       304545                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       304545                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst       929145                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      1391287                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2320432                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst       929145                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      1391287                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2320432                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.014307                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.250259                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.141506                       # miss rate for ReadReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.764706                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::total     0.764706                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.383463                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.383463                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.014308                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.279367                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.173232                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.014308                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.279367                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.173232                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76161.355853                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 64594.928529                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 65133.978945                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.383733                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.383733                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.014307                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.279476                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.173297                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.014307                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.279476                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.173297                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72810.670353                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65135.874908                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 65493.517254                       # average ReadReq miss latency
 system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 14653.692308                       # average UpgradeReq miss latency
 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 14653.692308                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70182.441426                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70182.441426                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76161.355853                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66272.923540                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 66599.950504                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76161.355853                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66272.923540                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 66599.950504                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68550.106329                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68550.106329                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72810.670353                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66162.029563                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 66381.813465                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72810.670353                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66162.029563                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 66381.813465                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -954,66 +870,66 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        73954                       # number of writebacks
-system.cpu.l2cache.writebacks::total            73954                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        13292                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       271915                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total       285207                       # number of ReadReq MSHR misses
+system.cpu.l2cache.writebacks::writebacks        74205                       # number of writebacks
+system.cpu.l2cache.writebacks::total            74205                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        13293                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       271967                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total       285260                       # number of ReadReq MSHR misses
 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           13                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.UpgradeReq_mshr_misses::total           13                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       116708                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       116708                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        13292                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       388623                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       401915                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        13292                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       388623                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       401915                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    845706258                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  14164824509                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total  15010530767                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       116864                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       116864                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        13293                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       388831                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       402124                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        13293                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       388831                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       402124                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    801329759                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  14314442009                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  15115771768                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       230011                       # number of UpgradeReq MSHR miss cycles
 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       230011                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6731491626                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6731491626                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    845706258                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  20896316135                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  21742022393                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    845706258                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  20896316135                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  21742022393                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1334145500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1334145500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   1895642000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   1895642000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6549827374                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6549827374                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    801329759                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  20864269383                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  21665599142                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    801329759                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  20864269383                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  21665599142                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   1334146000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   1334146000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   1895641500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   1895641500                       # number of WriteReq MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   3229787500                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency::total   3229787500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.014308                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.250214                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.141490                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.014307                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.250259                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.141506                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.764706                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.764706                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.383463                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.383463                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.014308                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.279367                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.173232                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.014308                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.279367                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.173232                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63625.207493                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52092.839707                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52630.302787                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.383733                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.383733                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.014307                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.279476                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.173297                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.014307                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.279476                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.173297                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60282.085233                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52633.010656                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52989.454421                       # average ReadReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17693.153846                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17693.153846                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57678.065137                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57678.065137                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63625.207493                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53770.147765                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54096.071042                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63625.207493                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53770.147765                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54096.071042                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56046.578707                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56046.578707                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60282.085233                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53658.965934                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53877.906173                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60282.085233                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53658.965934                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53877.906173                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1021,13 +937,13 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements           1390568                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.978915                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            14049173                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1391080                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             10.099472                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         107298250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.978915                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.replacements           1390774                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.978892                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            14051964                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1391286                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             10.099982                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         107796250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.978892                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999959                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999959                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
@@ -1035,72 +951,72 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0          187
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          257                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2           68                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          63152102                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         63152102                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data      7814622                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total         7814622                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      5852326                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        5852326                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       182986                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       182986                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       199222                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       199222                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      13666948                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         13666948                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     13666948                       # number of overall hits
-system.cpu.dcache.overall_hits::total        13666948                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1069470                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1069470                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       304370                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       304370                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        17259                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        17259                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      1373840                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1373840                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1373840                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1373840                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  28875755759                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  28875755759                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  11035273137                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  11035273137                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    228925250                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    228925250                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  39911028896                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  39911028896                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  39911028896                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  39911028896                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data      8884092                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total      8884092                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      6156696                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      6156696                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       200245                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       200245                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       199222                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       199222                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     15040788                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     15040788                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     15040788                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     15040788                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.120380                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.120380                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.049437                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.049437                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.086189                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.086189                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.091341                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.091341                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.091341                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.091341                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27000.061487                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 27000.061487                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36256.113076                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 36256.113076                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13264.108581                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13264.108581                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 29050.711070                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 29050.711070                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 29050.711070                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 29050.711070                       # average overall miss latency
+system.cpu.dcache.tags.tag_accesses          63164291                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         63164291                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data      7816324                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total         7816324                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      5853358                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        5853358                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       183027                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       183027                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       199238                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       199238                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      13669682                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         13669682                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     13669682                       # number of overall hits
+system.cpu.dcache.overall_hits::total        13669682                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1069509                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1069509                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       304562                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       304562                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        17233                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        17233                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data      1374071                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1374071                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1374071                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1374071                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  29019471009                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  29019471009                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  10854033885                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  10854033885                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    228736500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    228736500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  39873504894                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  39873504894                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  39873504894                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  39873504894                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data      8885833                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total      8885833                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      6157920                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      6157920                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       200260                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       200260                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       199238                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       199238                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     15043753                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     15043753                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     15043753                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     15043753                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.120361                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.120361                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.049459                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.049459                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.086053                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.086053                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.091338                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.091338                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.091338                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.091338                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27133.451901                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 27133.451901                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35638.175101                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 35638.175101                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13273.167760                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13273.167760                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 29018.518617                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 29018.518617                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 29018.518617                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 29018.518617                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -1109,54 +1025,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       835114                       # number of writebacks
-system.cpu.dcache.writebacks::total            835114                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1069470                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1069470                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       304370                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       304370                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        17259                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total        17259                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1373840                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1373840                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1373840                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1373840                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  26604805241                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  26604805241                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10372104863                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  10372104863                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    194393750                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    194393750                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  36976910104                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  36976910104                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  36976910104                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  36976910104                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1424235500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1424235500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2011442000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2011442000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.writebacks::writebacks       835359                       # number of writebacks
+system.cpu.dcache.writebacks::total            835359                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1069509                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1069509                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       304562                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       304562                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        17233                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total        17233                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1374071                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1374071                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1374071                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1374071                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  26755042991                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  26755042991                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10192844115                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  10192844115                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    194257500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    194257500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  36947887106                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  36947887106                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  36947887106                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  36947887106                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1424236000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1424236000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2011441500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2011441500                       # number of WriteReq MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3435677500                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_latency::total   3435677500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.120380                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.120380                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.049437                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.049437                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.086189                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.086189                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091341                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.091341                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091341                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.091341                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24876.626031                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24876.626031                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34077.290347                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34077.290347                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11263.326380                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11263.326380                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26915.004734                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 26915.004734                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26915.004734                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 26915.004734                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.120361                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.120361                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.049459                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.049459                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.086053                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.086053                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091338                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.091338                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091338                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.091338                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25016.192469                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25016.192469                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33467.222158                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33467.222158                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11272.413393                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11272.413393                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26889.358051                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 26889.358051                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26889.358051                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 26889.358051                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1164,31 +1080,31 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput               105179195                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq        2022861                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2022844                       # Transaction distribution
+system.cpu.toL2Bus.throughput               105199341                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq        2023010                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2022993                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq          9650                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp         9650                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       835114                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback       835359                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeReq           17                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeResp           17                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       345905                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       304355                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1858038                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3650630                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           5508668                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     59456576                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    142531220                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      201987796                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus         201977684                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus        11392                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy     2425850000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.trans_dist::ReadExReq       346097                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       304546                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1858310                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3651284                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           5509594                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     59465280                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    142559956                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      202025236                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         202015188                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus        11328                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy     2426388000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy       237000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy       235500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    1396163258                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    1396297259                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2191612646                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    2187438394                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
index 786f029ca84b717b926b03364d8e0de106ea3873..789d25c609c53fd632bba473cc73613b4a2b3ce3 100644 (file)
@@ -1,16 +1,16 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.196143                       # Number of seconds simulated
-sim_ticks                                1196142873000                       # Number of ticks simulated
-final_tick                               1196142873000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.196225                       # Number of seconds simulated
+sim_ticks                                1196225147500                       # Number of ticks simulated
+final_tick                               1196225147500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 497666                       # Simulator instruction rate (inst/s)
-host_op_rate                                   634118                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             9685782626                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 425428                       # Number of bytes of host memory used
-host_seconds                                   123.49                       # Real time elapsed on the host
-sim_insts                                    61459155                       # Number of instructions simulated
-sim_ops                                      78310163                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 669591                       # Simulator instruction rate (inst/s)
+host_op_rate                                   853186                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            13029857543                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 426076                       # Number of bytes of host memory used
+host_seconds                                    91.81                       # Real time elapsed on the host
+sim_insts                                    61472758                       # Number of instructions simulated
+sim_ops                                      78327958                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
@@ -33,142 +33,138 @@ system.realview.nvmem.bw_total::cpu1.inst           40                       # T
 system.realview.nvmem.bw_total::total              57                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bytes_read::realview.clcd     51904512                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.dtb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           393356                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          4724988                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker          192                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           378508                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          4532924                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.dtb.walker          256                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           324292                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          4798584                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             62146244                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       393356                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       324292                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          717648                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      4113152                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu1.inst           337988                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          4964984                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             62119428                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       378508                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       337988                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          716496                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      4092288                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         17000                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data       3010344                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7140496                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7119632                       # Number of bytes written to this memory
 system.physmem.num_reads::realview.clcd       6488064                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.dtb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             12374                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             73902                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker            3                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             12142                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             70901                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.dtb.walker            4                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              5158                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             75006                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               6654512                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           64268                       # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              5372                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             77606                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               6654093                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           63942                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             4250                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data           752586                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               821104                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd        43393238                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               820778                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd        43390253                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.dtb.walker            54                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker           107                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              328854                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             3950187                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker           161                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              316419                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             3789357                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu1.dtb.walker           214                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker            54                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst              271115                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             4011715                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                51955536                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         328854                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst         271115                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             599968                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3438680                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data              14212                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data            2516709                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                5969601                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3438680                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd       43393238                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst              282545                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             4150543                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                51929545                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         316419                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst         282545                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             598964                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3421001                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data              14211                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data            2516536                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                5951749                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3421001                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd       43390253                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.dtb.walker           54                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker          107                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             328854                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            3964399                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker          161                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             316419                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            3803568                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu1.dtb.walker          214                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker           54                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst             271115                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            6528424                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               57925137                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       6654512                       # Number of read requests accepted
-system.physmem.writeReqs                       821104                       # Number of write requests accepted
-system.physmem.readBursts                     6654512                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     821104                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                425857728                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     31040                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7268800                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  62146244                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7140496                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      485                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                  707525                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs          12040                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              415388                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              415219                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              415339                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              415675                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              422392                       # Per bank write bursts
+system.physmem.bw_total::cpu1.inst             282545                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            6667079                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               57881294                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       6654093                       # Number of read requests accepted
+system.physmem.writeReqs                       820778                       # Number of write requests accepted
+system.physmem.readBursts                     6654093                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     820778                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                425823936                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     38016                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   7142848                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  62119428                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7119632                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      594                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                  709146                       # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs          11979                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0              415258                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              415304                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              415298                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              415715                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              422332                       # Per bank write bursts
 system.physmem.perBankRdBursts::5              415542                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              415783                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              415483                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              416074                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              415577                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             415249                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             414844                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             415143                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             415555                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             415561                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             415203                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                6999                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                6843                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                7018                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                7170                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7419                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7182                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                7433                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                7180                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7611                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                7217                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7107                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6660                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               6804                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               7009                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7096                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               6827                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              415821                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              415579                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              415943                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              415582                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             415396                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             414885                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             414891                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             415396                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             415532                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             415025                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                6797                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                6838                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                6874                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                7108                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                7245                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7088                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                7332                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                7150                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7392                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                7114                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7008                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6578                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               6732                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               6801                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7004                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               6546                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1196138285000                       # Total gap between requests
+system.physmem.totGap                    1196220625500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                    6849                       # Read request sizes (log2)
 system.physmem.readPktSize::3                 6488064                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  159599                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  159180                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                 756836                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  64268                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    628282                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    475071                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                    476093                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                   1580129                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                   1132007                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                   1126499                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                   1123122                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                     25082                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                     24371                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      9325                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                     9268                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                     9185                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                     8944                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                     8860                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                     8817                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                     8783                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      173                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                       16                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  63942                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    568386                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    406756                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                    406740                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                    413202                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                    408903                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                    410926                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                   1188562                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                   1189774                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                   1562236                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                     22558                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                    14685                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                    15166                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                    13714                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                    12546                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                     9828                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                     9386                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                      119                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                       12                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
@@ -183,758 +179,434 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                      5162                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                      5166                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                      5163                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                      5163                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                      5163                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                      5161                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                      5162                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                      5163                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                      5162                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                      5161                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                     5161                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                     5161                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                     5161                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                     5161                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                     5162                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     5162                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     5161                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5164                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5166                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5163                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     5163                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5166                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        74541                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean     5810.577695                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     397.196541                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev   13066.067638                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64-71          25758     34.56%     34.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-135        15237     20.44%     55.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192-199         3243      4.35%     59.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-263         2416      3.24%     62.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320-327         1619      2.17%     64.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-391         1307      1.75%     66.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448-455         1041      1.40%     67.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-519         1103      1.48%     69.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576-583          718      0.96%     70.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-647          614      0.82%     71.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704-711          577      0.77%     71.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-775          705      0.95%     72.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832-839          343      0.46%     73.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-903          280      0.38%     73.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960-967          211      0.28%     74.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1031          365      0.49%     74.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088-1095          178      0.24%     74.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152-1159          141      0.19%     74.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216-1223          142      0.19%     75.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280-1287          160      0.21%     75.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344-1351          121      0.16%     75.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408-1415         2248      3.02%     78.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472-1479          145      0.19%     78.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536-1543          165      0.22%     78.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600-1607           59      0.08%     79.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664-1671           66      0.09%     79.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1728-1735           46      0.06%     79.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1792-1799          116      0.16%     79.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856-1863           53      0.07%     79.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1920-1927           27      0.04%     79.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984-1991           17      0.02%     79.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2048-2055          120      0.16%     79.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112-2119           17      0.02%     79.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2176-2183           20      0.03%     79.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2240-2247           29      0.04%     79.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2304-2311           31      0.04%     79.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2368-2375           12      0.02%     79.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2432-2439           26      0.03%     79.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2496-2503           23      0.03%     79.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2560-2567           90      0.12%     79.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2624-2631           24      0.03%     79.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2688-2695           12      0.02%     79.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2752-2759           29      0.04%     80.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2816-2823           36      0.05%     80.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2880-2887           10      0.01%     80.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2944-2951           25      0.03%     80.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3008-3015           10      0.01%     80.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3072-3079          133      0.18%     80.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3136-3143           21      0.03%     80.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3200-3207           12      0.02%     80.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3264-3271           14      0.02%     80.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3328-3335           45      0.06%     80.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3392-3399            4      0.01%     80.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3456-3463            9      0.01%     80.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3520-3527           21      0.03%     80.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3584-3591           88      0.12%     80.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3648-3655            4      0.01%     80.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3712-3719           17      0.02%     80.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3776-3783           31      0.04%     80.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3840-3847           79      0.11%     80.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3904-3911           18      0.02%     80.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3968-3975            3      0.00%     80.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4032-4039            4      0.01%     80.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4096-4103          183      0.25%     81.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4160-4167            2      0.00%     81.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4224-4231            2      0.00%     81.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4288-4295           17      0.02%     81.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4352-4359           24      0.03%     81.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4416-4423            3      0.00%     81.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4480-4487           18      0.02%     81.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4544-4551            3      0.00%     81.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4608-4615           17      0.02%     81.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4672-4679           18      0.02%     81.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4736-4743            2      0.00%     81.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4800-4807            4      0.01%     81.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4864-4871           95      0.13%     81.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4928-4935           11      0.01%     81.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4992-4999            5      0.01%     81.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5056-5063           15      0.02%     81.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5120-5127          100      0.13%     81.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5184-5191            3      0.00%     81.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5248-5255           19      0.03%     81.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5312-5319            4      0.01%     81.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5376-5383           16      0.02%     81.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5440-5447          174      0.23%     81.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5504-5511           59      0.08%     81.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5632-5639            9      0.01%     81.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5696-5703            1      0.00%     81.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5888-5895           93      0.12%     82.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6016-6023            3      0.00%     82.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6144-6151          214      0.29%     82.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6400-6407           32      0.04%     82.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6528-6535            2      0.00%     82.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6592-6599            2      0.00%     82.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6656-6663           12      0.02%     82.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6912-6919           17      0.02%     82.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7040-7047            1      0.00%     82.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7168-7175          160      0.21%     82.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7232-7239            1      0.00%     82.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7360-7367            1      0.00%     82.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7424-7431           23      0.03%     82.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7616-7623            1      0.00%     82.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7680-7687           12      0.02%     82.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7744-7751            1      0.00%     82.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7936-7943           24      0.03%     82.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8000-8007            1      0.00%     82.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8192-8199          265      0.36%     83.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8448-8455           29      0.04%     83.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8640-8647            1      0.00%     83.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8704-8711           17      0.02%     83.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8960-8967           27      0.04%     83.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9088-9095            1      0.00%     83.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9216-9223          153      0.21%     83.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9472-9479           18      0.02%     83.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9664-9671            1      0.00%     83.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9728-9735           16      0.02%     83.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9984-9991           33      0.04%     83.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10048-10055            1      0.00%     83.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10176-10183            1      0.00%     83.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10240-10247          214      0.29%     83.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10368-10375            1      0.00%     83.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10496-10503           86      0.12%     83.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10560-10567            1      0.00%     83.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10624-10631            2      0.00%     83.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10752-10759           12      0.02%     83.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11008-11015           17      0.02%     83.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11136-11143            1      0.00%     83.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11264-11271          106      0.14%     84.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11328-11335            1      0.00%     84.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11392-11399            1      0.00%     84.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11520-11527           81      0.11%     84.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11776-11783           14      0.02%     84.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12032-12039           16      0.02%     84.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12096-12103            3      0.00%     84.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12224-12231            1      0.00%     84.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12288-12295          158      0.21%     84.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12416-12423            1      0.00%     84.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12480-12487            1      0.00%     84.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12544-12551           76      0.10%     84.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12800-12807           84      0.11%     84.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13056-13063           29      0.04%     84.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13184-13191            1      0.00%     84.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13312-13319          105      0.14%     84.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13376-13383            1      0.00%     84.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13568-13575           26      0.03%     84.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13824-13831           82      0.11%     84.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14080-14087           13      0.02%     84.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14336-14343           92      0.12%     85.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14592-14599           80      0.11%     85.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14848-14855           81      0.11%     85.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14912-14919            1      0.00%     85.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15104-15111           16      0.02%     85.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15360-15367          110      0.15%     85.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15488-15495            1      0.00%     85.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15616-15623           77      0.10%     85.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15808-15815            1      0.00%     85.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15872-15879           13      0.02%     85.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16128-16135           82      0.11%     85.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16256-16263            3      0.00%     85.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16384-16391          155      0.21%     85.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16640-16647           83      0.11%     86.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16896-16903            8      0.01%     86.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17024-17031            2      0.00%     86.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17152-17159           77      0.10%     86.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17408-17415          119      0.16%     86.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17664-17671           21      0.03%     86.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17920-17927           82      0.11%     86.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17984-17991            1      0.00%     86.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18176-18183           80      0.11%     86.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18368-18375            1      0.00%     86.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18432-18439           83      0.11%     86.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18496-18503            3      0.00%     86.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18688-18695           10      0.01%     86.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18880-18887            1      0.00%     86.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18944-18951           83      0.11%     86.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19200-19207           26      0.03%     86.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19328-19335            2      0.00%     86.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19456-19463          103      0.14%     86.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19584-19591            1      0.00%     86.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19648-19655            1      0.00%     86.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19712-19719           25      0.03%     87.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19904-19911            1      0.00%     87.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19968-19975           80      0.11%     87.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20160-20167            1      0.00%     87.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20224-20231           73      0.10%     87.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20480-20487          155      0.21%     87.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20608-20615            1      0.00%     87.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20736-20743           19      0.03%     87.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20992-20999           16      0.02%     87.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21248-21255           81      0.11%     87.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21376-21383            2      0.00%     87.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21504-21511           95      0.13%     87.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21760-21767           10      0.01%     87.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22016-22023            9      0.01%     87.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22272-22279           89      0.12%     87.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22400-22407            1      0.00%     87.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22464-22471            1      0.00%     87.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22528-22535          219      0.29%     88.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22784-22791           30      0.04%     88.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22912-22919            1      0.00%     88.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23040-23047           13      0.02%     88.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23296-23303           21      0.03%     88.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23424-23431            2      0.00%     88.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23552-23559          145      0.19%     88.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23680-23687            1      0.00%     88.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23808-23815           22      0.03%     88.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23872-23879            1      0.00%     88.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24000-24007            1      0.00%     88.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24064-24071           13      0.02%     88.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24320-24327           23      0.03%     88.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24384-24391            3      0.00%     88.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24576-24583          273      0.37%     88.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24832-24839           26      0.03%     88.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24896-24903            2      0.00%     88.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24960-24967            1      0.00%     88.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25088-25095           15      0.02%     88.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25344-25351           24      0.03%     88.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25472-25479            2      0.00%     88.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25600-25607          143      0.19%     89.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25664-25671            1      0.00%     89.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25856-25863           19      0.03%     89.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26112-26119           12      0.02%     89.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26368-26375           28      0.04%     89.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26432-26439            1      0.00%     89.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26496-26503            2      0.00%     89.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26624-26631          214      0.29%     89.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26880-26887           90      0.12%     89.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27136-27143           12      0.02%     89.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27200-27207            1      0.00%     89.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27264-27271            1      0.00%     89.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27392-27399           13      0.02%     89.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27456-27463            1      0.00%     89.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27584-27591            1      0.00%     89.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27648-27655           92      0.12%     89.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27904-27911           79      0.11%     89.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28160-28167           14      0.02%     89.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28352-28359            1      0.00%     89.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28416-28423           19      0.03%     89.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28480-28487            1      0.00%     89.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28608-28615            1      0.00%     89.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28672-28679          159      0.21%     90.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28800-28807            1      0.00%     90.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28928-28935           74      0.10%     90.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29120-29127            1      0.00%     90.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29184-29191           82      0.11%     90.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29440-29447           26      0.03%     90.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29504-29511            2      0.00%     90.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29696-29703           92      0.12%     90.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29888-29895            1      0.00%     90.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29952-29959           27      0.04%     90.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30208-30215           80      0.11%     90.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30272-30279            1      0.00%     90.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30464-30471            9      0.01%     90.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30528-30535            2      0.00%     90.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30720-30727           85      0.11%     90.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30976-30983           81      0.11%     90.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31104-31111            1      0.00%     90.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31232-31239           79      0.11%     91.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31488-31495           18      0.02%     91.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31552-31559            1      0.00%     91.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31616-31623            1      0.00%     91.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31744-31751          112      0.15%     91.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31936-31943            1      0.00%     91.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32000-32007           76      0.10%     91.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32256-32263            8      0.01%     91.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32320-32327            1      0.00%     91.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32384-32391            1      0.00%     91.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32448-32455            1      0.00%     91.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32512-32519           82      0.11%     91.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32768-32775          154      0.21%     91.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33024-33031           83      0.11%     91.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33088-33095            1      0.00%     91.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33152-33159            1      0.00%     91.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33216-33223            2      0.00%     91.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33280-33287           23      0.03%     91.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33344-33351            1      0.00%     91.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33536-33543           76      0.10%     91.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33600-33607            1      0.00%     91.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33792-33799          112      0.15%     92.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33920-33927            2      0.00%     92.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33984-33991            1      0.00%     92.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34048-34055           18      0.02%     92.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34304-34311           79      0.11%     92.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34432-34439            1      0.00%     92.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34560-34567           80      0.11%     92.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34816-34823           78      0.10%     92.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34880-34887            1      0.00%     92.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35008-35015            2      0.00%     92.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35072-35079            8      0.01%     92.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35328-35335           80      0.11%     92.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35584-35591           27      0.04%     92.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35648-35655            1      0.00%     92.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35840-35847           91      0.12%     92.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36032-36039            1      0.00%     92.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36096-36103           24      0.03%     92.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36224-36231            1      0.00%     92.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36352-36359           82      0.11%     92.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36608-36615           73      0.10%     92.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36864-36871          149      0.20%     93.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37120-37127           15      0.02%     93.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37376-37383           14      0.02%     93.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37632-37639           80      0.11%     93.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37888-37895           93      0.12%     93.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37952-37959            1      0.00%     93.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38080-38087            1      0.00%     93.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38144-38151           10      0.01%     93.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38272-38279            1      0.00%     93.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38336-38343            1      0.00%     93.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38400-38407           11      0.01%     93.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38528-38535            1      0.00%     93.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38656-38663           90      0.12%     93.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38912-38919          212      0.28%     93.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39040-39047            1      0.00%     93.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39104-39111            1      0.00%     93.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39168-39175           27      0.04%     93.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39424-39431           11      0.01%     93.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39552-39559            1      0.00%     93.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39680-39687           20      0.03%     93.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39872-39879            1      0.00%     93.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39936-39943          144      0.19%     94.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40192-40199           21      0.03%     94.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40448-40455           14      0.02%     94.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40576-40583            1      0.00%     94.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40640-40647            1      0.00%     94.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40704-40711           25      0.03%     94.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40960-40967          269      0.36%     94.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41152-41159            2      0.00%     94.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41216-41223           23      0.03%     94.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41472-41479           10      0.01%     94.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41600-41607            1      0.00%     94.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41728-41735           23      0.03%     94.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41856-41863            1      0.00%     94.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41984-41991          146      0.20%     94.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42240-42247           21      0.03%     94.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42496-42503           11      0.01%     94.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42624-42631            1      0.00%     94.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42688-42695            1      0.00%     94.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42752-42759           31      0.04%     94.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43008-43015          219      0.29%     95.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43072-43079            1      0.00%     95.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43264-43271           87      0.12%     95.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43520-43527            9      0.01%     95.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43648-43655            1      0.00%     95.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43776-43783           11      0.01%     95.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44032-44039           92      0.12%     95.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44288-44295           80      0.11%     95.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44544-44551           18      0.02%     95.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44800-44807           17      0.02%     95.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44928-44935            1      0.00%     95.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45056-45063          149      0.20%     95.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45312-45319           71      0.10%     95.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45568-45575           78      0.10%     96.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45696-45703            1      0.00%     96.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45824-45831           27      0.04%     96.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45888-45895            1      0.00%     96.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45952-45959            1      0.00%     96.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46080-46087           99      0.13%     96.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46336-46343           27      0.04%     96.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46592-46599           83      0.11%     96.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46656-46663            1      0.00%     96.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46848-46855           11      0.01%     96.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47104-47111           90      0.12%     96.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47168-47175            1      0.00%     96.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47360-47367           82      0.11%     96.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47552-47559            1      0.00%     96.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47616-47623           83      0.11%     96.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47680-47687            1      0.00%     96.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47872-47879           18      0.02%     96.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48000-48007            1      0.00%     96.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48128-48135          130      0.17%     96.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48192-48199            2      0.00%     96.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48256-48263            1      0.00%     96.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48320-48327            2      0.00%     96.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48384-48391          100      0.13%     97.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48576-48583            1      0.00%     97.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48640-48647            6      0.01%     97.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48768-48775           13      0.02%     97.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48896-48903           79      0.11%     97.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48960-48967            5      0.01%     97.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::49024-49031            5      0.01%     97.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::49088-49095            6      0.01%     97.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::49152-49159         2052      2.75%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          74541                       # Bytes accessed per row activation
-system.physmem.totQLat                   159547739500                       # Total ticks spent queuing
-system.physmem.totMemAccLat              202481649500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                  33270135000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                  9663775000                       # Total ticks spent accessing banks
-system.physmem.avgQLat                       23977.62                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                     1452.32                       # Average bank access latency per DRAM burst
+system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     2656                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2719                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     3656                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     5124                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     5129                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     5125                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     5127                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     5169                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     5182                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     5159                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     6206                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     5353                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     5316                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     6283                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     5251                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     5231                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     5217                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     5137                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     1141                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                     1090                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                     1087                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                     1087                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                     1076                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                     1076                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                     1074                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                     1072                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                     1074                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                     1072                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                     1070                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                     1069                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                     1069                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                     1067                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                     1067                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                     1065                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                     1065                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                     1064                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                     1064                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                     1064                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                     1064                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       427748                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      996.884371                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     962.233746                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     147.681447                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127           5003      1.17%      1.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         3928      0.92%      2.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         2092      0.49%      2.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         1312      0.31%      2.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         1079      0.25%      3.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          787      0.18%      3.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          742      0.17%      3.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          447      0.10%      3.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151       412358     96.40%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         427748                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5121                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean      1299.254638                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev    29808.283067                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-65535          5114     99.86%     99.86% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::196608-262143            3      0.06%     99.92% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::589824-655359            1      0.02%     99.94% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::786432-851967            1      0.02%     99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::983040-1.04858e+06            1      0.02%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1.57286e+06-1.6384e+06            1      0.02%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            5121                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5121                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        21.793986                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       20.383938                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        9.006526                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               2131     41.61%     41.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                296      5.78%     47.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                286      5.58%     52.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19               1314     25.66%     78.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                 15      0.29%     78.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                  5      0.10%     79.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                  2      0.04%     79.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                  2      0.04%     79.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                  1      0.02%     79.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28                  3      0.06%     79.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::34                  1      0.02%     79.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::35                  1      0.02%     79.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::39                953     18.61%     97.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40                 61      1.19%     99.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::41                 17      0.33%     99.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::42                 33      0.64%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5121                       # Writes before turning the bus around for reads
+system.physmem.totQLat                   249828830750                       # Total ticks spent queuing
+system.physmem.totMemAccLat              297299498250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                  33267495000                       # Total ticks spent in databus transfers
+system.physmem.totBankLat                 14203172500                       # Total ticks spent accessing banks
+system.physmem.avgQLat                       37548.49                       # Average queueing delay per DRAM burst
+system.physmem.avgBankLat                     2134.69                       # Average bank access latency per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  30429.94                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         356.03                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           6.08                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       51.96                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        5.97                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  44683.18                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         355.97                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           5.97                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       51.93                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        5.95                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           2.83                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       2.78                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.05                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         0.17                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        12.60                       # Average write queue length when enqueuing
-system.physmem.readRowHits                    6598250                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     94811                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   99.16                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  83.48                       # Row buffer hit rate for writes
-system.physmem.avgGap                       160005.31                       # Average gap between requests
-system.physmem.pageHitRate                      98.90                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               4.94                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                     59942042                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq             7703387                       # Transaction distribution
-system.membus.trans_dist::ReadResp            7703387                       # Transaction distribution
-system.membus.trans_dist::WriteReq             767577                       # Transaction distribution
-system.membus.trans_dist::WriteResp            767577                       # Transaction distribution
-system.membus.trans_dist::Writeback             64268                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq            31533                       # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq          17272                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp           12040                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            137758                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           137334                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      2382660                       # Packet count per connected master and slave (bytes)
+system.physmem.avgRdQLen                         4.56                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        29.44                       # Average write queue length when enqueuing
+system.physmem.readRowHits                    6202256                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     93908                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   93.22                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  84.12                       # Row buffer hit rate for writes
+system.physmem.avgGap                       160032.28                       # Average gap between requests
+system.physmem.pageHitRate                      93.07                       # Row buffer hit rate, read and write combined
+system.physmem.prechargeAllPercent               6.14                       # Percentage of time for which DRAM has all the banks in precharge state
+system.membus.throughput                     59898120                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq             7703395                       # Transaction distribution
+system.membus.trans_dist::ReadResp            7703395                       # Transaction distribution
+system.membus.trans_dist::WriteReq             767585                       # Transaction distribution
+system.membus.trans_dist::WriteResp            767585                       # Transaction distribution
+system.membus.trans_dist::Writeback             63942                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq            31730                       # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq          17317                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp           11979                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            137317                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           136921                       # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave      2382690                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           34                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        10292                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        10302                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio            4                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio          910                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1972105                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total      4366005                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio          914                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      1971094                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total      4365038                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     12976128                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total     12976128                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total               17342133                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave      2390026                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count::total               17341166                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave      2390070                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port           68                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio        20584                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio        20604                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio            8                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio         1820                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     17382228                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::total     19794734                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio         1828                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port     17334548                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::total     19747126                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port     51904512                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.iocache.mem_side::total     51904512                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            71699246                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus               71699246                       # Total data (bytes)
+system.membus.tot_pkt_size::total            71651638                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               71651638                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy          1224801500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy          1224825500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy               18000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             9220500                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             9234000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer4.occupancy                2500                       # Layer occupancy (ticks)
 system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer5.occupancy              782500                       # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy              786000                       # Layer occupancy (ticks)
 system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer6.occupancy          9211496500                       # Layer occupancy (ticks)
+system.membus.reqLayer6.occupancy          9208108500                       # Layer occupancy (ticks)
 system.membus.reqLayer6.utilization               0.8                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         5081612097                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         5075173558                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.4                       # Layer utilization (%)
-system.membus.respLayer2.occupancy        14657936499                       # Layer occupancy (ticks)
-system.membus.respLayer2.utilization              1.2                       # Layer utilization (%)
+system.membus.respLayer2.occupancy        16181474500                       # Layer occupancy (ticks)
+system.membus.respLayer2.utilization              1.4                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.l2c.tags.replacements                    69480                       # number of replacements
-system.l2c.tags.tagsinuse                52958.538682                       # Cycle average of tags in use
-system.l2c.tags.total_refs                    1674406                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                   134639                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                    12.436263                       # Average number of references to valid blocks.
+system.l2c.tags.replacements                    69062                       # number of replacements
+system.l2c.tags.tagsinuse                52959.899517                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    1674433                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   134270                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    12.470641                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks   40140.336267                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker     0.000411                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker     0.001545                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst     3711.388388                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data     4232.378884                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker     2.742427                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker     0.001688                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst     2812.770235                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data     2058.918835                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks      0.612493                       # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::writebacks   40142.433744                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker     0.000410                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker     0.003238                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     3707.808501                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     4231.213775                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker     2.742447                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     2816.465022                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     2059.232379                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.612525                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000000                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst       0.056631                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data       0.064581                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.056577                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.064563                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000042                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.042919                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data       0.031417                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total           0.808083                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.042976                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.031421                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.808104                       # Average percentage of cache occupancy
 system.l2c.tags.occ_task_id_blocks::1023            5                       # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024        65154                       # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024        65203                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1023::4            4                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0           20                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1           27                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2         1929                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3         8108                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4        55070                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0           24                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1           71                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2         1924                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3         7908                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4        55276                       # Occupied blocks per task id
 system.l2c.tags.occ_task_id_percent::1023     0.000076                       # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024     0.994171                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                 17216542                       # Number of tag accesses
-system.l2c.tags.data_accesses                17216542                       # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker         3810                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker         1731                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst             419647                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             206017                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker         5550                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker         1931                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             464603                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data             143237                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1246526                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          570959                       # number of Writeback hits
-system.l2c.Writeback_hits::total               570959                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data            1148                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data             589                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                1737                       # number of UpgradeReq hits
+system.l2c.tags.occ_task_id_percent::1024     0.994919                       # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses                 17240213                       # Number of tag accesses
+system.l2c.tags.data_accesses                17240213                       # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.dtb.walker         2997                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker         1656                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.inst             349452                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data             169925                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker         6371                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker         1905                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst             535287                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data             180837                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1248430                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          572475                       # number of Writeback hits
+system.l2c.Writeback_hits::total               572475                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data            1043                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data             587                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                1630                       # number of UpgradeReq hits
 system.l2c.SCUpgradeReq_hits::cpu0.data           220                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data           100                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total               320                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            56693                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            52725                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               109418                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker          3810                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker          1731                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              419647                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              262710                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker          5550                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          1931                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              464603                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              195962                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1355944                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker         3810                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker         1731                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             419647                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             262710                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker         5550                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         1931                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             464603                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             195962                       # number of overall hits
-system.l2c.overall_hits::total                1355944                       # number of overall hits
+system.l2c.SCUpgradeReq_hits::cpu1.data            84                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total               304                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data            47236                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            62412                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               109648                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.dtb.walker          2997                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker          1656                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst              349452                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              217161                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker          6371                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker          1905                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              535287                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              243249                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 1358078                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker         2997                       # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker         1656                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst             349452                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             217161                       # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker         6371                       # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker         1905                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             535287                       # number of overall hits
+system.l2c.overall_hits::cpu1.data             243249                       # number of overall hits
+system.l2c.overall_hits::total                1358078                       # number of overall hits
 system.l2c.ReadReq_misses::cpu0.dtb.walker            1                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.itb.walker            2                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst             5732                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data             7847                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.itb.walker            3                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.inst             5500                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data             7825                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu1.dtb.walker            4                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.itb.walker            1                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst             5061                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data             3618                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                22266                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data          4882                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data          3680                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              8562                       # number of UpgradeReq misses
+system.l2c.ReadReq_misses::cpu1.inst             5275                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data             3652                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                22260                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data          3753                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data          4772                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              8525                       # number of UpgradeReq misses
 system.l2c.SCUpgradeReq_misses::cpu0.data          571                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data          474                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total            1045                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          67309                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          72458                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             139767                       # number of ReadExReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data          460                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total            1031                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data          63889                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data          75455                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             139344                       # number of ReadExReq misses
 system.l2c.demand_misses::cpu0.dtb.walker            1                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst              5732                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data             75156                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.itb.walker            3                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst              5500                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data             71714                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu1.dtb.walker            4                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.itb.walker            1                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              5061                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data             76076                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                162033                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst              5275                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data             79107                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                161604                       # number of demand (read+write) misses
 system.l2c.overall_misses::cpu0.dtb.walker            1                       # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst             5732                       # number of overall misses
-system.l2c.overall_misses::cpu0.data            75156                       # number of overall misses
+system.l2c.overall_misses::cpu0.itb.walker            3                       # number of overall misses
+system.l2c.overall_misses::cpu0.inst             5500                       # number of overall misses
+system.l2c.overall_misses::cpu0.data            71714                       # number of overall misses
 system.l2c.overall_misses::cpu1.dtb.walker            4                       # number of overall misses
-system.l2c.overall_misses::cpu1.itb.walker            1                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             5061                       # number of overall misses
-system.l2c.overall_misses::cpu1.data            76076                       # number of overall misses
-system.l2c.overall_misses::total               162033                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst             5275                       # number of overall misses
+system.l2c.overall_misses::cpu1.data            79107                       # number of overall misses
+system.l2c.overall_misses::total               161604                       # number of overall misses
 system.l2c.ReadReq_miss_latency::cpu0.dtb.walker        32000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.itb.walker       149500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.inst    403588750                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data    587952999                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.dtb.walker       347000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.itb.walker        74500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst    364948250                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data    284058750                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total     1641151749                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0.data     13131433                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data     12135478                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total     25266911                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data      1819924                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data      2531891                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total      4351815                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data   4527558160                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data   5454938401                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   9982496561                       # number of ReadExReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.itb.walker       224500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.inst    385138750                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.data    587705249                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.dtb.walker       334500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst    381420250                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data    283658250                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total     1638513499                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu0.data     11041523                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data     13954898                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total     24996421                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data      1841422                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data      2322900                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total      4164322                       # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data   4291032858                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data   5578462720                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   9869495578                       # number of ReadExReq miss cycles
 system.l2c.demand_miss_latency::cpu0.dtb.walker        32000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.itb.walker       149500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst    403588750                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data   5115511159                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker       347000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.itb.walker        74500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst    364948250                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data   5738997151                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total     11623648310                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.itb.walker       224500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.inst    385138750                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data   4878738107                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.dtb.walker       334500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst    381420250                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data   5862120970                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total     11508009077                       # number of demand (read+write) miss cycles
 system.l2c.overall_miss_latency::cpu0.dtb.walker        32000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.itb.walker       149500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst    403588750                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data   5115511159                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker       347000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.itb.walker        74500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst    364948250                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data   5738997151                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    11623648310                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.dtb.walker         3811                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker         1733                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst         425379                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data         213864                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker         5554                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker         1932                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst         469664                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data         146855                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            1268792                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       570959                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           570959                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data         6030                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data         4269                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total           10299                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.overall_miss_latency::cpu0.itb.walker       224500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.inst    385138750                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data   4878738107                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.dtb.walker       334500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst    381420250                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data   5862120970                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total    11508009077                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.dtb.walker         2998                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker         1659                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.inst         354952                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data         177750                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker         6375                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker         1905                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst         540562                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data         184489                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            1270690                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       572475                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           572475                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data         4796                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data         5359                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total           10155                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.SCUpgradeReq_accesses::cpu0.data          791                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data          574                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total          1365                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       124002                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data       125183                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           249185                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker         3811                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker         1733                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst          425379                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data          337866                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker         5554                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker         1932                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          469664                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          272038                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             1517977                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker         3811                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker         1733                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         425379                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data         337866                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker         5554                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker         1932                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         469664                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         272038                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            1517977                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000262                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.001154                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.013475                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.036692                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000720                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.000518                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.010776                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.024637                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.017549                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.809619                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.862029                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.831343                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_accesses::cpu1.data          544                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total          1335                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       111125                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data       137867                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           248992                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker         2998                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker         1659                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst          354952                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data          288875                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker         6375                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker         1905                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          540562                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data          322356                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             1519682                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker         2998                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker         1659                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         354952                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data         288875                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker         6375                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker         1905                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         540562                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data         322356                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            1519682                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000334                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.001808                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.015495                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.044023                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000627                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst      0.009758                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data      0.019795                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.017518                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.782527                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.890465                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.839488                       # miss rate for UpgradeReq accesses
 system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.721871                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.825784                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.765568                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.542806                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.578817                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.560897                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000262                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.001154                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.013475                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.222443                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000720                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker     0.000518                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.010776                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.279652                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.106743                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000262                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.001154                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.013475                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.222443                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000720                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker     0.000518                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.010776                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.279652                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.106743                       # miss rate for overall accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.845588                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.772285                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.574929                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.547303                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.559632                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000334                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.001808                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.015495                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.248253                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000627                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.009758                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.245403                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.106341                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000334                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.001808                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.015495                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.248253                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000627                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.009758                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.245403                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.106341                       # miss rate for overall accesses
 system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker        32000                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        74750                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 70409.760991                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 74927.105773                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        86750                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker        74500                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72109.909109                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 78512.645108                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 73706.626650                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  2689.765055                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  3297.684239                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  2951.052441                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  3187.257443                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  5341.542194                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  4164.416268                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 67265.271509                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 75284.142552                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 71422.414168                       # average ReadExReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 74833.333333                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.inst 70025.227273                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.data 75106.102109                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        83625                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72307.156398                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 77672.029025                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 73607.973899                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  2942.052491                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  2924.329003                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  2932.131496                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  3224.907180                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  5049.782609                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total  4039.109602                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 67163.875753                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 73930.988271                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 70828.278060                       # average ReadExReq miss latency
 system.l2c.demand_avg_miss_latency::cpu0.dtb.walker        32000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.itb.walker        74750                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 70409.760991                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 68065.239755                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        86750                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker        74500                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 72109.909109                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 75437.682725                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 71736.302543                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.itb.walker 74833.333333                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 70025.227273                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 68030.483685                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        83625                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 72307.156398                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 74103.694616                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 71211.164804                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu0.dtb.walker        32000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker        74750                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 70409.760991                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 68065.239755                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        86750                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker        74500                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 72109.909109                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 75437.682725                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 71736.302543                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.itb.walker 74833.333333                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 70025.227273                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 68030.483685                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        83625                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 72307.156398                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 74103.694616                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 71211.164804                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -943,8 +615,8 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               64268                       # number of writebacks
-system.l2c.writebacks::total                    64268                       # number of writebacks
+system.l2c.writebacks::writebacks               63942                       # number of writebacks
+system.l2c.writebacks::total                    63942                       # number of writebacks
 system.l2c.ReadReq_mshr_hits::cpu0.inst             1                       # number of ReadReq MSHR hits
 system.l2c.ReadReq_mshr_hits::total                 1                       # number of ReadReq MSHR hits
 system.l2c.demand_mshr_hits::cpu0.inst              1                       # number of demand (read+write) MSHR hits
@@ -952,162 +624,150 @@ system.l2c.demand_mshr_hits::total                  1                       # nu
 system.l2c.overall_mshr_hits::cpu0.inst             1                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::total                 1                       # number of overall MSHR hits
 system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker            1                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            2                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.inst         5731                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.data         7847                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            3                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.inst         5499                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.data         7825                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker            4                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.itb.walker            1                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst         5061                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data         3618                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total           22265                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data         4882                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data         3680                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total         8562                       # number of UpgradeReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.inst         5275                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.data         3652                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total           22259                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data         3753                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data         4772                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total         8525                       # number of UpgradeReq MSHR misses
 system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          571                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          474                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total         1045                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data        67309                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data        72458                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        139767                       # number of ReadExReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          460                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total         1031                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data        63889                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data        75455                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        139344                       # number of ReadExReq MSHR misses
 system.l2c.demand_mshr_misses::cpu0.dtb.walker            1                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.itb.walker            2                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst         5731                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data        75156                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.itb.walker            3                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst         5499                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data        71714                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu1.dtb.walker            4                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.itb.walker            1                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst         5061                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data        76076                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           162032                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst         5275                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data        79107                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           161603                       # number of demand (read+write) MSHR misses
 system.l2c.overall_mshr_misses::cpu0.dtb.walker            1                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.itb.walker            2                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst         5731                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data        75156                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.itb.walker            3                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst         5499                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data        71714                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu1.dtb.walker            4                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.itb.walker            1                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst         5061                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data        76076                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          162032                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst         5275                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data        79107                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          161603                       # number of overall MSHR misses
 system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker        20000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker       125000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    330890500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.data    490057499                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker       297000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker        62500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    300853250                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data    239085250                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total   1361390999                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     48852378                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     36863673                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total     85716051                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      5720067                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      4752971                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total     10473038                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   3658860326                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   4532497595                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   8191357921                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker       187500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    315394500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.data    490118749                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker       284500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    314655750                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data    238278250                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total   1358939249                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     37548751                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     47763765                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total     85312516                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      5717068                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      4604958                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total     10322026                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   3469064140                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   4618288780                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   8087352920                       # number of ReadExReq MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker        20000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       125000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst    330890500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data   4148917825                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       297000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.itb.walker        62500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst    300853250                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data   4771582845                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total   9552748920                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       187500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst    315394500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data   3959182889                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       284500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst    314655750                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data   4856567030                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   9446292169                       # number of demand (read+write) MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker        20000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       125000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst    330890500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data   4148917825                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       297000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.itb.walker        62500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst    300853250                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data   4771582845                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total   9552748920                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    345201250                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data  12458267494                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      5350750                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154290476246                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 167099295740                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   1046790495                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data  15722211628                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total  16769002123                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    345201250                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data  13505057989                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      5350750                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data 170012687874                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 183868297863                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000262                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.001154                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.013473                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.036692                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000720                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.000518                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.010776                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.024637                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.017548                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.809619                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.862029                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.831343                       # mshr miss rate for UpgradeReq accesses
+system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       187500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst    315394500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data   3959182889                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       284500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst    314655750                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data   4856567030                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   9446292169                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    352326000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data  11221595994                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      5508250                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 155529668246                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 167109098490                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   1041121994                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data  15728911223                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total  16770033217                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    352326000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data  12262717988                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      5508250                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data 171258579469                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 183879131707                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000334                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.001808                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.015492                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.044023                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000627                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.009758                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.019795                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.017517                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.782527                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.890465                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.839488                       # mshr miss rate for UpgradeReq accesses
 system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.721871                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.825784                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.765568                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.542806                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.578817                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.560897                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000262                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.001154                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.013473                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.222443                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000720                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.000518                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.010776                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.279652                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.106742                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000262                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.001154                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.013473                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.222443                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000720                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.000518                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.010776                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.279652                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.106742                       # mshr miss rate for overall accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.845588                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.772285                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.574929                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.547303                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.559632                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000334                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.001808                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.015492                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.248253                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000627                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.009758                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.245403                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.106340                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000334                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.001808                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.015492                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.248253                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000627                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.009758                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.245403                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.106340                       # mshr miss rate for overall accesses
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker        20000                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 57736.956901                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 62451.573722                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        74250                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker        62500                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59445.415926                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 66082.158651                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 61144.891040                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10006.632118                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10017.302446                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10011.218290                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10017.630473                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10027.364979                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10022.045933                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 54359.154437                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62553.446065                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 58607.238626                       # average ReadExReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 57354.882706                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 62634.983898                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        71125                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59650.379147                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65245.961117                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 61051.226425                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10004.996270                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10009.171207                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10007.333255                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10012.378284                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10010.778261                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10011.664403                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 54298.300803                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61205.868133                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 58038.759616                       # average ReadExReq mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker        20000                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 57736.956901                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 55204.079847                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        74250                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker        62500                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59445.415926                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62721.263539                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 58955.940308                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 57354.882706                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 55207.949480                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        71125                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59650.379147                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61392.380320                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 58453.693118                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker        20000                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        62500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 57736.956901                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 55204.079847                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        74250                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker        62500                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59445.415926                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62721.263539                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 58955.940308                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 57354.882706                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 55207.949480                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        71125                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59650.379147                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61392.380320                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 58453.693118                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
@@ -1128,62 +788,62 @@ system.cf0.dma_read_txs                             0                       # Nu
 system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
-system.toL2Bus.throughput                   119544694                       # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq            2535779                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp           2535779                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq            767577                       # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp           767577                       # Transaction distribution
-system.toL2Bus.trans_dist::Writeback           570959                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq           30837                       # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq         17592                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp          48429                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq           260947                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp          260947                       # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side       864602                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      1227966                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side         6129                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        12680                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side       940064                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side      4600791                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side         6258                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side        15477                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total               7673967                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     27250848                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     41432384                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side         6932                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        15244                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     30058932                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     39583066                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side         7728                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side        22216                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size::total          138377350                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus             138377350                       # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus         4615184                       # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy         4759626187                       # Layer occupancy (ticks)
+system.toL2Bus.throughput                   119642613                       # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq            2536412                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp           2536412                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq            767585                       # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp           767585                       # Transaction distribution
+system.toL2Bus.trans_dist::Writeback           572475                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq           30937                       # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq         17621                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp          48558                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq           260776                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp          260776                       # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side       723469                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side      1059051                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side         4339                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side         7907                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side      1082141                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side      4772543                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side         7929                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side        20256                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total               7677635                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side     22743520                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side     35146882                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side         6636                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side        11992                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side     34596404                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side     46050592                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side         7620                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side        25500                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size::total          138589146                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus             138589146                       # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus         4530356                       # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy         4766758175                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              0.4                       # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy        1926082966                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization             0.2                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy        1756498781                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy        1607753214                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization             0.1                       # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy        1517597206                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             0.1                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy           4396000                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy           2680000                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy           8869000                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy           4909499                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer3.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy        2116921475                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer6.occupancy        2437223968                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer6.utilization             0.2                       # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy        2926499865                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer7.utilization             0.2                       # Layer utilization (%)
-system.toL2Bus.respLayer8.occupancy           4326000                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.occupancy        3163938724                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.utilization             0.3                       # Layer utilization (%)
+system.toL2Bus.respLayer8.occupancy           6024000                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer8.utilization             0.0                       # Layer utilization (%)
-system.toL2Bus.respLayer9.occupancy           9923499                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer9.occupancy          13881500                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer9.utilization             0.0                       # Layer utilization (%)
-system.iobus.throughput                      45391348                       # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq              7671431                       # Transaction distribution
-system.iobus.trans_dist::ReadResp             7671431                       # Transaction distribution
-system.iobus.trans_dist::WriteReq                7963                       # Transaction distribution
-system.iobus.trans_dist::WriteResp               7963                       # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        30550                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         8056                       # Packet count per connected master and slave (bytes)
+system.iobus.throughput                      45388263                       # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq              7671442                       # Transaction distribution
+system.iobus.trans_dist::ReadResp             7671442                       # Transaction distribution
+system.iobus.trans_dist::WriteReq                7967                       # Transaction distribution
+system.iobus.trans_dist::WriteResp               7967                       # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        30566                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio         8070                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio          742                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio           36                       # Packet count per connected master and slave (bytes)
@@ -1205,12 +865,12 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio
 system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total      2382660                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total      2382690                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side     12976128                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.realview.clcd.dma::total     12976128                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                15358788                       # Packet count per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio        40319                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio        16112                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total                15358818                       # Packet count per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio        40335                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio        16140                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio         1484                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio           72                       # Cumulative packet size per connected master and slave (bytes)
@@ -1232,14 +892,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total      2390026                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::total      2390070                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side     51904512                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.realview.clcd.dma::total     51904512                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total             54294538                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus                54294538                       # Total data (bytes)
-system.iobus.reqLayer0.occupancy             21418000                       # Layer occupancy (ticks)
+system.iobus.tot_pkt_size::total             54294582                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus                54294582                       # Total data (bytes)
+system.iobus.reqLayer0.occupancy             21430000                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
-system.iobus.reqLayer1.occupancy              4034000                       # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy              4041000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer2.occupancy                34000                       # Layer occupancy (ticks)
 system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
@@ -1285,10 +945,10 @@ system.iobus.reqLayer23.occupancy                8000                       # La
 system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer25.occupancy          6488064000                       # Layer occupancy (ticks)
 system.iobus.reqLayer25.utilization               0.5                       # Layer utilization (%)
-system.iobus.respLayer0.occupancy          2374697000                       # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy          2374723000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.2                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy         17777962501                       # Layer occupancy (ticks)
-system.iobus.respLayer1.utilization               1.5                       # Layer utilization (%)
+system.iobus.respLayer1.occupancy         16195242500                       # Layer occupancy (ticks)
+system.iobus.respLayer1.utilization               1.4                       # Layer utilization (%)
 system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1312,25 +972,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                     7070497                       # DTB read hits
-system.cpu0.dtb.read_misses                      3747                       # DTB read misses
-system.cpu0.dtb.write_hits                    5655659                       # DTB write hits
-system.cpu0.dtb.write_misses                      806                       # DTB write misses
+system.cpu0.dtb.read_hits                     5879584                       # DTB read hits
+system.cpu0.dtb.read_misses                      2138                       # DTB read misses
+system.cpu0.dtb.write_hits                    4838515                       # DTB write hits
+system.cpu0.dtb.write_misses                      406                       # DTB write misses
 system.cpu0.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    1708                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_entries                    1387                       # Number of entries that have been flushed from TLB
 system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                   142                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults                    88                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      204                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                 7074244                       # DTB read accesses
-system.cpu0.dtb.write_accesses                5656465                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      203                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                 5881722                       # DTB read accesses
+system.cpu0.dtb.write_accesses                4838921                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         12726156                       # DTB hits
-system.cpu0.dtb.misses                           4553                       # DTB misses
-system.cpu0.dtb.accesses                     12730709                       # DTB accesses
+system.cpu0.dtb.hits                         10718099                       # DTB hits
+system.cpu0.dtb.misses                           2544                       # DTB misses
+system.cpu0.dtb.accesses                     10720643                       # DTB accesses
 system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1352,8 +1012,8 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu0.itb.inst_hits                    29571351                       # ITB inst hits
-system.cpu0.itb.inst_misses                      2205                       # ITB inst misses
+system.cpu0.itb.inst_hits                    24773464                       # ITB inst hits
+system.cpu0.itb.inst_misses                      1350                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
@@ -1362,95 +1022,94 @@ system.cpu0.itb.flush_tlb                           4                       # Nu
 system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
 system.cpu0.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    1181                       # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries                     963                       # Number of entries that have been flushed from TLB
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                29573556                       # ITB inst accesses
-system.cpu0.itb.hits                         29571351                       # DTB hits
-system.cpu0.itb.misses                           2205                       # DTB misses
-system.cpu0.itb.accesses                     29573556                       # DTB accesses
-system.cpu0.numCycles                      2392285746                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                24774814                       # ITB inst accesses
+system.cpu0.itb.hits                         24773464                       # DTB hits
+system.cpu0.itb.misses                           1350                       # DTB misses
+system.cpu0.itb.accesses                     24774814                       # DTB accesses
+system.cpu0.numCycles                      2391604989                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   28873226                       # Number of instructions committed
-system.cpu0.committedOps                     37212709                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             33137047                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                  3860                       # Number of float alu accesses
-system.cpu0.num_func_calls                    1242091                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      4373605                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    33137047                       # number of integer instructions
-system.cpu0.num_fp_insts                         3860                       # number of float instructions
-system.cpu0.num_int_register_reads          192300691                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          36265278                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads                3022                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes                840                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                     13394015                       # number of memory refs
-system.cpu0.num_load_insts                    7407936                       # Number of load instructions
-system.cpu0.num_store_insts                   5986079                       # Number of store instructions
-system.cpu0.num_idle_cycles              2246427166.466122                       # Number of idle cycles
-system.cpu0.num_busy_cycles              145858579.533878                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.060970                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.939030                       # Percentage of idle cycles
-system.cpu0.Branches                          5601726                       # Number of branches fetched
+system.cpu0.committedInsts                   24375312                       # Number of instructions committed
+system.cpu0.committedOps                     31460856                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses             28085533                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                  4364                       # Number of float alu accesses
+system.cpu0.num_func_calls                    1070699                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      3751745                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    28085533                       # number of integer instructions
+system.cpu0.num_fp_insts                         4364                       # number of float instructions
+system.cpu0.num_int_register_reads          162520351                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          30535592                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads                3980                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes                384                       # number of times the floating registers were written
+system.cpu0.num_mem_refs                     11309766                       # number of memory refs
+system.cpu0.num_load_insts                    6158982                       # Number of load instructions
+system.cpu0.num_store_insts                   5150784                       # Number of store instructions
+system.cpu0.num_idle_cycles              2265857607.135565                       # Number of idle cycles
+system.cpu0.num_busy_cycles              125747381.864435                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.052579                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.947421                       # Percentage of idle cycles
+system.cpu0.Branches                          4778581                       # Number of branches fetched
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   46915                       # number of quiesce instructions executed
-system.cpu0.icache.tags.replacements           425414                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          509.356883                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs           29145407                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs           425926                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs            68.428335                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle      76234819000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   509.356883                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.994838                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.994838                       # Average percentage of cache occupancy
+system.cpu0.kern.inst.quiesce                   39137                       # number of quiesce instructions executed
+system.cpu0.icache.tags.replacements           354708                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          509.352361                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           24418226                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           355220                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            68.741135                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      76254991000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   509.352361                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.994829                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.994829                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0           38                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1          196                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2          266                       # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::3           12                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2          464                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::3           47                       # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::4            1                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses         29997261                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses        29997261                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst     29145407                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       29145407                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     29145407                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        29145407                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     29145407                       # number of overall hits
-system.cpu0.icache.overall_hits::total       29145407                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       425927                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       425927                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       425927                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        425927                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       425927                       # number of overall misses
-system.cpu0.icache.overall_misses::total       425927                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   5899388216                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total   5899388216                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst   5899388216                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total   5899388216                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst   5899388216                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total   5899388216                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     29571334                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     29571334                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     29571334                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     29571334                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     29571334                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     29571334                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014403                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.014403                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014403                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.014403                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014403                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.014403                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13850.702623                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 13850.702623                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13850.702623                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 13850.702623                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13850.702623                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 13850.702623                       # average overall miss latency
+system.cpu0.icache.tags.tag_accesses         25128668                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses        25128668                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst     24418226                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       24418226                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     24418226                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        24418226                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     24418226                       # number of overall hits
+system.cpu0.icache.overall_hits::total       24418226                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       355221                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       355221                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       355221                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        355221                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       355221                       # number of overall misses
+system.cpu0.icache.overall_misses::total       355221                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   4963623214                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total   4963623214                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst   4963623214                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total   4963623214                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst   4963623214                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total   4963623214                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     24773447                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     24773447                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     24773447                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     24773447                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     24773447                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     24773447                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014339                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.014339                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014339                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.014339                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014339                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.014339                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13973.338327                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 13973.338327                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13973.338327                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 13973.338327                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13973.338327                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 13973.338327                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1459,128 +1118,126 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       425927                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       425927                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       425927                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       425927                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       425927                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       425927                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   5045293784                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total   5045293784                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   5045293784                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total   5045293784                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   5045293784                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total   5045293784                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    437016250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    437016250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    437016250                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency::total    437016250                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.014403                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.014403                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.014403                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.014403                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.014403                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.014403                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11845.442491                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11845.442491                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11845.442491                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 11845.442491                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11845.442491                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 11845.442491                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       355221                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       355221                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       355221                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       355221                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       355221                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       355221                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   4251043786                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total   4251043786                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   4251043786                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total   4251043786                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   4251043786                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total   4251043786                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    443885000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    443885000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    443885000                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total    443885000                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.014339                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.014339                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.014339                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.014339                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.014339                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.014339                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11967.321149                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11967.321149                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11967.321149                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 11967.321149                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11967.321149                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 11967.321149                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements           330503                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          455.093016                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs           12270625                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs           331015                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs            37.069695                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle        667204250                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   455.093016                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.888854                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.888854                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0           71                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1          345                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2           95                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses         50903218                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses        50903218                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data      6600273                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        6600273                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      5350518                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       5350518                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       147975                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       147975                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       149621                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       149621                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     11950791                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        11950791                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     11950791                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       11950791                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       227769                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       227769                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       141711                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       141711                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         9370                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total         9370                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data         7532                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total         7532                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       369480                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total        369480                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       369480                       # number of overall misses
-system.cpu0.dcache.overall_misses::total       369480                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   3309712250                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total   3309712250                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   5686464712                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total   5686464712                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data     92538750                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total     92538750                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     44740069                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total     44740069                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data   8996176962                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total   8996176962                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data   8996176962                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total   8996176962                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      6828042                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      6828042                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      5492229                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      5492229                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       157345                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       157345                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       157153                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       157153                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     12320271                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     12320271                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     12320271                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     12320271                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.033358                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.033358                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.025802                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.025802                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.059551                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.059551                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.047928                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.047928                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.029990                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.029990                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.029990                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.029990                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14531.004000                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 14531.004000                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40127.193457                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 40127.193457                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data  9876.067236                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  9876.067236                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  5939.998540                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  5939.998540                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24348.210896                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 24348.210896                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24348.210896                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 24348.210896                       # average overall miss latency
+system.cpu0.dcache.tags.replacements           278858                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          453.142717                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           10319958                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           279247                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            36.956379                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle        673996250                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   453.142717                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.885044                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.885044                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024          389                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2          379                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::3           10                       # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024     0.759766                       # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses         42855830                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses        42855830                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data      5473702                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        5473702                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      4567964                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       4567964                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       129389                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       129389                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       130155                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       130155                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     10041666                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        10041666                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     10041666                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       10041666                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       191503                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       191503                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       126416                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       126416                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         8708                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total         8708                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data         7742                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total         7742                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data       317919                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total        317919                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data       317919                       # number of overall misses
+system.cpu0.dcache.overall_misses::total       317919                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   2845005745                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total   2845005745                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   5278408391                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total   5278408391                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data     82648500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total     82648500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     45599070                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total     45599070                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data   8123414136                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total   8123414136                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data   8123414136                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total   8123414136                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      5665205                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      5665205                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      4694380                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      4694380                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       138097                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       138097                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       137897                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       137897                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     10359585                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     10359585                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     10359585                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     10359585                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.033803                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.033803                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.026929                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.026929                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.063057                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.063057                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.056143                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.056143                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.030688                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.030688                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.030688                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.030688                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14856.194133                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 14856.194133                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41754.274704                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 41754.274704                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data  9491.100138                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total  9491.100138                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  5889.830793                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  5889.830793                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25551.835958                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 25551.835958                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 25551.835958                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 25551.835958                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1589,62 +1246,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       306085                       # number of writebacks
-system.cpu0.dcache.writebacks::total           306085                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       227769                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       227769                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       141711                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       141711                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         9370                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         9370                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         7530                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total         7530                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       369480                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       369480                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       369480                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       369480                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2852244750                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   2852244750                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   5372105288                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   5372105288                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     73750250                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     73750250                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     29678931                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     29678931                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   8224350038                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total   8224350038                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   8224350038                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total   8224350038                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  13565968500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  13565968500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1170779500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1170779500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  14736748000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  14736748000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.033358                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.033358                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.025802                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.025802                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.059551                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059551                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.047915                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.047915                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.029990                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.029990                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.029990                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.029990                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12522.532698                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12522.532698                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37908.879960                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37908.879960                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data  7870.891142                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  7870.891142                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  3941.425100                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  3941.425100                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22259.256355                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22259.256355                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22259.256355                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22259.256355                       # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks       257140                       # number of writebacks
+system.cpu0.dcache.writebacks::total           257140                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       191503                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       191503                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       126416                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       126416                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         8708                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8708                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         7738                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total         7738                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       317919                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       317919                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       317919                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       317919                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2460118255                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   2460118255                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   4997663609                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4997663609                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     65185500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     65185500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     30121930                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     30121930                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   7457781864                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total   7457781864                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   7457781864                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total   7457781864                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  12214482000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  12214482000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1164635000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1164635000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  13379117000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  13379117000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.033803                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.033803                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.026929                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.026929                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.063057                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.063057                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.056114                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.056114                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.030688                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.030688                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.030688                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.030688                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12846.369274                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12846.369274                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39533.473682                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39533.473682                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data  7485.702802                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  7485.702802                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  3892.728095                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  3892.728095                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23458.119408                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23458.119408                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23458.119408                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23458.119408                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1675,25 +1332,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # D
 system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                     8312417                       # DTB read hits
-system.cpu1.dtb.read_misses                      3644                       # DTB read misses
-system.cpu1.dtb.write_hits                    5828126                       # DTB write hits
-system.cpu1.dtb.write_misses                     1438                       # DTB write misses
+system.cpu1.dtb.read_hits                     9507781                       # DTB read hits
+system.cpu1.dtb.read_misses                      5255                       # DTB read misses
+system.cpu1.dtb.write_hits                    6647969                       # DTB write hits
+system.cpu1.dtb.write_misses                     1834                       # DTB write misses
 system.cpu1.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    1864                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries                    2187                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   139                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                   188                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                      248                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                 8316061                       # DTB read accesses
-system.cpu1.dtb.write_accesses                5829564                       # DTB write accesses
+system.cpu1.dtb.perms_faults                      249                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                 9513036                       # DTB read accesses
+system.cpu1.dtb.write_accesses                6649803                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         14140543                       # DTB hits
-system.cpu1.dtb.misses                           5082                       # DTB misses
-system.cpu1.dtb.accesses                     14145625                       # DTB accesses
+system.cpu1.dtb.hits                         16155750                       # DTB hits
+system.cpu1.dtb.misses                           7089                       # DTB misses
+system.cpu1.dtb.accesses                     16162839                       # DTB accesses
 system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -1715,8 +1372,8 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
 system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu1.itb.inst_hits                    33196912                       # ITB inst hits
-system.cpu1.itb.inst_misses                      2171                       # ITB inst misses
+system.cpu1.itb.inst_hits                    38008437                       # ITB inst hits
+system.cpu1.itb.inst_misses                      3017                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
@@ -1725,94 +1382,95 @@ system.cpu1.itb.flush_tlb                           4                       # Nu
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
 system.cpu1.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                    1276                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                    1485                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                33199083                       # ITB inst accesses
-system.cpu1.itb.hits                         33196912                       # DTB hits
-system.cpu1.itb.misses                           2171                       # DTB misses
-system.cpu1.itb.accesses                     33199083                       # DTB accesses
-system.cpu1.numCycles                      2390815191                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                38011454                       # ITB inst accesses
+system.cpu1.itb.hits                         38008437                       # DTB hits
+system.cpu1.itb.misses                           3017                       # DTB misses
+system.cpu1.itb.accesses                     38011454                       # DTB accesses
+system.cpu1.numCycles                      2392450295                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   32585929                       # Number of instructions committed
-system.cpu1.committedOps                     41097454                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             37620588                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                  6793                       # Number of float alu accesses
-system.cpu1.num_func_calls                     962436                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      3733629                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    37620588                       # number of integer instructions
-system.cpu1.num_fp_insts                         6793                       # number of float instructions
-system.cpu1.num_int_register_reads          218203394                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          39762349                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads                4535                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes               2260                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                     14678716                       # number of memory refs
-system.cpu1.num_load_insts                    8634369                       # Number of load instructions
-system.cpu1.num_store_insts                   6044347                       # Number of store instructions
-system.cpu1.num_idle_cycles              1874341984.155535                       # Number of idle cycles
-system.cpu1.num_busy_cycles              516473206.844465                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.216024                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.783976                       # Percentage of idle cycles
-system.cpu1.Branches                          4945874                       # Number of branches fetched
+system.cpu1.committedInsts                   37097446                       # Number of instructions committed
+system.cpu1.committedOps                     46867102                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             42687988                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                  5457                       # Number of float alu accesses
+system.cpu1.num_func_calls                    1134316                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      4357000                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    42687988                       # number of integer instructions
+system.cpu1.num_fp_insts                         5457                       # number of float instructions
+system.cpu1.num_int_register_reads          248074220                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          45509439                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads                3577                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes               1884                       # number of times the floating registers were written
+system.cpu1.num_mem_refs                     16770062                       # number of memory refs
+system.cpu1.num_load_insts                    9887948                       # Number of load instructions
+system.cpu1.num_store_insts                   6882114                       # Number of store instructions
+system.cpu1.num_idle_cycles              1855714829.552449                       # Number of idle cycles
+system.cpu1.num_busy_cycles              536735465.447551                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.224346                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.775654                       # Percentage of idle cycles
+system.cpu1.Branches                          5771094                       # Number of branches fetched
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                   44317                       # number of quiesce instructions executed
-system.cpu1.icache.tags.replacements           469670                       # number of replacements
-system.cpu1.icache.tags.tagsinuse          478.560169                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs           32726726                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs           470182                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            69.604379                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle      94003216500                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst   478.560169                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.934688                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.934688                       # Average percentage of cache occupancy
+system.cpu1.kern.inst.quiesce                   52097                       # number of quiesce instructions executed
+system.cpu1.icache.tags.replacements           540849                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          478.554171                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs           37467072                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs           541361                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            69.209034                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle      94011084500                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst   478.554171                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.934676                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.934676                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2          448                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::3           63                       # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::4            1                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0           53                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1          244                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2          203                       # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::3           12                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses         33667090                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses        33667090                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst     32726726                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total       32726726                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst     32726726                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total        32726726                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst     32726726                       # number of overall hits
-system.cpu1.icache.overall_hits::total       32726726                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       470182                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       470182                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       470182                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        470182                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       470182                       # number of overall misses
-system.cpu1.icache.overall_misses::total       470182                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   6443403725                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   6443403725                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   6443403725                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   6443403725                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   6443403725                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   6443403725                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst     33196908                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total     33196908                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst     33196908                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total     33196908                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst     33196908                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total     33196908                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.014163                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.014163                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.014163                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.014163                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.014163                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.014163                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13704.062948                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 13704.062948                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13704.062948                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 13704.062948                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13704.062948                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 13704.062948                       # average overall miss latency
+system.cpu1.icache.tags.tag_accesses         38549794                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses        38549794                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst     37467072                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total       37467072                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst     37467072                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total        37467072                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst     37467072                       # number of overall hits
+system.cpu1.icache.overall_hits::total       37467072                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       541361                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       541361                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       541361                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        541361                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       541361                       # number of overall misses
+system.cpu1.icache.overall_misses::total       541361                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   7383473218                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   7383473218                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   7383473218                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   7383473218                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   7383473218                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   7383473218                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst     38008433                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total     38008433                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst     38008433                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total     38008433                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst     38008433                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total     38008433                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.014243                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.014243                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.014243                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.014243                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.014243                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.014243                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13638.723916                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 13638.723916                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13638.723916                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 13638.723916                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13638.723916                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 13638.723916                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1821,126 +1479,127 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       470182                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       470182                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       470182                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       470182                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       470182                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       470182                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   5501099275                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   5501099275                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   5501099275                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   5501099275                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   5501099275                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   5501099275                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      6820250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      6820250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      6820250                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total      6820250                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.014163                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.014163                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.014163                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.014163                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.014163                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.014163                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11699.935929                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11699.935929                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11699.935929                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 11699.935929                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11699.935929                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 11699.935929                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       541361                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       541361                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       541361                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       541361                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       541361                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       541361                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   6298814782                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   6298814782                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   6298814782                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   6298814782                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   6298814782                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   6298814782                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      6977250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      6977250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      6977250                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total      6977250                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.014243                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.014243                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.014243                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.014243                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.014243                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.014243                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11635.146939                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11635.146939                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11635.146939                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 11635.146939                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11635.146939                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 11635.146939                       # average overall mshr miss latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.tags.replacements           292321                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse          471.500981                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs           11963226                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs           292696                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs            40.872530                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle      85292295250                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data   471.500981                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.920900                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.920900                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024          375                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2          361                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::3           14                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.732422                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses         49443351                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses        49443351                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data      6947316                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        6947316                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      4827697                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       4827697                       # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        82016                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        82016                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        82738                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        82738                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data     11775013                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total        11775013                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data     11775013                       # number of overall hits
-system.cpu1.dcache.overall_hits::total       11775013                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       170735                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       170735                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data       150073                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total       150073                       # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        11224                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total        11224                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data        10063                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total        10063                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       320808                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        320808                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       320808                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       320808                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2220021998                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   2220021998                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   6568353267                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total   6568353267                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     96536250                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total     96536250                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     52014971                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total     52014971                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data   8788375265                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total   8788375265                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data   8788375265                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total   8788375265                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      7118051                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      7118051                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      4977770                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      4977770                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        93240                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        93240                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        92801                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        92801                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data     12095821                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total     12095821                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data     12095821                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total     12095821                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.023986                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.023986                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.030149                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.030149                       # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.120378                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.120378                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.108436                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.108436                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.026522                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.026522                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.026522                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.026522                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13002.735221                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 13002.735221                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 43767.721489                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 43767.721489                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  8600.877584                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  8600.877584                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  5168.932823                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  5168.932823                       # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 27394.501587                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 27394.501587                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 27394.501587                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 27394.501587                       # average overall miss latency
+system.cpu1.dcache.tags.replacements           343803                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          472.607785                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs           13921652                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs           344315                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            40.432894                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle      85311468250                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data   472.607785                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.923062                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.923062                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0           78                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::1          377                       # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2           57                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses         57519242                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses        57519242                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data      8078143                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        8078143                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      5612875                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       5612875                       # number of WriteReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data       100617                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total       100617                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data       102310                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total       102310                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data     13691018                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total        13691018                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data     13691018                       # number of overall hits
+system.cpu1.dcache.overall_hits::total       13691018                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       207066                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       207066                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data       165297                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total       165297                       # number of WriteReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        11987                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total        11987                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data         9884                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total         9884                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data       372363                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        372363                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       372363                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       372363                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2696827750                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   2696827750                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   6860807042                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total   6860807042                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    107474000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total    107474000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     50841959                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total     50841959                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data   9557634792                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total   9557634792                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data   9557634792                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total   9557634792                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      8285209                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      8285209                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      5778172                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      5778172                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data       112604                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total       112604                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data       112194                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total       112194                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data     14063381                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total     14063381                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data     14063381                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total     14063381                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.024992                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.024992                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.028607                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.028607                       # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.106453                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.106453                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.088097                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.088097                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.026477                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.026477                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.026477                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.026477                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13024.000802                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 13024.000802                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41505.938051                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 41505.938051                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  8965.879703                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  8965.879703                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  5143.864731                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  5143.864731                       # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 25667.520113                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 25667.520113                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 25667.520113                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 25667.520113                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1949,62 +1608,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks       264874                       # number of writebacks
-system.cpu1.dcache.writebacks::total           264874                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       170735                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total       170735                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       150073                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total       150073                       # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data        11224                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total        11224                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        10062                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total        10062                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       320808                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       320808                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       320808                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       320808                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1877877002                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1877877002                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   6244849733                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   6244849733                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     74077750                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     74077750                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     31889029                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     31889029                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   8122726735                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   8122726735                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   8122726735                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   8122726735                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168606064250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168606064250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  25182609871                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total  25182609871                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 193788674121                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 193788674121                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.023986                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.023986                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.030149                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.030149                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.120378                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.120378                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.108426                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.108426                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.026522                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.026522                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.026522                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.026522                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10998.781749                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10998.781749                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 41612.080341                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 41612.080341                       # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  6599.942088                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  6599.942088                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  3169.253528                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  3169.253528                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25319.589084                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25319.589084                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 25319.589084                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 25319.589084                       # average overall mshr miss latency
+system.cpu1.dcache.writebacks::writebacks       315335                       # number of writebacks
+system.cpu1.dcache.writebacks::total           315335                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       207066                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total       207066                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       165297                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total       165297                       # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data        11987                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total        11987                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data         9883                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total         9883                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       372363                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       372363                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       372363                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       372363                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   2282040250                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   2282040250                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   6506824958                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   6506824958                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     83489000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     83489000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     31075041                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     31075041                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   8788865208                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   8788865208                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   8788865208                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   8788865208                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169960243250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169960243250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  25194386277                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total  25194386277                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 195154629527                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 195154629527                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.024992                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.024992                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.028607                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.028607                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.106453                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.106453                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.088088                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.088088                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.026477                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.026477                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.026477                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.026477                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11020.835144                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11020.835144                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 39364.446772                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 39364.446772                       # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  6964.962042                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  6964.962042                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  3144.292320                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  3144.292320                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23602.949831                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23602.949831                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23602.949831                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23602.949831                       # average overall mshr miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
@@ -2028,10 +1687,10 @@ system.iocache.avg_blocked_cycles::no_mshrs          nan                       #
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 651823594501                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 651823594501                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 651823594501                       # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 651823594501                       # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 746722879500                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 746722879500                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 746722879500                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 746722879500                       # number of overall MSHR uncacheable cycles
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
index 524da38ffacee401d37161bba382cee435a885df..823848f29399306a5b01454fc414854cc8cdd844 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.616552                       # Number of seconds simulated
-sim_ticks                                2616552083000                       # Number of ticks simulated
-final_tick                               2616552083000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.616536                       # Number of seconds simulated
+sim_ticks                                2616536215000                       # Number of ticks simulated
+final_tick                               2616536215000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 423166                       # Simulator instruction rate (inst/s)
-host_op_rate                                   538494                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            18392483259                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 421292                       # Number of bytes of host memory used
-host_seconds                                   142.26                       # Real time elapsed on the host
-sim_insts                                    60200379                       # Number of instructions simulated
-sim_ops                                      76607188                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 594955                       # Simulator instruction rate (inst/s)
+host_op_rate                                   757104                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            25859148121                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 420956                       # Number of bytes of host memory used
+host_seconds                                   101.18                       # Real time elapsed on the host
+sim_insts                                    60200059                       # Number of instructions simulated
+sim_ops                                      76606878                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.realview.nvmem.bytes_read::cpu.inst           20                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu.inst           20                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total           20                       # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu.inst            5                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total              5                       # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu.inst             8                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total                8                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu.inst            8                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total            8                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.inst            8                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total               8                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bytes_read::realview.clcd    122683392                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.dtb.walker          320                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker          128                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.inst            703944                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9089880                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            132477664                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9089816                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            132477600                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read::cpu.inst       703944                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total          703944                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      3706304                       # Number of bytes written to this memory
+system.physmem.bytes_written::writebacks      3706240                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data        3016072                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6722376                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           6722312                       # Number of bytes written to this memory
 system.physmem.num_reads::realview.clcd      15335424                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.dtb.walker            5                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.itb.walker            2                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.inst              17211                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             142065                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total              15494707                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           57911                       # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu.data             142064                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total              15494706                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           57910                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data            754018                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               811929                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd        46887426                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total               811928                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd        46887710                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.dtb.walker            122                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.itb.walker             49                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               269035                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3473992                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                50630624                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          269035                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             269035                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1416484                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data             1152689                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2569173                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1416484                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd       46887426                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               269037                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3473988                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                50630906                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          269037                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             269037                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1416468                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data             1152696                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2569165                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1416468                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd       46887710                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.dtb.walker           122                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.itb.walker            49                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              269035                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             4626681                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               53199797                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                      15494707                       # Number of read requests accepted
-system.physmem.writeReqs                       811929                       # Number of write requests accepted
-system.physmem.readBursts                    15494707                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     811929                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                991550144                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                    111104                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   6844864                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 132477664                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                6722376                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                     1736                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                  704958                       # Number of DRAM write bursts merged with an existing one
+system.physmem.bw_total::cpu.inst              269037                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             4626685                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               53200071                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                      15494706                       # Number of read requests accepted
+system.physmem.writeReqs                       811928                       # Number of write requests accepted
+system.physmem.readBursts                    15494706                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     811928                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                991531648                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                    129536                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   6740736                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 132477600                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                6722312                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                     2024                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                  706583                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs           4515                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              967983                       # Per bank write bursts
+system.physmem.perBankRdBursts::0              967775                       # Per bank write bursts
 system.physmem.perBankRdBursts::1              967715                       # Per bank write bursts
 system.physmem.perBankRdBursts::2              967672                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              967769                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              974609                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              968229                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              967819                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              967736                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              968546                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              967748                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              974561                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              968173                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              967769                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              967703                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              968545                       # Per bank write bursts
 system.physmem.perBankRdBursts::9              968137                       # Per bank write bursts
 system.physmem.perBankRdBursts::10             967949                       # Per bank write bursts
 system.physmem.perBankRdBursts::11             967746                       # Per bank write bursts
 system.physmem.perBankRdBursts::12             967851                       # Per bank write bursts
 system.physmem.perBankRdBursts::13             967741                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             967672                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             967800                       # Per bank write bursts
 system.physmem.perBankRdBursts::15             967797                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                6609                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                6410                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                6425                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                6343                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                6914                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7103                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6905                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                6899                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7185                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                6844                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               6668                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               6551                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               6595                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               6390                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               6535                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               6575                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                6510                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                6313                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                6323                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                6241                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                6804                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                6995                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6800                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                6791                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7084                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                6747                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               6568                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               6457                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               6495                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               6295                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               6428                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               6473                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    2616547722000                       # Total gap between requests
+system.physmem.totGap                    2616531854000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                    6664                       # Read request sizes (log2)
 system.physmem.readPktSize::3                15335424                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  152619                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  152618                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                 754018                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  57911                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1246677                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                   1099488                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                   1103361                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                   3738048                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                   2684438                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                   2678406                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                   2686634                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                     54458                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                     57693                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                     20801                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                    20770                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                    20680                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                    20429                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                    20361                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                    20300                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                    20267                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      160                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  57910                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1116573                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    960474                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                    961347                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                    975907                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                    963056                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                    965451                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                   2812276                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                   2805674                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                   3709925                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                     42008                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                    34639                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                    36264                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                    33338                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                    31474                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                    22310                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                    21858                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                      108                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
@@ -156,563 +144,198 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                      4862                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                      4862                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                      4864                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                      4862                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                      4862                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                      4862                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                      4863                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                      4862                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                      4862                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                      4862                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                     4862                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                     4863                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                     4862                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                     4862                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                     4863                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     4862                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     4862                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4862                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4863                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     4863                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     4862                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     4862                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        89706                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean    11129.630393                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean    1027.657053                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev   16709.623735                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64-71          23265     25.93%     25.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-135        14539     16.21%     42.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192-199         2841      3.17%     45.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-263         2049      2.28%     47.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320-327         1384      1.54%     49.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-391         1206      1.34%     50.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448-455          956      1.07%     51.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-519         1124      1.25%     52.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576-583          653      0.73%     53.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-647          549      0.61%     54.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704-711          562      0.63%     54.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-775          672      0.75%     55.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832-839          328      0.37%     55.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-903          247      0.28%     56.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960-967          203      0.23%     56.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1031          737      0.82%     57.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088-1095          166      0.19%     57.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152-1159          154      0.17%     57.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216-1223          147      0.16%     57.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280-1287          151      0.17%     57.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344-1351          100      0.11%     58.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408-1415         2290      2.55%     60.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472-1479          108      0.12%     60.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536-1543          177      0.20%     60.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600-1607           64      0.07%     60.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664-1671           54      0.06%     61.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1728-1735           47      0.05%     61.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1792-1799          132      0.15%     61.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856-1863           30      0.03%     61.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1920-1927           28      0.03%     61.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984-1991           20      0.02%     61.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2048-2055          301      0.34%     61.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112-2119           24      0.03%     61.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2176-2183           30      0.03%     61.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2240-2247           15      0.02%     61.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2304-2311          101      0.11%     61.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2368-2375           18      0.02%     61.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2432-2439           16      0.02%     61.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2496-2503           24      0.03%     61.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2560-2567           89      0.10%     61.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2624-2631            8      0.01%     61.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2688-2695           22      0.02%     62.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2752-2759           13      0.01%     62.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2816-2823          154      0.17%     62.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2880-2887           15      0.02%     62.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2944-2951           13      0.01%     62.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3008-3015           13      0.01%     62.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3072-3079          380      0.42%     62.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3136-3143           14      0.02%     62.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3200-3207           15      0.02%     62.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3264-3271           13      0.01%     62.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3328-3335          154      0.17%     62.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3392-3399           16      0.02%     62.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3456-3463           17      0.02%     62.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3520-3527           10      0.01%     62.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3584-3591           98      0.11%     63.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3648-3655           14      0.02%     63.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3712-3719           13      0.01%     63.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3776-3783           34      0.04%     63.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3840-3847           92      0.10%     63.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3904-3911           11      0.01%     63.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3968-3975           10      0.01%     63.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4032-4039            9      0.01%     63.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4096-4103          228      0.25%     63.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4160-4167            7      0.01%     63.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4224-4231            8      0.01%     63.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4288-4295            6      0.01%     63.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4352-4359          164      0.18%     63.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4416-4423           10      0.01%     63.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4480-4487            9      0.01%     63.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4544-4551            9      0.01%     63.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4608-4615           80      0.09%     63.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4672-4679            9      0.01%     63.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4736-4743            6      0.01%     63.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4800-4807            8      0.01%     63.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4864-4871           90      0.10%     63.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4928-4935            8      0.01%     63.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4992-4999            8      0.01%     63.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5056-5063            9      0.01%     63.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5120-5127          436      0.49%     64.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5184-5191           10      0.01%     64.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5248-5255            7      0.01%     64.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5312-5319            8      0.01%     64.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5376-5383           28      0.03%     64.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5440-5447           18      0.02%     64.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5504-5511           68      0.08%     64.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5568-5575           11      0.01%     64.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5632-5639          279      0.31%     64.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5696-5703            1      0.00%     64.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5760-5767            1      0.00%     64.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5888-5895           70      0.08%     65.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6016-6023            2      0.00%     65.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6144-6151          270      0.30%     65.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6336-6343            1      0.00%     65.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6400-6407           20      0.02%     65.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6528-6535            3      0.00%     65.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6592-6599            1      0.00%     65.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6656-6663           82      0.09%     65.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6784-6791            3      0.00%     65.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6912-6919          143      0.16%     65.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6976-6983            1      0.00%     65.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7040-7047            2      0.00%     65.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7168-7175          411      0.46%     66.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7232-7239            1      0.00%     66.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7424-7431           87      0.10%     66.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7680-7687           21      0.02%     66.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7744-7751            1      0.00%     66.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7808-7815            1      0.00%     66.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7936-7943           78      0.09%     66.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8064-8071            2      0.00%     66.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8192-8199          402      0.45%     66.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8256-8263            2      0.00%     66.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8448-8455           81      0.09%     66.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8704-8711           23      0.03%     66.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8832-8839            1      0.00%     66.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8960-8967           84      0.09%     66.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9024-9031            1      0.00%     66.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9088-9095            5      0.01%     66.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9216-9223          405      0.45%     67.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9472-9479          148      0.16%     67.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9728-9735           87      0.10%     67.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9984-9991           20      0.02%     67.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10048-10055            1      0.00%     67.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10112-10119            2      0.00%     67.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10240-10247          273      0.30%     68.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10304-10311            1      0.00%     68.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10496-10503           69      0.08%     68.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10624-10631            1      0.00%     68.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10752-10759          145      0.16%     68.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10816-10823            1      0.00%     68.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11008-11015           18      0.02%     68.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11072-11079            1      0.00%     68.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11136-11143            7      0.01%     68.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11264-11271          431      0.48%     68.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11520-11527           83      0.09%     68.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11776-11783           80      0.09%     68.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12032-12039          159      0.18%     69.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12160-12167            2      0.00%     69.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12288-12295          208      0.23%     69.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12480-12487            3      0.00%     69.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12544-12551           82      0.09%     69.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12800-12807           88      0.10%     69.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12928-12935            2      0.00%     69.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12992-12999            1      0.00%     69.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13056-13063          148      0.16%     69.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13184-13191            3      0.00%     69.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13312-13319          354      0.39%     70.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13440-13447            2      0.00%     70.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13568-13575          141      0.16%     70.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13632-13639            1      0.00%     70.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13824-13831           73      0.08%     70.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14080-14087           83      0.09%     70.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14208-14215            3      0.00%     70.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14272-14279            1      0.00%     70.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14336-14343          279      0.31%     70.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14400-14407            1      0.00%     70.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14464-14471            1      0.00%     70.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14592-14599           93      0.10%     70.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14656-14663            1      0.00%     70.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14848-14855           91      0.10%     70.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14976-14983            1      0.00%     70.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15104-15111           15      0.02%     70.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15232-15239            4      0.00%     70.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15360-15367          490      0.55%     71.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15424-15431            1      0.00%     71.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15552-15559            1      0.00%     71.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15616-15623           72      0.08%     71.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15744-15751            2      0.00%     71.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15872-15879          143      0.16%     71.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16128-16135           77      0.09%     71.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16256-16263           10      0.01%     71.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16384-16391          534      0.60%     72.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16640-16647           75      0.08%     72.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16704-16711            1      0.00%     72.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16768-16775            2      0.00%     72.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16896-16903          145      0.16%     72.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17152-17159           76      0.08%     72.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17280-17287            3      0.00%     72.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17408-17415          492      0.55%     73.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17472-17479            1      0.00%     73.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17664-17671           16      0.02%     73.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17856-17863            2      0.00%     73.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::17920-17927           87      0.10%     73.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18048-18055            2      0.00%     73.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18176-18183           95      0.11%     73.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18240-18247            2      0.00%     73.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18304-18311            4      0.00%     73.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18432-18439          275      0.31%     73.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18560-18567            1      0.00%     73.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18688-18695           81      0.09%     73.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::18944-18951           73      0.08%     74.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19072-19079            1      0.00%     74.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19200-19207          143      0.16%     74.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19328-19335            2      0.00%     74.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19392-19399            1      0.00%     74.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19456-19463          347      0.39%     74.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19584-19591            2      0.00%     74.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19712-19719          136      0.15%     74.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19776-19783            1      0.00%     74.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::19968-19975           88      0.10%     74.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20032-20039            1      0.00%     74.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20160-20167            2      0.00%     74.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20224-20231           84      0.09%     74.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20352-20359            5      0.01%     74.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20480-20487          216      0.24%     75.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20544-20551            1      0.00%     75.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20736-20743          155      0.17%     75.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::20992-20999           77      0.09%     75.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21184-21191            1      0.00%     75.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21248-21255           79      0.09%     75.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21376-21383            5      0.01%     75.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21440-21447            1      0.00%     75.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21504-21511          419      0.47%     76.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21632-21639            1      0.00%     76.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21696-21703            1      0.00%     76.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21760-21767           21      0.02%     76.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::21888-21895            1      0.00%     76.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22016-22023          147      0.16%     76.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22272-22279           72      0.08%     76.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22336-22343            1      0.00%     76.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22400-22407            4      0.00%     76.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22528-22535          265      0.30%     76.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::22784-22791           21      0.02%     76.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23040-23047           84      0.09%     76.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23168-23175            1      0.00%     76.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23296-23303          141      0.16%     76.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23424-23431            5      0.01%     76.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23488-23495            1      0.00%     76.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23552-23559          410      0.46%     77.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23680-23687            1      0.00%     77.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::23808-23815           87      0.10%     77.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24064-24071           18      0.02%     77.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24320-24327           80      0.09%     77.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24384-24391            1      0.00%     77.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24448-24455            3      0.00%     77.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24576-24583          395      0.44%     78.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24704-24711            2      0.00%     78.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24832-24839           76      0.08%     78.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::24896-24903            1      0.00%     78.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25088-25095           19      0.02%     78.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25280-25287            1      0.00%     78.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25344-25351           88      0.10%     78.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25472-25479            2      0.00%     78.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25600-25607          409      0.46%     78.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25728-25735            1      0.00%     78.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25856-25863          141      0.16%     78.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25920-25927            2      0.00%     78.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::25984-25991            1      0.00%     78.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26112-26119           88      0.10%     78.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26240-26247            1      0.00%     78.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26304-26311            1      0.00%     78.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26368-26375           20      0.02%     78.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26496-26503            3      0.00%     78.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26624-26631          274      0.31%     79.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26688-26695            1      0.00%     79.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::26880-26887           69      0.08%     79.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27008-27015            2      0.00%     79.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27136-27143          144      0.16%     79.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27392-27399           23      0.03%     79.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27456-27463            1      0.00%     79.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27520-27527            1      0.00%     79.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27648-27655          414      0.46%     79.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27776-27783            1      0.00%     79.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::27904-27911           80      0.09%     80.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28032-28039            2      0.00%     80.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28160-28167           76      0.08%     80.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28288-28295            1      0.00%     80.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28352-28359            1      0.00%     80.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28416-28423          158      0.18%     80.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28480-28487            1      0.00%     80.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28544-28551            2      0.00%     80.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28672-28679          213      0.24%     80.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28928-28935           78      0.09%     80.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::28992-28999            1      0.00%     80.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29184-29191           89      0.10%     80.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29248-29255            1      0.00%     80.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29312-29319            2      0.00%     80.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29440-29447          137      0.15%     80.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29504-29511            1      0.00%     80.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29568-29575            1      0.00%     80.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29696-29703          346      0.39%     81.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29824-29831            1      0.00%     81.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29888-29895            2      0.00%     81.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::29952-29959          142      0.16%     81.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30080-30087            1      0.00%     81.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30208-30215           72      0.08%     81.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30336-30343            1      0.00%     81.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30400-30407            2      0.00%     81.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30464-30471           82      0.09%     81.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30592-30599            4      0.00%     81.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30720-30727          276      0.31%     81.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30784-30791            1      0.00%     81.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30848-30855            1      0.00%     81.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::30976-30983           91      0.10%     82.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31168-31175            1      0.00%     82.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31232-31239           88      0.10%     82.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31488-31495           20      0.02%     82.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31616-31623            5      0.01%     82.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31680-31687            1      0.00%     82.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::31744-31751          482      0.54%     82.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32000-32007           73      0.08%     82.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32128-32135            1      0.00%     82.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32256-32263          142      0.16%     82.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32320-32327            2      0.00%     82.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32384-32391            2      0.00%     82.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32512-32519           83      0.09%     83.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32640-32647            1      0.00%     83.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32704-32711            1      0.00%     83.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32768-32775          535      0.60%     83.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32832-32839            1      0.00%     83.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::32896-32903            1      0.00%     83.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33024-33031           89      0.10%     83.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33280-33287          149      0.17%     83.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33408-33415            5      0.01%     83.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33536-33543           76      0.08%     84.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33792-33799          481      0.54%     84.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::33856-33863            1      0.00%     84.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34048-34055           15      0.02%     84.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34304-34311           88      0.10%     84.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34368-34375            1      0.00%     84.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34432-34439            2      0.00%     84.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34560-34567           92      0.10%     84.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34624-34631            1      0.00%     84.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34688-34695            3      0.00%     84.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34816-34823          267      0.30%     85.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::34944-34951            2      0.00%     85.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35072-35079           81      0.09%     85.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35136-35143            1      0.00%     85.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35200-35207            1      0.00%     85.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35328-35335           74      0.08%     85.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35584-35591          144      0.16%     85.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35648-35655            1      0.00%     85.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35712-35719            2      0.00%     85.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::35840-35847          346      0.39%     85.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36032-36039            1      0.00%     85.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36096-36103          134      0.15%     85.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36288-36295            1      0.00%     85.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36352-36359           86      0.10%     86.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36480-36487            1      0.00%     86.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36544-36551            1      0.00%     86.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36608-36615           79      0.09%     86.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36736-36743            1      0.00%     86.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36864-36871          207      0.23%     86.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::36992-36999            2      0.00%     86.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37056-37063            1      0.00%     86.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37120-37127          154      0.17%     86.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37184-37191            1      0.00%     86.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37376-37383           75      0.08%     86.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37504-37511            2      0.00%     86.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37632-37639           87      0.10%     86.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::37888-37895          418      0.47%     87.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38016-38023            2      0.00%     87.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38080-38087            1      0.00%     87.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38144-38151           20      0.02%     87.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38208-38215            1      0.00%     87.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38400-38407          142      0.16%     87.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38528-38535            3      0.00%     87.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38656-38663           69      0.08%     87.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38848-38855            1      0.00%     87.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::38912-38919          267      0.30%     87.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39040-39047            1      0.00%     87.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39168-39175           18      0.02%     87.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39232-39239            1      0.00%     87.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39296-39303            2      0.00%     87.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39424-39431           85      0.09%     87.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39552-39559            1      0.00%     87.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39616-39623            2      0.00%     87.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39680-39687          145      0.16%     88.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::39936-39943          411      0.46%     88.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40192-40199           83      0.09%     88.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40256-40263            1      0.00%     88.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40320-40327            2      0.00%     88.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40448-40455           16      0.02%     88.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40576-40583            3      0.00%     88.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40640-40647            1      0.00%     88.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40704-40711           79      0.09%     88.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::40960-40967          395      0.44%     89.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41152-41159            1      0.00%     89.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41216-41223           77      0.09%     89.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41344-41351            1      0.00%     89.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41472-41479           17      0.02%     89.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41600-41607            3      0.00%     89.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41728-41735           89      0.10%     89.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::41984-41991          405      0.45%     89.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42048-42055            1      0.00%     89.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42112-42119            2      0.00%     89.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42240-42247          142      0.16%     89.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42368-42375            1      0.00%     89.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42496-42503           82      0.09%     90.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42624-42631            4      0.00%     90.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::42752-42759           22      0.02%     90.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43008-43015          265      0.30%     90.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43136-43143            1      0.00%     90.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43200-43207            1      0.00%     90.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43264-43271           69      0.08%     90.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43520-43527          144      0.16%     90.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43648-43655            4      0.00%     90.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43776-43783           21      0.02%     90.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::43840-43847            1      0.00%     90.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44032-44039          417      0.46%     91.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44096-44103            1      0.00%     91.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44160-44167            1      0.00%     91.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44288-44295           79      0.09%     91.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44544-44551           77      0.09%     91.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44672-44679            4      0.00%     91.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::44800-44807          154      0.17%     91.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45056-45063          203      0.23%     91.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45184-45191            1      0.00%     91.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45312-45319           82      0.09%     91.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45440-45447            1      0.00%     91.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45504-45511            1      0.00%     91.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45568-45575           88      0.10%     91.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45696-45703            2      0.00%     91.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45760-45767            1      0.00%     91.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45824-45831          135      0.15%     92.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::45952-45959            2      0.00%     92.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46080-46087          348      0.39%     92.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46336-46343          145      0.16%     92.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46592-46599           73      0.08%     92.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46720-46727            2      0.00%     92.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46848-46855           84      0.09%     92.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::46976-46983            3      0.00%     92.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47104-47111          268      0.30%     93.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47232-47239            2      0.00%     93.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47296-47303            1      0.00%     93.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47360-47367           92      0.10%     93.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47424-47431            1      0.00%     93.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47616-47623           87      0.10%     93.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47680-47687            1      0.00%     93.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47744-47751            4      0.00%     93.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::47872-47879           19      0.02%     93.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48064-48071            1      0.00%     93.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48128-48135          511      0.57%     93.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48192-48199            2      0.00%     93.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48256-48263            1      0.00%     93.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48320-48327            2      0.00%     93.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48384-48391           90      0.10%     94.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48640-48647          140      0.16%     94.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48768-48775           73      0.08%     94.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48896-48903           73      0.08%     94.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::48960-48967            6      0.01%     94.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::49024-49031            6      0.01%     94.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::49088-49095            7      0.01%     94.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::49152-49159         5078      5.66%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          89706                       # Bytes accessed per row activation
-system.physmem.totQLat                   373696644500                       # Total ticks spent queuing
-system.physmem.totMemAccLat              469604897000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                  77464855000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                 18443397500                       # Total ticks spent accessing banks
-system.physmem.avgQLat                       24120.40                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                     1190.44                       # Average bank access latency per DRAM burst
+system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     2478                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     2541                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     3152                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     4807                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     4792                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     4786                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     4793                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     4827                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     4839                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     4834                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     5981                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     4975                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     4962                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     5804                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     4869                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     4878                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     4878                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     4793                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     1099                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                     1078                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                     1070                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                     1076                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                     1063                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                     1063                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                     1060                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                     1060                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                     1060                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                     1060                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                     1060                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                     1060                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                     1060                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                     1060                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                     1060                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                     1059                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                     1059                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                     1059                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                     1059                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                     1058                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                     1058                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       977394                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean     1014.625651                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean    1002.644045                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev      87.222028                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127           3543      0.36%      0.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         3286      0.34%      0.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         1787      0.18%      0.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         1165      0.12%      1.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639          902      0.09%      1.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          711      0.07%      1.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          580      0.06%      1.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          432      0.04%      1.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151       964988     98.73%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         977394                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          4784                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean      3238.435619                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev    134294.504205                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-524287         4779     99.90%     99.90% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::524288-1.04858e+06            3      0.06%     99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1.04858e+06-1.57286e+06            1      0.02%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::8.9129e+06-9.43718e+06            1      0.02%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            4784                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          4784                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        22.015886                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       20.524536                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        9.242033                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               2224     46.49%     46.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 36      0.75%     47.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                227      4.74%     51.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19               1224     25.59%     77.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                  8      0.17%     77.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                  4      0.08%     77.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                  1      0.02%     77.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::33                  1      0.02%     77.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::34                  1      0.02%     77.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::39                945     19.75%     97.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40                 67      1.40%     99.04% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::41                 15      0.31%     99.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::42                 31      0.65%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            4784                       # Writes before turning the bus around for reads
+system.physmem.totQLat                   588095657500                       # Total ticks spent queuing
+system.physmem.totMemAccLat              694960871250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                  77463410000                       # Total ticks spent in databus transfers
+system.physmem.totBankLat                 29401803750                       # Total ticks spent accessing banks
+system.physmem.avgQLat                       37959.58                       # Average queueing delay per DRAM burst
+system.physmem.avgBankLat                     1897.79                       # Average bank access latency per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  30310.84                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  44857.36                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                         378.95                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           2.62                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgWrBW                           2.58                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                       50.63                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        2.57                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           2.98                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       2.96                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.02                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         0.18                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        14.55                       # Average write queue length when enqueuing
-system.physmem.readRowHits                   15419069                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     91147                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   99.52                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  85.21                       # Row buffer hit rate for writes
-system.physmem.avgGap                       160459.07                       # Average gap between requests
-system.physmem.pageHitRate                      99.42                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               2.19                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                     54116372                       # Throughput (bytes/s)
+system.physmem.avgRdQLen                         7.03                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        29.46                       # Average write queue length when enqueuing
+system.physmem.readRowHits                   14490606                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     90101                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   93.53                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  85.53                       # Row buffer hit rate for writes
+system.physmem.avgGap                       160458.12                       # Average gap between requests
+system.physmem.pageHitRate                      93.48                       # Row buffer hit rate, read and write combined
+system.physmem.prechargeAllPercent               3.85                       # Percentage of time for which DRAM has all the banks in precharge state
+system.realview.nvmem.bytes_read::cpu.inst           20                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu.inst           20                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total           20                       # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu.inst            5                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total              5                       # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu.inst             8                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total                8                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu.inst            8                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total            8                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.inst            8                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total               8                       # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput                     54116651                       # Throughput (bytes/s)
 system.membus.trans_dist::ReadReq            16546597                       # Transaction distribution
 system.membus.trans_dist::ReadResp           16546597                       # Transaction distribution
 system.membus.trans_dist::WriteReq             763385                       # Transaction distribution
 system.membus.trans_dist::WriteResp            763385                       # Transaction distribution
-system.membus.trans_dist::Writeback             57911                       # Transaction distribution
+system.membus.trans_dist::Writeback             57910                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq             4515                       # Transaction distribution
 system.membus.trans_dist::UpgradeResp            4515                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            132218                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           132218                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            132217                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           132217                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave      2383088                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           10                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         3850                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio            2                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1893543                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      4280493                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1893540                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      4280490                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::system.physmem.port     30670848                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.iocache.mem_side::total     30670848                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total               34951341                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total               34951338                       # Packet count per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave      2390542                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port           20                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio         7700                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio            4                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16516648                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     18914914                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16516520                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     18914786                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port    122683392                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.iocache.mem_side::total    122683392                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total           141598306                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus              141598306                       # Total data (bytes)
+system.membus.tot_pkt_size::total           141598178                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus              141598178                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy          1206226000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy          1206225000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer1.occupancy                5000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             3614000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             3615000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
 system.membus.reqLayer4.occupancy                1000                       # Layer occupancy (ticks)
 system.membus.reqLayer4.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer6.occupancy         17910626500                       # Layer occupancy (ticks)
+system.membus.reqLayer6.occupancy         17911294000                       # Layer occupancy (ticks)
 system.membus.reqLayer6.utilization               0.7                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         4950468826                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         4951349139                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
-system.membus.respLayer2.occupancy        34635984750                       # Layer occupancy (ticks)
-system.membus.respLayer2.utilization              1.3                       # Layer utilization (%)
+system.membus.respLayer2.occupancy        38238689000                       # Layer occupancy (ticks)
+system.membus.respLayer2.utilization              1.5                       # Layer utilization (%)
 system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
 system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
 system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
-system.iobus.throughput                      47801049                       # Throughput (bytes/s)
+system.iobus.throughput                      47801339                       # Throughput (bytes/s)
 system.iobus.trans_dist::ReadReq             16518785                       # Transaction distribution
 system.iobus.trans_dist::ReadResp            16518785                       # Transaction distribution
 system.iobus.trans_dist::WriteReq                8183                       # Transaction distribution
@@ -822,8 +445,8 @@ system.iobus.reqLayer25.occupancy         15335424000                       # La
 system.iobus.reqLayer25.utilization               0.6                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy          2374905000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.1                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy         42035727250                       # Layer occupancy (ticks)
-system.iobus.respLayer1.utilization               1.6                       # Layer utilization (%)
+system.iobus.respLayer1.occupancy         38265059000                       # Layer occupancy (ticks)
+system.iobus.respLayer1.utilization               1.5                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
@@ -848,25 +471,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DT
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     14996193                       # DTB read hits
-system.cpu.dtb.read_misses                       7334                       # DTB read misses
-system.cpu.dtb.write_hits                    11230326                       # DTB write hits
-system.cpu.dtb.write_misses                      2212                       # DTB write misses
+system.cpu.dtb.read_hits                     14996179                       # DTB read hits
+system.cpu.dtb.read_misses                       7337                       # DTB read misses
+system.cpu.dtb.write_hits                    11230334                       # DTB write hits
+system.cpu.dtb.write_misses                      2213                       # DTB write misses
 system.cpu.dtb.flush_tlb                            2                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
 system.cpu.dtb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                     3405                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.flush_entries                     3411                       # Number of entries that have been flushed from TLB
 system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                    192                       # Number of TLB faults due to prefetch
+system.cpu.dtb.prefetch_faults                    194                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
 system.cpu.dtb.perms_faults                       452                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 15003527                       # DTB read accesses
-system.cpu.dtb.write_accesses                11232538                       # DTB write accesses
+system.cpu.dtb.read_accesses                 15003516                       # DTB read accesses
+system.cpu.dtb.write_accesses                11232547                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          26226519                       # DTB hits
-system.cpu.dtb.misses                            9546                       # DTB misses
-system.cpu.dtb.accesses                      26236065                       # DTB accesses
+system.cpu.dtb.hits                          26226513                       # DTB hits
+system.cpu.dtb.misses                            9550                       # DTB misses
+system.cpu.dtb.accesses                      26236063                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
 system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
 system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
@@ -888,7 +511,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.inst_hits                     61494253                       # ITB inst hits
+system.cpu.itb.inst_hits                     61493932                       # ITB inst hits
 system.cpu.itb.inst_misses                       4471                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
@@ -905,88 +528,88 @@ system.cpu.itb.domain_faults                        0                       # Nu
 system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                 61498724                       # ITB inst accesses
-system.cpu.itb.hits                          61494253                       # DTB hits
+system.cpu.itb.inst_accesses                 61498403                       # ITB inst accesses
+system.cpu.itb.hits                          61493932                       # DTB hits
 system.cpu.itb.misses                            4471                       # DTB misses
-system.cpu.itb.accesses                      61498724                       # DTB accesses
-system.cpu.numCycles                       5233104166                       # number of cpu cycles simulated
+system.cpu.itb.accesses                      61498403                       # DTB accesses
+system.cpu.numCycles                       5233072430                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                    60200379                       # Number of instructions committed
-system.cpu.committedOps                      76607188                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses              69208982                       # Number of integer alu accesses
+system.cpu.committedInsts                    60200059                       # Number of instructions committed
+system.cpu.committedOps                      76606878                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses              69208659                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                  10269                       # Number of float alu accesses
-system.cpu.num_func_calls                     2140473                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts      7948700                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                     69208982                       # number of integer instructions
+system.cpu.num_func_calls                     2140468                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts      7948676                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                     69208659                       # number of integer instructions
 system.cpu.num_fp_insts                         10269                       # number of float instructions
-system.cpu.num_int_register_reads           401369988                       # number of times the integer registers were read
-system.cpu.num_int_register_writes           74519463                       # number of times the integer registers were written
+system.cpu.num_int_register_reads           401368432                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           74518953                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                 7493                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                2780                       # number of times the floating registers were written
-system.cpu.num_mem_refs                      27394064                       # number of memory refs
-system.cpu.num_load_insts                    15660288                       # Number of load instructions
-system.cpu.num_store_insts                   11733776                       # Number of store instructions
-system.cpu.num_idle_cycles               4581523252.608249                       # Number of idle cycles
-system.cpu.num_busy_cycles               651580913.391751                       # Number of busy cycles
-system.cpu.not_idle_fraction                 0.124511                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.875489                       # Percentage of idle cycles
-system.cpu.Branches                          10308817                       # Number of branches fetched
+system.cpu.num_mem_refs                      27394027                       # number of memory refs
+system.cpu.num_load_insts                    15660244                       # Number of load instructions
+system.cpu.num_store_insts                   11733783                       # Number of store instructions
+system.cpu.num_idle_cycles               4581664281.608249                       # Number of idle cycles
+system.cpu.num_busy_cycles               651408148.391751                       # Number of busy cycles
+system.cpu.not_idle_fraction                 0.124479                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.875521                       # Percentage of idle cycles
+system.cpu.Branches                          10308791                       # Number of branches fetched
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
 system.cpu.kern.inst.quiesce                    83016                       # number of quiesce instructions executed
-system.cpu.icache.tags.replacements            856260                       # number of replacements
-system.cpu.icache.tags.tagsinuse           510.867590                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            60637481                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            856772                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             70.774350                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       19998571250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   510.867590                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.997788                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.997788                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements            856277                       # number of replacements
+system.cpu.icache.tags.tagsinuse           510.865256                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            60637143                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            856789                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             70.772551                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       20019652250                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   510.865256                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.997784                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.997784                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           44                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          195                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2          267                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3            6                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          62351025                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         62351025                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     60637481                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        60637481                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      60637481                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         60637481                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     60637481                       # number of overall hits
-system.cpu.icache.overall_hits::total        60637481                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       856772                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        856772                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       856772                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         856772                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       856772                       # number of overall misses
-system.cpu.icache.overall_misses::total        856772                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  11774299750                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  11774299750                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  11774299750                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  11774299750                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  11774299750                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  11774299750                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     61494253                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     61494253                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     61494253                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     61494253                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     61494253                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     61494253                       # number of overall (read+write) accesses
+system.cpu.icache.tags.tag_accesses          62350721                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         62350721                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     60637143                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        60637143                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      60637143                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         60637143                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     60637143                       # number of overall hits
+system.cpu.icache.overall_hits::total        60637143                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       856789                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        856789                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       856789                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         856789                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       856789                       # number of overall misses
+system.cpu.icache.overall_misses::total        856789                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  11768796500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  11768796500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  11768796500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  11768796500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  11768796500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  11768796500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     61493932                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     61493932                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     61493932                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     61493932                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     61493932                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     61493932                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.013933                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.013933                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.013933                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.013933                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.013933                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.013933                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13742.629019                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13742.629019                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13742.629019                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13742.629019                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13742.629019                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13742.629019                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13735.933234                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13735.933234                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13735.933234                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13735.933234                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13735.933234                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13735.933234                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -995,186 +618,186 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       856772                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       856772                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       856772                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       856772                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       856772                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       856772                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  10056704250                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  10056704250                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  10056704250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  10056704250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  10056704250                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  10056704250                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    435943750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    435943750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    435943750                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::total    435943750                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       856789                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       856789                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       856789                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       856789                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       856789                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       856789                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  10051259500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  10051259500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  10051259500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  10051259500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  10051259500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  10051259500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    442799750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    442799750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    442799750                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::total    442799750                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.013933                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.013933                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.013933                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.013933                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.013933                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.013933                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11737.900223                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11737.900223                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11737.900223                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11737.900223                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11737.900223                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11737.900223                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11731.312494                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11731.312494                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11731.312494                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11731.312494                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11731.312494                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11731.312494                       # average overall mshr miss latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements            62511                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        50754.773862                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1682280                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           127893                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            13.153808                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle     2565659385000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 37718.578019                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     3.884348                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.replacements            62510                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        50754.341814                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            1682268                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           127892                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            13.153817                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle     2565667436000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 37718.224228                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     3.884316                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.000703                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  6993.361988                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  6038.948805                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.575540                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  6993.295627                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  6038.936941                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.575534                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000059                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.106710                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.106709                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.092147                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.774456                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.774450                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1023            4                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        65378                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1023::4            4                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           28                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1           22                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2163                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6898                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        56267                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2162                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6903                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        56263                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000061                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.997589                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         17137404                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        17137404                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker         8705                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         3532                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst       844551                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data       369636                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1226424                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       595238                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       595238                       # number of Writeback hits
+system.cpu.l2cache.tags.tag_accesses         17138143                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        17138143                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker         8709                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         3533                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.inst       844568                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data       369661                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        1226471                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       595273                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       595273                       # number of Writeback hits
 system.cpu.l2cache.UpgradeReq_hits::cpu.data           26                       # number of UpgradeReq hits
 system.cpu.l2cache.UpgradeReq_hits::total           26                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       113388                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       113388                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker         8705                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker         3532                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst       844551                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       483024                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         1339812                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker         8705                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker         3532                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst       844551                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       483024                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        1339812                       # number of overall hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       113398                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       113398                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker         8709                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.itb.walker         3533                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst       844568                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       483059                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         1339869                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.dtb.walker         8709                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.itb.walker         3533                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst       844568                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       483059                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        1339869                       # number of overall hits
 system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker            5                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            2                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.inst        10585                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.data         9809                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::total        20401                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data         2908                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total         2908                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       133825                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       133825                       # number of ReadExReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data         2905                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total         2905                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       133827                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       133827                       # number of ReadExReq misses
 system.cpu.l2cache.demand_misses::cpu.dtb.walker            5                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.itb.walker            2                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.inst        10585                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       143634                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        154226                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       143636                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        154228                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.dtb.walker            5                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.itb.walker            2                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.inst        10585                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       143634                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       154226                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker       305250                       # number of ReadReq miss cycles
+system.cpu.l2cache.overall_misses::cpu.data       143636                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       154228                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker       397250                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       150000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    752786250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data    737923500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total   1491165000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    747154500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data    739313250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   1487015000                       # number of ReadReq miss cycles
 system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       469980                       # number of UpgradeReq miss cycles
 system.cpu.l2cache.UpgradeReq_miss_latency::total       469980                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   9621111643                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   9621111643                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker       305250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   9526600640                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   9526600640                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker       397250                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       150000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    752786250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  10359035143                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  11112276643                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker       305250                       # number of overall miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    747154500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  10265913890                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  11013615640                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker       397250                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       150000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    752786250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  10359035143                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  11112276643                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker         8710                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         3534                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.inst       855136                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data       379445                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      1246825                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       595238                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       595238                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2934                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total         2934                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       247213                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       247213                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker         8710                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker         3534                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst       855136                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       626658                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      1494038                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker         8710                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker         3534                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst       855136                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       626658                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      1494038                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_miss_latency::cpu.inst    747154500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  10265913890                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  11013615640                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker         8714                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         3535                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.inst       855153                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data       379470                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      1246872                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       595273                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       595273                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data         2931                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total         2931                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       247225                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       247225                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker         8714                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.itb.walker         3535                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst       855153                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       626695                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      1494097                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker         8714                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.itb.walker         3535                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst       855153                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       626695                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      1494097                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000574                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.000566                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.012378                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.025851                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.025849                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::total     0.016362                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.991138                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.991138                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.541335                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.541335                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.991129                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.991129                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.541317                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.541317                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000574                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.000566                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.012378                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.229206                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.103228                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.229196                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.103225                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000574                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.000566                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.012378                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.229206                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.103228                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker        61050                       # average ReadReq miss latency
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.229196                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.103225                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker        79450                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        75000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71118.209731                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75229.228260                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 73092.740552                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data   161.616231                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   161.616231                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71893.231033                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71893.231033                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker        61050                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70586.159660                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75370.909369                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 72889.319151                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data   161.783133                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   161.783133                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71185.938861                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71185.938861                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker        79450                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        75000                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71118.209731                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72121.051722                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 72051.902033                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker        61050                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70586.159660                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71471.733340                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 71411.258915                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker        79450                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        75000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71118.209731                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72121.051722                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 72051.902033                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70586.159660                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71471.733340                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 71411.258915                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1183,92 +806,92 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        57911                       # number of writebacks
-system.cpu.l2cache.writebacks::total            57911                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks        57910                       # number of writebacks
+system.cpu.l2cache.writebacks::total            57910                       # number of writebacks
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker            5                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            2                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        10585                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data         9809                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::total        20401                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2908                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total         2908                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       133825                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       133825                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2905                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total         2905                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       133827                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       133827                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker            5                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            2                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.inst        10585                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       143634                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       154226                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       143636                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       154228                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker            5                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            2                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst        10585                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       143634                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       154226                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker       242750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.overall_mshr_misses::cpu.data       143636                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       154228                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker       335750                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       125000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    620216750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    615039000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1235623500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     29085908                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     29085908                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7946453357                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7946453357                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker       242750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    614626500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    616437250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1231524500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     29056905                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     29056905                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7852026860                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7852026860                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker       335750                       # number of demand (read+write) MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       125000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    620216750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   8561492357                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   9182076857                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker       242750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    614626500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   8468464110                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   9083551360                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker       335750                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       125000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    620216750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8561492357                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   9182076857                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    344358750                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166664193250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167008552000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data  16706218159                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total  16706218159                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    344358750                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 183370411409                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total 183714770159                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    614626500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8468464110                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   9083551360                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    351469750                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166664489250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167015959000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data  16706272596                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total  16706272596                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    351469750                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 183370761846                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total 183722231596                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000574                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000566                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.012378                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.025851                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.025849                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.016362                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.991138                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.991138                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.541335                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.541335                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.991129                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.991129                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.541317                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.541317                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000574                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000566                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.012378                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.229206                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.103228                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.229196                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.103225                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000574                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000566                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.012378                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.229206                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.103228                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker        48550                       # average ReadReq mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.229196                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.103225                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker        67150                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        62500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58593.930090                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62701.498624                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60566.810450                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.031637                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.031637                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59379.438498                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59379.438498                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker        48550                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58065.800661                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62844.046284                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60365.888927                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.376936                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.376936                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58672.964798                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58672.964798                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker        67150                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        62500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58593.930090                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59606.307399                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59536.503942                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker        48550                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58065.800661                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58957.810786                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58896.901730                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker        67150                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        62500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58593.930090                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59606.307399                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59536.503942                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58065.800661                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58957.810786                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58896.901730                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -1278,86 +901,87 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements            626146                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.876591                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            23656108                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            626658                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             37.749631                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         664772250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.876591                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999759                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999759                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements            626183                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.875243                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            23656065                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            626695                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             37.747333                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         671680250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.875243                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999756                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999756                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           74                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          329                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          109                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          108                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          97757722                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         97757722                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     13196248                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        13196248                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      9972755                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        9972755                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       236393                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       236393                       # number of LoadLockedReq hits
+system.cpu.dcache.tags.tag_accesses          97757735                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         97757735                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     13196205                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        13196205                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      9972754                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        9972754                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       236397                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       236397                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data       247778                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total       247778                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      23169003                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         23169003                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     23169003                       # number of overall hits
-system.cpu.dcache.overall_hits::total        23169003                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       368059                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        368059                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       250147                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       250147                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        11386                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        11386                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data       618206                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         618206                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       618206                       # number of overall misses
-system.cpu.dcache.overall_misses::total        618206                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   5416606500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   5416606500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  11623055265                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  11623055265                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    158362000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    158362000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  17039661765                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  17039661765                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  17039661765                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  17039661765                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     13564307                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     13564307                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     10222902                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     10222902                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_hits::cpu.data      23168959                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         23168959                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     23168959                       # number of overall hits
+system.cpu.dcache.overall_hits::total        23168959                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       368088                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        368088                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       250156                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       250156                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        11382                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        11382                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data       618244                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         618244                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       618244                       # number of overall misses
+system.cpu.dcache.overall_misses::total        618244                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   5418733500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   5418733500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  11526229765                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  11526229765                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    157891250                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    157891250                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  16944963265                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  16944963265                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  16944963265                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  16944963265                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     13564293                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     13564293                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     10222910                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     10222910                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data       247779                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total       247779                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data       247778                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total       247778                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     23787209                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     23787209                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     23787209                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     23787209                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.027134                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.027134                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.024469                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.024469                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.045952                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.045952                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.025989                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.025989                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.025989                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.025989                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14716.679934                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14716.679934                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46464.899699                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 46464.899699                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13908.484103                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13908.484103                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 27563.080535                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 27563.080535                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 27563.080535                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 27563.080535                       # average overall miss latency
+system.cpu.dcache.demand_accesses::cpu.data     23787203                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     23787203                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     23787203                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     23787203                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.027137                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.027137                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.024470                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.024470                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.045936                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.045936                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.025991                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.025991                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.025991                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.025991                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14721.298983                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14721.298983                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46076.167531                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 46076.167531                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13872.012827                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13872.012827                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 27408.213044                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 27408.213044                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 27408.213044                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 27408.213044                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -1366,54 +990,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       595238                       # number of writebacks
-system.cpu.dcache.writebacks::total            595238                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       368059                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       368059                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       250147                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       250147                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        11386                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total        11386                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       618206                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       618206                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       618206                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       618206                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   4678192500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   4678192500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11070820735                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  11070820735                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    135536000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    135536000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  15749013235                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  15749013235                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  15749013235                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  15749013235                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182058328250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182058328250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data  26237936841                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  26237936841                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208296265091                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 208296265091                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.027134                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.027134                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.024469                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.024469                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.045952                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.045952                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.025989                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.025989                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.025989                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.025989                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12710.441804                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12710.441804                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44257.259671                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44257.259671                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11903.741437                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11903.741437                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25475.348403                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 25475.348403                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25475.348403                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 25475.348403                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks       595273                       # number of writebacks
+system.cpu.dcache.writebacks::total            595273                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       368088                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       368088                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       250156                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       250156                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        11382                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total        11382                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       618244                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       618244                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       618244                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       618244                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   4680319500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   4680319500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10976351235                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  10976351235                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    135073750                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    135073750                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  15656670735                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  15656670735                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  15656670735                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  15656670735                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182058625250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182058625250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data  26242395404                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  26242395404                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208301020654                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 208301020654                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.027137                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.027137                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.024470                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.024470                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.045936                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.045936                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.025991                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.025991                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.025991                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.025991                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12715.218915                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12715.218915                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43878.025052                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43878.025052                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11867.312423                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11867.312423                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25324.420027                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 25324.420027                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25324.420027                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 25324.420027                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1421,37 +1045,37 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput                52965248                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq        2454635                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2454635                       # Transaction distribution
+system.cpu.toL2Bus.throughput                52967752                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq        2454681                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2454681                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteReq        763385                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WriteResp       763385                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback       595238                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2934                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2934                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       247213                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       247213                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1725170                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      5749474                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        12460                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        27430                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           7514534                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     54755228                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     83615814                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        14136                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        34840                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      138420018                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus         138420018                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus       166312                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy     3008633500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.trans_dist::Writeback       595273                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2931                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2931                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       247225                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       247225                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1725204                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      5749577                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        12461                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        27438                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           7514680                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     54756316                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     83620422                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side        14140                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side        34856                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      138425734                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         138425734                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus       166308                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy     3008713250                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    1295454000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    1295332250                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2534439174                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    2533285861                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer2.occupancy       8926000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy      18720500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy      18724250                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
 system.iocache.tags.replacements                    0                       # number of replacements
 system.iocache.tags.tagsinuse                       0                       # Cycle average of tags in use
@@ -1469,10 +1093,10 @@ system.iocache.avg_blocked_cycles::no_mshrs          nan                       #
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1538398399250                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1538398399250                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1538398399250                       # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1538398399250                       # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1763840630000                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1763840630000                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1763840630000                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1763840630000                       # number of overall MSHR uncacheable cycles
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
index 64ad0ab7f29002879e8b7dcdf30c898fcb4158c6..03f4934d5038c4f74dee6ee89165327826c50bf6 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  5.196390                       # Number of seconds simulated
-sim_ticks                                5196390180000                       # Number of ticks simulated
-final_tick                               5196390180000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  5.200402                       # Number of seconds simulated
+sim_ticks                                5200402495000                       # Number of ticks simulated
+final_tick                               5200402495000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 991078                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1910460                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            40129605273                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 591204                       # Number of bytes of host memory used
-host_seconds                                   129.49                       # Real time elapsed on the host
-sim_insts                                   128334813                       # Number of instructions simulated
-sim_ops                                     247385808                       # Number of ops (including micro ops) simulated
+host_inst_rate                                1256922                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2423033                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            50949381192                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 591984                       # Number of bytes of host memory used
+host_seconds                                   102.07                       # Real time elapsed on the host
+sim_insts                                   128294014                       # Number of instructions simulated
+sim_ops                                     247318948                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::pc.south_bridge.ide      2883712                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker          128                       # Number of bytes read from this memory
+system.physmem.bytes_read::pc.south_bridge.ide      2869888                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker           64                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker          320                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst            824512                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           8989184                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             12697856                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       824512                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          824512                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      8110912                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8110912                       # Number of bytes written to this memory
-system.physmem.num_reads::pc.south_bridge.ide        45058                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker            2                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::cpu.inst            826752                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           8970624                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             12667648                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       826752                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          826752                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8094016                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           8094016                       # Number of bytes written to this memory
+system.physmem.num_reads::pc.south_bridge.ide        44842                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker            1                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.itb.walker            5                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              12883                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             140456                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                198404                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          126733                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               126733                       # Number of write requests responded to by this memory
-system.physmem.bw_read::pc.south_bridge.ide       554945                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker             25                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::cpu.inst              12918                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             140166                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                197932                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          126469                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               126469                       # Number of write requests responded to by this memory
+system.physmem.bw_read::pc.south_bridge.ide       551859                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker             12                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.itb.walker             62                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               158670                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1729890                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2443592                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          158670                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             158670                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1560874                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1560874                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1560874                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide       554945                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker            25                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               158978                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1724986                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2435898                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          158978                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             158978                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1556421                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1556421                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1556421                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide       551859                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker            12                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.itb.walker            62                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              158670                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1729890                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4004466                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        198404                       # Number of read requests accepted
-system.physmem.writeReqs                       126733                       # Number of write requests accepted
-system.physmem.readBursts                      198404                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     126733                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 12694144                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      3712                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   8109888                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  12697856                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                8110912                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                       58                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::cpu.inst              158978                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1724986                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3992319                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        197932                       # Number of read requests accepted
+system.physmem.writeReqs                       126469                       # Number of write requests accepted
+system.physmem.readBursts                      197932                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     126469                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 12654528                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     13120                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   8092032                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  12667648                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                8094016                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      205                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs           1616                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               12580                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               12146                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               12820                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               12639                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               12420                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               12033                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               12032                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               12154                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               12328                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               11842                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              12289                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              12385                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              12618                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              13039                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              12508                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              12513                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                8180                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7837                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                8283                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                8150                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                7961                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7589                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                7480                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                7728                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7696                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                7447                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7846                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               7788                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               8080                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               8539                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               8032                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               8081                       # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs           1622                       # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0               12706                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               12058                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               12568                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               12134                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               12521                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               12218                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               12048                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               12245                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               12013                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               12113                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              12409                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              12495                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              12992                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              12976                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              12442                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              11789                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                8349                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7660                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                8054                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                7772                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                8164                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7804                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                7601                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                7742                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7412                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                7677                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               8006                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               7919                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               8539                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               8375                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               8051                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7313                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
-system.physmem.numWrRetry                           7                       # Number of times write queue was full causing retry
-system.physmem.totGap                    5196390116500                       # Total gap between requests
+system.physmem.numWrRetry                           2                       # Number of times write queue was full causing retry
+system.physmem.totGap                    5200402431500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  198404                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  197932                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 126733                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    155323                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     13571                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                      6905                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      2932                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      2598                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      2604                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      1783                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      1802                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      1789                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      1294                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                      932                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      826                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      797                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      790                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                      755                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                      733                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16                      725                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17                      712                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18                      712                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19                      711                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20                       52                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 126469                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    153822                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      2802                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                      2836                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      2322                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      2661                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      5083                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      4526                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      4292                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      3878                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                      2499                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                     2187                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                     1998                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                     1775                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                     1455                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                     1085                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                     1035                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16                      994                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17                      939                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18                      873                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19                      635                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20                       30                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
@@ -141,215 +141,131 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0                      5072                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1                      5130                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2                      5143                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3                      5187                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4                      5411                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5                      5609                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6                      5671                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7                      5668                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8                      6394                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9                      6161                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10                     6233                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11                     6275                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12                     6715                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13                     6051                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14                     6223                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     6456                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     6523                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5298                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5238                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5186                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     5154                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5136                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                      305                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                      234                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                       63                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                       43                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                       33                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                       28                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                       26                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                       24                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                       23                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                       20                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        53708                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      387.265063                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     159.541838                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev    1283.636288                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64-67          22377     41.66%     41.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-131         8801     16.39%     58.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192-195         5780     10.76%     68.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-259         3435      6.40%     75.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320-323         2322      4.32%     79.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-387         1859      3.46%     82.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448-451         1339      2.49%     85.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-515         1034      1.93%     87.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576-579          806      1.50%     88.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-643          663      1.23%     90.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704-707          546      1.02%     91.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-771          427      0.80%     91.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832-835          325      0.61%     92.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-899          307      0.57%     93.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960-963          277      0.52%     93.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1027          550      1.02%     94.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088-1091          185      0.34%     95.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152-1155          190      0.35%     95.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216-1219          112      0.21%     95.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280-1283          109      0.20%     95.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344-1347          125      0.23%     96.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408-1411          422      0.79%     96.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472-1475          149      0.28%     97.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536-1539           87      0.16%     97.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600-1603           55      0.10%     97.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664-1667           85      0.16%     97.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1728-1731           52      0.10%     97.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1792-1795           36      0.07%     97.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856-1859           25      0.05%     97.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1920-1923           24      0.04%     97.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984-1987           18      0.03%     97.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2048-2051           26      0.05%     97.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112-2115           25      0.05%     97.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2176-2179           20      0.04%     97.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2240-2243           14      0.03%     97.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2304-2307           13      0.02%     97.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2368-2371            9      0.02%     97.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2432-2435           14      0.03%     98.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2496-2499           11      0.02%     98.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2560-2563           11      0.02%     98.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2624-2627           14      0.03%     98.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2688-2691           11      0.02%     98.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2752-2755            9      0.02%     98.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2816-2819           10      0.02%     98.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2880-2883           13      0.02%     98.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2944-2947           10      0.02%     98.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3008-3011            8      0.01%     98.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3072-3075           26      0.05%     98.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3136-3139           12      0.02%     98.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3200-3203            9      0.02%     98.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3264-3267           19      0.04%     98.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3328-3331           10      0.02%     98.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3392-3395            9      0.02%     98.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3456-3459           12      0.02%     98.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3520-3523            7      0.01%     98.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3584-3587           12      0.02%     98.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3648-3651           15      0.03%     98.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3712-3715           10      0.02%     98.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3776-3779           20      0.04%     98.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3840-3843           13      0.02%     98.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3904-3907           24      0.04%     98.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3968-3971           13      0.02%     98.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4032-4035           11      0.02%     98.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4096-4099           19      0.04%     98.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4160-4163           10      0.02%     98.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4224-4227           13      0.02%     98.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4288-4291            7      0.01%     98.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4352-4355            9      0.02%     98.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4416-4419           11      0.02%     98.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4480-4483            7      0.01%     98.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4544-4547            9      0.02%     98.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4608-4611            9      0.02%     98.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4672-4675            4      0.01%     98.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4736-4739           10      0.02%     98.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4800-4803            9      0.02%     98.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4864-4867            7      0.01%     98.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4928-4931            9      0.02%     98.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4992-4995            7      0.01%     98.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5056-5059            5      0.01%     98.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5120-5123           13      0.02%     98.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5184-5187            8      0.01%     98.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5248-5251            7      0.01%     98.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5312-5315            8      0.01%     98.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5376-5379           10      0.02%     98.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5440-5443            5      0.01%     98.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5504-5507            9      0.02%     98.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5568-5571          151      0.28%     99.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5696-5699            1      0.00%     99.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5760-5763            1      0.00%     99.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5824-5827            2      0.00%     99.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6144-6147            1      0.00%     99.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6208-6211            3      0.01%     99.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6272-6275            2      0.00%     99.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6400-6403            1      0.00%     99.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6528-6531            2      0.00%     99.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6592-6595            4      0.01%     99.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6720-6723            1      0.00%     99.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6784-6787            1      0.00%     99.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6848-6851            5      0.01%     99.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6912-6915            4      0.01%     99.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7040-7043            2      0.00%     99.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7104-7107            1      0.00%     99.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7168-7171           19      0.04%     99.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7232-7235            4      0.01%     99.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7424-7427            1      0.00%     99.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7616-7619            2      0.00%     99.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7808-7811            1      0.00%     99.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7872-7875            4      0.01%     99.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8064-8067            3      0.01%     99.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8128-8131            2      0.00%     99.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8192-8195           14      0.03%     99.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8256-8259            2      0.00%     99.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8384-8387            1      0.00%     99.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8512-8515            3      0.01%     99.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8576-8579            1      0.00%     99.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8768-8771            2      0.00%     99.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9152-9155            2      0.00%     99.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9216-9219            4      0.01%     99.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9280-9283            1      0.00%     99.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9472-9475            1      0.00%     99.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9536-9539            2      0.00%     99.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9664-9667            1      0.00%     99.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9792-9795            1      0.00%     99.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10112-10115            1      0.00%     99.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10176-10179            2      0.00%     99.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10624-10627            1      0.00%     99.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11136-11139            3      0.01%     99.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11200-11203            1      0.00%     99.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11264-11267            4      0.01%     99.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11520-11523            1      0.00%     99.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11904-11907            1      0.00%     99.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12160-12163            1      0.00%     99.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12224-12227            4      0.01%     99.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12416-12419            2      0.00%     99.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12480-12483            1      0.00%     99.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12544-12547            2      0.00%     99.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12608-12611            1      0.00%     99.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12800-12803            1      0.00%     99.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12864-12867            2      0.00%     99.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13120-13123            1      0.00%     99.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13248-13251            4      0.01%     99.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13312-13315            6      0.01%     99.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13632-13635            2      0.00%     99.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13760-13763            2      0.00%     99.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13824-13827            1      0.00%     99.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13888-13891            2      0.00%     99.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14080-14083            1      0.00%     99.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14208-14211            2      0.00%     99.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14336-14339            1      0.00%     99.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14400-14403            2      0.00%     99.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14592-14595            2      0.00%     99.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14848-14851            3      0.01%     99.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14912-14915            7      0.01%     99.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14976-14979            2      0.00%     99.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15168-15171            2      0.00%     99.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15232-15235            3      0.01%     99.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15360-15363           32      0.06%     99.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15680-15683            1      0.00%     99.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15872-15875            3      0.01%     99.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16000-16003            1      0.00%     99.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16064-16067            1      0.00%     99.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16256-16259            1      0.00%     99.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16384-16387          178      0.33%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          53708                       # Bytes accessed per row activation
-system.physmem.totQLat                     5080719250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                8752324250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    991730000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                  2679875000                       # Total ticks spent accessing banks
-system.physmem.avgQLat                       25615.44                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    13511.11                       # Average bank access latency per DRAM burst
+system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     1772                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     1931                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     2266                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     4818                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     4882                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     4906                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     4927                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     5009                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     5027                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     5140                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     6982                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     5886                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     6125                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     7452                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     6738                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     7068                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     7200                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     7099                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     2363                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                     2255                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                     2123                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                     2044                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                     2150                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                     2242                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                     2142                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                     2203                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                     2178                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                     2139                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                     1928                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                     1612                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                     1254                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                     1001                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                      780                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                      690                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                      574                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                      476                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                      359                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                      245                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                      164                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                      101                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       66                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                       43                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                       28                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                       25                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                       15                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                       10                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        7                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        6                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples        36378                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      449.321238                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     264.022911                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     400.116091                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127           9783     26.89%     26.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         7520     20.67%     47.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         3398      9.34%     56.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         1958      5.38%     62.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         1470      4.04%     66.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          950      2.61%     68.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          669      1.84%     70.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          516      1.42%     72.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        10114     27.80%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          36378                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          6806                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        29.049956                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      579.203336                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047           6805     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::47104-49151            1      0.01%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            6806                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          6806                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        18.577432                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.979234                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        6.072144                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-17            4358     64.03%     64.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18-19            1673     24.58%     88.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-21              85      1.25%     89.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22-23              45      0.66%     90.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-25              78      1.15%     91.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26-27             127      1.87%     93.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-29              53      0.78%     94.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30-31              38      0.56%     94.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-33              25      0.37%     95.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::34-35              74      1.09%     96.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-37              52      0.76%     97.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::38-39              16      0.24%     97.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-41              72      1.06%     98.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::42-43              19      0.28%     98.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-45              28      0.41%     99.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::46-47              13      0.19%     99.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-49               8      0.12%     99.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::50-51               5      0.07%     99.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-53               7      0.10%     99.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::54-55               5      0.07%     99.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-57               2      0.03%     99.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::58-59               2      0.03%     99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-61               1      0.01%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::62-63               5      0.07%     99.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-65              13      0.19%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-69               1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::74-75               1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            6806                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     5807464000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                9465482750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    988635000                       # Total ticks spent in databus transfers
+system.physmem.totBankLat                  2669383750                       # Total ticks spent accessing banks
+system.physmem.avgQLat                       29371.12                       # Average queueing delay per DRAM burst
+system.physmem.avgBankLat                    13500.35                       # Average bank access latency per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  44126.55                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           2.44                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  47871.47                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           2.43                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           1.56                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        2.44                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        1.56                       # Average system write bandwidth in MiByte/s
@@ -357,99 +273,99 @@ system.physmem.peakBW                        12800.00                       # Th
 system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         0.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                         8.98                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     173438                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     97917                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   87.44                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  77.26                       # Row buffer hit rate for writes
-system.physmem.avgGap                     15982155.57                       # Average gap between requests
-system.physmem.pageHitRate                      83.47                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               0.27                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                      4365247                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq              623514                       # Transaction distribution
-system.membus.trans_dist::ReadResp             623514                       # Transaction distribution
-system.membus.trans_dist::WriteReq              13775                       # Transaction distribution
-system.membus.trans_dist::WriteResp             13775                       # Transaction distribution
-system.membus.trans_dist::Writeback            126733                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq             2150                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp            1634                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            159484                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           159484                       # Transaction distribution
-system.membus.trans_dist::MessageReq             1655                       # Transaction distribution
-system.membus.trans_dist::MessageResp            1655                       # Transaction distribution
-system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave         3310                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.apicbridge.master::total         3310                       # Packet count per connected master and slave (bytes)
+system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        26.17                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     167067                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     99118                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   84.49                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  78.37                       # Row buffer hit rate for writes
+system.physmem.avgGap                     16030784.22                       # Average gap between requests
+system.physmem.pageHitRate                      82.11                       # Row buffer hit rate, read and write combined
+system.physmem.prechargeAllPercent               0.28                       # Percentage of time for which DRAM has all the banks in precharge state
+system.membus.throughput                      4355532                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq              623246                       # Transaction distribution
+system.membus.trans_dist::ReadResp             623246                       # Transaction distribution
+system.membus.trans_dist::WriteReq              13777                       # Transaction distribution
+system.membus.trans_dist::WriteResp             13777                       # Transaction distribution
+system.membus.trans_dist::Writeback            126469                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             2149                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp            1640                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            159500                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           159500                       # Transaction distribution
+system.membus.trans_dist::MessageReq             1656                       # Transaction distribution
+system.membus.trans_dist::MessageResp            1656                       # Transaction distribution
+system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave         3312                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.apicbridge.master::total         3312                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       480328                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio       710114                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       391174                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1581616                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       139281                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total       139281                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1724207                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6620                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.apicbridge.master::total         6620                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio       710118                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       390403                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1580849                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       139069                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total       139069                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1723230                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6624                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.apicbridge.master::total         6624                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       246444                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      1420225                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     14938368                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     16605037                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      5870400                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::total      5870400                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total            22482057                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus               22482057                       # Total data (bytes)
-system.membus.snoop_data_through_bus           201472                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy           256796500                       # Layer occupancy (ticks)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      1420233                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     14905088                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     16571765                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port      5856576                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::total      5856576                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total            22434965                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus               22434965                       # Total data (bytes)
+system.membus.snoop_data_through_bus           215552                       # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy           256796000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer1.occupancy           359316000                       # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy           359324000                       # Layer occupancy (ticks)
 system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer2.occupancy             3310000                       # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy             3312000                       # Layer occupancy (ticks)
 system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
-system.membus.reqLayer3.occupancy          1352149000                       # Layer occupancy (ticks)
+system.membus.reqLayer3.occupancy          1349763000                       # Layer occupancy (ticks)
 system.membus.reqLayer3.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer0.occupancy            1655000                       # Layer occupancy (ticks)
+system.membus.respLayer0.occupancy            1656000                       # Layer occupancy (ticks)
 system.membus.respLayer0.utilization              0.0                       # Layer utilization (%)
-system.membus.respLayer2.occupancy         2612327754                       # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy         2610332746                       # Layer occupancy (ticks)
 system.membus.respLayer2.utilization              0.1                       # Layer utilization (%)
-system.membus.respLayer4.occupancy          428873750                       # Layer occupancy (ticks)
+system.membus.respLayer4.occupancy          429200500                       # Layer occupancy (ticks)
 system.membus.respLayer4.utilization              0.0                       # Layer utilization (%)
-system.iocache.tags.replacements                47501                       # number of replacements
-system.iocache.tags.tagsinuse                0.113099                       # Cycle average of tags in use
+system.iocache.tags.replacements                47505                       # number of replacements
+system.iocache.tags.tagsinuse                0.134382                       # Cycle average of tags in use
 system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                47517                       # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs                47521                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle         5049776837000                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.113099                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::pc.south_bridge.ide     0.007069                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total       0.007069                       # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle         5049788540000                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.134382                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::pc.south_bridge.ide     0.008399                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.008399                       # Average percentage of cache occupancy
 system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
 system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
 system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses               428004                       # Number of tag accesses
-system.iocache.tags.data_accesses              428004                       # Number of data accesses
-system.iocache.ReadReq_misses::pc.south_bridge.ide          836                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              836                       # number of ReadReq misses
+system.iocache.tags.tag_accesses               428040                       # Number of tag accesses
+system.iocache.tags.data_accesses              428040                       # Number of data accesses
+system.iocache.ReadReq_misses::pc.south_bridge.ide          840                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              840                       # number of ReadReq misses
 system.iocache.WriteReq_misses::pc.south_bridge.ide        46720                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total           46720                       # number of WriteReq misses
-system.iocache.demand_misses::pc.south_bridge.ide        47556                       # number of demand (read+write) misses
-system.iocache.demand_misses::total             47556                       # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide        47556                       # number of overall misses
-system.iocache.overall_misses::total            47556                       # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    144134686                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total    144134686                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::pc.south_bridge.ide  12487439330                       # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total  12487439330                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide  12631574016                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total  12631574016                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide  12631574016                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total  12631574016                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide          836                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            836                       # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::pc.south_bridge.ide        47560                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             47560                       # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide        47560                       # number of overall misses
+system.iocache.overall_misses::total            47560                       # number of overall misses
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    142383686                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total    142383686                       # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::pc.south_bridge.ide  12484793248                       # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total  12484793248                       # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide  12627176934                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total  12627176934                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide  12627176934                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total  12627176934                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::pc.south_bridge.ide          840                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            840                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::pc.south_bridge.ide        46720                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total         46720                       # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide        47556                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           47556                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide        47556                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          47556                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::pc.south_bridge.ide        47560                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           47560                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide        47560                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          47560                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteReq accesses
@@ -458,40 +374,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 172409.911483                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 172409.911483                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 267282.519906                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 267282.519906                       # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 265614.728236                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 265614.728236                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 265614.728236                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 265614.728236                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs        216457                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 169504.388095                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 169504.388095                       # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 267225.882877                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 267225.882877                       # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 265499.935534                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 265499.935534                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 265499.935534                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 265499.935534                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs        224342                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                11594                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                18183                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs    18.669743                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs    12.338008                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           46667                       # number of writebacks
 system.iocache.writebacks::total                46667                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          836                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          836                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          840                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          840                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total        46720                       # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide        47556                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total        47556                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide        47556                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total        47556                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide    100637686                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total    100637686                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide  10056284830                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total  10056284830                       # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide  10156922516                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total  10156922516                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide  10156922516                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total  10156922516                       # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::pc.south_bridge.ide        47560                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total        47560                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide        47560                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total        47560                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     98678186                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     98678186                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide  10053057748                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total  10053057748                       # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide  10151735934                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total  10151735934                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide  10151735934                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total  10151735934                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteReq accesses
@@ -500,14 +416,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 120380.007177                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 120380.007177                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 215245.822560                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 215245.822560                       # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 213578.150307                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 213578.150307                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 213578.150307                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 213578.150307                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 117474.030952                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 117474.030952                       # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 215176.749743                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 215176.749743                       # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 213451.134020                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 213451.134020                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 213451.134020                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 213451.134020                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
@@ -521,13 +437,13 @@ system.pc.south_bridge.ide.disks1.dma_read_txs            0
 system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
-system.iobus.throughput                        631264                       # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq               230141                       # Transaction distribution
-system.iobus.trans_dist::ReadResp              230141                       # Transaction distribution
+system.iobus.throughput                        630784                       # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq               230145                       # Transaction distribution
+system.iobus.trans_dist::ReadResp              230145                       # Transaction distribution
 system.iobus.trans_dist::WriteReq               57579                       # Transaction distribution
 system.iobus.trans_dist::WriteResp              57579                       # Transaction distribution
-system.iobus.trans_dist::MessageReq              1655                       # Transaction distribution
-system.iobus.trans_dist::MessageResp             1655                       # Transaction distribution
+system.iobus.trans_dist::MessageReq              1656                       # Transaction distribution
+system.iobus.trans_dist::MessageResp             1656                       # Transaction distribution
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           44                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11088                       # Packet count per connected master and slave (bytes)
@@ -547,11 +463,11 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio
 system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio         2128                       # Packet count per connected master and slave (bytes)
 system.iobus.pkt_count_system.bridge.master::total       480328                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95112                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95112                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3310                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3310                       # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total                  578750                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95120                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95120                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3312                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3312                       # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total                  578760                       # Packet count per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6686                       # Cumulative packet size per connected master and slave (bytes)
@@ -571,13 +487,13 @@ system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio
 system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio         4256                       # Cumulative packet size per connected master and slave (bytes)
 system.iobus.tot_pkt_size_system.bridge.master::total       246444                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027232                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total      3027232                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6620                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total         6620                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total              3280296                       # Cumulative packet size per connected master and slave (bytes)
-system.iobus.data_through_bus                 3280296                       # Total data (bytes)
-system.iobus.reqLayer0.occupancy              3948164                       # Layer occupancy (ticks)
+system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027264                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total      3027264                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6624                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total         6624                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::total              3280332                       # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus                 3280332                       # Total data (bytes)
+system.iobus.reqLayer0.occupancy              3953400                       # Layer occupancy (ticks)
 system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
 system.iobus.reqLayer1.occupancy                34000                       # Layer occupancy (ticks)
 system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
@@ -613,98 +529,98 @@ system.iobus.reqLayer16.occupancy                9000                       # La
 system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
 system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
-system.iobus.reqLayer18.occupancy           424033266                       # Layer occupancy (ticks)
+system.iobus.reqLayer18.occupancy           425604434                       # Layer occupancy (ticks)
 system.iobus.reqLayer18.utilization               0.0                       # Layer utilization (%)
 system.iobus.reqLayer19.occupancy             1064000                       # Layer occupancy (ticks)
 system.iobus.reqLayer19.utilization               0.0                       # Layer utilization (%)
 system.iobus.respLayer0.occupancy           469469000                       # Layer occupancy (ticks)
 system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer1.occupancy            52989250                       # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy            53343500                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               0.0                       # Layer utilization (%)
-system.iobus.respLayer2.occupancy             1655000                       # Layer occupancy (ticks)
+system.iobus.respLayer2.occupancy             1656000                       # Layer occupancy (ticks)
 system.iobus.respLayer2.utilization               0.0                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
-system.cpu.numCycles                      10392780360                       # number of cpu cycles simulated
+system.cpu.numCycles                      10400804990                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   128334813                       # Number of instructions committed
-system.cpu.committedOps                     247385808                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             231978567                       # Number of integer alu accesses
+system.cpu.committedInsts                   128294014                       # Number of instructions committed
+system.cpu.committedOps                     247318948                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             231911784                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
-system.cpu.num_func_calls                     2299773                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     23169265                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    231978567                       # number of integer instructions
+system.cpu.num_func_calls                     2299833                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts     23159249                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    231911784                       # number of integer instructions
 system.cpu.num_fp_insts                             0                       # number of float instructions
-system.cpu.num_int_register_reads           434513747                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          197852200                       # number of times the integer registers were written
+system.cpu.num_int_register_reads           434400113                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          197801183                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_cc_register_reads            132813019                       # number of times the CC registers were read
-system.cpu.num_cc_register_writes            95534921                       # number of times the CC registers were written
-system.cpu.num_mem_refs                      22245363                       # number of memory refs
-system.cpu.num_load_insts                    13878746                       # Number of load instructions
-system.cpu.num_store_insts                    8366617                       # Number of store instructions
-system.cpu.num_idle_cycles               9785238216.998117                       # Number of idle cycles
-system.cpu.num_busy_cycles               607542143.001883                       # Number of busy cycles
-system.cpu.not_idle_fraction                 0.058458                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.941542                       # Percentage of idle cycles
-system.cpu.Branches                          26307103                       # Number of branches fetched
+system.cpu.num_cc_register_reads            132752064                       # number of times the CC registers were read
+system.cpu.num_cc_register_writes            95494911                       # number of times the CC registers were written
+system.cpu.num_mem_refs                      22235692                       # number of memory refs
+system.cpu.num_load_insts                    13875118                       # Number of load instructions
+system.cpu.num_store_insts                    8360574                       # Number of store instructions
+system.cpu.num_idle_cycles               9794078774.998117                       # Number of idle cycles
+system.cpu.num_busy_cycles               606726215.001883                       # Number of busy cycles
+system.cpu.not_idle_fraction                 0.058335                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.941665                       # Percentage of idle cycles
+system.cpu.Branches                          26297154                       # Number of branches fetched
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
 system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed
-system.cpu.icache.tags.replacements            788090                       # number of replacements
-system.cpu.icache.tags.tagsinuse           510.351939                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           144584753                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            788602                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs            183.343122                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle      161436066250                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   510.351939                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.996781                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.996781                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements            791422                       # number of replacements
+system.cpu.icache.tags.tagsinuse           510.352385                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           144521518                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            791934                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs            182.491872                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle      161455178250                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   510.352385                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.996782                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.996782                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           45                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          161                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          299                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3            7                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           58                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          145                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          303                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            6                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         146161971                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        146161971                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    144584753                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       144584753                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     144584753                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        144584753                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    144584753                       # number of overall hits
-system.cpu.icache.overall_hits::total       144584753                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       788609                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        788609                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       788609                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         788609                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       788609                       # number of overall misses
-system.cpu.icache.overall_misses::total        788609                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  11107362758                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  11107362758                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  11107362758                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  11107362758                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  11107362758                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  11107362758                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    145373362                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    145373362                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    145373362                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    145373362                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    145373362                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    145373362                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.005425                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.005425                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.005425                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.005425                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.005425                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.005425                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14084.752720                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 14084.752720                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 14084.752720                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 14084.752720                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 14084.752720                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 14084.752720                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses         146105400                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        146105400                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    144521518                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       144521518                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     144521518                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        144521518                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    144521518                       # number of overall hits
+system.cpu.icache.overall_hits::total       144521518                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       791941                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        791941                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       791941                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         791941                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       791941                       # number of overall misses
+system.cpu.icache.overall_misses::total        791941                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  11119349759                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  11119349759                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  11119349759                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  11119349759                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  11119349759                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  11119349759                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    145313459                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    145313459                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    145313459                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    145313459                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    145313459                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    145313459                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.005450                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.005450                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.005450                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.005450                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.005450                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.005450                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14040.628985                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 14040.628985                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 14040.628985                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 14040.628985                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 14040.628985                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 14040.628985                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -713,88 +629,88 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       788609                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       788609                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       788609                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       788609                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       788609                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       788609                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   9525299242                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total   9525299242                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst   9525299242                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total   9525299242                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst   9525299242                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total   9525299242                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.005425                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.005425                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.005425                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.005425                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.005425                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.005425                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12078.608337                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12078.608337                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12078.608337                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12078.608337                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12078.608337                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12078.608337                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       791941                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       791941                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       791941                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       791941                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       791941                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       791941                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   9530763241                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total   9530763241                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   9530763241                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total   9530763241                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst   9530763241                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total   9530763241                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.005450                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.005450                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.005450                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.005450                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.005450                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.005450                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12034.688494                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12034.688494                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12034.688494                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 12034.688494                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12034.688494                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 12034.688494                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.itb_walker_cache.tags.replacements         3741                       # number of replacements
-system.cpu.itb_walker_cache.tags.tagsinuse     3.069761                       # Cycle average of tags in use
-system.cpu.itb_walker_cache.tags.total_refs         7617                       # Total number of references to valid blocks.
-system.cpu.itb_walker_cache.tags.sampled_refs         3752                       # Sample count of references to valid blocks.
-system.cpu.itb_walker_cache.tags.avg_refs     2.030117                       # Average number of references to valid blocks.
-system.cpu.itb_walker_cache.tags.warmup_cycle 5169682535000                       # Cycle when the warmup percentage was hit.
-system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     3.069761                       # Average occupied blocks per requestor
-system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.191860                       # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.tags.occ_percent::total     0.191860                       # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024           11                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.replacements         3448                       # number of replacements
+system.cpu.itb_walker_cache.tags.tagsinuse     3.074851                       # Cycle average of tags in use
+system.cpu.itb_walker_cache.tags.total_refs         7916                       # Total number of references to valid blocks.
+system.cpu.itb_walker_cache.tags.sampled_refs         3460                       # Sample count of references to valid blocks.
+system.cpu.itb_walker_cache.tags.avg_refs     2.287861                       # Average number of references to valid blocks.
+system.cpu.itb_walker_cache.tags.warmup_cycle 5178780288000                       # Cycle when the warmup percentage was hit.
+system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     3.074851                       # Average occupied blocks per requestor
+system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.192178                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.tags.occ_percent::total     0.192178                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024           12                       # Occupied blocks per task id
 system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0            3                       # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1            2                       # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2            4                       # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024     0.687500                       # Percentage of cache occupancy per task id
-system.cpu.itb_walker_cache.tags.tag_accesses        29050                       # Number of tag accesses
-system.cpu.itb_walker_cache.tags.data_accesses        29050                       # Number of data accesses
-system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker         7617                       # number of ReadReq hits
-system.cpu.itb_walker_cache.ReadReq_hits::total         7617                       # number of ReadReq hits
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1            3                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2            5                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
+system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024     0.750000                       # Percentage of cache occupancy per task id
+system.cpu.itb_walker_cache.tags.tag_accesses        28763                       # Number of tag accesses
+system.cpu.itb_walker_cache.tags.data_accesses        28763                       # Number of data accesses
+system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker         7916                       # number of ReadReq hits
+system.cpu.itb_walker_cache.ReadReq_hits::total         7916                       # number of ReadReq hits
 system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            2                       # number of WriteReq hits
 system.cpu.itb_walker_cache.WriteReq_hits::total            2                       # number of WriteReq hits
-system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker         7619                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.demand_hits::total         7619                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker         7619                       # number of overall hits
-system.cpu.itb_walker_cache.overall_hits::total         7619                       # number of overall hits
-system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker         4604                       # number of ReadReq misses
-system.cpu.itb_walker_cache.ReadReq_misses::total         4604                       # number of ReadReq misses
-system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker         4604                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.demand_misses::total         4604                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker         4604                       # number of overall misses
-system.cpu.itb_walker_cache.overall_misses::total         4604                       # number of overall misses
-system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker     44886750                       # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.ReadReq_miss_latency::total     44886750                       # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker     44886750                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::total     44886750                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker     44886750                       # number of overall miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::total     44886750                       # number of overall miss cycles
-system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        12221                       # number of ReadReq accesses(hits+misses)
-system.cpu.itb_walker_cache.ReadReq_accesses::total        12221                       # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker         7918                       # number of demand (read+write) hits
+system.cpu.itb_walker_cache.demand_hits::total         7918                       # number of demand (read+write) hits
+system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker         7918                       # number of overall hits
+system.cpu.itb_walker_cache.overall_hits::total         7918                       # number of overall hits
+system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker         4309                       # number of ReadReq misses
+system.cpu.itb_walker_cache.ReadReq_misses::total         4309                       # number of ReadReq misses
+system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker         4309                       # number of demand (read+write) misses
+system.cpu.itb_walker_cache.demand_misses::total         4309                       # number of demand (read+write) misses
+system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker         4309                       # number of overall misses
+system.cpu.itb_walker_cache.overall_misses::total         4309                       # number of overall misses
+system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker     42842750                       # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.ReadReq_miss_latency::total     42842750                       # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker     42842750                       # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::total     42842750                       # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker     42842750                       # number of overall miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::total     42842750                       # number of overall miss cycles
+system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        12225                       # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.ReadReq_accesses::total        12225                       # number of ReadReq accesses(hits+misses)
 system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            2                       # number of WriteReq accesses(hits+misses)
 system.cpu.itb_walker_cache.WriteReq_accesses::total            2                       # number of WriteReq accesses(hits+misses)
-system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        12223                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.demand_accesses::total        12223                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        12223                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::total        12223                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.376729                       # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.376729                       # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.376667                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_miss_rate::total     0.376667                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.376667                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_miss_rate::total     0.376667                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker  9749.511295                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total  9749.511295                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker  9749.511295                       # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::total  9749.511295                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker  9749.511295                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::total  9749.511295                       # average overall miss latency
+system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        12227                       # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.demand_accesses::total        12227                       # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        12227                       # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::total        12227                       # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.352474                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.352474                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.352417                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_miss_rate::total     0.352417                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.352417                       # miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_miss_rate::total     0.352417                       # miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker  9942.620097                       # average ReadReq miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total  9942.620097                       # average ReadReq miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker  9942.620097                       # average overall miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::total  9942.620097                       # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker  9942.620097                       # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::total  9942.620097                       # average overall miss latency
 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -803,86 +719,86 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.itb_walker_cache.writebacks::writebacks          621                       # number of writebacks
-system.cpu.itb_walker_cache.writebacks::total          621                       # number of writebacks
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker         4604                       # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::total         4604                       # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker         4604                       # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::total         4604                       # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker         4604                       # number of overall MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::total         4604                       # number of overall MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker     35677750                       # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total     35677750                       # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker     35677750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::total     35677750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker     35677750                       # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::total     35677750                       # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.376729                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.376729                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.376667                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.376667                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.376667                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.376667                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  7749.294092                       # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total  7749.294092                       # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  7749.294092                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  7749.294092                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  7749.294092                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  7749.294092                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.writebacks::writebacks          776                       # number of writebacks
+system.cpu.itb_walker_cache.writebacks::total          776                       # number of writebacks
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker         4309                       # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::total         4309                       # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker         4309                       # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::total         4309                       # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker         4309                       # number of overall MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::total         4309                       # number of overall MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker     34223750                       # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total     34223750                       # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker     34223750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::total     34223750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker     34223750                       # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::total     34223750                       # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.352474                       # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.352474                       # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.352417                       # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.352417                       # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.352417                       # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.352417                       # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  7942.388025                       # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total  7942.388025                       # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  7942.388025                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  7942.388025                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  7942.388025                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  7942.388025                       # average overall mshr miss latency
 system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.dtb_walker_cache.tags.replacements         7948                       # number of replacements
-system.cpu.dtb_walker_cache.tags.tagsinuse     5.052475                       # Cycle average of tags in use
-system.cpu.dtb_walker_cache.tags.total_refs        12793                       # Total number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.sampled_refs         7961                       # Sample count of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.avg_refs     1.606959                       # Average number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.warmup_cycle 5168018375000                       # Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker     5.052475                       # Average occupied blocks per requestor
-system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.315780                       # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.tags.occ_percent::total     0.315780                       # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024           13                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.replacements         8116                       # number of replacements
+system.cpu.dtb_walker_cache.tags.tagsinuse     5.061830                       # Cycle average of tags in use
+system.cpu.dtb_walker_cache.tags.total_refs        12619                       # Total number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.sampled_refs         8130                       # Sample count of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.avg_refs     1.552153                       # Average number of references to valid blocks.
+system.cpu.dtb_walker_cache.tags.warmup_cycle 5165732872000                       # Cycle when the warmup percentage was hit.
+system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker     5.061830                       # Average occupied blocks per requestor
+system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.316364                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.tags.occ_percent::total     0.316364                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024           14                       # Occupied blocks per task id
 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0            2                       # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            5                       # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2            4                       # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024     0.812500                       # Percentage of cache occupancy per task id
-system.cpu.dtb_walker_cache.tags.tag_accesses        53026                       # Number of tag accesses
-system.cpu.dtb_walker_cache.tags.data_accesses        53026                       # Number of data accesses
-system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker        12806                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.ReadReq_hits::total        12806                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker        12806                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::total        12806                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker        12806                       # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::total        12806                       # number of overall hits
-system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker         9138                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.ReadReq_misses::total         9138                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker         9138                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_misses::total         9138                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker         9138                       # number of overall misses
-system.cpu.dtb_walker_cache.overall_misses::total         9138                       # number of overall misses
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker     97347500                       # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::total     97347500                       # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker     97347500                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::total     97347500                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker     97347500                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::total     97347500                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker        21944                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.ReadReq_accesses::total        21944                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker        21944                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::total        21944                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker        21944                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::total        21944                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.416424                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.416424                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.416424                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::total     0.416424                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.416424                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::total     0.416424                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10653.042241                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10653.042241                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10653.042241                       # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10653.042241                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10653.042241                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10653.042241                       # average overall miss latency
+system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            6                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2            5                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
+system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024     0.875000                       # Percentage of cache occupancy per task id
+system.cpu.dtb_walker_cache.tags.tag_accesses        53134                       # Number of tag accesses
+system.cpu.dtb_walker_cache.tags.data_accesses        53134                       # Number of data accesses
+system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker        12626                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.ReadReq_hits::total        12626                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker        12626                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.demand_hits::total        12626                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker        12626                       # number of overall hits
+system.cpu.dtb_walker_cache.overall_hits::total        12626                       # number of overall hits
+system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker         9294                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.ReadReq_misses::total         9294                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker         9294                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.demand_misses::total         9294                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker         9294                       # number of overall misses
+system.cpu.dtb_walker_cache.overall_misses::total         9294                       # number of overall misses
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker     98603000                       # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::total     98603000                       # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker     98603000                       # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::total     98603000                       # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker     98603000                       # number of overall miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::total     98603000                       # number of overall miss cycles
+system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker        21920                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.ReadReq_accesses::total        21920                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker        21920                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.demand_accesses::total        21920                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker        21920                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::total        21920                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.423996                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.423996                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.423996                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::total     0.423996                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.423996                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::total     0.423996                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10609.317839                       # average ReadReq miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10609.317839                       # average ReadReq miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10609.317839                       # average overall miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10609.317839                       # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10609.317839                       # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10609.317839                       # average overall miss latency
 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -891,98 +807,98 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.dtb_walker_cache.writebacks::writebacks         3106                       # number of writebacks
-system.cpu.dtb_walker_cache.writebacks::total         3106                       # number of writebacks
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker         9138                       # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total         9138                       # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker         9138                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::total         9138                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker         9138                       # number of overall MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::total         9138                       # number of overall MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker     79071000                       # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total     79071000                       # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker     79071000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total     79071000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker     79071000                       # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total     79071000                       # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.416424                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.416424                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.416424                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.416424                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.416424                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.416424                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker  8652.987525                       # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total  8652.987525                       # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker  8652.987525                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total  8652.987525                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker  8652.987525                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total  8652.987525                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.writebacks::writebacks         3085                       # number of writebacks
+system.cpu.dtb_walker_cache.writebacks::total         3085                       # number of writebacks
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker         9294                       # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total         9294                       # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker         9294                       # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::total         9294                       # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker         9294                       # number of overall MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::total         9294                       # number of overall MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker     80015000                       # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total     80015000                       # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker     80015000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total     80015000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker     80015000                       # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total     80015000                       # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.423996                       # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.423996                       # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.423996                       # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.423996                       # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.423996                       # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.423996                       # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker  8609.317839                       # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total  8609.317839                       # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker  8609.317839                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total  8609.317839                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker  8609.317839                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total  8609.317839                       # average overall mshr miss latency
 system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements           1621547                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.997026                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            20035701                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1622059                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             12.352017                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle          50992250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.997026                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999994                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999994                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements           1620672                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.997242                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            20026945                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1621184                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             12.353283                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle          51279250                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.997242                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999995                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999995                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          100                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          333                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           78                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          102                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          307                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          102                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          88253354                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         88253354                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     11993197                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        11993197                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      8040328                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        8040328                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      20033525                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         20033525                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     20033525                       # number of overall hits
-system.cpu.dcache.overall_hits::total        20033525                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1308312                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1308312                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       315974                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       315974                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      1624286                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1624286                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1624286                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1624286                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  18913909300                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  18913909300                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  11002078938                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  11002078938                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  29915988238                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  29915988238                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  29915988238                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  29915988238                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     13301509                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     13301509                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      8356302                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      8356302                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     21657811                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     21657811                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     21657811                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     21657811                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.098358                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.098358                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037813                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.037813                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.074998                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.074998                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.074998                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.074998                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14456.726912                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14456.726912                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34819.570401                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 34819.570401                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 18417.931471                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 18417.931471                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 18417.931471                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 18417.931471                       # average overall miss latency
+system.cpu.dcache.tags.tag_accesses          88213750                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         88213750                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     11989262                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        11989262                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      8035472                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        8035472                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      20024734                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         20024734                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     20024734                       # number of overall hits
+system.cpu.dcache.overall_hits::total        20024734                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1308613                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1308613                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       314792                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       314792                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      1623405                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1623405                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1623405                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1623405                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  18824282553                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  18824282553                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  10745506942                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  10745506942                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  29569789495                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  29569789495                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  29569789495                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  29569789495                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     13297875                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     13297875                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      8350264                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      8350264                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     21648139                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     21648139                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     21648139                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     21648139                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.098408                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.098408                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037698                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.037698                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.074991                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.074991                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.074991                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.074991                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14384.911775                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14384.911775                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34135.260559                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 34135.260559                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 18214.671936                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 18214.671936                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 18214.671936                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 18214.671936                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -991,46 +907,46 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      1538973                       # number of writebacks
-system.cpu.dcache.writebacks::total           1538973                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1308312                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1308312                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       315974                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       315974                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1624286                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1624286                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1624286                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1624286                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  16288101700                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  16288101700                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10316379062                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  10316379062                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  26604480762                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  26604480762                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  26604480762                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  26604480762                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  94214673000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  94214673000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2537491500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2537491500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  96752164500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  96752164500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.098358                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.098358                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.037813                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.037813                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.074998                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.074998                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.074998                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.074998                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12449.707486                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12449.707486                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32649.455531                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32649.455531                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16379.184923                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 16379.184923                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16379.184923                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 16379.184923                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks      1537729                       # number of writebacks
+system.cpu.dcache.writebacks::total           1537729                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1308613                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1308613                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       314792                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       314792                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1623405                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1623405                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1623405                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1623405                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  16198393447                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  16198393447                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10064156058                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  10064156058                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  26262549505                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  26262549505                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  26262549505                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  26262549505                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  94214672500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  94214672500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2537739500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2537739500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  96752412000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  96752412000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.098408                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.098408                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.037698                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.037698                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.074991                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.074991                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.074991                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.074991                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12378.291708                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12378.291708                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31970.812657                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31970.812657                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16177.447713                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 16177.447713                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16177.447713                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 16177.447713                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1038,184 +954,184 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput                49185341                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq        2692945                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp       2692419                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq         13775                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp        13775                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback      1542700                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq         2176                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp         2176                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       360518                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       313820                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1577205                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      5977035                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side         8133                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        18986                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           7581359                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     50470144                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    203948077                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       225856                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       630272                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total      255274349                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus         255253101                       # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus       333120                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy     3831866500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.throughput                49161645                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq        2696443                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       2695917                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq         13777                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp        13777                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback      1541590                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         2211                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp         2211                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       359301                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       312590                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1583869                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      5973994                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side         7897                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        19197                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           7584957                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     50683392                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    203806901                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       229632                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       633792                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total      255353717                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus         255333045                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus       327296                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy     3831359500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy       498000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy       484500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    1185336258                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy    1190263759                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    3054054238                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    3051445995                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy       6906500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy       6464000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy      13707250                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy      13941000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
-system.cpu.l2cache.tags.replacements            86910                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        64731.196890                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            3488433                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           151626                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            23.006826                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements            86417                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        64729.830083                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            3490254                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           151212                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            23.081859                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 50120.476905                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     0.033461                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.141258                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  3445.447212                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 11165.098054                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.764778                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000001                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks 50287.594494                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     0.027550                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.141486                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  3384.035479                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 11058.031076                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.767328                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000000                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000002                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.052573                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.170366                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.987720                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        64716                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           23                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1           89                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2864                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         4951                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        56789                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.987488                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         32180081                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        32180081                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker         6740                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         2903                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst       775712                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data      1279207                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        2064562                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      1542700                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      1542700                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data          304                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total          304                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       200752                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       200752                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker         6740                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker         2903                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst       775712                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      1479959                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2265314                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker         6740                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker         2903                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst       775712                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      1479959                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2265314                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker            2                       # number of ReadReq misses
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.051636                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.168732                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.987699                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        64795                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           57                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          115                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2818                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         4824                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        56981                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.988693                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         32189031                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        32189031                       # Number of data accesses
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker         6817                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         2807                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.inst       779009                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data      1279777                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        2068410                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      1541590                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      1541590                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data          307                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total          307                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       199552                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       199552                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker         6817                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.itb.walker         2807                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst       779009                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      1479329                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2267962                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.dtb.walker         6817                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.itb.walker         2807                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst       779009                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      1479329                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2267962                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker            1                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            5                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.inst        12884                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data        28341                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total        41232                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data         1356                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total         1356                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       113042                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       113042                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker            2                       # number of demand (read+write) misses
+system.cpu.l2cache.ReadReq_misses::cpu.inst        12919                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data        28035                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        40960                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data         1395                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total         1395                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       113025                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       113025                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.dtb.walker            1                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.itb.walker            5                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst        12884                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       141383                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        154274                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker            2                       # number of overall misses
+system.cpu.l2cache.demand_misses::cpu.inst        12919                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       141060                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        153985                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.dtb.walker            1                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.itb.walker            5                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst        12884                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       141383                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       154274                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker       136750                       # number of ReadReq miss cycles
+system.cpu.l2cache.overall_misses::cpu.inst        12919                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       141060                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       153985                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker        75000                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker       347500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    979557242                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data   2186954200                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total   3166995692                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     16260363                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total     16260363                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   7957275400                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   7957275400                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker       136750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    948719241                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data   2091207947                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   3040349688                       # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     16786842                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total     16786842                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   7717314435                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   7717314435                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker        75000                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_latency::cpu.itb.walker       347500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    979557242                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  10144229600                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  11124271092                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker       136750                       # number of overall miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    948719241                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   9808522382                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  10757664123                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker        75000                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_latency::cpu.itb.walker       347500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    979557242                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  10144229600                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  11124271092                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker         6742                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         2908                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.inst       788596                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      1307548                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      2105794                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      1542700                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      1542700                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data         1660                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total         1660                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       313794                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       313794                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker         6742                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker         2908                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst       788596                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      1621342                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2419588                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker         6742                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker         2908                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst       788596                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      1621342                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2419588                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000297                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.001719                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.016338                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.021675                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.019580                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.816867                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.816867                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.360243                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.360243                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000297                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.001719                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016338                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.087201                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.063760                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000297                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.001719                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016338                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.087201                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.063760                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker        68375                       # average ReadReq miss latency
+system.cpu.l2cache.overall_miss_latency::cpu.inst    948719241                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   9808522382                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  10757664123                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker         6818                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         2812                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.inst       791928                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      1307812                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      2109370                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      1541590                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      1541590                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data         1702                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total         1702                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       312577                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       312577                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker         6818                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.itb.walker         2812                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst       791928                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      1620389                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2421947                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker         6818                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.itb.walker         2812                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst       791928                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      1620389                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2421947                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000147                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.001778                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.016313                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.021437                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.019418                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.819624                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.819624                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.361591                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.361591                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000147                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.001778                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016313                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.087053                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.063579                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000147                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.001778                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016313                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.087053                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.063579                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker        75000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        69500                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76028.969419                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77165.738682                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 76809.169868                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11991.418142                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11991.418142                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70392.202898                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70392.202898                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker        68375                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73435.965709                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74592.757161                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 74227.287305                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12033.578495                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12033.578495                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68279.711878                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68279.711878                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker        75000                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker        69500                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76028.969419                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71749.995403                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 72107.231886                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker        68375                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73435.965709                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69534.399419                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 69861.766555                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker        75000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        69500                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76028.969419                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71749.995403                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 72107.231886                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73435.965709                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69534.399419                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 69861.766555                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1224,90 +1140,90 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        80066                       # number of writebacks
-system.cpu.l2cache.writebacks::total            80066                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker            2                       # number of ReadReq MSHR misses
+system.cpu.l2cache.writebacks::writebacks        79802                       # number of writebacks
+system.cpu.l2cache.writebacks::total            79802                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker            1                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            5                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        12884                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        28341                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total        41232                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         1356                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total         1356                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       113042                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       113042                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker            2                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        12919                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        28035                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        40960                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         1395                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total         1395                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       113025                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       113025                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker            1                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            5                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        12884                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       141383                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       154274                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker            2                       # number of overall MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        12919                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       141060                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       153985                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker            1                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            5                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        12884                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       141383                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       154274                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker       111250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        12919                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       141060                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       153985                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker        62500                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker       285000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    818022758                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1831787800                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2650206808                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     14478338                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     14478338                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6543285600                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6543285600                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker       111250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    786875759                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1740299053                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2527522312                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     14883877                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     14883877                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6303896565                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6303896565                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker        62500                       # number of demand (read+write) MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker       285000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    818022758                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   8375073400                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   9193492408                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker       111250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    786875759                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   8044195618                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   8831418877                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker        62500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker       285000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    818022758                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8375073400                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   9193492408                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  86655869500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  86655869500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2370854000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2370854000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  89026723500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  89026723500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000297                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.001719                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.016338                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.021675                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.019580                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.816867                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.816867                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.360243                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.360243                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000297                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.001719                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016338                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.087201                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.063760                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000297                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.001719                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016338                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.087201                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.063760                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker        55625                       # average ReadReq mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    786875759                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8044195618                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   8831418877                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data  86655869000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  86655869000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   2371074000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   2371074000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  89026943000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total  89026943000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000147                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.001778                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.016313                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.021437                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.019418                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.819624                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.819624                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.361591                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.361591                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.000147                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.001778                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.016313                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.087053                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.063579                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.000147                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.001778                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.016313                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.087053                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.063579                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker        62500                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        57000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63491.365880                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64633.844960                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64275.485254                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10677.240413                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10677.240413                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57883.668017                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57883.668017                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker        55625                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60908.410790                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62075.942679                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61707.087695                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10669.445878                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10669.445878                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55774.355806                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55774.355806                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker        62500                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        57000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63491.365880                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59236.778113                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59591.975369                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker        55625                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60908.410790                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57026.766043                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57352.462103                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker        62500                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        57000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63491.365880                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59236.778113                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59591.975369                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60908.410790                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57026.766043                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57352.462103                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
index 116ba4c7208bbe22924c12c6e80a9381450d25a5..0bab63428c6d3cd0788022cc9f211b542774212a 100644 (file)
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000025                       # Number of seconds simulated
-sim_ticks                                    25485000                       # Number of ticks simulated
-final_tick                                   25485000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000026                       # Number of seconds simulated
+sim_ticks                                    25552000                       # Number of ticks simulated
+final_tick                                   25552000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  24806                       # Simulator instruction rate (inst/s)
-host_op_rate                                    24805                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               98922905                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 229760                       # Number of bytes of host memory used
-host_seconds                                     0.26                       # Real time elapsed on the host
+host_inst_rate                                  78801                       # Simulator instruction rate (inst/s)
+host_op_rate                                    78787                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              314994021                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 262608                       # Number of bytes of host memory used
+host_seconds                                     0.08                       # Real time elapsed on the host
 sim_insts                                        6390                       # Number of instructions simulated
 sim_ops                                          6390                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total           19200                       # Nu
 system.physmem.num_reads::cpu.inst                300                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                168                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   468                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            753384344                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            421895232                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1175279576                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       753384344                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          753384344                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           753384344                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           421895232                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1175279576                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            751408892                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            420788979                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1172197871                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       751408892                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          751408892                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           751408892                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           420788979                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1172197871                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           469                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                         469                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        25470500                       # Total gap between requests
+system.physmem.totGap                        25537500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -90,9 +90,9 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       317                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       124                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        20                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       313                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       126                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        22                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         8                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -154,54 +154,77 @@ system.physmem.wrQLenPdf::28                        0                       # Wh
 system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples           84                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      294.095238                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     157.496730                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     421.391602                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64                37     44.05%     44.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128               14     16.67%     60.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192                5      5.95%     66.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256                5      5.95%     72.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320                4      4.76%     77.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384                5      5.95%     83.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448                1      1.19%     84.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576                1      1.19%     85.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704                2      2.38%     88.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768                1      1.19%     89.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832                1      1.19%     90.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896                2      2.38%     92.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960                1      1.19%     94.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216               2      2.38%     96.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1792               1      1.19%     97.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856               1      1.19%     98.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2240               1      1.19%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total             84                       # Bytes accessed per row activation
-system.physmem.totQLat                        2272250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  12262250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples           54                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      317.629630                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     196.201768                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     327.982069                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             16     29.63%     29.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           16     29.63%     59.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383            7     12.96%     72.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            4      7.41%     79.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            1      1.85%     81.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            1      1.85%     83.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            2      3.70%     87.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151            7     12.96%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total             54                       # Bytes accessed per row activation
+system.physmem.totQLat                        2560250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  12605250                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      2345000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                     7645000                       # Total ticks spent accessing banks
-system.physmem.avgQLat                        4844.88                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    16300.64                       # Average bank access latency per DRAM burst
+system.physmem.totBankLat                     7700000                       # Total ticks spent accessing banks
+system.physmem.avgQLat                        5458.96                       # Average queueing delay per DRAM burst
+system.physmem.avgBankLat                    16417.91                       # Average bank access latency per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  26145.52                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        1177.79                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  26876.87                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        1174.70                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     1177.79                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     1174.70                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           9.20                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       9.20                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           9.18                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       9.18                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         0.48                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.50                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                        385                       # Number of row buffer hits during reads
+system.physmem.readRowHits                        378                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.09                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   80.60                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        54308.10                       # Average gap between requests
-system.physmem.pageHitRate                      82.09                       # Row buffer hit rate, read and write combined
+system.physmem.avgGap                        54450.96                       # Average gap between requests
+system.physmem.pageHitRate                      80.60                       # Row buffer hit rate, read and write combined
 system.physmem.prechargeAllPercent               0.05                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                   1175279576                       # Throughput (bytes/s)
+system.membus.throughput                   1172197871                       # Throughput (bytes/s)
 system.membus.trans_dist::ReadReq                 396                       # Transaction distribution
 system.membus.trans_dist::ReadResp                395                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                73                       # Transaction distribution
@@ -214,8 +237,8 @@ system.membus.data_through_bus                  29952                       # To
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
 system.membus.reqLayer0.occupancy              560000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               2.2                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            4374750                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             17.2                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            4371250                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             17.1                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                    1632                       # Number of BP lookups
 system.cpu.branchPred.condPredicted              1160                       # Number of conditional branches predicted
@@ -230,18 +253,18 @@ system.cpu.dtb.fetch_hits                           0                       # IT
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                         1184                       # DTB read hits
+system.cpu.dtb.read_hits                         1183                       # DTB read hits
 system.cpu.dtb.read_misses                          7                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                     1191                       # DTB read accesses
-system.cpu.dtb.write_hits                         893                       # DTB write hits
+system.cpu.dtb.read_accesses                     1190                       # DTB read accesses
+system.cpu.dtb.write_hits                         890                       # DTB write hits
 system.cpu.dtb.write_misses                         3                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                     896                       # DTB write accesses
-system.cpu.dtb.data_hits                         2077                       # DTB hits
+system.cpu.dtb.write_accesses                     893                       # DTB write accesses
+system.cpu.dtb.data_hits                         2073                       # DTB hits
 system.cpu.dtb.data_misses                         10                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                     2087                       # DTB accesses
+system.cpu.dtb.data_accesses                     2083                       # DTB accesses
 system.cpu.itb.fetch_hits                         915                       # ITB hits
 system.cpu.itb.fetch_misses                        17                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
@@ -259,18 +282,18 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   17                       # Number of system calls
-system.cpu.numCycles                            50971                       # number of cpu cycles simulated
+system.cpu.numCycles                            51105                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.branch_predictor.predictedTaken          502                       # Number of Branches Predicted As Taken (True).
 system.cpu.branch_predictor.predictedNotTaken         1130                       # Number of Branches Predicted As Not Taken (False).
-system.cpu.regfile_manager.intRegFileReads         5174                       # Number of Reads from Int. Register File
+system.cpu.regfile_manager.intRegFileReads         5177                       # Number of Reads from Int. Register File
 system.cpu.regfile_manager.intRegFileWrites         4567                       # Number of Writes to Int. Register File
-system.cpu.regfile_manager.intRegFileAccesses         9741                       # Total Accesses (Read+Write) to the Int. Register File
+system.cpu.regfile_manager.intRegFileAccesses         9744                       # Total Accesses (Read+Write) to the Int. Register File
 system.cpu.regfile_manager.floatRegFileReads            8                       # Number of Reads from FP Register File
 system.cpu.regfile_manager.floatRegFileWrites            2                       # Number of Writes to FP Register File
 system.cpu.regfile_manager.floatRegFileAccesses           10                       # Total Accesses (Read+Write) to the FP Register File
-system.cpu.regfile_manager.regForwards           2976                       # Number of Registers Read Through Forwarding Logic
+system.cpu.regfile_manager.regForwards           2973                       # Number of Registers Read Through Forwarding Logic
 system.cpu.agen_unit.agens                       2152                       # Number of Address Generations
 system.cpu.execution_unit.predictedTakenIncorrect          320                       # Number of Branches Incorrectly Predicted As Taken.
 system.cpu.execution_unit.predictedNotTakenIncorrect          325                       # Number of Branches Incorrectly Predicted As Not Taken).
@@ -281,12 +304,12 @@ system.cpu.execution_unit.executions             4448                       # Nu
 system.cpu.mult_div_unit.multiplies                 1                       # Number of Multipy Operations Executed
 system.cpu.mult_div_unit.divides                    0                       # Number of Divide Operations Executed
 system.cpu.contextSwitches                          1                       # Number of context switches
-system.cpu.threadCycles                         11614                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles                         11596                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
 system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled                             467                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           43595                       # Number of cycles cpu's stages were not processed
-system.cpu.runCycles                             7376                       # Number of cycles cpu stages are processed.
-system.cpu.activity                         14.470974                       # Percentage of cycles cpu is active
+system.cpu.timesIdled                             469                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           43730                       # Number of cycles cpu's stages were not processed
+system.cpu.runCycles                             7375                       # Number of cycles cpu stages are processed.
+system.cpu.activity                         14.431073                       # Percentage of cycles cpu is active
 system.cpu.comLoads                              1183                       # Number of Load instructions committed
 system.cpu.comStores                              865                       # Number of Store instructions committed
 system.cpu.comBranches                           1050                       # Number of Branches instructions committed
@@ -298,36 +321,36 @@ system.cpu.committedInsts                        6390                       # Nu
 system.cpu.committedOps                          6390                       # Number of Ops committed (Per-Thread)
 system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
 system.cpu.committedInsts_total                  6390                       # Number of Instructions committed (Total)
-system.cpu.cpi                               7.976682                       # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi                               7.997653                       # CPI: Cycles Per Instruction (Per-Thread)
 system.cpu.smt_cpi                                nan                       # CPI: Total SMT-CPI
-system.cpu.cpi_total                         7.976682                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.125365                       # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.cpi_total                         7.997653                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.125037                       # IPC: Instructions Per Cycle (Per-Thread)
 system.cpu.smt_ipc                                nan                       # IPC: Total SMT-IPC
-system.cpu.ipc_total                         0.125365                       # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles                    46047                       # Number of cycles 0 instructions are processed.
+system.cpu.ipc_total                         0.125037                       # IPC: Total IPC of All Threads
+system.cpu.stage0.idleCycles                    46181                       # Number of cycles 0 instructions are processed.
 system.cpu.stage0.runCycles                      4924                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization                9.660395                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles                    47078                       # Number of cycles 0 instructions are processed.
+system.cpu.stage0.utilization                9.635065                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles                    47212                       # Number of cycles 0 instructions are processed.
 system.cpu.stage1.runCycles                      3893                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization                7.637676                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles                    46810                       # Number of cycles 0 instructions are processed.
+system.cpu.stage1.utilization                7.617650                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles                    46944                       # Number of cycles 0 instructions are processed.
 system.cpu.stage2.runCycles                      4161                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization                8.163465                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage3.idleCycles                    49637                       # Number of cycles 0 instructions are processed.
-system.cpu.stage3.runCycles                      1334                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage3.utilization                2.617174                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles                    46513                       # Number of cycles 0 instructions are processed.
-system.cpu.stage4.runCycles                      4458                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization                8.746150                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.utilization                8.142060                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles                    49775                       # Number of cycles 0 instructions are processed.
+system.cpu.stage3.runCycles                      1330                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage3.utilization                2.602485                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles                    46641                       # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles                      4464                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization                8.734957                       # Percentage of cycles stage was utilized (processing insts).
 system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse           142.311081                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse           142.169993                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                 560                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               301                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs              1.860465                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   142.311081                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.069488                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.069488                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   142.169993                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.069419                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.069419                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          301                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0          126                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          175                       # Occupied blocks per task id
@@ -346,12 +369,12 @@ system.cpu.icache.demand_misses::cpu.inst          355                       # n
 system.cpu.icache.demand_misses::total            355                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          355                       # number of overall misses
 system.cpu.icache.overall_misses::total           355                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     24550250                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     24550250                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     24550250                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     24550250                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     24550250                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     24550250                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     25349750                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     25349750                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     25349750                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     25349750                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     25349750                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     25349750                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst          915                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total          915                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst          915                       # number of demand (read+write) accesses
@@ -364,12 +387,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.387978
 system.cpu.icache.demand_miss_rate::total     0.387978                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.387978                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.387978                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69155.633803                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 69155.633803                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 69155.633803                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 69155.633803                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 69155.633803                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 69155.633803                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71407.746479                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 71407.746479                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 71407.746479                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 71407.746479                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 71407.746479                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 71407.746479                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs           89                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 1                       # number of cycles access was blocked
@@ -390,26 +413,26 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          302
 system.cpu.icache.demand_mshr_misses::total          302                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          302                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          302                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     20718250                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     20718250                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     20718250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     20718250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     20718250                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     20718250                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     21532500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     21532500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     21532500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     21532500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     21532500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     21532500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.330055                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.330055                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.330055                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.330055                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.330055                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.330055                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68603.476821                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68603.476821                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68603.476821                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 68603.476821                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68603.476821                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 68603.476821                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71299.668874                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71299.668874                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71299.668874                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 71299.668874                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71299.668874                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 71299.668874                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput              1177790857                       # Throughput (bytes/s)
+system.cpu.toL2Bus.throughput              1174702567                       # Throughput (bytes/s)
 system.cpu.toL2Bus.trans_dist::ReadReq            397                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp           396                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           73                       # Transaction distribution
@@ -424,21 +447,21 @@ system.cpu.toL2Bus.data_through_bus             30016                       # To
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
 system.cpu.toL2Bus.reqLayer0.occupancy         235000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.9                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        508750                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy        508000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          2.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        276000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy        274750                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.1                       # Layer utilization (%)
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          199.093004                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          198.925679                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  1                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              395                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.002532                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   142.347593                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    56.745411                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004344                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.001732                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.006076                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   142.205920                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    56.719759                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004340                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.001731                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.006071                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          395                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          155                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          240                       # Occupied blocks per task id
@@ -462,17 +485,17 @@ system.cpu.l2cache.demand_misses::total           469                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          301                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          168                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          469                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     20399750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      7465250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     27865000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      4857750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      4857750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     20399750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data     12323000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     32722750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     20399750                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data     12323000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     32722750                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     21214000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      6927250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     28141250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      4931500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      4931500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     21214000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data     11858750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     33072750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     21214000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data     11858750                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     33072750                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst          302                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data           95                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total          397                       # number of ReadReq accesses(hits+misses)
@@ -495,17 +518,17 @@ system.cpu.l2cache.demand_miss_rate::total     0.997872                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996689                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.997872                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67773.255814                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78581.578947                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 70366.161616                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66544.520548                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66544.520548                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67773.255814                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73351.190476                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 69771.321962                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67773.255814                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73351.190476                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 69771.321962                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70478.405316                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72918.421053                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 71063.762626                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67554.794521                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67554.794521                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70478.405316                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70587.797619                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 70517.590618                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70478.405316                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70587.797619                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 70517.590618                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -525,17 +548,17 @@ system.cpu.l2cache.demand_mshr_misses::total          469
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          301                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          168                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          469                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     16625250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      6283250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     22908500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      3954250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      3954250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     16625250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     10237500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     26862750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     16625250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     10237500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     26862750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     17443000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      5745750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     23188750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      4029500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      4029500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     17443000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      9775250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     27218250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     17443000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      9775250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     27218250                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.996689                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.997481                       # mshr miss rate for ReadReq accesses
@@ -547,27 +570,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.997872
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996689                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.997872                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55233.388704                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66139.473684                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57849.747475                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54167.808219                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54167.808219                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55233.388704                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60937.500000                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57276.652452                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55233.388704                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60937.500000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57276.652452                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57950.166113                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60481.578947                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58557.449495                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55198.630137                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55198.630137                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57950.166113                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58186.011905                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58034.648188                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57950.166113                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58186.011905                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58034.648188                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           103.493430                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse           103.450623                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs                1601                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               168                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs              9.529762                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   103.493430                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.025267                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.025267                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data   103.450623                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.025256                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.025256                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          168                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           40                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          128                       # Occupied blocks per task id
@@ -590,14 +613,14 @@ system.cpu.dcache.demand_misses::cpu.data          447                       # n
 system.cpu.dcache.demand_misses::total            447                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data          447                       # number of overall misses
 system.cpu.dcache.overall_misses::total           447                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      7909250                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      7909250                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     21376500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     21376500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     29285750                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     29285750                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     29285750                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     29285750                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      7371250                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      7371250                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     21672250                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     21672250                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     29043500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     29043500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     29043500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     29043500                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data         1183                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total         1183                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          865                       # number of WriteReq accesses(hits+misses)
@@ -614,19 +637,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.218262
 system.cpu.dcache.demand_miss_rate::total     0.218262                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.218262                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.218262                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 81538.659794                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 81538.659794                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61075.714286                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 61075.714286                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 65516.219239                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 65516.219239                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 65516.219239                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 65516.219239                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs          467                       # number of cycles access was blocked
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75992.268041                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 75992.268041                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61920.714286                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 61920.714286                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 64974.272931                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 64974.272931                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 64974.272931                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 64974.272931                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs          487                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                30                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                26                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    15.566667                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    18.730769                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
@@ -646,14 +669,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          168
 system.cpu.dcache.demand_mshr_misses::total          168                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          168                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          168                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      7566750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      7566750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      4935250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      4935250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     12502000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     12502000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     12502000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     12502000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      7028750                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      7028750                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      5009000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      5009000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     12037750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     12037750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     12037750                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     12037750                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.080304                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.080304                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.084393                       # mshr miss rate for WriteReq accesses
@@ -662,14 +685,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.082031
 system.cpu.dcache.demand_mshr_miss_rate::total     0.082031                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.082031                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.082031                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data        79650                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total        79650                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67606.164384                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67606.164384                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74416.666667                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 74416.666667                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74416.666667                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 74416.666667                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73986.842105                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73986.842105                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68616.438356                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68616.438356                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71653.273810                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 71653.273810                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71653.273810                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 71653.273810                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 7833baea695c03d1049c9aad7dcf63cf2d70ef6c..8bfd28333bf0e988c1a35975f3f2a4068503de88 100644 (file)
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000021                       # Number of seconds simulated
-sim_ticks                                    21065000                       # Number of ticks simulated
-final_tick                                   21065000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    21078000                       # Number of ticks simulated
+final_tick                                   21078000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  40027                       # Simulator instruction rate (inst/s)
-host_op_rate                                    40023                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              132300521                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 230780                       # Number of bytes of host memory used
-host_seconds                                     0.16                       # Real time elapsed on the host
+host_inst_rate                                  72140                       # Simulator instruction rate (inst/s)
+host_op_rate                                    72127                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              238549554                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 265696                       # Number of bytes of host memory used
+host_seconds                                     0.09                       # Real time elapsed on the host
 sim_insts                                        6372                       # Number of instructions simulated
 sim_ops                                          6372                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total           20032                       # Nu
 system.physmem.num_reads::cpu.inst                313                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                174                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   487                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            950961310                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            528649418                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1479610729                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       950961310                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          950961310                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           950961310                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           528649418                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1479610729                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            950374798                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            528323370                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1478698169                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       950374798                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          950374798                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           950374798                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           528323370                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1478698169                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           488                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                         488                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        21032000                       # Total gap between requests
+system.physmem.totGap                        21045000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -90,10 +90,10 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       288                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       138                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        45                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        12                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       276                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       146                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        48                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        13                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         5                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
@@ -154,54 +154,76 @@ system.physmem.wrQLenPdf::28                        0                       # Wh
 system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples           85                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      326.023529                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     167.928934                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     483.454089                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64                37     43.53%     43.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128                8      9.41%     52.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192               10     11.76%     64.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256                7      8.24%     72.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320                3      3.53%     76.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384                2      2.35%     78.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448                2      2.35%     81.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512                4      4.71%     85.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576                1      1.18%     87.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640                1      1.18%     88.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832                2      2.35%     90.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960                1      1.18%     91.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024               1      1.18%     92.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472               3      3.53%     96.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1920               1      1.18%     97.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2304               1      1.18%     98.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2432               1      1.18%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total             85                       # Bytes accessed per row activation
-system.physmem.totQLat                        3258750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  13288750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples           61                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      328.393443                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     194.167058                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     347.898610                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             21     34.43%     34.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           16     26.23%     60.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383            6      9.84%     70.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            4      6.56%     77.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            3      4.92%     81.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            1      1.64%     83.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151           10     16.39%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total             61                       # Bytes accessed per row activation
+system.physmem.totQLat                        3243750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  13328750                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      2440000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                     7590000                       # Total ticks spent accessing banks
-system.physmem.avgQLat                        6677.77                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    15553.28                       # Average bank access latency per DRAM burst
+system.physmem.totBankLat                     7645000                       # Total ticks spent accessing banks
+system.physmem.avgQLat                        6647.03                       # Average queueing delay per DRAM burst
+system.physmem.avgBankLat                    15665.98                       # Average bank access latency per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  27231.05                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        1482.65                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  27313.01                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        1481.73                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     1482.65                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     1481.73                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                          11.58                       # Data bus utilization in percentage
 system.physmem.busUtilRead                      11.58                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         0.63                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.72                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                        403                       # Number of row buffer hits during reads
+system.physmem.readRowHits                        394                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.58                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   80.74                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        43098.36                       # Average gap between requests
-system.physmem.pageHitRate                      82.58                       # Row buffer hit rate, read and write combined
+system.physmem.avgGap                        43125.00                       # Average gap between requests
+system.physmem.pageHitRate                      80.74                       # Row buffer hit rate, read and write combined
 system.physmem.prechargeAllPercent               0.10                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                   1479610729                       # Throughput (bytes/s)
+system.membus.throughput                   1478698169                       # Throughput (bytes/s)
 system.membus.trans_dist::ReadReq                 415                       # Transaction distribution
 system.membus.trans_dist::ReadResp                414                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                73                       # Transaction distribution
@@ -212,40 +234,40 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
 system.membus.tot_pkt_size::total               31168                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.data_through_bus                  31168                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy              619000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy              617000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               2.9                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            4556000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy            4550500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization             21.6                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                    2883                       # Number of BP lookups
-system.cpu.branchPred.condPredicted              1697                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect               511                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups                 2200                       # Number of BTB lookups
+system.cpu.branchPred.lookups                    2894                       # Number of BP lookups
+system.cpu.branchPred.condPredicted              1702                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect               512                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups                 2209                       # Number of BTB lookups
 system.cpu.branchPred.BTBHits                     756                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             34.363636                       # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct             34.223631                       # BTB Hit Percentage
 system.cpu.branchPred.usedRAS                     416                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                 74                       # Number of incorrect RAS predictions.
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                         2076                       # DTB read hits
+system.cpu.dtb.read_hits                         2078                       # DTB read hits
 system.cpu.dtb.read_misses                         47                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                     2123                       # DTB read accesses
-system.cpu.dtb.write_hits                        1063                       # DTB write hits
+system.cpu.dtb.read_accesses                     2125                       # DTB read accesses
+system.cpu.dtb.write_hits                        1062                       # DTB write hits
 system.cpu.dtb.write_misses                        31                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                    1094                       # DTB write accesses
-system.cpu.dtb.data_hits                         3139                       # DTB hits
+system.cpu.dtb.write_accesses                    1093                       # DTB write accesses
+system.cpu.dtb.data_hits                         3140                       # DTB hits
 system.cpu.dtb.data_misses                         78                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                     3217                       # DTB accesses
-system.cpu.itb.fetch_hits                        2382                       # ITB hits
+system.cpu.dtb.data_accesses                     3218                       # DTB accesses
+system.cpu.itb.fetch_hits                        2388                       # ITB hits
 system.cpu.itb.fetch_misses                        39                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                    2421                       # ITB accesses
+system.cpu.itb.fetch_accesses                    2427                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -259,95 +281,95 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   17                       # Number of system calls
-system.cpu.numCycles                            42131                       # number of cpu cycles simulated
+system.cpu.numCycles                            42157                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles               8531                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          16553                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        2883                       # Number of branches that fetch encountered
+system.cpu.fetch.icacheStallCycles               8510                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          16605                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        2894                       # Number of branches that fetch encountered
 system.cpu.fetch.predictedBranches               1172                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          2963                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                    1902                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles                   1547                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.Cycles                          2970                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                    1911                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles                   1405                       # Number of cycles fetch has spent blocked
 system.cpu.fetch.MiscStallCycles                   25                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingTrapStallCycles           747                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                      2382                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   383                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              15113                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.095282                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.492986                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines                      2388                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   385                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples              14964                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.109663                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.506678                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                    12150     80.39%     80.39% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                      318      2.10%     82.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      234      1.55%     84.05% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      214      1.42%     85.46% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      255      1.69%     87.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      240      1.59%     88.74% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      264      1.75%     90.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      183      1.21%     91.70% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     1255      8.30%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                    11994     80.15%     80.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                      318      2.13%     82.28% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      234      1.56%     83.84% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      214      1.43%     85.27% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      255      1.70%     86.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      241      1.61%     88.59% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      264      1.76%     90.35% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      184      1.23%     91.58% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                     1260      8.42%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                15113                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.068429                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.392894                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                     9345                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                  1711                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      2764                       # Number of cycles decode is running
+system.cpu.fetch.rateDist::total                14964                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.068648                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.393885                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                     9327                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                  1567                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      2770                       # Number of cycles decode is running
 system.cpu.decode.UnblockCycles                    74                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                   1219                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved                  242                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                    85                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts                  15308                       # Number of instructions handled by decode
+system.cpu.decode.SquashCycles                   1226                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved                  243                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                    86                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts                  15343                       # Number of instructions handled by decode
 system.cpu.decode.SquashedInsts                   223                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                   1219                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                     9554                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                     808                       # Number of cycles rename is blocking
+system.cpu.rename.SquashCycles                   1226                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                     9537                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                     678                       # Number of cycles rename is blocking
 system.cpu.rename.serializeStallCycles            554                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      2623                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                   355                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  14604                       # Number of instructions processed by rename
+system.cpu.rename.RunCycles                      2628                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                   341                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                  14637                       # Number of instructions processed by rename
 system.cpu.rename.ROBFullEvents                    10                       # Number of times rename has blocked due to ROB full
 system.cpu.rename.IQFullEvents                      5                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents                   313                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands               10951                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 18225                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            18216                       # Number of integer rename lookups
+system.cpu.rename.LSQFullEvents                   297                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands               10979                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 18262                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            18253                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups                 8                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps                  4570                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                     6381                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                 29                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts             23                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                       808                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 2766                       # Number of loads inserted to the mem dependence unit.
+system.cpu.rename.UndoneMaps                     6409                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                 30                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts             24                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                       843                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads                 2769                       # Number of loads inserted to the mem dependence unit.
 system.cpu.memDep0.insertedStores                1356                       # Number of stores inserted to the mem dependence unit.
 system.cpu.memDep0.conflictingLoads                 3                       # Number of conflicting loads.
 system.cpu.memDep0.conflictingStores                0                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                      12953                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsAdded                      12974                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqNonSpecInstsAdded                  29                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                     10771                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued                54                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined            6180                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined         3598                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued                     10780                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued                56                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined            6201                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined         3614                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved             12                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         15113                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.712698                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.354769                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples         14964                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.720396                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.363744                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0               10572     69.95%     69.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                1678     11.10%     81.06% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                1174      7.77%     88.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 728      4.82%     93.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 498      3.30%     96.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 270      1.79%     98.72% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 146      0.97%     99.69% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0               10463     69.92%     69.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                1623     10.85%     80.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                1158      7.74%     88.51% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 756      5.05%     93.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 501      3.35%     96.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 270      1.80%     98.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 146      0.98%     99.69% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                  33      0.22%     99.91% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                  14      0.09%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           15113                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           14964                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntAlu                      14     12.50%     12.50% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                      0      0.00%     12.50% # attempts to use FU when none available
@@ -383,113 +405,113 @@ system.cpu.iq.fu_full::MemWrite                    38     33.93%    100.00% # at
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 2      0.02%      0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                  7236     67.18%     67.20% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    1      0.01%     67.21% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.21% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     67.23% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.23% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.23% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.23% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.23% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.23% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 2397     22.25%     89.48% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                1133     10.52%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                  7243     67.19%     67.21% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    1      0.01%     67.22% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.22% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.24% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 2399     22.25%     89.49% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1133     10.51%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                  10771                       # Type of FU issued
-system.cpu.iq.rate                           0.255655                       # Inst issue rate
+system.cpu.iq.FU_type_0::total                  10780                       # Type of FU issued
+system.cpu.iq.rate                           0.255711                       # Inst issue rate
 system.cpu.iq.fu_busy_cnt                         112                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.010398                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              36800                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             19167                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses         9598                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fu_busy_rate                   0.010390                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              36671                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             19208                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses         9602                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                  21                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                 10                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses           10                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                  10870                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                  10879                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                      11                       # Number of floating point alu accesses
 system.cpu.iew.lsq.thread0.forwLoads               73                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads         1583                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads         1586                       # Number of loads squashed
 system.cpu.iew.lsq.thread0.ignoredResponses            2                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation           17                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.memOrderViolation           16                       # Number of memory ordering violations
 system.cpu.iew.lsq.thread0.squashedStores          491                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            1                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked           131                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked           127                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                   1219                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                     264                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                    22                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               13071                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                   1226                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                     247                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                    13                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts               13092                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts               175                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  2766                       # Number of dispatched load instructions
+system.cpu.iew.iewDispLoadInsts                  2769                       # Number of dispatched load instructions
 system.cpu.iew.iewDispStoreInsts                 1356                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts                 29                       # Number of dispatched non-speculative instructions
 system.cpu.iew.iewIQFullEvents                      2                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewLSQFullEvents                     0                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents             17                       # Number of memory order violations
+system.cpu.iew.memOrderViolationEvents             16                       # Number of memory order violations
 system.cpu.iew.predictedTakenIncorrect            122                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect          381                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                  503                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                 10067                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                  2134                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts               704                       # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedNotTakenIncorrect          382                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts                  504                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts                 10072                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                  2136                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts               708                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                            89                       # number of nop insts executed
-system.cpu.iew.exec_refs                         3230                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                     1588                       # Number of branches executed
-system.cpu.iew.exec_stores                       1096                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.238945                       # Inst execution rate
-system.cpu.iew.wb_sent                           9751                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                          9608                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                      5048                       # num instructions producing a value
-system.cpu.iew.wb_consumers                      6764                       # num instructions consuming a value
+system.cpu.iew.exec_refs                         3231                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                     1589                       # Number of branches executed
+system.cpu.iew.exec_stores                       1095                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.238916                       # Inst execution rate
+system.cpu.iew.wb_sent                           9755                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                          9612                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                      5080                       # num instructions producing a value
+system.cpu.iew.wb_consumers                      6838                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.228051                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.746304                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.228005                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.742907                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts            6680                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts            6701                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              17                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts               430                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        13894                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.459839                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.263268                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts               431                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples        13738                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.465060                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.277866                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0        11073     79.70%     79.70% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1         1524     10.97%     90.67% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          530      3.81%     94.48% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          235      1.69%     96.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          148      1.07%     97.24% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5          110      0.79%     98.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6          103      0.74%     98.77% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           28      0.20%     98.97% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8          143      1.03%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0        10960     79.78%     79.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1         1479     10.77%     90.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          519      3.78%     94.32% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          236      1.72%     96.04% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          157      1.14%     97.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5          106      0.77%     97.95% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6          104      0.76%     98.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           34      0.25%     98.96% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8          143      1.04%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        13894                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        13738                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts                 6389                       # Number of instructions committed
 system.cpu.commit.committedOps                   6389                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -502,24 +524,24 @@ system.cpu.commit.int_insts                      6307                       # Nu
 system.cpu.commit.function_calls                  127                       # Number of function calls committed.
 system.cpu.commit.bw_lim_events                   143                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                        26469                       # The number of ROB reads
-system.cpu.rob.rob_writes                       27366                       # The number of ROB writes
-system.cpu.timesIdled                             271                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           27018                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                        26334                       # The number of ROB reads
+system.cpu.rob.rob_writes                       27415                       # The number of ROB writes
+system.cpu.timesIdled                             272                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           27193                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        6372                       # Number of Instructions Simulated
 system.cpu.committedOps                          6372                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total                  6372                       # Number of Instructions Simulated
-system.cpu.cpi                               6.611896                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         6.611896                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.151243                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.151243                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    12780                       # number of integer regfile reads
-system.cpu.int_regfile_writes                    7264                       # number of integer regfile writes
+system.cpu.cpi                               6.615976                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         6.615976                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.151149                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.151149                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                    12785                       # number of integer regfile reads
+system.cpu.int_regfile_writes                    7268                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                         8                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                        2                       # number of floating regfile writes
 system.cpu.misc_regfile_reads                       1                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput              1482648944                       # Throughput (bytes/s)
+system.cpu.toL2Bus.throughput              1481734510                       # Throughput (bytes/s)
 system.cpu.toL2Bus.trans_dist::ReadReq            416                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp           415                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           73                       # Transaction distribution
@@ -534,61 +556,61 @@ system.cpu.toL2Bus.data_through_bus             31232                       # To
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
 system.cpu.toL2Bus.reqLayer0.occupancy         244500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        529000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy        528000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          2.5                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        278500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy        276000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.3                       # Layer utilization (%)
 system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse           159.548856                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                1893                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           159.411930                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                1899                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               314                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              6.028662                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs              6.047771                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   159.548856                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.077905                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.077905                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   159.411930                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.077838                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.077838                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          314                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          143                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          171                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          144                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          170                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.153320                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses              5078                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses             5078                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst         1893                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            1893                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          1893                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             1893                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         1893                       # number of overall hits
-system.cpu.icache.overall_hits::total            1893                       # number of overall hits
+system.cpu.icache.tags.tag_accesses              5090                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses             5090                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst         1899                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            1899                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          1899                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             1899                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         1899                       # number of overall hits
+system.cpu.icache.overall_hits::total            1899                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst          489                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total           489                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst          489                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total            489                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          489                       # number of overall misses
 system.cpu.icache.overall_misses::total           489                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     31381500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     31381500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     31381500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     31381500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     31381500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     31381500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         2382                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         2382                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         2382                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         2382                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         2382                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         2382                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.205290                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.205290                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.205290                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.205290                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.205290                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.205290                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64174.846626                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 64174.846626                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 64174.846626                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 64174.846626                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 64174.846626                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 64174.846626                       # average overall miss latency
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     31431750                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     31431750                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     31431750                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     31431750                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     31431750                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     31431750                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         2388                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         2388                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         2388                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         2388                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         2388                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         2388                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.204774                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.204774                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.204774                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.204774                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.204774                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.204774                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64277.607362                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 64277.607362                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 64277.607362                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 64277.607362                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 64277.607362                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 64277.607362                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -609,39 +631,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          315
 system.cpu.icache.demand_mshr_misses::total          315                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          315                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          315                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     22109000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     22109000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     22109000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     22109000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     22109000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     22109000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.132242                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.132242                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.132242                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.132242                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.132242                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.132242                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70187.301587                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70187.301587                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70187.301587                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 70187.301587                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70187.301587                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 70187.301587                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     22098000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     22098000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     22098000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     22098000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     22098000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     22098000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.131910                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.131910                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.131910                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.131910                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.131910                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.131910                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70152.380952                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70152.380952                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70152.380952                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 70152.380952                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70152.380952                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 70152.380952                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          219.420292                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          219.244506                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  1                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              414                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.002415                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   159.632644                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    59.787647                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004872                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.001825                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.006696                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   159.494883                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    59.749622                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004867                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.001823                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.006691                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          414                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          182                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          232                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          183                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          231                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.012634                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses             4399                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses            4399                       # Number of data accesses
@@ -662,17 +684,17 @@ system.cpu.l2cache.demand_misses::total           488                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          314                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          174                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          488                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     21783000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      7718750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     29501750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      5390750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      5390750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     21783000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data     13109500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     34892500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     21783000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data     13109500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     34892500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     21772000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      7725500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     29497500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      5467500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      5467500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     21772000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data     13193000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     34965000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     21772000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data     13193000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     34965000                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst          315                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data          101                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total          416                       # number of ReadReq accesses(hits+misses)
@@ -695,17 +717,17 @@ system.cpu.l2cache.demand_miss_rate::total     0.997955                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996825                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.997955                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69372.611465                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76423.267327                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 71088.554217                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73845.890411                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73845.890411                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69372.611465                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75341.954023                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 71501.024590                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69372.611465                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75341.954023                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 71501.024590                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69337.579618                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76490.099010                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 71078.313253                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74897.260274                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74897.260274                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69337.579618                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75821.839080                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 71649.590164                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69337.579618                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75821.839080                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 71649.590164                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -725,17 +747,17 @@ system.cpu.l2cache.demand_mshr_misses::total          488
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          314                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          174                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          488                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     17830500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      6478250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     24308750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      4491250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      4491250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     17830500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     10969500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     28800000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     17830500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     10969500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     28800000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     17823000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      6485500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     24308500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      4573000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      4573000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     17823000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     11058500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     28881500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     17823000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     11058500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     28881500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.996825                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.997596                       # mshr miss rate for ReadReq accesses
@@ -747,33 +769,33 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.997955
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996825                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.997955                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56785.031847                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64141.089109                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58575.301205                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61523.972603                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61523.972603                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56785.031847                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63043.103448                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59016.393443                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56785.031847                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63043.103448                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59016.393443                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56761.146497                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64212.871287                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58574.698795                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62643.835616                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62643.835616                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56761.146497                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63554.597701                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59183.401639                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56761.146497                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63554.597701                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59183.401639                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           107.351368                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse           107.267771                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs                2230                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               174                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs             12.816092                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   107.351368                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.026209                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.026209                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data   107.267771                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.026188                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.026188                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          174                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           50                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          124                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.042480                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses              5692                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses             5692                       # Number of data accesses
+system.cpu.dcache.tags.tag_accesses              5694                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             5694                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data         1724                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total            1724                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          506                       # number of WriteReq hits
@@ -782,94 +804,94 @@ system.cpu.dcache.demand_hits::cpu.data          2230                       # nu
 system.cpu.dcache.demand_hits::total             2230                       # number of demand (read+write) hits
 system.cpu.dcache.overall_hits::cpu.data         2230                       # number of overall hits
 system.cpu.dcache.overall_hits::total            2230                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          170                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           170                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::cpu.data          171                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           171                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data          359                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_misses::total          359                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          529                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            529                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          529                       # number of overall misses
-system.cpu.dcache.overall_misses::total           529                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     11435000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     11435000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     23196228                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     23196228                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     34631228                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     34631228                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     34631228                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     34631228                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         1894                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         1894                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data          530                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            530                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          530                       # number of overall misses
+system.cpu.dcache.overall_misses::total           530                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     11467500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     11467500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     23223733                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     23223733                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     34691233                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     34691233                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     34691233                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     34691233                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         1895                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1895                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          865                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total          865                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         2759                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2759                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         2759                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2759                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.089757                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.089757                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data         2760                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2760                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2760                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2760                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.090237                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.090237                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.415029                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.415029                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.191736                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.191736                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.191736                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.191736                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67264.705882                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 67264.705882                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64613.448468                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 64613.448468                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 65465.459357                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 65465.459357                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 65465.459357                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 65465.459357                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs         1486                       # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data     0.192029                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.192029                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.192029                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.192029                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67061.403509                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 67061.403509                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64690.064067                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 64690.064067                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 65455.156604                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 65455.156604                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 65455.156604                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 65455.156604                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs         1533                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                33                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                29                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    45.030303                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    52.862069                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data           69                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total           69                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data          286                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total          286                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          355                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          355                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          355                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          355                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data          101                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          101                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data           73                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total           73                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data          287                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total          287                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          356                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          356                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          356                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          356                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          102                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          102                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data           72                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total           72                       # number of WriteReq MSHR misses
 system.cpu.dcache.demand_mshr_misses::cpu.data          174                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.demand_mshr_misses::total          174                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          174                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          174                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      7827250                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      7827250                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      5466750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      5466750                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     13294000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     13294000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     13294000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     13294000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.053326                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.053326                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.084393                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.084393                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.063066                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.063066                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.063066                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.063066                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77497.524752                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77497.524752                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74886.986301                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74886.986301                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76402.298851                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 76402.298851                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76402.298851                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 76402.298851                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      7915000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      7915000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      5462500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      5462500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     13377500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     13377500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     13377500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     13377500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.053826                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.053826                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.083237                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.083237                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.063043                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.063043                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.063043                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.063043                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77598.039216                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77598.039216                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75868.055556                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75868.055556                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76882.183908                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 76882.183908                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76882.183908                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 76882.183908                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index baea5f5ebc4c77e1da19850342814d17ea5a8ac8..88231a1ee22d03d46176ab622ffe8001b3f6471c 100644 (file)
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000012                       # Number of seconds simulated
-sim_ticks                                    11990500                       # Number of ticks simulated
-final_tick                                   11990500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    12006500                       # Number of ticks simulated
+final_tick                                   12006500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  21306                       # Simulator instruction rate (inst/s)
-host_op_rate                                    21301                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              106974940                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 229436                       # Number of bytes of host memory used
-host_seconds                                     0.11                       # Real time elapsed on the host
+host_inst_rate                                  60243                       # Simulator instruction rate (inst/s)
+host_op_rate                                    60220                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              302796832                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 264400                       # Number of bytes of host memory used
+host_seconds                                     0.04                       # Real time elapsed on the host
 sim_insts                                        2387                       # Number of instructions simulated
 sim_ops                                          2387                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total           12032                       # Nu
 system.physmem.num_reads::cpu.inst                188                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                 85                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   273                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst           1003461073                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            453692507                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1457153580                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      1003461073                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         1003461073                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          1003461073                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           453692507                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1457153580                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst           1002123850                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            453087911                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1455211760                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      1002123850                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         1002123850                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          1002123850                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           453087911                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1455211760                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           273                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                         273                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        11901000                       # Total gap between requests
+system.physmem.totGap                        11917000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -154,51 +154,76 @@ system.physmem.wrQLenPdf::28                        0                       # Wh
 system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples           42                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      339.809524                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     162.784505                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     471.889985                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64                23     54.76%     54.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128                1      2.38%     57.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192                3      7.14%     64.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256                1      2.38%     66.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320                2      4.76%     71.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448                2      4.76%     76.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512                2      4.76%     80.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640                1      2.38%     83.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768                2      4.76%     88.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960                1      2.38%     90.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088               1      2.38%     92.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280               1      2.38%     95.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664               1      2.38%     97.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112               1      2.38%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total             42                       # Bytes accessed per row activation
-system.physmem.totQLat                        1695750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                   7213250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples           24                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean             464                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     290.487911                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     387.347726                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127              6     25.00%     25.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255            4     16.67%     41.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383            3     12.50%     54.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            1      4.17%     58.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            2      8.33%     66.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            2      8.33%     75.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151            6     25.00%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total             24                       # Bytes accessed per row activation
+system.physmem.totQLat                        1638000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                   7265500                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      1365000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                     4152500                       # Total ticks spent accessing banks
-system.physmem.avgQLat                        6211.54                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    15210.62                       # Average bank access latency per DRAM burst
+system.physmem.totBankLat                     4262500                       # Total ticks spent accessing banks
+system.physmem.avgQLat                        6000.00                       # Average queueing delay per DRAM burst
+system.physmem.avgBankLat                    15613.55                       # Average bank access latency per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  26422.16                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        1457.15                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  26613.55                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        1455.21                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     1457.15                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     1455.21                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                          11.38                       # Data bus utilization in percentage
-system.physmem.busUtilRead                      11.38                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                          11.37                       # Data bus utilization in percentage
+system.physmem.busUtilRead                      11.37                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         0.60                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.70                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                        231                       # Number of row buffer hits during reads
+system.physmem.readRowHits                        225                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   84.62                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   82.42                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        43593.41                       # Average gap between requests
-system.physmem.pageHitRate                      84.62                       # Row buffer hit rate, read and write combined
+system.physmem.avgGap                        43652.01                       # Average gap between requests
+system.physmem.pageHitRate                      82.42                       # Row buffer hit rate, read and write combined
 system.physmem.prechargeAllPercent               0.18                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                   1457153580                       # Throughput (bytes/s)
+system.membus.throughput                   1455211760                       # Throughput (bytes/s)
 system.membus.trans_dist::ReadReq                 249                       # Transaction distribution
 system.membus.trans_dist::ReadResp                249                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                24                       # Transaction distribution
@@ -211,7 +236,7 @@ system.membus.data_through_bus                  17472                       # To
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
 system.membus.reqLayer0.occupancy              344000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               2.9                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            2551500                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy            2552500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization             21.3                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                    1176                       # Number of BP lookups
@@ -227,18 +252,18 @@ system.cpu.dtb.fetch_hits                           0                       # IT
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                          707                       # DTB read hits
+system.cpu.dtb.read_hits                          710                       # DTB read hits
 system.cpu.dtb.read_misses                         31                       # DTB read misses
 system.cpu.dtb.read_acv                             1                       # DTB read access violations
-system.cpu.dtb.read_accesses                      738                       # DTB read accesses
+system.cpu.dtb.read_accesses                      741                       # DTB read accesses
 system.cpu.dtb.write_hits                         368                       # DTB write hits
 system.cpu.dtb.write_misses                        20                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
 system.cpu.dtb.write_accesses                     388                       # DTB write accesses
-system.cpu.dtb.data_hits                         1075                       # DTB hits
+system.cpu.dtb.data_hits                         1078                       # DTB hits
 system.cpu.dtb.data_misses                         51                       # DTB misses
 system.cpu.dtb.data_acv                             1                       # DTB access violations
-system.cpu.dtb.data_accesses                     1126                       # DTB accesses
+system.cpu.dtb.data_accesses                     1129                       # DTB accesses
 system.cpu.itb.fetch_hits                        1065                       # ITB hits
 system.cpu.itb.fetch_misses                        30                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
@@ -256,10 +281,10 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                    4                       # Number of system calls
-system.cpu.numCycles                            23982                       # number of cpu cycles simulated
+system.cpu.numCycles                            24014                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles               4347                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.icacheStallCycles               4349                       # Number of cycles fetch is stalled on an Icache miss
 system.cpu.fetch.Insts                           7011                       # Number of instructions fetch has processed
 system.cpu.fetch.Branches                        1176                       # Number of branches that fetch encountered
 system.cpu.fetch.predictedBranches                465                       # Number of branches that fetch has predicted taken
@@ -271,11 +296,11 @@ system.cpu.fetch.PendingTrapStallCycles          1022                       # Nu
 system.cpu.fetch.IcacheWaitRetryStallCycles           11                       # Number of stall cycles due to full MSHR
 system.cpu.fetch.CacheLines                      1065                       # Number of cache lines fetched
 system.cpu.fetch.IcacheSquashes                   187                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples               7720                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.908161                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.314945                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples               7722                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.907925                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.314691                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                     6511     84.34%     84.34% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                     6513     84.34%     84.34% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::1                       53      0.69%     85.03% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::2                      115      1.49%     86.52% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::3                       95      1.23%     87.75% # Number of instructions fetched each cycle (Total)
@@ -287,10 +312,10 @@ system.cpu.fetch.rateDist::8                      565      7.32%    100.00% # Nu
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                 7720                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.049037                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.292344                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                     5485                       # Number of cycles decode is idle
+system.cpu.fetch.rateDist::total                 7722                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.048971                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.291955                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                     5487                       # Number of cycles decode is idle
 system.cpu.decode.BlockedCycles                   579                       # Number of cycles decode is blocked
 system.cpu.decode.RunCycles                      1153                       # Number of cycles decode is running
 system.cpu.decode.UnblockCycles                     9                       # Number of cycles decode is unblocking
@@ -300,52 +325,52 @@ system.cpu.decode.BranchMispred                    81                       # Nu
 system.cpu.decode.DecodedInsts                   6199                       # Number of instructions handled by decode
 system.cpu.decode.SquashedInsts                   292                       # Number of squashed instructions handled by decode
 system.cpu.rename.SquashCycles                    494                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                     5584                       # Number of cycles rename is idle
+system.cpu.rename.IdleCycles                     5585                       # Number of cycles rename is idle
 system.cpu.rename.BlockCycles                     254                       # Number of cycles rename is blocking
 system.cpu.rename.serializeStallCycles            290                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      1062                       # Number of cycles rename is running
+system.cpu.rename.RunCycles                      1063                       # Number of cycles rename is running
 system.cpu.rename.UnblockCycles                    36                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                   5897                       # Number of instructions processed by rename
+system.cpu.rename.RenamedInsts                   5900                       # Number of instructions processed by rename
 system.cpu.rename.ROBFullEvents                     1                       # Number of times rename has blocked due to ROB full
 system.cpu.rename.IQFullEvents                     14                       # Number of times rename has blocked due to IQ full
 system.cpu.rename.LSQFullEvents                    13                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands                4276                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                  6670                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups             6663                       # Number of integer rename lookups
+system.cpu.rename.RenamedOperands                4279                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                  6674                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups             6667                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups                 6                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps                  1768                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                     2508                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps                     2511                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts                  8                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts              6                       # count of temporary serializing insts renamed
 system.cpu.rename.skidInsts                       139                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                  955                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                 468                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.insertedLoads                  956                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                 469                       # Number of stores inserted to the mem dependence unit.
 system.cpu.memDep0.conflictingLoads                 3                       # Number of conflicting loads.
 system.cpu.memDep0.conflictingStores                3                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                       4960                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsAdded                       4966                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqNonSpecInstsAdded                   6                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                      4040                       # Number of instructions issued
+system.cpu.iq.iqInstsIssued                      4045                       # Number of instructions issued
 system.cpu.iq.iqSquashedInstsIssued                54                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined            2335                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined         1384                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedInstsExamined            2341                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined         1389                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved              2                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples          7720                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.523316                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.238697                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples          7722                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.523828                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.238657                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0                6098     78.99%     78.99% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                 566      7.33%     86.32% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                 399      5.17%     91.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 262      3.39%     94.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 199      2.58%     97.46% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 121      1.57%     99.03% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0                6098     78.97%     78.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                 565      7.32%     86.29% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                 401      5.19%     91.48% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 263      3.41%     94.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 200      2.59%     97.47% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 120      1.55%     99.03% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                  47      0.61%     99.64% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                  17      0.22%     99.86% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                  11      0.14%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total            7720                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total            7722                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntAlu                       3      6.82%      6.82% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                      0      0.00%      6.82% # attempts to use FU when none available
@@ -381,57 +406,57 @@ system.cpu.iq.fu_full::MemWrite                    22     50.00%    100.00% # at
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                  2861     70.82%     70.82% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    1      0.02%     70.84% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     70.84% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     70.84% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     70.84% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     70.84% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     70.84% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     70.84% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     70.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     70.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     70.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     70.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     70.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     70.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     70.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     70.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     70.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     70.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     70.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     70.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     70.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     70.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     70.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     70.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     70.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     70.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     70.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     70.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     70.84% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                  783     19.38%     90.22% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                 395      9.78%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                  2864     70.80%     70.80% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    1      0.02%     70.83% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     70.83% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     70.83% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     70.83% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     70.83% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     70.83% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     70.83% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     70.83% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     70.83% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     70.83% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     70.83% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     70.83% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     70.83% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     70.83% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     70.83% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     70.83% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     70.83% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     70.83% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     70.83% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     70.83% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     70.83% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     70.83% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     70.83% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     70.83% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     70.83% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     70.83% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     70.83% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     70.83% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                  785     19.41%     90.23% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                 395      9.77%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                   4040                       # Type of FU issued
-system.cpu.iq.rate                           0.168460                       # Inst issue rate
+system.cpu.iq.FU_type_0::total                   4045                       # Type of FU issued
+system.cpu.iq.rate                           0.168443                       # Inst issue rate
 system.cpu.iq.fu_busy_cnt                          44                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.010891                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              15885                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes              7299                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses         3649                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fu_busy_rate                   0.010878                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              15897                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes              7311                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses         3652                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                  13                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                  6                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses            6                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                   4077                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                   4082                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                       7                       # Number of floating point alu accesses
 system.cpu.iew.lsq.thread0.forwLoads               33                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads          540                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads          541                       # Number of loads squashed
 system.cpu.iew.lsq.thread0.ignoredResponses            1                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread0.memOrderViolation            4                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores          174                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores          175                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
@@ -440,42 +465,42 @@ system.cpu.iew.iewIdleCycles                        0                       # Nu
 system.cpu.iew.iewSquashCycles                    494                       # Number of cycles IEW is squashing
 system.cpu.iew.iewBlockCycles                     228                       # Number of cycles IEW is blocking
 system.cpu.iew.iewUnblockCycles                     4                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts                5302                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispatchedInsts                5308                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts               162                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                   955                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                  468                       # Number of dispatched store instructions
+system.cpu.iew.iewDispLoadInsts                   956                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                  469                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts                  6                       # Number of dispatched non-speculative instructions
 system.cpu.iew.iewIQFullEvents                      2                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewLSQFullEvents                     0                       # Number of times the LSQ has become full, causing a stall
 system.cpu.iew.memOrderViolationEvents              4                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect             52                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedTakenIncorrect             53                       # Number of branches that were predicted taken incorrectly
 system.cpu.iew.predictedNotTakenIncorrect          162                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                  214                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                  3849                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                   739                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts               191                       # Number of squashed instructions skipped in execute
+system.cpu.iew.branchMispredicts                  215                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts                  3855                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                   742                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts               190                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                           336                       # number of nop insts executed
-system.cpu.iew.exec_refs                         1127                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                      643                       # Number of branches executed
+system.cpu.iew.exec_refs                         1130                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                      644                       # Number of branches executed
 system.cpu.iew.exec_stores                        388                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.160495                       # Inst execution rate
-system.cpu.iew.wb_sent                           3735                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                          3655                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                      1708                       # num instructions producing a value
-system.cpu.iew.wb_consumers                      2206                       # num instructions consuming a value
+system.cpu.iew.exec_rate                     0.160531                       # Inst execution rate
+system.cpu.iew.wb_sent                           3738                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                          3658                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                      1710                       # num instructions producing a value
+system.cpu.iew.wb_consumers                      2211                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.152406                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.774252                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.152328                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.773406                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts            2720                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts            2726                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls               4                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts               180                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples         7226                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.356490                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.198597                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples         7228                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.356392                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.198445                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0         6357     87.97%     87.97% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0         6359     87.98%     87.98% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::1          204      2.82%     90.80% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::2          308      4.26%     95.06% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::3          114      1.58%     96.64% # Number of insts commited each cycle
@@ -487,7 +512,7 @@ system.cpu.commit.committed_per_cycle::8           63      0.87%    100.00% # Nu
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total         7226                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total         7228                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts                 2576                       # Number of instructions committed
 system.cpu.commit.committedOps                   2576                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -500,23 +525,23 @@ system.cpu.commit.int_insts                      2367                       # Nu
 system.cpu.commit.function_calls                   71                       # Number of function calls committed.
 system.cpu.commit.bw_lim_events                    63                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                        12212                       # The number of ROB reads
-system.cpu.rob.rob_writes                       11099                       # The number of ROB writes
+system.cpu.rob.rob_reads                        12220                       # The number of ROB reads
+system.cpu.rob.rob_writes                       11111                       # The number of ROB writes
 system.cpu.timesIdled                             158                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           16262                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles                           16292                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        2387                       # Number of Instructions Simulated
 system.cpu.committedOps                          2387                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total                  2387                       # Number of Instructions Simulated
-system.cpu.cpi                              10.046921                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                        10.046921                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.099533                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.099533                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                     4665                       # number of integer regfile reads
-system.cpu.int_regfile_writes                    2823                       # number of integer regfile writes
+system.cpu.cpi                              10.060327                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                        10.060327                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.099400                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.099400                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                     4672                       # number of integer regfile reads
+system.cpu.int_regfile_writes                    2825                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                         6                       # number of floating regfile reads
 system.cpu.misc_regfile_reads                       1                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput              1457153580                       # Throughput (bytes/s)
+system.cpu.toL2Bus.throughput              1455211760                       # Throughput (bytes/s)
 system.cpu.toL2Bus.trans_dist::ReadReq            249                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp           249                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           24                       # Transaction distribution
@@ -531,19 +556,19 @@ system.cpu.toL2Bus.data_through_bus             17472                       # To
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
 system.cpu.toL2Bus.reqLayer0.occupancy         136500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        316000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy        315500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          2.6                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy        133000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.1                       # Layer utilization (%)
 system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse            93.236237                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse            93.163170                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                 815                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               188                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs              4.335106                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst    93.236237                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.045526                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.045526                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst    93.163170                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.045490                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.045490                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          188                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0          161                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1           27                       # Occupied blocks per task id
@@ -562,12 +587,12 @@ system.cpu.icache.demand_misses::cpu.inst          250                       # n
 system.cpu.icache.demand_misses::total            250                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          250                       # number of overall misses
 system.cpu.icache.overall_misses::total           250                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     17655999                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     17655999                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     17655999                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     17655999                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     17655999                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     17655999                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     17591499                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     17591499                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     17591499                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     17591499                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     17591499                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     17591499                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst         1065                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total         1065                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst         1065                       # number of demand (read+write) accesses
@@ -580,12 +605,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.234742
 system.cpu.icache.demand_miss_rate::total     0.234742                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.234742                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.234742                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70623.996000                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 70623.996000                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 70623.996000                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 70623.996000                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 70623.996000                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 70623.996000                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70365.996000                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 70365.996000                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 70365.996000                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 70365.996000                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 70365.996000                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 70365.996000                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs          112                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 2                       # number of cycles access was blocked
@@ -606,36 +631,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          188
 system.cpu.icache.demand_mshr_misses::total          188                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          188                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          188                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     13162749                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     13162749                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     13162749                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     13162749                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     13162749                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     13162749                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     13162249                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     13162249                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     13162249                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     13162249                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     13162249                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     13162249                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.176526                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.176526                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.176526                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.176526                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.176526                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.176526                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70014.622340                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70014.622340                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70014.622340                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 70014.622340                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70014.622340                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 70014.622340                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70011.962766                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70011.962766                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70011.962766                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 70011.962766                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70011.962766                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 70011.962766                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          122.122128                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          122.028433                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  0                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              249                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs                    0                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    93.433851                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    28.688277                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.002851                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    93.360563                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    28.667870                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.002849                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.000875                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.003727                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.003724                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          249                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          211                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1           38                       # Occupied blocks per task id
@@ -653,17 +678,17 @@ system.cpu.l2cache.demand_misses::total           273                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          188                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data           85                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          273                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     12974000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      4692750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     17666750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      1665750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      1665750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     12974000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data      6358500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     19332500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     12974000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data      6358500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     19332500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     12973500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      4680750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     17654250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      1693750                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      1693750                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     12973500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      6374500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     19348000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     12973500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      6374500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     19348000                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst          188                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data           61                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total          249                       # number of ReadReq accesses(hits+misses)
@@ -686,17 +711,17 @@ system.cpu.l2cache.demand_miss_rate::total            1                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total            1                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69010.638298                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76930.327869                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 70950.803213                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69406.250000                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69406.250000                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69010.638298                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74805.882353                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 70815.018315                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69010.638298                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74805.882353                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 70815.018315                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69007.978723                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76733.606557                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 70900.602410                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70572.916667                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70572.916667                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69007.978723                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74994.117647                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 70871.794872                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69007.978723                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74994.117647                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 70871.794872                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -716,17 +741,17 @@ system.cpu.l2cache.demand_mshr_misses::total          273
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          188                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data           85                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          273                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     10604500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      3946250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     14550750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      1371750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      1371750                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     10604500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      5318000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     15922500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     10604500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5318000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     15922500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     10603500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      3934250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     14537750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      1399750                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      1399750                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     10603500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      5334000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     15937500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     10603500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5334000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     15937500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -738,81 +763,81 @@ system.cpu.l2cache.demand_mshr_miss_rate::total            1
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56406.914894                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64692.622951                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58436.746988                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57156.250000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57156.250000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56406.914894                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62564.705882                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58324.175824                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56406.914894                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62564.705882                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58324.175824                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56401.595745                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64495.901639                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58384.538153                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58322.916667                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58322.916667                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56401.595745                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62752.941176                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58379.120879                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56401.595745                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62752.941176                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58379.120879                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            45.667407                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                 758                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse            45.630537                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                 759                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs                85                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs              8.917647                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs              8.929412                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    45.667407                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.011149                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.011149                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data    45.630537                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.011140                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.011140                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024           85                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           66                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           19                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.020752                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses              1989                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses             1989                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data          545                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total             545                       # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses              1995                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses             1995                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data          546                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total             546                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          213                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total            213                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data           758                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total              758                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data          758                       # number of overall hits
-system.cpu.dcache.overall_hits::total             758                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          113                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           113                       # number of ReadReq misses
+system.cpu.dcache.demand_hits::cpu.data           759                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total              759                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data          759                       # number of overall hits
+system.cpu.dcache.overall_hits::total             759                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          115                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           115                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data           81                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_misses::total           81                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          194                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            194                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          194                       # number of overall misses
-system.cpu.dcache.overall_misses::total           194                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      7226000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      7226000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data      5211250                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      5211250                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     12437250                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     12437250                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     12437250                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     12437250                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data          658                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total          658                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data          196                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            196                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          196                       # number of overall misses
+system.cpu.dcache.overall_misses::total           196                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      7964000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      7964000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data      5323250                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      5323250                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     13287250                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     13287250                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     13287250                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     13287250                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data          661                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total          661                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          294                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total          294                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data          952                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total          952                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data          952                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total          952                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.171733                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.171733                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data          955                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total          955                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data          955                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total          955                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.173979                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.173979                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.275510                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.275510                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.203782                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.203782                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.203782                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.203782                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63946.902655                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 63946.902655                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64336.419753                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 64336.419753                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 64109.536082                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 64109.536082                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 64109.536082                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 64109.536082                       # average overall miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.205236                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.205236                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.205236                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.205236                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69252.173913                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 69252.173913                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65719.135802                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 65719.135802                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 67792.091837                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 67792.091837                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 67792.091837                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 67792.091837                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs          145                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 4                       # number of cycles access was blocked
@@ -821,14 +846,14 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs    36.250000
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data           52                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           52                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           54                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           54                       # number of ReadReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::cpu.data           57                       # number of WriteReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::total           57                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          109                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          109                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          109                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          109                       # number of overall MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          111                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          111                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          111                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          111                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data           61                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total           61                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data           24                       # number of WriteReq MSHR misses
@@ -837,30 +862,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data           85
 system.cpu.dcache.demand_mshr_misses::total           85                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data           85                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total           85                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4753750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      4753750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      1691250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      1691250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      6445000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      6445000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      6445000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      6445000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.092705                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.092705                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4741750                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      4741750                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      1719250                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      1719250                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      6461000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      6461000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      6461000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      6461000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.092284                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.092284                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.081633                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.081633                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.089286                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.089286                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.089286                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.089286                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77930.327869                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77930.327869                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70468.750000                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70468.750000                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75823.529412                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 75823.529412                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75823.529412                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 75823.529412                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.089005                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.089005                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.089005                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.089005                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77733.606557                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77733.606557                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71635.416667                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71635.416667                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76011.764706                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 76011.764706                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76011.764706                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 76011.764706                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 783b95f7898f403ea50cbfaa0087c82d0bc78f2b..18325fbc5ef56faee52b572090d07a4a5ea3c799 100644 (file)
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000017                       # Number of seconds simulated
-sim_ticks                                    16981000                       # Number of ticks simulated
-final_tick                                   16981000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    17056000                       # Number of ticks simulated
+final_tick                                   17056000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  39940                       # Simulator instruction rate (inst/s)
-host_op_rate                                    49834                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              147693403                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 267784                       # Number of bytes of host memory used
-host_seconds                                     0.12                       # Real time elapsed on the host
+host_inst_rate                                  29277                       # Simulator instruction rate (inst/s)
+host_op_rate                                    36530                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              108745688                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 308972                       # Number of bytes of host memory used
+host_seconds                                     0.16                       # Real time elapsed on the host
 sim_insts                                        4591                       # Number of instructions simulated
 sim_ops                                          5729                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total           17280                       # Nu
 system.physmem.num_reads::cpu.inst                270                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                122                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   392                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst           1017607915                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            459808021                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1477415935                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      1017607915                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         1017607915                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          1017607915                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           459808021                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1477415935                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst           1013133208                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            457786116                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1470919325                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      1013133208                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         1013133208                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          1013133208                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           457786116                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1470919325                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           392                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                         392                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        16923500                       # Total gap between requests
+system.physmem.totGap                        16998500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -91,8 +91,8 @@ system.physmem.writePktSize::4                      0                       # Wr
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
 system.physmem.rdQLenPdf::0                       207                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       122                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        44                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       120                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        46                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                        14                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
@@ -154,55 +154,76 @@ system.physmem.wrQLenPdf::28                        0                       # Wh
 system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples           60                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      374.400000                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     181.494324                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     535.569369                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64                25     41.67%     41.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128                8     13.33%     55.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192                5      8.33%     63.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256                3      5.00%     68.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320                3      5.00%     73.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384                1      1.67%     75.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448                2      3.33%     78.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512                1      1.67%     80.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640                2      3.33%     83.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768                2      3.33%     86.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896                1      1.67%     88.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024               1      1.67%     90.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152               1      1.67%     91.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536               1      1.67%     93.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664               1      1.67%     95.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856               1      1.67%     96.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984               1      1.67%     98.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2432               1      1.67%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total             60                       # Bytes accessed per row activation
-system.physmem.totQLat                        3153000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  10516750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples           32                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean             450                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     276.111928                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     399.674706                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127              7     21.88%     21.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255            8     25.00%     46.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383            4     12.50%     59.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            1      3.12%     62.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            2      6.25%     68.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            1      3.12%     71.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151            9     28.12%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total             32                       # Bytes accessed per row activation
+system.physmem.totQLat                        4223500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  11614750                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      1960000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                     5403750                       # Total ticks spent accessing banks
-system.physmem.avgQLat                        8043.37                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    13785.08                       # Average bank access latency per DRAM burst
+system.physmem.totBankLat                     5431250                       # Total ticks spent accessing banks
+system.physmem.avgQLat                       10774.23                       # Average queueing delay per DRAM burst
+system.physmem.avgBankLat                    13855.23                       # Average bank access latency per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  26828.44                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        1477.42                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  29629.46                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        1470.92                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     1477.42                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     1470.92                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                          11.54                       # Data bus utilization in percentage
-system.physmem.busUtilRead                      11.54                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                          11.49                       # Data bus utilization in percentage
+system.physmem.busUtilRead                      11.49                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         0.62                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.91                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                        332                       # Number of row buffer hits during reads
+system.physmem.readRowHits                        326                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   84.69                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   83.16                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        43172.19                       # Average gap between requests
-system.physmem.pageHitRate                      84.69                       # Row buffer hit rate, read and write combined
+system.physmem.avgGap                        43363.52                       # Average gap between requests
+system.physmem.pageHitRate                      83.16                       # Row buffer hit rate, read and write combined
 system.physmem.prechargeAllPercent               0.06                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                   1473647017                       # Throughput (bytes/s)
+system.membus.throughput                   1467166979                       # Throughput (bytes/s)
 system.membus.trans_dist::ReadReq                 351                       # Transaction distribution
 system.membus.trans_dist::ReadResp                350                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                41                       # Transaction distribution
@@ -213,10 +234,10 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
 system.membus.tot_pkt_size::total               25024                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.data_through_bus                  25024                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy              483500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy              484000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               2.8                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            3646500                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             21.5                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            3645250                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             21.4                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                    2481                       # Number of BP lookups
 system.cpu.branchPred.condPredicted              1780                       # Number of conditional branches predicted
@@ -399,10 +420,10 @@ system.cpu.itb.inst_accesses                        0                       # IT
 system.cpu.itb.hits                                 0                       # DTB hits
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
-system.cpu.numCycles                            33963                       # number of cpu cycles simulated
+system.cpu.numCycles                            34113                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles               6931                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.icacheStallCycles               6922                       # Number of cycles fetch is stalled on an Icache miss
 system.cpu.fetch.Insts                          11923                       # Number of instructions fetch has processed
 system.cpu.fetch.Branches                        2481                       # Number of branches that fetch encountered
 system.cpu.fetch.predictedBranches                990                       # Number of branches that fetch has predicted taken
@@ -411,26 +432,26 @@ system.cpu.fetch.SquashCycles                    1612                       # Nu
 system.cpu.fetch.BlockedCycles                   2574                       # Number of cycles fetch has spent blocked
 system.cpu.fetch.CacheLines                      1947                       # Number of cache lines fetched
 system.cpu.fetch.IcacheSquashes                   283                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              13238                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.137785                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.552533                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples              13229                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.138559                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.553229                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                    10611     80.16%     80.16% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                      226      1.71%     81.86% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      203      1.53%     83.40% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      226      1.71%     85.10% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      222      1.68%     86.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      269      2.03%     88.81% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                       92      0.69%     89.51% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                    10602     80.14%     80.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                      226      1.71%     81.85% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      203      1.53%     83.38% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      226      1.71%     85.09% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      222      1.68%     86.77% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      269      2.03%     88.80% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                       92      0.70%     89.50% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::7                      145      1.10%     90.60% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::8                     1244      9.40%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                13238                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.073050                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.351059                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                     6943                       # Number of cycles decode is idle
+system.cpu.fetch.rateDist::total                13229                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.072729                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.349515                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                     6934                       # Number of cycles decode is idle
 system.cpu.decode.BlockedCycles                  2849                       # Number of cycles decode is blocked
 system.cpu.decode.RunCycles                      2426                       # Number of cycles decode is running
 system.cpu.decode.UnblockCycles                    69                       # Number of cycles decode is unblocking
@@ -440,7 +461,7 @@ system.cpu.decode.BranchMispred                   159                       # Nu
 system.cpu.decode.DecodedInsts                  13218                       # Number of instructions handled by decode
 system.cpu.decode.SquashedInsts                   538                       # Number of squashed instructions handled by decode
 system.cpu.rename.SquashCycles                    951                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                     7209                       # Number of cycles rename is idle
+system.cpu.rename.IdleCycles                     7200                       # Number of cycles rename is idle
 system.cpu.rename.BlockCycles                     361                       # Number of cycles rename is blocking
 system.cpu.rename.serializeStallCycles           2278                       # count of cycles rename stalled for serializing inst
 system.cpu.rename.RunCycles                      2227                       # Number of cycles rename is running
@@ -457,7 +478,7 @@ system.cpu.rename.CommittedMaps                  5673                       # Nu
 system.cpu.rename.UndoneMaps                     6817                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts                 41                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts             38                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                       665                       # count of insts added to the skid buffer
+system.cpu.rename.skidInsts                       666                       # count of insts added to the skid buffer
 system.cpu.memDep0.insertedLoads                 2790                       # Number of loads inserted to the mem dependence unit.
 system.cpu.memDep0.insertedStores                1564                       # Number of stores inserted to the mem dependence unit.
 system.cpu.memDep0.conflictingLoads                37                       # Number of conflicting loads.
@@ -469,23 +490,23 @@ system.cpu.iq.iqSquashedInstsIssued               113                       # Nu
 system.cpu.iq.iqSquashedInstsExamined            5124                       # Number of squashed instructions iterated over during squash; mainly for profiling
 system.cpu.iq.iqSquashedOperandsExamined        14241                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved             12                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         13238                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.673893                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.378375                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples         13229                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.674352                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.378841                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0                9658     72.96%     72.96% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                1314      9.93%     82.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                 816      6.16%     89.05% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 544      4.11%     93.16% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 456      3.44%     96.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 260      1.96%     98.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0                9649     72.94%     72.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                1315      9.94%     82.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                 815      6.16%     89.04% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 543      4.10%     93.14% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 457      3.45%     96.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 260      1.97%     98.56% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                 123      0.93%     99.49% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                  55      0.42%     99.91% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                  12      0.09%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           13238                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           13229                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntAlu                       8      3.57%      3.57% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                      0      0.00%      3.57% # attempts to use FU when none available
@@ -555,10 +576,10 @@ system.cpu.iq.FU_type_0::MemWrite                1210     13.56%    100.00% # Ty
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::total                   8921                       # Type of FU issued
-system.cpu.iq.rate                           0.262668                       # Inst issue rate
+system.cpu.iq.rate                           0.261513                       # Inst issue rate
 system.cpu.iq.fu_busy_cnt                         224                       # FU busy when requested
 system.cpu.iq.fu_busy_rate                   0.025109                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              31381                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_reads              31372                       # Number of integer instruction queue reads
 system.cpu.iq.int_inst_queue_writes             16313                       # Number of integer instruction queue writes
 system.cpu.iq.int_inst_queue_wakeup_accesses         8052                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                  36                       # Number of floating instruction queue reads
@@ -599,35 +620,35 @@ system.cpu.iew.exec_nop                             0                       # nu
 system.cpu.iew.exec_refs                         3299                       # number of memory reference insts executed
 system.cpu.iew.exec_branches                     1437                       # Number of branches executed
 system.cpu.iew.exec_stores                       1160                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.250950                       # Inst execution rate
+system.cpu.iew.exec_rate                     0.249846                       # Inst execution rate
 system.cpu.iew.wb_sent                           8226                       # cumulative count of insts sent to commit
 system.cpu.iew.wb_count                          8068                       # cumulative count of insts written-back
 system.cpu.iew.wb_producers                      3883                       # num instructions producing a value
 system.cpu.iew.wb_consumers                      7788                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.237553                       # insts written-back per cycle
+system.cpu.iew.wb_rate                       0.236508                       # insts written-back per cycle
 system.cpu.iew.wb_fanout                     0.498588                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitSquashedInsts            5496                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              37                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts               327                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        12287                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.466265                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.297883                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples        12278                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.466607                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.298423                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0        10001     81.39%     81.39% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1         1069      8.70%     90.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          402      3.27%     93.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          263      2.14%     95.51% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          175      1.42%     96.93% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0         9992     81.38%     81.38% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1         1070      8.71%     90.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          401      3.27%     93.36% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          262      2.13%     95.50% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          176      1.43%     96.93% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::5          172      1.40%     98.33% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::6           49      0.40%     98.73% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           35      0.28%     99.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8          121      0.98%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           35      0.29%     99.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8          121      0.99%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        12287                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        12278                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts                 4591                       # Number of instructions committed
 system.cpu.commit.committedOps                   5729                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -640,23 +661,23 @@ system.cpu.commit.int_insts                      4976                       # Nu
 system.cpu.commit.function_calls                   82                       # Number of function calls committed.
 system.cpu.commit.bw_lim_events                   121                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                        23234                       # The number of ROB reads
+system.cpu.rob.rob_reads                        23225                       # The number of ROB reads
 system.cpu.rob.rob_writes                       23415                       # The number of ROB writes
-system.cpu.timesIdled                             221                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           20725                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.timesIdled                             220                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           20884                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        4591                       # Number of Instructions Simulated
 system.cpu.committedOps                          5729                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total                  4591                       # Number of Instructions Simulated
-system.cpu.cpi                               7.397735                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         7.397735                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.135177                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.135177                       # IPC: Total IPC of All Threads
+system.cpu.cpi                               7.430407                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         7.430407                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.134582                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.134582                       # IPC: Total IPC of All Threads
 system.cpu.int_regfile_reads                    39210                       # number of integer regfile reads
 system.cpu.int_regfile_writes                    7985                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
 system.cpu.misc_regfile_reads                    3239                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                     24                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput              1643248336                       # Throughput (bytes/s)
+system.cpu.toL2Bus.throughput              1636022514                       # Throughput (bytes/s)
 system.cpu.toL2Bus.trans_dist::ReadReq            396                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp           395                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           41                       # Transaction distribution
@@ -671,19 +692,19 @@ system.cpu.toL2Bus.data_through_bus             27904                       # To
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
 system.cpu.toL2Bus.reqLayer0.occupancy         218500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.3                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        479750                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy        478500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          2.8                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        229245                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          1.4                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy        228745                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          1.3                       # Layer utilization (%)
 system.cpu.icache.tags.replacements                 4                       # number of replacements
-system.cpu.icache.tags.tagsinuse           148.072869                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse           147.751269                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                1584                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               290                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs              5.462069                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   148.072869                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.072301                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.072301                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   147.751269                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.072144                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.072144                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          286                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0          168                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          118                       # Occupied blocks per task id
@@ -702,12 +723,12 @@ system.cpu.icache.demand_misses::cpu.inst          363                       # n
 system.cpu.icache.demand_misses::total            363                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          363                       # number of overall misses
 system.cpu.icache.overall_misses::total           363                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     23913500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     23913500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     23913500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     23913500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     23913500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     23913500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     24948500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     24948500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     24948500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     24948500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     24948500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     24948500                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst         1947                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total         1947                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst         1947                       # number of demand (read+write) accesses
@@ -720,12 +741,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.186441
 system.cpu.icache.demand_miss_rate::total     0.186441                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.186441                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.186441                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65877.410468                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 65877.410468                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 65877.410468                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 65877.410468                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 65877.410468                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 65877.410468                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68728.650138                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 68728.650138                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 68728.650138                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 68728.650138                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 68728.650138                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 68728.650138                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs          110                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 2                       # number of cycles access was blocked
@@ -746,39 +767,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          290
 system.cpu.icache.demand_mshr_misses::total          290                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          290                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          290                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     19169750                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     19169750                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     19169750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     19169750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     19169750                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     19169750                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     20177000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     20177000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     20177000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     20177000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     20177000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     20177000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.148947                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.148947                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.148947                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.148947                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.148947                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.148947                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66102.586207                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66102.586207                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66102.586207                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 66102.586207                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66102.586207                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 66102.586207                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69575.862069                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69575.862069                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69575.862069                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 69575.862069                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69575.862069                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 69575.862069                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          186.546841                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          186.152493                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                 40                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              350                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.114286                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   139.414103                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    47.132739                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004255                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.001438                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.005693                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   139.100090                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    47.052403                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004245                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.001436                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.005681                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          350                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          193                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          157                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          192                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          158                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.010681                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses             3887                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses            3887                       # Number of data accesses
@@ -802,17 +823,17 @@ system.cpu.l2cache.demand_misses::total           397                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          270                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          127                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          397                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     18673250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      6669500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     25342750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      2970250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      2970250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     18673250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data      9639750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     28313000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     18673250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data      9639750                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     28313000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     19680500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      6712250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     26392750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      3002000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      3002000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     19680500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      9714250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     29394750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     19680500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      9714250                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     29394750                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst          290                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data          106                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total          396                       # number of ReadReq accesses(hits+misses)
@@ -835,17 +856,17 @@ system.cpu.l2cache.demand_miss_rate::total     0.908467                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.931034                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.863946                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.908467                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69160.185185                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77552.325581                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 71187.500000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72445.121951                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72445.121951                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69160.185185                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75903.543307                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 71317.380353                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69160.185185                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75903.543307                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 71317.380353                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72890.740741                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78049.418605                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 74136.938202                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73219.512195                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73219.512195                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72890.740741                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76490.157480                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 74042.191436                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72890.740741                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76490.157480                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 74042.191436                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -871,17 +892,17 @@ system.cpu.l2cache.demand_mshr_misses::total          392
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          270                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          122                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          392                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     15282750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      5380500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     20663250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      2466250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2466250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     15282750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      7846750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     23129500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     15282750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      7846750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     23129500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     16292000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      5423750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     21715750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      2498500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2498500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     16292000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      7922250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     24214250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     16292000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      7922250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     24214250                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.931034                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.764151                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.886364                       # mshr miss rate for ReadReq accesses
@@ -893,27 +914,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.897025
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.931034                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.829932                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.897025                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56602.777778                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66425.925926                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58869.658120                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60152.439024                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60152.439024                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56602.777778                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64317.622951                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59003.826531                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56602.777778                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64317.622951                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59003.826531                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60340.740741                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66959.876543                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61868.233618                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60939.024390                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60939.024390                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60340.740741                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64936.475410                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61771.045918                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60340.740741                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64936.475410                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61771.045918                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            87.464066                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse            87.338696                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs                2394                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               146                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs             16.397260                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    87.464066                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.021354                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.021354                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data    87.338696                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.021323                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.021323                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          146                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           57                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           89                       # Occupied blocks per task id
@@ -942,16 +963,16 @@ system.cpu.dcache.demand_misses::cpu.data          496                       # n
 system.cpu.dcache.demand_misses::total            496                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data          496                       # number of overall misses
 system.cpu.dcache.overall_misses::total           496                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     11356993                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     11356993                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     19957500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     19957500                       # number of WriteReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     11160743                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     11160743                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     20397000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     20397000                       # number of WriteReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       130000                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::total       130000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     31314493                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     31314493                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     31314493                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     31314493                       # number of overall miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     31557743                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     31557743                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     31557743                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     31557743                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data         1956                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total         1956                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          913                       # number of WriteReq accesses(hits+misses)
@@ -974,16 +995,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.172883
 system.cpu.dcache.demand_miss_rate::total     0.172883                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.172883                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.172883                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60089.910053                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 60089.910053                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65008.143322                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 65008.143322                       # average WriteReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59051.550265                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 59051.550265                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66439.739414                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 66439.739414                       # average WriteReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        65000                       # average LoadLockedReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        65000                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 63134.058468                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 63134.058468                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 63134.058468                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 63134.058468                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 63624.481855                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 63624.481855                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 63624.481855                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 63624.481855                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs           98                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 3                       # number of cycles access was blocked
@@ -1010,14 +1031,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          147
 system.cpu.dcache.demand_mshr_misses::total          147                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          147                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          147                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      6979505                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      6979505                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      3012250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      3012250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      9991755                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      9991755                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      9991755                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      9991755                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      7022255                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      7022255                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      3044000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      3044000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     10066255                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     10066255                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     10066255                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     10066255                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.054192                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.054192                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.044907                       # mshr miss rate for WriteReq accesses
@@ -1026,14 +1047,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.051237
 system.cpu.dcache.demand_mshr_miss_rate::total     0.051237                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.051237                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.051237                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65844.386792                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65844.386792                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73469.512195                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73469.512195                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67971.122449                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 67971.122449                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67971.122449                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 67971.122449                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66247.688679                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66247.688679                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74243.902439                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74243.902439                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68477.925170                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 68477.925170                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68477.925170                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 68477.925170                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 20f1d1a3b22a8e01ba611a880174f37464a169ba..b2921c80fe1dbc93757aba838a51576265b1cf98 100644 (file)
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000017                       # Number of seconds simulated
-sim_ticks                                    16981000                       # Number of ticks simulated
-final_tick                                   16981000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    17056000                       # Number of ticks simulated
+final_tick                                   17056000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  45620                       # Simulator instruction rate (inst/s)
-host_op_rate                                    56920                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              168691831                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 267756                       # Number of bytes of host memory used
-host_seconds                                     0.10                       # Real time elapsed on the host
+host_inst_rate                                  53685                       # Simulator instruction rate (inst/s)
+host_op_rate                                    66982                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              199380443                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 308976                       # Number of bytes of host memory used
+host_seconds                                     0.09                       # Real time elapsed on the host
 sim_insts                                        4591                       # Number of instructions simulated
 sim_ops                                          5729                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total           17280                       # Nu
 system.physmem.num_reads::cpu.inst                270                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                122                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   392                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst           1017607915                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            459808021                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1477415935                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      1017607915                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         1017607915                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          1017607915                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           459808021                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1477415935                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst           1013133208                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            457786116                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1470919325                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      1013133208                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         1013133208                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          1013133208                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           457786116                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1470919325                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           392                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                         392                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        16923500                       # Total gap between requests
+system.physmem.totGap                        16998500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -91,8 +91,8 @@ system.physmem.writePktSize::4                      0                       # Wr
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
 system.physmem.rdQLenPdf::0                       207                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       122                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        44                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       120                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        46                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                        14                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
@@ -154,55 +154,76 @@ system.physmem.wrQLenPdf::28                        0                       # Wh
 system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples           60                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      374.400000                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     181.494324                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     535.569369                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64                25     41.67%     41.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128                8     13.33%     55.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192                5      8.33%     63.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256                3      5.00%     68.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320                3      5.00%     73.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384                1      1.67%     75.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448                2      3.33%     78.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512                1      1.67%     80.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640                2      3.33%     83.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768                2      3.33%     86.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896                1      1.67%     88.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024               1      1.67%     90.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152               1      1.67%     91.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536               1      1.67%     93.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664               1      1.67%     95.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856               1      1.67%     96.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984               1      1.67%     98.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2432               1      1.67%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total             60                       # Bytes accessed per row activation
-system.physmem.totQLat                        3153000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  10516750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples           32                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean             450                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     276.111928                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     399.674706                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127              7     21.88%     21.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255            8     25.00%     46.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383            4     12.50%     59.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            1      3.12%     62.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            2      6.25%     68.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            1      3.12%     71.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151            9     28.12%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total             32                       # Bytes accessed per row activation
+system.physmem.totQLat                        4223500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  11614750                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      1960000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                     5403750                       # Total ticks spent accessing banks
-system.physmem.avgQLat                        8043.37                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    13785.08                       # Average bank access latency per DRAM burst
+system.physmem.totBankLat                     5431250                       # Total ticks spent accessing banks
+system.physmem.avgQLat                       10774.23                       # Average queueing delay per DRAM burst
+system.physmem.avgBankLat                    13855.23                       # Average bank access latency per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  26828.44                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        1477.42                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  29629.46                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        1470.92                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     1477.42                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     1470.92                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                          11.54                       # Data bus utilization in percentage
-system.physmem.busUtilRead                      11.54                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                          11.49                       # Data bus utilization in percentage
+system.physmem.busUtilRead                      11.49                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         0.62                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.91                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                        332                       # Number of row buffer hits during reads
+system.physmem.readRowHits                        326                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   84.69                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   83.16                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        43172.19                       # Average gap between requests
-system.physmem.pageHitRate                      84.69                       # Row buffer hit rate, read and write combined
+system.physmem.avgGap                        43363.52                       # Average gap between requests
+system.physmem.pageHitRate                      83.16                       # Row buffer hit rate, read and write combined
 system.physmem.prechargeAllPercent               0.06                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                   1473647017                       # Throughput (bytes/s)
+system.membus.throughput                   1467166979                       # Throughput (bytes/s)
 system.membus.trans_dist::ReadReq                 351                       # Transaction distribution
 system.membus.trans_dist::ReadResp                350                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                41                       # Transaction distribution
@@ -213,10 +234,10 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
 system.membus.tot_pkt_size::total               25024                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.data_through_bus                  25024                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy              483500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy              484000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               2.8                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            3646500                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             21.5                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            3645250                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             21.4                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                    2481                       # Number of BP lookups
 system.cpu.branchPred.condPredicted              1780                       # Number of conditional branches predicted
@@ -312,10 +333,10 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                   13                       # Number of system calls
-system.cpu.numCycles                            33963                       # number of cpu cycles simulated
+system.cpu.numCycles                            34113                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles               6931                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.icacheStallCycles               6922                       # Number of cycles fetch is stalled on an Icache miss
 system.cpu.fetch.Insts                          11923                       # Number of instructions fetch has processed
 system.cpu.fetch.Branches                        2481                       # Number of branches that fetch encountered
 system.cpu.fetch.predictedBranches                990                       # Number of branches that fetch has predicted taken
@@ -324,26 +345,26 @@ system.cpu.fetch.SquashCycles                    1612                       # Nu
 system.cpu.fetch.BlockedCycles                   2574                       # Number of cycles fetch has spent blocked
 system.cpu.fetch.CacheLines                      1947                       # Number of cache lines fetched
 system.cpu.fetch.IcacheSquashes                   283                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              13238                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.137785                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.552533                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples              13229                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.138559                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.553229                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                    10611     80.16%     80.16% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                      226      1.71%     81.86% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      203      1.53%     83.40% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      226      1.71%     85.10% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      222      1.68%     86.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      269      2.03%     88.81% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                       92      0.69%     89.51% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                    10602     80.14%     80.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                      226      1.71%     81.85% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      203      1.53%     83.38% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      226      1.71%     85.09% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      222      1.68%     86.77% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      269      2.03%     88.80% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                       92      0.70%     89.50% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::7                      145      1.10%     90.60% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::8                     1244      9.40%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                13238                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.073050                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.351059                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                     6943                       # Number of cycles decode is idle
+system.cpu.fetch.rateDist::total                13229                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.072729                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.349515                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                     6934                       # Number of cycles decode is idle
 system.cpu.decode.BlockedCycles                  2849                       # Number of cycles decode is blocked
 system.cpu.decode.RunCycles                      2426                       # Number of cycles decode is running
 system.cpu.decode.UnblockCycles                    69                       # Number of cycles decode is unblocking
@@ -353,7 +374,7 @@ system.cpu.decode.BranchMispred                   159                       # Nu
 system.cpu.decode.DecodedInsts                  13218                       # Number of instructions handled by decode
 system.cpu.decode.SquashedInsts                   538                       # Number of squashed instructions handled by decode
 system.cpu.rename.SquashCycles                    951                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                     7209                       # Number of cycles rename is idle
+system.cpu.rename.IdleCycles                     7200                       # Number of cycles rename is idle
 system.cpu.rename.BlockCycles                     361                       # Number of cycles rename is blocking
 system.cpu.rename.serializeStallCycles           2278                       # count of cycles rename stalled for serializing inst
 system.cpu.rename.RunCycles                      2227                       # Number of cycles rename is running
@@ -370,7 +391,7 @@ system.cpu.rename.CommittedMaps                  5673                       # Nu
 system.cpu.rename.UndoneMaps                     6817                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts                 41                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts             38                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                       665                       # count of insts added to the skid buffer
+system.cpu.rename.skidInsts                       666                       # count of insts added to the skid buffer
 system.cpu.memDep0.insertedLoads                 2790                       # Number of loads inserted to the mem dependence unit.
 system.cpu.memDep0.insertedStores                1564                       # Number of stores inserted to the mem dependence unit.
 system.cpu.memDep0.conflictingLoads                37                       # Number of conflicting loads.
@@ -382,23 +403,23 @@ system.cpu.iq.iqSquashedInstsIssued               113                       # Nu
 system.cpu.iq.iqSquashedInstsExamined            5124                       # Number of squashed instructions iterated over during squash; mainly for profiling
 system.cpu.iq.iqSquashedOperandsExamined        14241                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved             12                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         13238                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.673893                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.378375                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples         13229                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.674352                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.378841                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0                9658     72.96%     72.96% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                1314      9.93%     82.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                 816      6.16%     89.05% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 544      4.11%     93.16% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 456      3.44%     96.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 260      1.96%     98.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0                9649     72.94%     72.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                1315      9.94%     82.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                 815      6.16%     89.04% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 543      4.10%     93.14% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 457      3.45%     96.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 260      1.97%     98.56% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                 123      0.93%     99.49% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                  55      0.42%     99.91% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                  12      0.09%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           13238                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           13229                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntAlu                       8      3.57%      3.57% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                      0      0.00%      3.57% # attempts to use FU when none available
@@ -468,10 +489,10 @@ system.cpu.iq.FU_type_0::MemWrite                1210     13.56%    100.00% # Ty
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::total                   8921                       # Type of FU issued
-system.cpu.iq.rate                           0.262668                       # Inst issue rate
+system.cpu.iq.rate                           0.261513                       # Inst issue rate
 system.cpu.iq.fu_busy_cnt                         224                       # FU busy when requested
 system.cpu.iq.fu_busy_rate                   0.025109                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              31381                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_reads              31372                       # Number of integer instruction queue reads
 system.cpu.iq.int_inst_queue_writes             16313                       # Number of integer instruction queue writes
 system.cpu.iq.int_inst_queue_wakeup_accesses         8052                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                  36                       # Number of floating instruction queue reads
@@ -512,35 +533,35 @@ system.cpu.iew.exec_nop                             0                       # nu
 system.cpu.iew.exec_refs                         3299                       # number of memory reference insts executed
 system.cpu.iew.exec_branches                     1437                       # Number of branches executed
 system.cpu.iew.exec_stores                       1160                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.250950                       # Inst execution rate
+system.cpu.iew.exec_rate                     0.249846                       # Inst execution rate
 system.cpu.iew.wb_sent                           8226                       # cumulative count of insts sent to commit
 system.cpu.iew.wb_count                          8068                       # cumulative count of insts written-back
 system.cpu.iew.wb_producers                      3883                       # num instructions producing a value
 system.cpu.iew.wb_consumers                      7788                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.237553                       # insts written-back per cycle
+system.cpu.iew.wb_rate                       0.236508                       # insts written-back per cycle
 system.cpu.iew.wb_fanout                     0.498588                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitSquashedInsts            5496                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              37                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts               327                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        12287                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.466265                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.297883                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples        12278                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.466607                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.298423                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0        10001     81.39%     81.39% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1         1069      8.70%     90.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          402      3.27%     93.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          263      2.14%     95.51% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          175      1.42%     96.93% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0         9992     81.38%     81.38% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1         1070      8.71%     90.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          401      3.27%     93.36% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          262      2.13%     95.50% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          176      1.43%     96.93% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::5          172      1.40%     98.33% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::6           49      0.40%     98.73% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           35      0.28%     99.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8          121      0.98%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           35      0.29%     99.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8          121      0.99%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        12287                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        12278                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts                 4591                       # Number of instructions committed
 system.cpu.commit.committedOps                   5729                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -553,23 +574,23 @@ system.cpu.commit.int_insts                      4976                       # Nu
 system.cpu.commit.function_calls                   82                       # Number of function calls committed.
 system.cpu.commit.bw_lim_events                   121                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                        23234                       # The number of ROB reads
+system.cpu.rob.rob_reads                        23225                       # The number of ROB reads
 system.cpu.rob.rob_writes                       23415                       # The number of ROB writes
-system.cpu.timesIdled                             221                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           20725                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.timesIdled                             220                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           20884                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        4591                       # Number of Instructions Simulated
 system.cpu.committedOps                          5729                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total                  4591                       # Number of Instructions Simulated
-system.cpu.cpi                               7.397735                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         7.397735                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.135177                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.135177                       # IPC: Total IPC of All Threads
+system.cpu.cpi                               7.430407                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         7.430407                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.134582                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.134582                       # IPC: Total IPC of All Threads
 system.cpu.int_regfile_reads                    39210                       # number of integer regfile reads
 system.cpu.int_regfile_writes                    7985                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
 system.cpu.misc_regfile_reads                    3239                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                     24                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput              1643248336                       # Throughput (bytes/s)
+system.cpu.toL2Bus.throughput              1636022514                       # Throughput (bytes/s)
 system.cpu.toL2Bus.trans_dist::ReadReq            396                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp           395                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           41                       # Transaction distribution
@@ -584,19 +605,19 @@ system.cpu.toL2Bus.data_through_bus             27904                       # To
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
 system.cpu.toL2Bus.reqLayer0.occupancy         218500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.3                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        479750                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy        478500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          2.8                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        229245                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          1.4                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy        228745                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          1.3                       # Layer utilization (%)
 system.cpu.icache.tags.replacements                 4                       # number of replacements
-system.cpu.icache.tags.tagsinuse           148.072869                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse           147.751269                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                1584                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               290                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs              5.462069                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   148.072869                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.072301                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.072301                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   147.751269                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.072144                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.072144                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          286                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0          168                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          118                       # Occupied blocks per task id
@@ -615,12 +636,12 @@ system.cpu.icache.demand_misses::cpu.inst          363                       # n
 system.cpu.icache.demand_misses::total            363                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          363                       # number of overall misses
 system.cpu.icache.overall_misses::total           363                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     23913500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     23913500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     23913500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     23913500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     23913500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     23913500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     24948500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     24948500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     24948500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     24948500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     24948500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     24948500                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst         1947                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total         1947                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst         1947                       # number of demand (read+write) accesses
@@ -633,12 +654,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.186441
 system.cpu.icache.demand_miss_rate::total     0.186441                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.186441                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.186441                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65877.410468                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 65877.410468                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 65877.410468                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 65877.410468                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 65877.410468                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 65877.410468                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68728.650138                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 68728.650138                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 68728.650138                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 68728.650138                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 68728.650138                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 68728.650138                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs          110                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 2                       # number of cycles access was blocked
@@ -659,39 +680,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          290
 system.cpu.icache.demand_mshr_misses::total          290                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          290                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          290                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     19169750                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     19169750                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     19169750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     19169750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     19169750                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     19169750                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     20177000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     20177000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     20177000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     20177000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     20177000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     20177000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.148947                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.148947                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.148947                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.148947                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.148947                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.148947                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66102.586207                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66102.586207                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66102.586207                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 66102.586207                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66102.586207                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 66102.586207                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69575.862069                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69575.862069                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69575.862069                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 69575.862069                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69575.862069                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 69575.862069                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          186.546841                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          186.152493                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                 40                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              350                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.114286                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   139.414103                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    47.132739                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004255                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.001438                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.005693                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   139.100090                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    47.052403                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004245                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.001436                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.005681                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          350                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          193                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          157                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          192                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          158                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.010681                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses             3887                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses            3887                       # Number of data accesses
@@ -715,17 +736,17 @@ system.cpu.l2cache.demand_misses::total           397                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          270                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          127                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          397                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     18673250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      6669500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     25342750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      2970250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      2970250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     18673250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data      9639750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     28313000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     18673250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data      9639750                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     28313000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     19680500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      6712250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     26392750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      3002000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      3002000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     19680500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      9714250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     29394750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     19680500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      9714250                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     29394750                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst          290                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data          106                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total          396                       # number of ReadReq accesses(hits+misses)
@@ -748,17 +769,17 @@ system.cpu.l2cache.demand_miss_rate::total     0.908467                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.931034                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.863946                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.908467                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69160.185185                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77552.325581                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 71187.500000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72445.121951                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72445.121951                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69160.185185                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75903.543307                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 71317.380353                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69160.185185                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75903.543307                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 71317.380353                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72890.740741                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78049.418605                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 74136.938202                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73219.512195                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73219.512195                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72890.740741                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76490.157480                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 74042.191436                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72890.740741                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76490.157480                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 74042.191436                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -784,17 +805,17 @@ system.cpu.l2cache.demand_mshr_misses::total          392
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          270                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          122                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          392                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     15282750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      5380500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     20663250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      2466250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2466250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     15282750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      7846750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     23129500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     15282750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      7846750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     23129500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     16292000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      5423750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     21715750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      2498500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2498500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     16292000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      7922250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     24214250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     16292000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      7922250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     24214250                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.931034                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.764151                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.886364                       # mshr miss rate for ReadReq accesses
@@ -806,27 +827,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.897025
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.931034                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.829932                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.897025                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56602.777778                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66425.925926                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58869.658120                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60152.439024                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60152.439024                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56602.777778                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64317.622951                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59003.826531                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56602.777778                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64317.622951                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59003.826531                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60340.740741                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66959.876543                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61868.233618                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60939.024390                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60939.024390                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60340.740741                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64936.475410                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61771.045918                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60340.740741                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64936.475410                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61771.045918                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            87.464066                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse            87.338696                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs                2394                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               146                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs             16.397260                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    87.464066                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.021354                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.021354                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data    87.338696                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.021323                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.021323                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          146                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           57                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           89                       # Occupied blocks per task id
@@ -855,16 +876,16 @@ system.cpu.dcache.demand_misses::cpu.data          496                       # n
 system.cpu.dcache.demand_misses::total            496                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data          496                       # number of overall misses
 system.cpu.dcache.overall_misses::total           496                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     11356993                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     11356993                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     19957500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     19957500                       # number of WriteReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     11160743                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     11160743                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     20397000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     20397000                       # number of WriteReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       130000                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::total       130000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     31314493                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     31314493                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     31314493                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     31314493                       # number of overall miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     31557743                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     31557743                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     31557743                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     31557743                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data         1956                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total         1956                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          913                       # number of WriteReq accesses(hits+misses)
@@ -887,16 +908,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.172883
 system.cpu.dcache.demand_miss_rate::total     0.172883                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.172883                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.172883                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60089.910053                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 60089.910053                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65008.143322                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 65008.143322                       # average WriteReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59051.550265                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 59051.550265                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66439.739414                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 66439.739414                       # average WriteReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        65000                       # average LoadLockedReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        65000                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 63134.058468                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 63134.058468                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 63134.058468                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 63134.058468                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 63624.481855                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 63624.481855                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 63624.481855                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 63624.481855                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs           98                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 3                       # number of cycles access was blocked
@@ -923,14 +944,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          147
 system.cpu.dcache.demand_mshr_misses::total          147                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          147                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          147                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      6979505                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      6979505                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      3012250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      3012250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      9991755                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      9991755                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      9991755                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      9991755                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      7022255                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      7022255                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      3044000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      3044000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     10066255                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     10066255                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     10066255                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     10066255                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.054192                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.054192                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.044907                       # mshr miss rate for WriteReq accesses
@@ -939,14 +960,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.051237
 system.cpu.dcache.demand_mshr_miss_rate::total     0.051237                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.051237                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.051237                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65844.386792                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65844.386792                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73469.512195                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73469.512195                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67971.122449                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 67971.122449                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67971.122449                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 67971.122449                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66247.688679                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66247.688679                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74243.902439                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74243.902439                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68477.925170                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 68477.925170                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68477.925170                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 68477.925170                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 3e4b6f41c10a6ab1f92a46be07f93f0c2403d079..5e15549ca7bdf60b06ae7a90a168a0e3a385dd28 100644 (file)
@@ -4,11 +4,11 @@ sim_seconds                                  0.000025                       # Nu
 sim_ticks                                    24975000                       # Number of ticks simulated
 final_tick                                   24975000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  42229                       # Simulator instruction rate (inst/s)
-host_op_rate                                    42225                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              181364329                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 230516                       # Number of bytes of host memory used
-host_seconds                                     0.14                       # Real time elapsed on the host
+host_inst_rate                                  86020                       # Simulator instruction rate (inst/s)
+host_op_rate                                    86001                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              369354314                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 263428                       # Number of bytes of host memory used
+host_seconds                                     0.07                       # Real time elapsed on the host
 sim_insts                                        5814                       # Number of instructions simulated
 sim_ops                                          5814                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -90,8 +90,8 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       304                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       121                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       303                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       122                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        23                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         4                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         2                       # What read queue length does an incoming req see
@@ -154,34 +154,59 @@ system.physmem.wrQLenPdf::28                        0                       # Wh
 system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          107                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      245.831776                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     162.727359                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     292.380874                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64                36     33.64%     33.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128               20     18.69%     52.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192               15     14.02%     66.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256                9      8.41%     74.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320                4      3.74%     78.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384                8      7.48%     85.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448                1      0.93%     86.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512                4      3.74%     90.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576                2      1.87%     92.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704                2      1.87%     94.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768                2      1.87%     96.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832                1      0.93%     97.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024               1      0.93%     98.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216               1      0.93%     99.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2240               1      0.93%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            107                       # Bytes accessed per row activation
-system.physmem.totQLat                        3167500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  13555000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples           75                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      267.093333                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     186.339521                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     256.296765                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             18     24.00%     24.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           29     38.67%     62.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383            9     12.00%     74.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            8     10.67%     85.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            4      5.33%     90.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            1      1.33%     92.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            1      1.33%     93.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151            5      6.67%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total             75                       # Bytes accessed per row activation
+system.physmem.totQLat                        3086250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  13542500                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      2275000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                     8112500                       # Total ticks spent accessing banks
-system.physmem.avgQLat                        6961.54                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    17829.67                       # Average bank access latency per DRAM burst
+system.physmem.totBankLat                     8181250                       # Total ticks spent accessing banks
+system.physmem.avgQLat                        6782.97                       # Average queueing delay per DRAM burst
+system.physmem.avgBankLat                    17980.77                       # Average bank access latency per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29791.21                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  29763.74                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                        1165.97                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                     1165.97                       # Average system read bandwidth in MiByte/s
@@ -190,14 +215,14 @@ system.physmem.peakBW                        12800.00                       # Th
 system.physmem.busUtil                           9.11                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       9.11                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         0.54                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.51                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                        348                       # Number of row buffer hits during reads
+system.physmem.readRowHits                        344                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   76.48                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   75.60                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
 system.physmem.avgGap                        54712.09                       # Average gap between requests
-system.physmem.pageHitRate                      76.48                       # Row buffer hit rate, read and write combined
+system.physmem.pageHitRate                      75.60                       # Row buffer hit rate, read and write combined
 system.physmem.prechargeAllPercent               0.04                       # Percentage of time for which DRAM has all the banks in precharge state
 system.membus.throughput                   1165965966                       # Throughput (bytes/s)
 system.membus.trans_dist::ReadReq                 404                       # Transaction distribution
@@ -212,8 +237,8 @@ system.membus.data_through_bus                  29120                       # To
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
 system.membus.reqLayer0.occupancy              552000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               2.2                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            4260750                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             17.1                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            4258000                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             17.0                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                    1156                       # Number of BP lookups
 system.cpu.branchPred.condPredicted               861                       # Number of conditional branches predicted
@@ -294,24 +319,24 @@ system.cpu.stage0.utilization                7.303157                       # Pe
 system.cpu.stage1.idleCycles                    47138                       # Number of cycles 0 instructions are processed.
 system.cpu.stage1.runCycles                      2813                       # Number of cycles 1+ instructions are processed.
 system.cpu.stage1.utilization                5.631519                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles                    47185                       # Number of cycles 0 instructions are processed.
-system.cpu.stage2.runCycles                      2766                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization                5.537427                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles                    47184                       # Number of cycles 0 instructions are processed.
+system.cpu.stage2.runCycles                      2767                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage2.utilization                5.539429                       # Percentage of cycles stage was utilized (processing insts).
 system.cpu.stage3.idleCycles                    48713                       # Number of cycles 0 instructions are processed.
 system.cpu.stage3.runCycles                      1238                       # Number of cycles 1+ instructions are processed.
 system.cpu.stage3.utilization                2.478429                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles                    47060                       # Number of cycles 0 instructions are processed.
-system.cpu.stage4.runCycles                      2891                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization                5.787672                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles                    47063                       # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles                      2888                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization                5.781666                       # Percentage of cycles stage was utilized (processing insts).
 system.cpu.icache.tags.replacements                13                       # number of replacements
-system.cpu.icache.tags.tagsinuse           150.636983                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse           150.508435                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                 428                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               319                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs              1.341693                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   150.636983                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.073553                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.073553                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   150.508435                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.073490                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.073490                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          306                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0          128                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          178                       # Occupied blocks per task id
@@ -330,12 +355,12 @@ system.cpu.icache.demand_misses::cpu.inst          350                       # n
 system.cpu.icache.demand_misses::total            350                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          350                       # number of overall misses
 system.cpu.icache.overall_misses::total           350                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     25425500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     25425500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     25425500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     25425500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     25425500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     25425500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     25364500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     25364500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     25364500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     25364500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     25364500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     25364500                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst          778                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total          778                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst          778                       # number of demand (read+write) accesses
@@ -348,12 +373,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.449871
 system.cpu.icache.demand_miss_rate::total     0.449871                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.449871                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.449871                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72644.285714                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 72644.285714                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 72644.285714                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 72644.285714                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 72644.285714                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 72644.285714                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst        72470                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total        72470                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst        72470                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total        72470                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst        72470                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total        72470                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -374,24 +399,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          319
 system.cpu.icache.demand_mshr_misses::total          319                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          319                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          319                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     23091000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     23091000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     23091000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     23091000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     23091000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     23091000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     23031000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     23031000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     23031000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     23031000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     23031000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     23031000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.410026                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.410026                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.410026                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.410026                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.410026                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.410026                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72385.579937                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72385.579937                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72385.579937                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 72385.579937                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72385.579937                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 72385.579937                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72197.492163                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72197.492163                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72197.492163                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 72197.492163                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72197.492163                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 72197.492163                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.throughput              1171091091                       # Throughput (bytes/s)
 system.cpu.toL2Bus.trans_dist::ReadReq            406                       # Transaction distribution
@@ -408,21 +433,21 @@ system.cpu.toL2Bus.data_through_bus             29248                       # To
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
 system.cpu.toL2Bus.reqLayer0.occupancy         228500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.9                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        538500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy        538000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          2.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        225750                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy        225500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.9                       # Layer utilization (%)
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          208.420638                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          208.255183                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  2                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              404                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.004950                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   152.318425                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    56.102213                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004648                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.001712                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.006360                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   152.186433                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    56.068750                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004644                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.001711                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.006355                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          404                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          155                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          249                       # Occupied blocks per task id
@@ -446,17 +471,17 @@ system.cpu.l2cache.demand_misses::total           455                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          317                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          138                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          455                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     22745500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      6874750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     29620250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      3847000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      3847000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     22745500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data     10721750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     33467250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     22745500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data     10721750                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     33467250                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     22685500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      6903000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     29588500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      3846500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      3846500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     22685500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data     10749500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     33435000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     22685500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data     10749500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     33435000                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst          319                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data           87                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total          406                       # number of ReadReq accesses(hits+misses)
@@ -479,17 +504,17 @@ system.cpu.l2cache.demand_miss_rate::total     0.995624                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.993730                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.995624                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71752.365931                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79020.114943                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 73317.450495                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75431.372549                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75431.372549                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71752.365931                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77693.840580                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 73554.395604                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71752.365931                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77693.840580                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 73554.395604                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71563.091483                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79344.827586                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 73238.861386                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75421.568627                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75421.568627                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71563.091483                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77894.927536                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 73483.516484                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71563.091483                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77894.927536                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 73483.516484                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -509,17 +534,17 @@ system.cpu.l2cache.demand_mshr_misses::total          455
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          317                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          138                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          455                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     18763000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      5795250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     24558250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     18705000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      5824500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     24529500                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      3204500                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      3204500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     18763000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      8999750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     27762750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     18763000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      8999750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     27762750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     18705000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      9029000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     27734000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     18705000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      9029000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     27734000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.993730                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.995074                       # mshr miss rate for ReadReq accesses
@@ -531,27 +556,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.995624
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.993730                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.995624                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59189.274448                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66612.068966                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60787.747525                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59006.309148                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66948.275862                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60716.584158                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62833.333333                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62833.333333                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59189.274448                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65215.579710                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61017.032967                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59189.274448                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65215.579710                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61017.032967                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59006.309148                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65427.536232                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60953.846154                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59006.309148                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65427.536232                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60953.846154                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            90.339752                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse            90.278621                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs                1638                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               138                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs             11.869565                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    90.339752                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.022056                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.022056                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data    90.278621                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.022041                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.022041                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          138                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           30                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          108                       # Occupied blocks per task id
@@ -574,14 +599,14 @@ system.cpu.dcache.demand_misses::cpu.data          450                       # n
 system.cpu.dcache.demand_misses::total            450                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data          450                       # number of overall misses
 system.cpu.dcache.overall_misses::total           450                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      7659250                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      7659250                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     21762250                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     21762250                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     29421500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     29421500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     29421500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     29421500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      7687000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      7687000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     21761250                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     21761250                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     29448250                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     29448250                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     29448250                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     29448250                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data         1163                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total         1163                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          925                       # number of WriteReq accesses(hits+misses)
@@ -598,14 +623,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.215517
 system.cpu.dcache.demand_miss_rate::total     0.215517                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.215517                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.215517                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78961.340206                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 78961.340206                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61649.433428                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 61649.433428                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 65381.111111                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 65381.111111                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 65381.111111                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 65381.111111                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 79247.422680                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 79247.422680                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61646.600567                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 61646.600567                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 65440.555556                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 65440.555556                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 65440.555556                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 65440.555556                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs          265                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                13                       # number of cycles access was blocked
@@ -630,14 +655,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          138
 system.cpu.dcache.demand_mshr_misses::total          138                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          138                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          138                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      6968250                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      6968250                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      3901000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      3901000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     10869250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     10869250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     10869250                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     10869250                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      6996500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      6996500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      3900500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      3900500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     10897000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     10897000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     10897000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     10897000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.074807                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.074807                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.055135                       # mshr miss rate for WriteReq accesses
@@ -646,14 +671,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.066092
 system.cpu.dcache.demand_mshr_miss_rate::total     0.066092                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.066092                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.066092                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80094.827586                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80094.827586                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76490.196078                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76490.196078                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78762.681159                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 78762.681159                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78762.681159                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 78762.681159                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80419.540230                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80419.540230                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76480.392157                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76480.392157                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78963.768116                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 78963.768116                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78963.768116                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 78963.768116                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index b4a732973b804786b99984a1fb116a499f66dfe7..cbbbf2296215a0d50d0f84c5f633cf6c83eb6036 100644 (file)
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000022                       # Number of seconds simulated
-sim_ticks                                    21898500                       # Number of ticks simulated
-final_tick                                   21898500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    21918500                       # Number of ticks simulated
+final_tick                                   21918500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  38049                       # Simulator instruction rate (inst/s)
-host_op_rate                                    38045                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              161516903                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 231544                       # Number of bytes of host memory used
-host_seconds                                     0.14                       # Real time elapsed on the host
+host_inst_rate                                  56826                       # Simulator instruction rate (inst/s)
+host_op_rate                                    56817                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              241494238                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 266500                       # Number of bytes of host memory used
+host_seconds                                     0.09                       # Real time elapsed on the host
 sim_insts                                        5156                       # Number of instructions simulated
 sim_ops                                          5156                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total           21440                       # Nu
 system.physmem.num_reads::cpu.inst                335                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                142                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   477                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            979062493                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            415005594                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1394068087                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       979062493                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          979062493                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           979062493                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           415005594                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1394068087                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            978169127                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            414626913                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1392796040                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       978169127                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          978169127                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           978169127                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           414626913                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1392796040                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           477                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                         477                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        21819000                       # Total gap between requests
+system.physmem.totGap                        21839000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -154,52 +154,77 @@ system.physmem.wrQLenPdf::28                        0                       # Wh
 system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          118                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      230.508475                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     147.858901                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     317.434070                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64                46     38.98%     38.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128               20     16.95%     55.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192               19     16.10%     72.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256                8      6.78%     78.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320                7      5.93%     84.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384                3      2.54%     87.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448                4      3.39%     90.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512                2      1.69%     92.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576                2      1.69%     94.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704                1      0.85%     94.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768                1      0.85%     95.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832                1      0.85%     96.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024               2      1.69%     98.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1920               1      0.85%     99.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2368               1      0.85%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            118                       # Bytes accessed per row activation
-system.physmem.totQLat                        2620250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  13667750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples           87                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      246.436782                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     168.540369                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     250.647056                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             26     29.89%     29.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           32     36.78%     66.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           13     14.94%     81.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            6      6.90%     88.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            2      2.30%     90.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            1      1.15%     91.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            2      2.30%     94.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151            5      5.75%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total             87                       # Bytes accessed per row activation
+system.physmem.totQLat                        2715000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  13776250                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      2385000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                     8662500                       # Total ticks spent accessing banks
-system.physmem.avgQLat                        5493.19                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    18160.38                       # Average bank access latency per DRAM burst
+system.physmem.totBankLat                     8676250                       # Total ticks spent accessing banks
+system.physmem.avgQLat                        5691.82                       # Average queueing delay per DRAM burst
+system.physmem.avgBankLat                    18189.20                       # Average bank access latency per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  28653.56                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        1394.07                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  28881.03                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        1392.80                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     1394.07                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     1392.80                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                          10.89                       # Data bus utilization in percentage
-system.physmem.busUtilRead                      10.89                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                          10.88                       # Data bus utilization in percentage
+system.physmem.busUtilRead                      10.88                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         0.62                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.70                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                        359                       # Number of row buffer hits during reads
+system.physmem.readRowHits                        357                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   75.26                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   74.84                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        45742.14                       # Average gap between requests
-system.physmem.pageHitRate                      75.26                       # Row buffer hit rate, read and write combined
+system.physmem.avgGap                        45784.07                       # Average gap between requests
+system.physmem.pageHitRate                      74.84                       # Row buffer hit rate, read and write combined
 system.physmem.prechargeAllPercent               0.05                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                   1394068087                       # Throughput (bytes/s)
+system.membus.throughput                   1392796040                       # Throughput (bytes/s)
 system.membus.trans_dist::ReadReq                 426                       # Transaction distribution
 system.membus.trans_dist::ReadResp                426                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                51                       # Transaction distribution
@@ -212,7 +237,7 @@ system.membus.data_through_bus                  30528                       # To
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
 system.membus.reqLayer0.occupancy              605000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               2.8                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            4474750                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy            4473250                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization             20.4                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                    2174                       # Number of BP lookups
@@ -243,40 +268,40 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                    8                       # Number of system calls
-system.cpu.numCycles                            43798                       # number of cpu cycles simulated
+system.cpu.numCycles                            43838                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles               8822                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.icacheStallCycles               8831                       # Number of cycles fetch is stalled on an Icache miss
 system.cpu.fetch.Insts                          13183                       # Number of instructions fetch has processed
 system.cpu.fetch.Branches                        2174                       # Number of branches that fetch encountered
 system.cpu.fetch.predictedBranches                753                       # Number of branches that fetch has predicted taken
 system.cpu.fetch.Cycles                          3213                       # Number of cycles fetch has run and was not squashing or blocked
 system.cpu.fetch.SquashCycles                    1374                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles                   1344                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.BlockedCycles                   1408                       # Number of cycles fetch has spent blocked
 system.cpu.fetch.PendingTrapStallCycles           143                       # Number of stall cycles due to pending traps
 system.cpu.fetch.CacheLines                      1965                       # Number of cache lines fetched
 system.cpu.fetch.IcacheSquashes                   277                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              14432                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.913456                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.225567                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples              14505                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.908859                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.220900                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                    11219     77.74%     77.74% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                     1317      9.13%     86.86% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      104      0.72%     87.58% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      131      0.91%     88.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      305      2.11%     90.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      115      0.80%     91.40% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      150      1.04%     92.44% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      158      1.09%     93.54% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                      933      6.46%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                    11292     77.85%     77.85% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                     1317      9.08%     86.93% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      104      0.72%     87.65% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      131      0.90%     88.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      305      2.10%     90.65% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      115      0.79%     91.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      150      1.03%     92.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      158      1.09%     93.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                      933      6.43%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                14432                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.049637                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.300995                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                     8890                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                  1596                       # Number of cycles decode is blocked
+system.cpu.fetch.rateDist::total                14505                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.049592                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.300721                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                     8899                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                  1660                       # Number of cycles decode is blocked
 system.cpu.decode.RunCycles                      3025                       # Number of cycles decode is running
 system.cpu.decode.UnblockCycles                    53                       # Number of cycles decode is unblocking
 system.cpu.decode.SquashCycles                    868                       # Number of cycles decode is squashing
@@ -285,9 +310,9 @@ system.cpu.decode.BranchMispred                    43                       # Nu
 system.cpu.decode.DecodedInsts                  12292                       # Number of instructions handled by decode
 system.cpu.decode.SquashedInsts                   174                       # Number of squashed instructions handled by decode
 system.cpu.rename.SquashCycles                    868                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                     9072                       # Number of cycles rename is idle
+system.cpu.rename.IdleCycles                     9081                       # Number of cycles rename is idle
 system.cpu.rename.BlockCycles                     527                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles            919                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.serializeStallCycles            983                       # count of cycles rename stalled for serializing inst
 system.cpu.rename.RunCycles                      2898                       # Number of cycles rename is running
 system.cpu.rename.UnblockCycles                   148                       # Number of cycles rename is unblocking
 system.cpu.rename.RenamedInsts                  11862                       # Number of instructions processed by rename
@@ -314,23 +339,23 @@ system.cpu.iq.iqSquashedInstsIssued                39                       # Nu
 system.cpu.iq.iqSquashedInstsExamined            3412                       # Number of squashed instructions iterated over during squash; mainly for profiling
 system.cpu.iq.iqSquashedOperandsExamined         2076                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved              2                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         14432                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.574626                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.242806                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples         14505                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.571734                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.240341                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0               10849     75.17%     75.17% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                1422      9.85%     85.03% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                 891      6.17%     91.20% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 553      3.83%     95.03% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 355      2.46%     97.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 226      1.57%     99.06% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                  89      0.62%     99.67% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0               10922     75.30%     75.30% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                1422      9.80%     85.10% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                 891      6.14%     91.24% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 553      3.81%     95.06% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 355      2.45%     97.50% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 226      1.56%     99.06% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                  89      0.61%     99.68% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                  30      0.21%     99.88% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                  17      0.12%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           14432                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           14505                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntAlu                       5      3.12%      3.12% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                      0      0.00%      3.12% # attempts to use FU when none available
@@ -400,10 +425,10 @@ system.cpu.iq.FU_type_0::MemWrite                1104     13.31%    100.00% # Ty
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::total                   8293                       # Type of FU issued
-system.cpu.iq.rate                           0.189347                       # Inst issue rate
+system.cpu.iq.rate                           0.189174                       # Inst issue rate
 system.cpu.iq.fu_busy_cnt                         160                       # FU busy when requested
 system.cpu.iq.fu_busy_rate                   0.019293                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              31213                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_reads              31286                       # Number of integer instruction queue reads
 system.cpu.iq.int_inst_queue_writes             12643                       # Number of integer instruction queue writes
 system.cpu.iq.int_inst_queue_wakeup_accesses         7453                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                   4                       # Number of floating instruction queue reads
@@ -444,35 +469,35 @@ system.cpu.iew.exec_nop                          1512                       # nu
 system.cpu.iew.exec_refs                         3186                       # number of memory reference insts executed
 system.cpu.iew.exec_branches                     1344                       # Number of branches executed
 system.cpu.iew.exec_stores                       1079                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.180648                       # Inst execution rate
+system.cpu.iew.exec_rate                     0.180483                       # Inst execution rate
 system.cpu.iew.wb_sent                           7546                       # cumulative count of insts sent to commit
 system.cpu.iew.wb_count                          7455                       # cumulative count of insts written-back
 system.cpu.iew.wb_producers                      2921                       # num instructions producing a value
 system.cpu.iew.wb_consumers                      4197                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.170213                       # insts written-back per cycle
+system.cpu.iew.wb_rate                       0.170058                       # insts written-back per cycle
 system.cpu.iew.wb_fanout                     0.695973                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitSquashedInsts            4914                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              10                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts               396                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        13564                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.428561                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.209396                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples        13637                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.426267                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.206560                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0        11162     82.29%     82.29% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1          999      7.37%     89.66% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          630      4.64%     94.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          315      2.32%     96.62% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          149      1.10%     97.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5           94      0.69%     98.41% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0        11235     82.39%     82.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1          999      7.33%     89.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          630      4.62%     94.33% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          315      2.31%     96.64% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          149      1.09%     97.73% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5           94      0.69%     98.42% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::6           68      0.50%     98.92% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::7           41      0.30%     99.22% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::8          106      0.78%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        13564                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        13637                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts                 5813                       # Number of instructions committed
 system.cpu.commit.committedOps                   5813                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -485,23 +510,23 @@ system.cpu.commit.int_insts                      5111                       # Nu
 system.cpu.commit.function_calls                   87                       # Number of function calls committed.
 system.cpu.commit.bw_lim_events                   106                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                        24172                       # The number of ROB reads
+system.cpu.rob.rob_reads                        24245                       # The number of ROB reads
 system.cpu.rob.rob_writes                       22333                       # The number of ROB writes
-system.cpu.timesIdled                             285                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           29366                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.timesIdled                             286                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           29333                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        5156                       # Number of Instructions Simulated
 system.cpu.committedOps                          5156                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total                  5156                       # Number of Instructions Simulated
-system.cpu.cpi                               8.494569                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         8.494569                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.117722                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.117722                       # IPC: Total IPC of All Threads
+system.cpu.cpi                               8.502327                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         8.502327                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.117615                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.117615                       # IPC: Total IPC of All Threads
 system.cpu.int_regfile_reads                    10743                       # number of integer regfile reads
 system.cpu.int_regfile_writes                    5234                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                         3                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                        1                       # number of floating regfile writes
 system.cpu.misc_regfile_reads                     148                       # number of misc regfile reads
-system.cpu.toL2Bus.throughput              1402835811                       # Throughput (bytes/s)
+system.cpu.toL2Bus.throughput              1401555763                       # Throughput (bytes/s)
 system.cpu.toL2Bus.trans_dist::ReadReq            429                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp           429                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           51                       # Transaction distribution
@@ -518,17 +543,17 @@ system.cpu.toL2Bus.reqLayer0.occupancy         240000                       # La
 system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer0.occupancy        570750                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          2.6                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        227500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy        227000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.0                       # Layer utilization (%)
 system.cpu.icache.tags.replacements                17                       # number of replacements
-system.cpu.icache.tags.tagsinuse           161.632436                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse           161.390328                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                1514                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               338                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs              4.479290                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   161.632436                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.078922                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.078922                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   161.390328                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.078804                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.078804                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          321                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0          149                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          172                       # Occupied blocks per task id
@@ -547,12 +572,12 @@ system.cpu.icache.demand_misses::cpu.inst          451                       # n
 system.cpu.icache.demand_misses::total            451                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          451                       # number of overall misses
 system.cpu.icache.overall_misses::total           451                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     31196500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     31196500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     31196500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     31196500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     31196500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     31196500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     31256750                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     31256750                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     31256750                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     31256750                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     31256750                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     31256750                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst         1965                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total         1965                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst         1965                       # number of demand (read+write) accesses
@@ -565,12 +590,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.229517
 system.cpu.icache.demand_miss_rate::total     0.229517                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.229517                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.229517                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69171.840355                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 69171.840355                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 69171.840355                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 69171.840355                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 69171.840355                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 69171.840355                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69305.432373                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 69305.432373                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 69305.432373                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 69305.432373                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 69305.432373                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 69305.432373                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs           47                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 1                       # number of cycles access was blocked
@@ -591,39 +616,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          338
 system.cpu.icache.demand_mshr_misses::total          338                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          338                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          338                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     24201750                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     24201750                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     24201750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     24201750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     24201750                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     24201750                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     24262750                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     24262750                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     24262750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     24262750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     24262750                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     24262750                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.172010                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.172010                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.172010                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.172010                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.172010                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.172010                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71602.810651                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71602.810651                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71602.810651                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 71602.810651                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71602.810651                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 71602.810651                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71783.284024                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71783.284024                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71783.284024                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 71783.284024                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71783.284024                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 71783.284024                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          221.801023                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          221.496759                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  3                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              426                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.007042                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   163.923735                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    57.877288                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005003                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.001766                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.006769                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   163.678282                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    57.818477                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004995                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.001764                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.006760                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          426                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          188                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          238                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          189                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          237                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.013000                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses             4317                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses            4317                       # Number of data accesses
@@ -644,17 +669,17 @@ system.cpu.l2cache.demand_misses::total           477                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          335                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          142                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          477                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     23833750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      7026750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     30860500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      3814250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      3814250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     23833750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data     10841000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     34674750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     23833750                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data     10841000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     34674750                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     23894750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      7065750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     30960500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      3800750                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      3800750                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     23894750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data     10866500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     34761250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     23894750                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data     10866500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     34761250                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst          338                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data           91                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total          429                       # number of ReadReq accesses(hits+misses)
@@ -677,17 +702,17 @@ system.cpu.l2cache.demand_miss_rate::total     0.993750                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.991124                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.993750                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71145.522388                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77217.032967                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 72442.488263                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74789.215686                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74789.215686                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71145.522388                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76345.070423                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 72693.396226                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71145.522388                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76345.070423                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 72693.396226                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71327.611940                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77645.604396                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 72677.230047                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74524.509804                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74524.509804                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71327.611940                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76524.647887                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 72874.737945                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71327.611940                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76524.647887                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 72874.737945                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -707,17 +732,17 @@ system.cpu.l2cache.demand_mshr_misses::total          477
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          335                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          142                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          477                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     19597750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      5909750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     25507500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      3183250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      3183250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     19597750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      9093000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     28690750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     19597750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      9093000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     28690750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     19660250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      5948250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     25608500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      3170750                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      3170750                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     19660250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      9119000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     28779250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     19660250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      9119000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     28779250                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.991124                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.993007                       # mshr miss rate for ReadReq accesses
@@ -729,27 +754,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.993750
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.991124                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.993750                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58500.746269                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64942.307692                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59876.760563                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62416.666667                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62416.666667                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58500.746269                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64035.211268                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60148.322851                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58500.746269                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64035.211268                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60148.322851                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58687.313433                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65365.384615                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60113.849765                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62171.568627                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62171.568627                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58687.313433                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64218.309859                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60333.857442                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58687.313433                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64218.309859                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60333.857442                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            91.712882                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse            91.623425                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs                2395                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               142                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs             16.866197                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    91.712882                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.022391                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.022391                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data    91.623425                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.022369                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.022369                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          142                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           39                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          103                       # Occupied blocks per task id
@@ -772,14 +797,14 @@ system.cpu.dcache.demand_misses::cpu.data          510                       # n
 system.cpu.dcache.demand_misses::total            510                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data          510                       # number of overall misses
 system.cpu.dcache.overall_misses::total           510                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     10190250                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     10190250                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     22575249                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     22575249                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     32765499                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     32765499                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     32765499                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     32765499                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     10261250                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     10261250                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     22413999                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     22413999                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     32675249                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     32675249                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     32675249                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     32675249                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data         1980                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total         1980                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          925                       # number of WriteReq accesses(hits+misses)
@@ -796,14 +821,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.175559
 system.cpu.dcache.demand_miss_rate::total     0.175559                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.175559                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.175559                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68853.040541                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 68853.040541                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62362.566298                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 62362.566298                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 64246.076471                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 64246.076471                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 64246.076471                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 64246.076471                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69332.770270                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 69332.770270                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61917.124309                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 61917.124309                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 64069.115686                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 64069.115686                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 64069.115686                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 64069.115686                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs          605                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                11                       # number of cycles access was blocked
@@ -828,14 +853,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          142
 system.cpu.dcache.demand_mshr_misses::total          142                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          142                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          142                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      7121250                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      7121250                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      3866249                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      3866249                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     10987499                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     10987499                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     10987499                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     10987499                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      7160250                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      7160250                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      3852749                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      3852749                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     11012999                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     11012999                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     11012999                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     11012999                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.045960                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.045960                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.055135                       # mshr miss rate for WriteReq accesses
@@ -844,14 +869,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.048881
 system.cpu.dcache.demand_mshr_miss_rate::total     0.048881                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.048881                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.048881                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78255.494505                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78255.494505                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75808.803922                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75808.803922                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77376.753521                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 77376.753521                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77376.753521                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 77376.753521                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78684.065934                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78684.065934                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75544.098039                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75544.098039                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77556.330986                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 77556.330986                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77556.330986                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 77556.330986                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 66a92381f64099bcfe0214e0f805d24a4f923195..d62c7aac61b69745881292027c97a866dc26dd8f 100644 (file)
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000019                       # Number of seconds simulated
-sim_ticks                                    18905500                       # Number of ticks simulated
-final_tick                                   18905500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    19079500                       # Number of ticks simulated
+final_tick                                   19079500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  44009                       # Simulator instruction rate (inst/s)
-host_op_rate                                    44004                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              143620144                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 227496                       # Number of bytes of host memory used
-host_seconds                                     0.13                       # Real time elapsed on the host
+host_inst_rate                                  82615                       # Simulator instruction rate (inst/s)
+host_op_rate                                    82599                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              272039638                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 262500                       # Number of bytes of host memory used
+host_seconds                                     0.07                       # Real time elapsed on the host
 sim_insts                                        5792                       # Number of instructions simulated
 sim_ops                                          5792                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total           22080                       # Nu
 system.physmem.num_reads::cpu.inst                345                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                101                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   446                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst           1167914099                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            341911084                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1509825183                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      1167914099                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         1167914099                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          1167914099                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           341911084                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1509825183                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst           1157263031                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            338792945                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1496055976                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      1157263031                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         1157263031                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          1157263031                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           338792945                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1496055976                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           446                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                         446                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        18777000                       # Total gap between requests
+system.physmem.totGap                        18951000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -154,55 +154,77 @@ system.physmem.wrQLenPdf::28                        0                       # Wh
 system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples           78                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      329.846154                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     165.491272                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     472.454851                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64                36     46.15%     46.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128                8     10.26%     56.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192                8     10.26%     66.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256                4      5.13%     71.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320                2      2.56%     74.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384                3      3.85%     78.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448                1      1.28%     79.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512                2      2.56%     82.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576                2      2.56%     84.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704                2      2.56%     87.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896                1      1.28%     88.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960                1      1.28%     89.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024               2      2.56%     92.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088               1      1.28%     93.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280               1      1.28%     94.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600               1      1.28%     96.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1920               1      1.28%     97.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112               2      2.56%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total             78                       # Bytes accessed per row activation
-system.physmem.totQLat                        3018500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  11958500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples           58                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      379.586207                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     226.841802                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     367.136049                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             17     29.31%     29.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           14     24.14%     53.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383            6     10.34%     63.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            3      5.17%     68.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            4      6.90%     75.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            2      3.45%     79.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            1      1.72%     81.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151           11     18.97%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total             58                       # Bytes accessed per row activation
+system.physmem.totQLat                        2851500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  11984000                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      2230000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                     6710000                       # Total ticks spent accessing banks
-system.physmem.avgQLat                        6767.94                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    15044.84                       # Average bank access latency per DRAM burst
+system.physmem.totBankLat                     6902500                       # Total ticks spent accessing banks
+system.physmem.avgQLat                        6393.50                       # Average queueing delay per DRAM burst
+system.physmem.avgBankLat                    15476.46                       # Average bank access latency per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  26812.78                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        1509.83                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  26869.96                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        1496.06                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     1509.83                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     1496.06                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                          11.80                       # Data bus utilization in percentage
-system.physmem.busUtilRead                      11.80                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                          11.69                       # Data bus utilization in percentage
+system.physmem.busUtilRead                      11.69                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         0.63                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.80                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                        368                       # Number of row buffer hits during reads
+system.physmem.readRowHits                        358                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.51                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   80.27                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        42100.90                       # Average gap between requests
-system.physmem.pageHitRate                      82.51                       # Row buffer hit rate, read and write combined
+system.physmem.avgGap                        42491.03                       # Average gap between requests
+system.physmem.pageHitRate                      80.27                       # Row buffer hit rate, read and write combined
 system.physmem.prechargeAllPercent               0.06                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                   1509825183                       # Throughput (bytes/s)
+system.membus.throughput                   1496055976                       # Throughput (bytes/s)
 system.membus.trans_dist::ReadReq                 399                       # Transaction distribution
 system.membus.trans_dist::ReadResp                399                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                47                       # Transaction distribution
@@ -213,19 +235,19 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
 system.membus.tot_pkt_size::total               28544                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.data_through_bus                  28544                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy              566000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy              567500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               3.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            4177750                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             22.1                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            4177500                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             21.9                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                    2238                       # Number of BP lookups
-system.cpu.branchPred.condPredicted              1804                       # Number of conditional branches predicted
+system.cpu.branchPred.lookups                    2235                       # Number of BP lookups
+system.cpu.branchPred.condPredicted              1802                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect               419                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups                 1851                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                     603                       # Number of BTB hits
+system.cpu.branchPred.BTBLookups                 1850                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                     602                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             32.576985                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                     199                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             32.540541                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                     198                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                 32                       # Number of incorrect RAS predictions.
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
@@ -246,84 +268,84 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                    9                       # Number of system calls
-system.cpu.numCycles                            37812                       # number of cpu cycles simulated
+system.cpu.numCycles                            38160                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles               7436                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          13161                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        2238                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches                802                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          2263                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.icacheStallCycles               7440                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          13154                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        2235                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches                800                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                          2260                       # Number of cycles fetch has run and was not squashing or blocked
 system.cpu.fetch.SquashCycles                    1291                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles                   1215                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.CacheLines                      1814                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   311                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              11776                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.117612                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.534017                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.BlockedCycles                   1225                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.CacheLines                      1810                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   309                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples              11787                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.115975                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.532873                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                     9513     80.78%     80.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                      178      1.51%     82.29% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      176      1.49%     83.79% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      142      1.21%     84.99% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      227      1.93%     86.92% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      133      1.13%     88.05% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      257      2.18%     90.23% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      110      0.93%     91.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     1040      8.83%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                     9527     80.83%     80.83% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                      176      1.49%     82.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      176      1.49%     83.81% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      142      1.20%     85.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      227      1.93%     86.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      132      1.12%     88.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      257      2.18%     90.24% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      110      0.93%     91.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                     1040      8.82%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                11776                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.059188                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.348064                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                     7513                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                  1376                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      2098                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                    80                       # Number of cycles decode is unblocking
+system.cpu.fetch.rateDist::total                11787                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.058569                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.344706                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                     7519                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                  1384                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      2094                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                    81                       # Number of cycles decode is unblocking
 system.cpu.decode.SquashCycles                    709                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved                  341                       # Number of times decode resolved a branch
+system.cpu.decode.BranchResolved                  340                       # Number of times decode resolved a branch
 system.cpu.decode.BranchMispred                   154                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts                  11726                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                   436                       # Number of squashed instructions handled by decode
+system.cpu.decode.DecodedInsts                  11724                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                   431                       # Number of squashed instructions handled by decode
 system.cpu.rename.SquashCycles                    709                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                     7699                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                     670                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles            446                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      1987                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                   265                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  11308                       # Number of instructions processed by rename
+system.cpu.rename.IdleCycles                     7704                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                     677                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles            445                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                      1984                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                   268                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                  11305                       # Number of instructions processed by rename
 system.cpu.rename.IQFullEvents                      4                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents                   226                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands                9701                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 18192                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            18166                       # Number of integer rename lookups
+system.cpu.rename.LSQFullEvents                   230                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands                9699                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 18187                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            18161                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups                26                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps                  4998                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                     4703                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps                     4701                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts                 27                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts             27                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                       575                       # count of insts added to the skid buffer
+system.cpu.rename.skidInsts                       582                       # count of insts added to the skid buffer
 system.cpu.memDep0.insertedLoads                 2023                       # Number of loads inserted to the mem dependence unit.
 system.cpu.memDep0.insertedStores                1831                       # Number of stores inserted to the mem dependence unit.
 system.cpu.memDep0.conflictingLoads                52                       # Number of conflicting loads.
 system.cpu.memDep0.conflictingStores               33                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                      10305                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsAdded                      10303                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqNonSpecInstsAdded                  57                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                      8904                       # Number of instructions issued
+system.cpu.iq.iqInstsIssued                      8901                       # Number of instructions issued
 system.cpu.iq.iqSquashedInstsIssued               241                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined            4244                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined         3486                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedInstsExamined            4242                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined         3488                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved             41                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         11776                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.756114                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.487258                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples         11787                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.755154                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.486388                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0                8416     71.47%     71.47% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                1098      9.32%     80.79% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                 789      6.70%     87.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 501      4.25%     91.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 456      3.87%     95.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0                8427     71.49%     71.49% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                1098      9.32%     80.81% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                 791      6.71%     87.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 500      4.24%     91.76% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 455      3.86%     95.62% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::5                 306      2.60%     98.22% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                 132      1.12%     99.34% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                  45      0.38%     99.72% # Number of insts issued each cycle
@@ -331,7 +353,7 @@ system.cpu.iq.issued_per_cycle::8                  33      0.28%    100.00% # Nu
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           11776                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           11787                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntAlu                       8      4.62%      4.62% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                      0      0.00%      4.62% # attempts to use FU when none available
@@ -367,50 +389,50 @@ system.cpu.iq.fu_full::MemWrite                    92     53.18%    100.00% # at
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                  5478     61.52%     61.52% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                  5476     61.52%     61.52% # Type of FU issued
 system.cpu.iq.FU_type_0::IntMult                    0      0.00%     61.52% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     61.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     61.55% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     61.55% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     61.55% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     61.55% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     61.55% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     61.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     61.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     61.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     61.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     61.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     61.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     61.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     61.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     61.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     61.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     61.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     61.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     61.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     61.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     61.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     61.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     61.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     61.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     61.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     61.55% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     61.55% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 1796     20.17%     81.72% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                1628     18.28%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     61.54% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     61.54% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     61.54% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     61.54% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     61.54% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     61.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     61.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     61.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     61.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     61.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     61.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     61.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     61.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     61.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     61.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     61.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     61.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     61.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     61.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     61.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     61.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     61.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     61.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     61.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     61.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     61.54% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 1796     20.18%     81.72% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1627     18.28%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                   8904                       # Type of FU issued
-system.cpu.iq.rate                           0.235481                       # Inst issue rate
+system.cpu.iq.FU_type_0::total                   8901                       # Type of FU issued
+system.cpu.iq.rate                           0.233255                       # Inst issue rate
 system.cpu.iq.fu_busy_cnt                         173                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.019429                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              29936                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             14577                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses         8131                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fu_busy_rate                   0.019436                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              29941                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             14573                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses         8128                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                  62                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                 36                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses           27                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                   9043                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                   9040                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                      34                       # Number of floating point alu accesses
 system.cpu.iew.lsq.thread0.forwLoads               66                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
@@ -426,7 +448,7 @@ system.cpu.iew.iewIdleCycles                        0                       # Nu
 system.cpu.iew.iewSquashCycles                    709                       # Number of cycles IEW is squashing
 system.cpu.iew.iewBlockCycles                     457                       # Number of cycles IEW is blocking
 system.cpu.iew.iewUnblockCycles                    22                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               10362                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispatchedInsts               10360                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                55                       # Number of squashed instructions skipped by dispatch
 system.cpu.iew.iewDispLoadInsts                  2023                       # Number of dispatched load instructions
 system.cpu.iew.iewDispStoreInsts                 1831                       # Number of dispatched store instructions
@@ -437,43 +459,43 @@ system.cpu.iew.memOrderViolationEvents              7                       # Nu
 system.cpu.iew.predictedTakenIncorrect             66                       # Number of branches that were predicted taken incorrectly
 system.cpu.iew.predictedNotTakenIncorrect          262                       # Number of branches that were predicted not taken incorrectly
 system.cpu.iew.branchMispredicts                  328                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                  8503                       # Number of executed instructions
+system.cpu.iew.iewExecutedInsts                  8500                       # Number of executed instructions
 system.cpu.iew.iewExecLoadInsts                  1678                       # Number of load instructions executed
 system.cpu.iew.iewExecSquashedInsts               401                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                         3202                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                     1351                       # Number of branches executed
-system.cpu.iew.exec_stores                       1524                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.224876                       # Inst execution rate
-system.cpu.iew.wb_sent                           8273                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                          8158                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                      4220                       # num instructions producing a value
-system.cpu.iew.wb_consumers                      6682                       # num instructions consuming a value
+system.cpu.iew.exec_refs                         3201                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                     1350                       # Number of branches executed
+system.cpu.iew.exec_stores                       1523                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.222746                       # Inst execution rate
+system.cpu.iew.wb_sent                           8270                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                          8155                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                      4217                       # num instructions producing a value
+system.cpu.iew.wb_consumers                      6678                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.215752                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.631547                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.213705                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.631476                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts            4576                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts            4574                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              16                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts               266                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        11067                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.523358                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.324283                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples        11078                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.522838                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.323591                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0         8688     78.50%     78.50% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1         1007      9.10%     87.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          608      5.49%     93.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          271      2.45%     95.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          170      1.54%     97.08% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5          108      0.98%     98.06% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0         8698     78.52%     78.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1         1008      9.10%     87.62% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          609      5.50%     93.11% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          270      2.44%     95.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          170      1.53%     97.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5          108      0.97%     98.06% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::6           70      0.63%     98.69% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::7           44      0.40%     99.09% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::8          101      0.91%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        11067                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        11078                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts                 5792                       # Number of instructions committed
 system.cpu.commit.committedOps                   5792                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -486,22 +508,22 @@ system.cpu.commit.int_insts                      5698                       # Nu
 system.cpu.commit.function_calls                  103                       # Number of function calls committed.
 system.cpu.commit.bw_lim_events                   101                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                        21334                       # The number of ROB reads
-system.cpu.rob.rob_writes                       21446                       # The number of ROB writes
-system.cpu.timesIdled                             245                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           26036                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                        21343                       # The number of ROB reads
+system.cpu.rob.rob_writes                       21442                       # The number of ROB writes
+system.cpu.timesIdled                             246                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           26373                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        5792                       # Number of Instructions Simulated
 system.cpu.committedOps                          5792                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total                  5792                       # Number of Instructions Simulated
-system.cpu.cpi                               6.528315                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         6.528315                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.153179                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.153179                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    13476                       # number of integer regfile reads
-system.cpu.int_regfile_writes                    7049                       # number of integer regfile writes
+system.cpu.cpi                               6.588398                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         6.588398                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.151782                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.151782                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                    13470                       # number of integer regfile reads
+system.cpu.int_regfile_writes                    7047                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        25                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                        2                       # number of floating regfile writes
-system.cpu.toL2Bus.throughput              1533521991                       # Throughput (bytes/s)
+system.cpu.toL2Bus.throughput              1519536675                       # Throughput (bytes/s)
 system.cpu.toL2Bus.trans_dist::ReadReq            406                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp           406                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           47                       # Transaction distribution
@@ -516,111 +538,111 @@ system.cpu.toL2Bus.data_through_bus             28992                       # To
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
 system.cpu.toL2Bus.reqLayer0.occupancy         226500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        587000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy        585250                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          3.1                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy        161250                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.9                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.utilization          0.8                       # Layer utilization (%)
 system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse           169.362417                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                1372                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           168.852168                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                1369                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               351                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              3.908832                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs              3.900285                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   169.362417                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.082696                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.082696                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   168.852168                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.082447                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.082447                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          351                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0          196                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          155                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.171387                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses              3979                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses             3979                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst         1372                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            1372                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          1372                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             1372                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         1372                       # number of overall hits
-system.cpu.icache.overall_hits::total            1372                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          442                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           442                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          442                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            442                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          442                       # number of overall misses
-system.cpu.icache.overall_misses::total           442                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     30183750                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     30183750                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     30183750                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     30183750                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     30183750                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     30183750                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         1814                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         1814                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         1814                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         1814                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         1814                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         1814                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.243660                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.243660                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.243660                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.243660                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.243660                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.243660                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68289.027149                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 68289.027149                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 68289.027149                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 68289.027149                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 68289.027149                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 68289.027149                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          433                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses              3971                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses             3971                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst         1369                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            1369                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          1369                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             1369                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         1369                       # number of overall hits
+system.cpu.icache.overall_hits::total            1369                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          441                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           441                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          441                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            441                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          441                       # number of overall misses
+system.cpu.icache.overall_misses::total           441                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     30135000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     30135000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     30135000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     30135000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     30135000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     30135000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         1810                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         1810                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         1810                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         1810                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         1810                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         1810                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.243646                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.243646                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.243646                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.243646                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.243646                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.243646                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68333.333333                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 68333.333333                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 68333.333333                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 68333.333333                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 68333.333333                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 68333.333333                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          460                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 6                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    72.166667                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    76.666667                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst           91                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total           91                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst           91                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total           91                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst           91                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total           91                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst           90                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total           90                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst           90                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total           90                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst           90                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total           90                       # number of overall MSHR hits
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          351                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total          351                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst          351                       # number of demand (read+write) MSHR misses
 system.cpu.icache.demand_mshr_misses::total          351                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          351                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          351                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     24475000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     24475000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     24475000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     24475000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     24475000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     24475000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.193495                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.193495                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.193495                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.193495                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.193495                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.193495                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69729.344729                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69729.344729                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69729.344729                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 69729.344729                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69729.344729                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 69729.344729                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     24444750                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     24444750                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     24444750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     24444750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     24444750                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     24444750                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.193923                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.193923                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.193923                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.193923                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.193923                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.193923                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69643.162393                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69643.162393                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69643.162393                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 69643.162393                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69643.162393                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 69643.162393                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          199.747174                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          199.197303                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  7                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              399                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.017544                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   168.225208                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    31.521966                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005134                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.000962                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.006096                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   167.717049                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    31.480255                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005118                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.000961                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.006079                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          399                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          216                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          183                       # Occupied blocks per task id
@@ -647,17 +669,17 @@ system.cpu.l2cache.demand_misses::total           446                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          345                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          101                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          446                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     24063500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     24033250                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadReq_miss_latency::cpu.data      4074500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     28138000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      3590250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      3590250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     24063500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data      7664750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     31728250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     24063500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data      7664750                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     31728250                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     28107750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      3621750                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      3621750                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     24033250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      7696250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     31729500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     24033250                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      7696250                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     31729500                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst          351                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data           55                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total          406                       # number of ReadReq accesses(hits+misses)
@@ -680,17 +702,17 @@ system.cpu.l2cache.demand_miss_rate::total     0.984547                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.982906                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.990196                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.984547                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69749.275362                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69661.594203                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75453.703704                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 70521.303258                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76388.297872                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76388.297872                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69749.275362                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75888.613861                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 71139.573991                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69749.275362                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75888.613861                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 71139.573991                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 70445.488722                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77058.510638                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77058.510638                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69661.594203                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76200.495050                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 71142.376682                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69661.594203                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76200.495050                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 71142.376682                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -710,17 +732,17 @@ system.cpu.l2cache.demand_mshr_misses::total          446
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          345                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          101                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          446                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     19720000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     19691750                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      3410500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     23130500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      3013250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      3013250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     19720000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      6423750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     26143750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     19720000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      6423750                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     26143750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     23102250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      3044750                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      3044750                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     19691750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      6455250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     26147000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     19691750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      6455250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     26147000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.982906                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.981818                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.982759                       # mshr miss rate for ReadReq accesses
@@ -732,27 +754,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.984547
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.982906                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.990196                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.984547                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57159.420290                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57077.536232                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63157.407407                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57971.177945                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64111.702128                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64111.702128                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57159.420290                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63601.485149                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58618.273543                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57159.420290                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63601.485149                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58618.273543                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57900.375940                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64781.914894                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64781.914894                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57077.536232                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63913.366337                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58625.560538                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57077.536232                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63913.366337                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58625.560538                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            63.784946                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse            63.689105                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs                2188                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               102                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs             21.450980                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    63.784946                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.015572                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.015572                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data    63.689105                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.015549                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.015549                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          102                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           37                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           65                       # Occupied blocks per task id
@@ -775,14 +797,14 @@ system.cpu.dcache.demand_misses::cpu.data          435                       # n
 system.cpu.dcache.demand_misses::total            435                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data          435                       # number of overall misses
 system.cpu.dcache.overall_misses::total           435                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      7365250                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      7365250                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     19851746                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     19851746                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     27216996                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     27216996                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     27216996                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     27216996                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      7364750                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      7364750                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     20363246                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     20363246                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     27727996                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     27727996                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     27727996                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     27727996                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data         1577                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total         1577                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data         1046                       # number of WriteReq accesses(hits+misses)
@@ -799,14 +821,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.165841
 system.cpu.dcache.demand_miss_rate::total     0.165841                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.165841                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.165841                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70819.711538                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 70819.711538                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59975.063444                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 59975.063444                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 62567.806897                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 62567.806897                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 62567.806897                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 62567.806897                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70814.903846                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 70814.903846                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61520.380665                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 61520.380665                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 63742.519540                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 63742.519540                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 63742.519540                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 63742.519540                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs          501                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 5                       # number of cycles access was blocked
@@ -833,12 +855,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.data          102
 system.cpu.dcache.overall_mshr_misses::total          102                       # number of overall MSHR misses
 system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4140000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_latency::total      4140000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      3640248                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      3640248                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      7780248                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      7780248                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      7780248                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      7780248                       # number of overall MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      3671748                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      3671748                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      7811748                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      7811748                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      7811748                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      7811748                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.034876                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.034876                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.044933                       # mshr miss rate for WriteReq accesses
@@ -849,12 +871,12 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.038887
 system.cpu.dcache.overall_mshr_miss_rate::total     0.038887                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75272.727273                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75272.727273                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77452.085106                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77452.085106                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76276.941176                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 76276.941176                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76276.941176                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 76276.941176                       # average overall mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78122.297872                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78122.297872                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76585.764706                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 76585.764706                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76585.764706                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 76585.764706                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 005c2194964702a4c08c78ce0669908d1c7f86ec..ca26bca81b15d533b111762a185a6fd1bcdb665a 100644 (file)
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000021                       # Number of seconds simulated
-sim_ticks                                    20892500                       # Number of ticks simulated
-final_tick                                   20892500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    20970500                       # Number of ticks simulated
+final_tick                                   20970500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  24019                       # Simulator instruction rate (inst/s)
-host_op_rate                                    24017                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               94189663                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 236900                       # Number of bytes of host memory used
-host_seconds                                     0.22                       # Real time elapsed on the host
+host_inst_rate                                  71497                       # Simulator instruction rate (inst/s)
+host_op_rate                                    71482                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              281347268                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 269780                       # Number of bytes of host memory used
+host_seconds                                     0.07                       # Real time elapsed on the host
 sim_insts                                        5327                       # Number of instructions simulated
 sim_ops                                          5327                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total           18496                       # Nu
 system.physmem.num_reads::cpu.inst                289                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                134                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   423                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            885293766                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            410482230                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1295775996                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       885293766                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          885293766                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           885293766                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           410482230                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1295775996                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            882000906                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            408955437                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1290956343                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       882000906                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          882000906                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           882000906                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           408955437                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1290956343                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           423                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                         423                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        20823000                       # Total gap between requests
+system.physmem.totGap                        20901000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -91,9 +91,9 @@ system.physmem.writePktSize::4                      0                       # Wr
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
 system.physmem.rdQLenPdf::0                       251                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       132                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        29                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                         8                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       129                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        31                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                         9                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
@@ -154,53 +154,76 @@ system.physmem.wrQLenPdf::28                        0                       # Wh
 system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples           80                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      298.400000                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     178.623207                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     338.187934                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64                31     38.75%     38.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128               11     13.75%     52.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192                4      5.00%     57.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256                6      7.50%     65.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320                1      1.25%     66.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384                6      7.50%     73.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448                4      5.00%     78.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512                3      3.75%     82.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576                6      7.50%     90.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640                2      2.50%     92.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704                1      1.25%     93.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024               1      1.25%     95.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280               1      1.25%     96.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344               1      1.25%     97.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472               1      1.25%     98.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664               1      1.25%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total             80                       # Bytes accessed per row activation
-system.physmem.totQLat                        3229250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  11834250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples           48                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      337.333333                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     221.579222                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     300.401245                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             13     27.08%     27.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255            9     18.75%     45.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383            6     12.50%     58.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            7     14.58%     72.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            6     12.50%     85.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            2      4.17%     89.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151            5     10.42%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total             48                       # Bytes accessed per row activation
+system.physmem.totQLat                        3113750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  11732500                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      2115000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                     6490000                       # Total ticks spent accessing banks
-system.physmem.avgQLat                        7634.16                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    15342.79                       # Average bank access latency per DRAM burst
+system.physmem.totBankLat                     6503750                       # Total ticks spent accessing banks
+system.physmem.avgQLat                        7361.11                       # Average queueing delay per DRAM burst
+system.physmem.avgBankLat                    15375.30                       # Average bank access latency per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  27976.95                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        1295.78                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  27736.41                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        1290.96                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     1295.78                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     1290.96                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                          10.12                       # Data bus utilization in percentage
-system.physmem.busUtilRead                      10.12                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                          10.09                       # Data bus utilization in percentage
+system.physmem.busUtilRead                      10.09                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         0.57                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.66                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                        343                       # Number of row buffer hits during reads
+system.physmem.readRowHits                        339                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   81.09                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   80.14                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        49226.95                       # Average gap between requests
-system.physmem.pageHitRate                      81.09                       # Row buffer hit rate, read and write combined
+system.physmem.avgGap                        49411.35                       # Average gap between requests
+system.physmem.pageHitRate                      80.14                       # Row buffer hit rate, read and write combined
 system.physmem.prechargeAllPercent               0.06                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                   1295775996                       # Throughput (bytes/s)
+system.membus.throughput                   1290956343                       # Throughput (bytes/s)
 system.membus.trans_dist::ReadReq                 342                       # Transaction distribution
 system.membus.trans_dist::ReadResp                342                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                81                       # Transaction distribution
@@ -211,10 +234,10 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
 system.membus.tot_pkt_size::total               27072                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.data_through_bus                  27072                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy              502000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy              501500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               2.4                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            3930250                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             18.8                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            3929500                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             18.7                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                    1636                       # Number of BP lookups
 system.cpu.branchPred.condPredicted              1090                       # Number of conditional branches predicted
@@ -226,7 +249,7 @@ system.cpu.branchPred.BTBHitPct             43.484736                       # BT
 system.cpu.branchPred.usedRAS                      67                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                  4                       # Number of incorrect RAS predictions.
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
-system.cpu.numCycles                            41786                       # number of cpu cycles simulated
+system.cpu.numCycles                            41942                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.branch_predictor.predictedTaken          651                       # Number of Branches Predicted As Taken (True).
@@ -248,12 +271,12 @@ system.cpu.execution_unit.executions             3957                       # Nu
 system.cpu.mult_div_unit.multiplies                 0                       # Number of Multipy Operations Executed
 system.cpu.mult_div_unit.divides                    0                       # Number of Divide Operations Executed
 system.cpu.contextSwitches                          1                       # Number of context switches
-system.cpu.threadCycles                          9664                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles                          9659                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
 system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled                             428                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           35541                       # Number of cycles cpu's stages were not processed
-system.cpu.runCycles                             6245                       # Number of cycles cpu stages are processed.
-system.cpu.activity                         14.945197                       # Percentage of cycles cpu is active
+system.cpu.timesIdled                             424                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           35694                       # Number of cycles cpu's stages were not processed
+system.cpu.runCycles                             6248                       # Number of cycles cpu stages are processed.
+system.cpu.activity                         14.896762                       # Percentage of cycles cpu is active
 system.cpu.comLoads                               715                       # Number of Load instructions committed
 system.cpu.comStores                              673                       # Number of Store instructions committed
 system.cpu.comBranches                           1115                       # Number of Branches instructions committed
@@ -265,39 +288,39 @@ system.cpu.committedInsts                        5327                       # Nu
 system.cpu.committedOps                          5327                       # Number of Ops committed (Per-Thread)
 system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
 system.cpu.committedInsts_total                  5327                       # Number of Instructions committed (Total)
-system.cpu.cpi                               7.844190                       # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi                               7.873475                       # CPI: Cycles Per Instruction (Per-Thread)
 system.cpu.smt_cpi                                nan                       # CPI: Total SMT-CPI
-system.cpu.cpi_total                         7.844190                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.127483                       # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.cpi_total                         7.873475                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.127009                       # IPC: Instructions Per Cycle (Per-Thread)
 system.cpu.smt_ipc                                nan                       # IPC: Total SMT-IPC
-system.cpu.ipc_total                         0.127483                       # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles                    37146                       # Number of cycles 0 instructions are processed.
+system.cpu.ipc_total                         0.127009                       # IPC: Total IPC of All Threads
+system.cpu.stage0.idleCycles                    37302                       # Number of cycles 0 instructions are processed.
 system.cpu.stage0.runCycles                      4640                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization               11.104198                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles                    38591                       # Number of cycles 0 instructions are processed.
-system.cpu.stage1.runCycles                      3195                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization                7.646102                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles                    38753                       # Number of cycles 0 instructions are processed.
-system.cpu.stage2.runCycles                      3033                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization                7.258412                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage3.idleCycles                    40811                       # Number of cycles 0 instructions are processed.
-system.cpu.stage3.runCycles                       975                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage3.utilization                2.333317                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles                    38629                       # Number of cycles 0 instructions are processed.
+system.cpu.stage0.utilization               11.062896                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles                    38748                       # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles                      3194                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization                7.615278                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles                    38908                       # Number of cycles 0 instructions are processed.
+system.cpu.stage2.runCycles                      3034                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage2.utilization                7.233799                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles                    40966                       # Number of cycles 0 instructions are processed.
+system.cpu.stage3.runCycles                       976                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage3.utilization                2.327023                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles                    38785                       # Number of cycles 0 instructions are processed.
 system.cpu.stage4.runCycles                      3157                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization                7.555162                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.utilization                7.527061                       # Percentage of cycles stage was utilized (processing insts).
 system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse           142.907558                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse           142.644710                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                 892                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               291                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs              3.065292                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   142.907558                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.069779                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.069779                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   142.644710                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.069651                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.069651                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          291                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          143                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          148                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          144                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          147                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.142090                       # Percentage of cache occupancy per task id
 system.cpu.icache.tags.tag_accesses              2807                       # Number of tag accesses
 system.cpu.icache.tags.data_accesses             2807                       # Number of data accesses
@@ -313,12 +336,12 @@ system.cpu.icache.demand_misses::cpu.inst          366                       # n
 system.cpu.icache.demand_misses::total            366                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          366                       # number of overall misses
 system.cpu.icache.overall_misses::total           366                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     25613500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     25613500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     25613500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     25613500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     25613500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     25613500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     25482750                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     25482750                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     25482750                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     25482750                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     25482750                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     25482750                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst         1258                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total         1258                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst         1258                       # number of demand (read+write) accesses
@@ -331,12 +354,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.290938
 system.cpu.icache.demand_miss_rate::total     0.290938                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.290938                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.290938                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69982.240437                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 69982.240437                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 69982.240437                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 69982.240437                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 69982.240437                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 69982.240437                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst        69625                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total        69625                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst        69625                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total        69625                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst        69625                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total        69625                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -357,26 +380,26 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          291
 system.cpu.icache.demand_mshr_misses::total          291                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          291                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          291                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     20868000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     20868000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     20868000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     20868000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     20868000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     20868000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     20711750                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     20711750                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     20711750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     20711750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     20711750                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     20711750                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.231320                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.231320                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.231320                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.231320                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.231320                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.231320                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71711.340206                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71711.340206                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71711.340206                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 71711.340206                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71711.340206                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 71711.340206                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71174.398625                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71174.398625                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71174.398625                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 71174.398625                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71174.398625                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 71174.398625                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput              1304965897                       # Throughput (bytes/s)
+system.cpu.toL2Bus.throughput              1300112062                       # Throughput (bytes/s)
 system.cpu.toL2Bus.trans_dist::ReadReq            345                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp           345                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           81                       # Transaction distribution
@@ -391,21 +414,21 @@ system.cpu.toL2Bus.data_through_bus             27264                       # To
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
 system.cpu.toL2Bus.reqLayer0.occupancy         213000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        486500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy        485750                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          2.3                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        217250                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy        216250                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.0                       # Layer utilization (%)
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          169.400750                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          169.087834                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  3                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              342                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.008772                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   142.324573                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    27.076177                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004343                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.000826                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.005170                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   142.075458                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    27.012376                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004336                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.000824                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.005160                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          342                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          171                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          171                       # Occupied blocks per task id
@@ -432,17 +455,17 @@ system.cpu.l2cache.demand_misses::total           423                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          289                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          134                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          423                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     20549500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      3769000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     24318500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      6227750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      6227750                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     20549500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data      9996750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     30546250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     20549500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data      9996750                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     30546250                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     20393250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      4031000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     24424250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      6031750                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      6031750                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     20393250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data     10062750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     30456000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     20393250                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data     10062750                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     30456000                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst          291                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data           54                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total          345                       # number of ReadReq accesses(hits+misses)
@@ -465,17 +488,17 @@ system.cpu.l2cache.demand_miss_rate::total     0.992958                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.993127                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.992593                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.992958                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71105.536332                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71113.207547                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 71106.725146                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76885.802469                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76885.802469                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71105.536332                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74602.611940                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 72213.356974                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71105.536332                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74602.611940                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 72213.356974                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70564.878893                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76056.603774                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 71415.935673                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74466.049383                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74466.049383                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70564.878893                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75095.149254                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total        72000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70564.878893                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75095.149254                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total        72000                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -495,17 +518,17 @@ system.cpu.l2cache.demand_mshr_misses::total          423
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          289                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          134                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          423                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     16936000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      3114000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     20050000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      5232250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      5232250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     16936000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      8346250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     25282250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     16936000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      8346250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     25282250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     16781250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      3376000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     20157250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      5037250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      5037250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     16781250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      8413250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     25194500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     16781250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      8413250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     25194500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.993127                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.981481                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.991304                       # mshr miss rate for ReadReq accesses
@@ -517,27 +540,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.992958
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.993127                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.992593                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.992958                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58602.076125                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58754.716981                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58625.730994                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64595.679012                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64595.679012                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58602.076125                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62285.447761                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59768.912530                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58602.076125                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62285.447761                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59768.912530                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58066.608997                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63698.113208                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58939.327485                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62188.271605                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62188.271605                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58066.608997                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62785.447761                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59561.465721                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58066.608997                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62785.447761                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59561.465721                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            85.407936                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse            85.369033                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs                 914                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               135                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs              6.770370                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    85.407936                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.020852                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.020852                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data    85.369033                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.020842                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.020842                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          135                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           38                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           97                       # Occupied blocks per task id
@@ -560,14 +583,14 @@ system.cpu.dcache.demand_misses::cpu.data          474                       # n
 system.cpu.dcache.demand_misses::total            474                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data          474                       # number of overall misses
 system.cpu.dcache.overall_misses::total           474                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      4332750                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      4332750                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     29231250                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     29231250                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     33564000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     33564000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     33564000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     33564000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      4594750                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      4594750                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     29091500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     29091500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     33686250                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     33686250                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     33686250                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     33686250                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data          715                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total          715                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          673                       # number of WriteReq accesses(hits+misses)
@@ -584,19 +607,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.341499
 system.cpu.dcache.demand_miss_rate::total     0.341499                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.341499                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.341499                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71028.688525                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 71028.688525                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70777.845036                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 70777.845036                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 70810.126582                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 70810.126582                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 70810.126582                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 70810.126582                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs          792                       # number of cycles access was blocked
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75323.770492                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 75323.770492                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70439.467312                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 70439.467312                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 71068.037975                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 71068.037975                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 71068.037975                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 71068.037975                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs          818                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                31                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    25.548387                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    26.387097                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
@@ -616,14 +639,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          135
 system.cpu.dcache.demand_mshr_misses::total          135                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          135                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          135                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      3835500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      3835500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      6311250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      6311250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     10146750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     10146750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     10146750                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     10146750                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4097500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      4097500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      6115250                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      6115250                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     10212750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     10212750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     10212750                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     10212750                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.075524                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.075524                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.120357                       # mshr miss rate for WriteReq accesses
@@ -632,14 +655,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.097262
 system.cpu.dcache.demand_mshr_miss_rate::total     0.097262                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.097262                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.097262                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71027.777778                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71027.777778                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77916.666667                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77916.666667                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75161.111111                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 75161.111111                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75161.111111                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 75161.111111                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75879.629630                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75879.629630                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75496.913580                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75496.913580                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        75650                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total        75650                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        75650                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total        75650                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index d0b8bca455bede8f0ee83518a35bc3d5eab70c6c..33851c6e5c932b2c3786d86af45242b4496ccca6 100644 (file)
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000020                       # Number of seconds simulated
-sim_ticks                                    19970500                       # Number of ticks simulated
-final_tick                                   19970500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    20069500                       # Number of ticks simulated
+final_tick                                   20069500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                   4162                       # Simulator instruction rate (inst/s)
-host_op_rate                                     7540                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               15448311                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 248568                       # Number of bytes of host memory used
-host_seconds                                     1.29                       # Real time elapsed on the host
+host_inst_rate                                  42536                       # Simulator instruction rate (inst/s)
+host_op_rate                                    77054                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              158640887                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 283320                       # Number of bytes of host memory used
+host_seconds                                     0.13                       # Real time elapsed on the host
 sim_insts                                        5380                       # Number of instructions simulated
 sim_ops                                          9747                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total           17472                       # Nu
 system.physmem.num_reads::cpu.inst                273                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                141                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   414                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            874890463                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            451866503                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1326756967                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       874890463                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          874890463                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           874890463                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           451866503                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1326756967                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            870574753                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            449637510                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1320212262                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       870574753                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          870574753                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           870574753                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           449637510                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1320212262                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           415                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                         415                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        19922000                       # Total gap between requests
+system.physmem.totGap                        20021000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -154,50 +154,76 @@ system.physmem.wrQLenPdf::28                        0                       # Wh
 system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          103                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      226.174757                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     137.685606                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     319.474459                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64                47     45.63%     45.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128               17     16.50%     62.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192               14     13.59%     75.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256                5      4.85%     80.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320                5      4.85%     85.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384                3      2.91%     88.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640                4      3.88%     92.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704                2      1.94%     94.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896                1      0.97%     95.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960                2      1.94%     97.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024               1      0.97%     98.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216               1      0.97%     99.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2368               1      0.97%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            103                       # Bytes accessed per row activation
-system.physmem.totQLat                        2039250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  11731750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples           71                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      240.676056                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     152.837127                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     281.987222                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             26     36.62%     36.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           26     36.62%     73.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383            8     11.27%     84.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            2      2.82%     87.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            2      2.82%     90.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            2      2.82%     92.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151            5      7.04%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total             71                       # Bytes accessed per row activation
+system.physmem.totQLat                        2360500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  12135500                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      2075000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                     7617500                       # Total ticks spent accessing banks
-system.physmem.avgQLat                        4913.86                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    18355.42                       # Average bank access latency per DRAM burst
+system.physmem.totBankLat                     7700000                       # Total ticks spent accessing banks
+system.physmem.avgQLat                        5687.95                       # Average queueing delay per DRAM burst
+system.physmem.avgBankLat                    18554.22                       # Average bank access latency per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  28269.28                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        1329.96                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  29242.17                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        1323.40                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     1329.96                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     1323.40                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                          10.39                       # Data bus utilization in percentage
-system.physmem.busUtilRead                      10.39                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                          10.34                       # Data bus utilization in percentage
+system.physmem.busUtilRead                      10.34                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         0.59                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.61                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                        312                       # Number of row buffer hits during reads
+system.physmem.readRowHits                        307                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   75.18                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   73.98                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        48004.82                       # Average gap between requests
-system.physmem.pageHitRate                      75.18                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               0.06                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                   1326756967                       # Throughput (bytes/s)
+system.physmem.avgGap                        48243.37                       # Average gap between requests
+system.physmem.pageHitRate                      73.98                       # Row buffer hit rate, read and write combined
+system.physmem.prechargeAllPercent               0.05                       # Percentage of time for which DRAM has all the banks in precharge state
+system.membus.throughput                   1320212262                       # Throughput (bytes/s)
 system.membus.trans_dist::ReadReq                 338                       # Transaction distribution
 system.membus.trans_dist::ReadResp                337                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                77                       # Transaction distribution
@@ -212,8 +238,8 @@ system.membus.data_through_bus                  26496                       # To
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
 system.membus.reqLayer0.occupancy              500500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               2.5                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            3871500                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             19.4                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            3871750                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             19.3                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                    3084                       # Number of BP lookups
 system.cpu.branchPred.condPredicted              3084                       # Number of conditional branches predicted
@@ -226,49 +252,49 @@ system.cpu.branchPred.usedRAS                     207                       # Nu
 system.cpu.branchPred.RASInCorrect                 74                       # Number of incorrect RAS predictions.
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
-system.cpu.numCycles                            39942                       # number of cpu cycles simulated
+system.cpu.numCycles                            40140                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles              10287                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.icacheStallCycles              10289                       # Number of cycles fetch is stalled on an Icache miss
 system.cpu.fetch.Insts                          14134                       # Number of instructions fetch has processed
 system.cpu.fetch.Branches                        3084                       # Number of branches that fetch encountered
 system.cpu.fetch.predictedBranches                933                       # Number of branches that fetch has predicted taken
 system.cpu.fetch.Cycles                          3940                       # Number of cycles fetch has run and was not squashing or blocked
 system.cpu.fetch.SquashCycles                    2474                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles                   5300                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.BlockedCycles                   5352                       # Number of cycles fetch has spent blocked
 system.cpu.fetch.MiscStallCycles                   58                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingTrapStallCycles           392                       # Number of stall cycles due to pending traps
 system.cpu.fetch.IcacheWaitRetryStallCycles           11                       # Number of stall cycles due to full MSHR
 system.cpu.fetch.CacheLines                      1980                       # Number of cache lines fetched
 system.cpu.fetch.IcacheSquashes                   267                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              21845                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.153353                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.669079                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples              21899                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.150509                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.666400                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                    18006     82.43%     82.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                      216      0.99%     83.41% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      142      0.65%     84.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      224      1.03%     85.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      181      0.83%     85.92% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      200      0.92%     86.83% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      275      1.26%     88.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      159      0.73%     88.82% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     2442     11.18%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                    18060     82.47%     82.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                      216      0.99%     83.46% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      142      0.65%     84.10% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      224      1.02%     85.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      181      0.83%     85.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      200      0.91%     86.87% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      275      1.26%     88.12% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      159      0.73%     88.85% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                     2442     11.15%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                21845                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.077212                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.353863                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                    11079                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                  5195                       # Number of cycles decode is blocked
+system.cpu.fetch.rateDist::total                21899                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.076831                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.352118                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                    11081                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                  5247                       # Number of cycles decode is blocked
 system.cpu.decode.RunCycles                      3583                       # Number of cycles decode is running
 system.cpu.decode.UnblockCycles                   131                       # Number of cycles decode is unblocking
 system.cpu.decode.SquashCycles                   1857                       # Number of cycles decode is squashing
 system.cpu.decode.DecodedInsts                  24173                       # Number of instructions handled by decode
 system.cpu.rename.SquashCycles                   1857                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                    11444                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                    3834                       # Number of cycles rename is blocking
+system.cpu.rename.IdleCycles                    11446                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                    3886                       # Number of cycles rename is blocking
 system.cpu.rename.serializeStallCycles            603                       # count of cycles rename stalled for serializing inst
 system.cpu.rename.RunCycles                      3331                       # Number of cycles rename is running
 system.cpu.rename.UnblockCycles                   776                       # Number of cycles rename is unblocking
@@ -296,23 +322,23 @@ system.cpu.iq.iqSquashedInstsIssued               290                       # Nu
 system.cpu.iq.iqSquashedInstsExamined            9729                       # Number of squashed instructions iterated over during squash; mainly for profiling
 system.cpu.iq.iqSquashedOperandsExamined        13960                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved             14                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         21845                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.779446                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.654421                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples         21899                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.777524                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.652832                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0               16359     74.89%     74.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                1539      7.05%     81.93% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                1092      5.00%     86.93% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 724      3.31%     90.24% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 698      3.20%     93.44% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 576      2.64%     96.08% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 581      2.66%     98.74% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0               16413     74.95%     74.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                1539      7.03%     81.98% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                1092      4.99%     86.96% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 724      3.31%     90.27% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 698      3.19%     93.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 576      2.63%     96.09% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 581      2.65%     98.74% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                 234      1.07%     99.81% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                  42      0.19%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           21845                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           21899                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntAlu                     140     77.35%     77.35% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                      0      0.00%     77.35% # attempts to use FU when none available
@@ -382,10 +408,10 @@ system.cpu.iq.FU_type_0::MemWrite                1373      8.06%    100.00% # Ty
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::total                  17027                       # Type of FU issued
-system.cpu.iq.rate                           0.426293                       # Inst issue rate
+system.cpu.iq.rate                           0.424190                       # Inst issue rate
 system.cpu.iq.fu_busy_cnt                         181                       # FU busy when requested
 system.cpu.iq.fu_busy_rate                   0.010630                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              56362                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_reads              56416                       # Number of integer instruction queue reads
 system.cpu.iq.int_inst_queue_writes             29998                       # Number of integer instruction queue writes
 system.cpu.iq.int_inst_queue_wakeup_accesses        15642                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                   8                       # Number of floating instruction queue reads
@@ -405,7 +431,7 @@ system.cpu.iew.lsq.thread0.rescheduledLoads            1                       #
 system.cpu.iew.lsq.thread0.cacheBlocked            21                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
 system.cpu.iew.iewSquashCycles                   1857                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                    3034                       # Number of cycles IEW is blocking
+system.cpu.iew.iewBlockCycles                    3086                       # Number of cycles IEW is blocking
 system.cpu.iew.iewUnblockCycles                    35                       # Number of cycles IEW is unblocking
 system.cpu.iew.iewDispatchedInsts               20262                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                39                       # Number of squashed instructions skipped by dispatch
@@ -426,27 +452,27 @@ system.cpu.iew.exec_nop                             0                       # nu
 system.cpu.iew.exec_refs                         3127                       # number of memory reference insts executed
 system.cpu.iew.exec_branches                     1623                       # Number of branches executed
 system.cpu.iew.exec_stores                       1273                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.403685                       # Inst execution rate
+system.cpu.iew.exec_rate                     0.401694                       # Inst execution rate
 system.cpu.iew.wb_sent                          15865                       # cumulative count of insts sent to commit
 system.cpu.iew.wb_count                         15646                       # cumulative count of insts written-back
 system.cpu.iew.wb_producers                     10128                       # num instructions producing a value
 system.cpu.iew.wb_consumers                     15579                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.391718                       # insts written-back per cycle
+system.cpu.iew.wb_rate                       0.389786                       # insts written-back per cycle
 system.cpu.iew.wb_fanout                     0.650106                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitSquashedInsts           10526                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              12                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts               593                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        19988                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.487643                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.344274                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples        20042                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.486329                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.342699                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0        16420     82.15%     82.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1         1360      6.80%     88.95% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          589      2.95%     91.90% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          713      3.57%     95.47% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          364      1.82%     97.29% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0        16474     82.20%     82.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1         1360      6.79%     88.98% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          589      2.94%     91.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          713      3.56%     95.48% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          364      1.82%     97.30% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::5          136      0.68%     97.97% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::6          120      0.60%     98.57% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::7           74      0.37%     98.94% # Number of insts commited each cycle
@@ -454,7 +480,7 @@ system.cpu.commit.committed_per_cycle::8          212      1.06%    100.00% # Nu
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        19988                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        20042                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts                 5380                       # Number of instructions committed
 system.cpu.commit.committedOps                   9747                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -467,17 +493,17 @@ system.cpu.commit.int_insts                      9653                       # Nu
 system.cpu.commit.function_calls                  106                       # Number of function calls committed.
 system.cpu.commit.bw_lim_events                   212                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                        40049                       # The number of ROB reads
+system.cpu.rob.rob_reads                        40103                       # The number of ROB reads
 system.cpu.rob.rob_writes                       42426                       # The number of ROB writes
 system.cpu.timesIdled                             166                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           18097                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles                           18241                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        5380                       # Number of Instructions Simulated
 system.cpu.committedOps                          9747                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total                  5380                       # Number of Instructions Simulated
-system.cpu.cpi                               7.424164                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         7.424164                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.134695                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.134695                       # IPC: Total IPC of All Threads
+system.cpu.cpi                               7.460967                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         7.460967                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.134031                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.134031                       # IPC: Total IPC of All Threads
 system.cpu.int_regfile_reads                    20727                       # number of integer regfile reads
 system.cpu.int_regfile_writes                   12358                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                         4                       # number of floating regfile reads
@@ -485,7 +511,7 @@ system.cpu.cc_regfile_reads                      8004                       # nu
 system.cpu.cc_regfile_writes                     4850                       # number of cc regfile writes
 system.cpu.misc_regfile_reads                    7135                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput              1333166420                       # Throughput (bytes/s)
+system.cpu.toL2Bus.throughput              1326590099                       # Throughput (bytes/s)
 system.cpu.toL2Bus.trans_dist::ReadReq            340                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp           339                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           77                       # Transaction distribution
@@ -500,19 +526,19 @@ system.cpu.toL2Bus.data_through_bus             26624                       # To
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
 system.cpu.toL2Bus.reqLayer0.occupancy         208500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        458500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy        458250                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          2.3                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        236000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy        235500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.2                       # Layer utilization (%)
 system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse           130.946729                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse           130.897576                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                1609                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               274                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs              5.872263                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   130.946729                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.063939                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.063939                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   130.897576                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.063915                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.063915                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          274                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0          150                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          124                       # Occupied blocks per task id
@@ -531,12 +557,12 @@ system.cpu.icache.demand_misses::cpu.inst          371                       # n
 system.cpu.icache.demand_misses::total            371                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          371                       # number of overall misses
 system.cpu.icache.overall_misses::total           371                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     25087750                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     25087750                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     25087750                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     25087750                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     25087750                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     25087750                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     25180750                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     25180750                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     25180750                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     25180750                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     25180750                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     25180750                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst         1980                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total         1980                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst         1980                       # number of demand (read+write) accesses
@@ -549,12 +575,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.187374
 system.cpu.icache.demand_miss_rate::total     0.187374                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.187374                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.187374                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67621.967655                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 67621.967655                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 67621.967655                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 67621.967655                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 67621.967655                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 67621.967655                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67872.641509                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 67872.641509                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 67872.641509                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 67872.641509                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 67872.641509                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 67872.641509                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs           53                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 1                       # number of cycles access was blocked
@@ -575,39 +601,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          274
 system.cpu.icache.demand_mshr_misses::total          274                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          274                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          274                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     19639000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     19639000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     19639000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     19639000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     19639000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     19639000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     19745750                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     19745750                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     19745750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     19745750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     19745750                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     19745750                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.138384                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.138384                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.138384                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.138384                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.138384                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.138384                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71675.182482                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71675.182482                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71675.182482                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 71675.182482                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71675.182482                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 71675.182482                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72064.781022                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72064.781022                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72064.781022                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 72064.781022                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72064.781022                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 72064.781022                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          163.766589                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          163.708534                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  2                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              337                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.005935                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   131.016356                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    32.750233                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.003998                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   130.966386                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    32.742148                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.003997                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.000999                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.004998                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.004996                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          337                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          182                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          155                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          181                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          156                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.010284                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses             3750                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses            3750                       # Number of data accesses
@@ -631,17 +657,17 @@ system.cpu.l2cache.demand_misses::total           415                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          273                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          142                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          415                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     19353500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      5004000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     24357500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      5417000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      5417000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     19353500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data     10421000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     29774500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     19353500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data     10421000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     29774500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     19460250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      5265000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     24725250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      5444500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      5444500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     19460250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data     10709500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     30169750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     19460250                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data     10709500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     30169750                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst          274                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data           66                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total          340                       # number of ReadReq accesses(hits+misses)
@@ -664,17 +690,17 @@ system.cpu.l2cache.demand_miss_rate::total     0.995204                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996350                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.993007                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.995204                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70891.941392                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76984.615385                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 72063.609467                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70350.649351                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70350.649351                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70891.941392                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73387.323944                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 71745.783133                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70891.941392                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73387.323944                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 71745.783133                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71282.967033                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        81000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 73151.627219                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70707.792208                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70707.792208                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71282.967033                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75419.014085                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 72698.192771                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71282.967033                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75419.014085                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 72698.192771                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -694,17 +720,17 @@ system.cpu.l2cache.demand_mshr_misses::total          415
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          273                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          142                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          415                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     15927500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      4205500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     20133000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      4457500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      4457500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     15927500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      8663000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     24590500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     15927500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      8663000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     24590500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     16034750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      4466500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     20501250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      4485000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      4485000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     16034750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      8951500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     24986250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     16034750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      8951500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     24986250                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.996350                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.984848                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.994118                       # mshr miss rate for ReadReq accesses
@@ -716,27 +742,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.995204
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996350                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.993007                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.995204                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58342.490842                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        64700                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59565.088757                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57889.610390                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57889.610390                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58342.490842                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61007.042254                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59254.216867                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58342.490842                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61007.042254                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59254.216867                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58735.347985                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68715.384615                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60654.585799                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58246.753247                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58246.753247                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58735.347985                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63038.732394                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60207.831325                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58735.347985                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63038.732394                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60207.831325                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            83.239431                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse            83.267922                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs                2337                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               142                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs             16.457746                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    83.239431                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.020322                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.020322                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data    83.267922                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.020329                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.020329                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          142                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           51                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           91                       # Occupied blocks per task id
@@ -759,14 +785,14 @@ system.cpu.dcache.demand_misses::cpu.data          209                       # n
 system.cpu.dcache.demand_misses::total            209                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data          209                       # number of overall misses
 system.cpu.dcache.overall_misses::total           209                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      9408000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      9408000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data      5676000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      5676000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     15084000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     15084000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     15084000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     15084000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      9669000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      9669000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data      5702500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      5702500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     15371500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     15371500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     15371500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     15371500                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data         1611                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total         1611                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          935                       # number of WriteReq accesses(hits+misses)
@@ -783,14 +809,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.082090
 system.cpu.dcache.demand_miss_rate::total     0.082090                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.082090                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.082090                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71272.727273                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 71272.727273                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73714.285714                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 73714.285714                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 72172.248804                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 72172.248804                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 72172.248804                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 72172.248804                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data        73250                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total        73250                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74058.441558                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 74058.441558                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 73547.846890                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 73547.846890                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 73547.846890                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 73547.846890                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs          183                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 4                       # number of cycles access was blocked
@@ -813,14 +839,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          143
 system.cpu.dcache.demand_mshr_misses::total          143                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          143                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          143                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      5079000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      5079000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      5494000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      5494000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     10573000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     10573000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     10573000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     10573000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      5340000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      5340000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      5521500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      5521500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     10861500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     10861500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     10861500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     10861500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.040968                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.040968                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.082353                       # mshr miss rate for WriteReq accesses
@@ -829,14 +855,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.056167
 system.cpu.dcache.demand_mshr_miss_rate::total     0.056167                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.056167                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.056167                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76954.545455                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76954.545455                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71350.649351                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71350.649351                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73937.062937                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 73937.062937                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73937.062937                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 73937.062937                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80909.090909                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80909.090909                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71707.792208                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71707.792208                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75954.545455                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 75954.545455                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75954.545455                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 75954.545455                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 941a3afbfb38b616edc680c8d28d56205b58254d..e69a62b445bd2c2510e882ff5b00b304880a08d1 100644 (file)
@@ -1,56 +1,56 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000024                       # Number of seconds simulated
-sim_ticks                                    24229500                       # Number of ticks simulated
-final_tick                                   24229500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    24195500                       # Number of ticks simulated
+final_tick                                   24195500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  46987                       # Simulator instruction rate (inst/s)
-host_op_rate                                    46985                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               89318295                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 231368                       # Number of bytes of host memory used
-host_seconds                                     0.27                       # Real time elapsed on the host
+host_inst_rate                                  65180                       # Simulator instruction rate (inst/s)
+host_op_rate                                    65175                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              123719748                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 266292                       # Number of bytes of host memory used
+host_seconds                                     0.20                       # Real time elapsed on the host
 sim_insts                                       12745                       # Number of instructions simulated
 sim_ops                                         12745                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.inst             39936                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data             22464                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                62400                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data             22400                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                62336                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read::cpu.inst        39936                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total           39936                       # Number of instructions bytes read from this memory
 system.physmem.num_reads::cpu.inst                624                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data                351                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                   975                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst           1648238717                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            927134278                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              2575372996                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      1648238717                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         1648238717                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          1648238717                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           927134278                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             2575372996                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                           975                       # Number of read requests accepted
+system.physmem.num_reads::cpu.data                350                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                   974                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst           1650554855                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            925791986                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              2576346841                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      1650554855                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         1650554855                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          1650554855                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           925791986                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             2576346841                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                           974                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                         975                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                         974                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                    62400                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                    62336                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                     62400                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                     62336                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                  82                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                  83                       # Per bank write bursts
 system.physmem.perBankRdBursts::1                 153                       # Per bank write bursts
 system.physmem.perBankRdBursts::2                  77                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                  60                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                  59                       # Per bank write bursts
 system.physmem.perBankRdBursts::4                  87                       # Per bank write bursts
 system.physmem.perBankRdBursts::5                  49                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                  32                       # Per bank write bursts
 system.physmem.perBankRdBursts::7                  49                       # Per bank write bursts
 system.physmem.perBankRdBursts::8                  42                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                  39                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                  38                       # Per bank write bursts
 system.physmem.perBankRdBursts::10                 30                       # Per bank write bursts
 system.physmem.perBankRdBursts::11                 33                       # Per bank write bursts
 system.physmem.perBankRdBursts::12                 15                       # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        24081000                       # Total gap between requests
+system.physmem.totGap                        24047500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                     975                       # Read request sizes (log2)
+system.physmem.readPktSize::6                     974                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -90,12 +90,12 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       344                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       370                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       169                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        70                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       336                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       371                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       175                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        71                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                        15                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         5                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         4                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
@@ -154,102 +154,122 @@ system.physmem.wrQLenPdf::28                        0                       # Wh
 system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          217                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      271.926267                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     156.688517                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     360.951821                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64                92     42.40%     42.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128               33     15.21%     57.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192               21      9.68%     67.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256               20      9.22%     76.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320                3      1.38%     77.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384                8      3.69%     81.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448                3      1.38%     82.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512                4      1.84%     84.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576                4      1.84%     86.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640                4      1.84%     88.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704                5      2.30%     90.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768                4      1.84%     92.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832                2      0.92%     93.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896                2      0.92%     94.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960                3      1.38%     95.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024               1      0.46%     96.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408               2      0.92%     97.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536               2      0.92%     98.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600               1      0.46%     98.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856               2      0.92%     99.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2304               1      0.46%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            217                       # Bytes accessed per row activation
-system.physmem.totQLat                        9442250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  31257250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                      4875000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                    16940000                       # Total ticks spent accessing banks
-system.physmem.avgQLat                        9684.36                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    17374.36                       # Average bank access latency per DRAM burst
+system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples          173                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      267.838150                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     164.887930                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     289.529003                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             68     39.31%     39.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           43     24.86%     64.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           22     12.72%     76.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            7      4.05%     80.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            7      4.05%     84.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            7      4.05%     89.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            5      2.89%     91.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            2      1.16%     93.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151           12      6.94%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total            173                       # Bytes accessed per row activation
+system.physmem.totQLat                        8580250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  30335250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                      4870000                       # Total ticks spent in databus transfers
+system.physmem.totBankLat                    16885000                       # Total ticks spent accessing banks
+system.physmem.avgQLat                        8809.29                       # Average queueing delay per DRAM burst
+system.physmem.avgBankLat                    17335.73                       # Average bank access latency per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  32058.72                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        2575.37                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  31145.02                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        2576.35                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     2575.37                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     2576.35                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                          20.12                       # Data bus utilization in percentage
-system.physmem.busUtilRead                      20.12                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                          20.13                       # Data bus utilization in percentage
+system.physmem.busUtilRead                      20.13                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.29                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         2.36                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                        758                       # Number of row buffer hits during reads
+system.physmem.readRowHits                        752                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   77.74                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   77.21                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        24698.46                       # Average gap between requests
-system.physmem.pageHitRate                      77.74                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               0.09                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                   2575372996                       # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq                 829                       # Transaction distribution
-system.membus.trans_dist::ReadResp                829                       # Transaction distribution
+system.physmem.avgGap                        24689.43                       # Average gap between requests
+system.physmem.pageHitRate                      77.21                       # Row buffer hit rate, read and write combined
+system.physmem.prechargeAllPercent               0.10                       # Percentage of time for which DRAM has all the banks in precharge state
+system.membus.throughput                   2576346841                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq                 828                       # Transaction distribution
+system.membus.trans_dist::ReadResp                828                       # Transaction distribution
 system.membus.trans_dist::ReadExReq               146                       # Transaction distribution
 system.membus.trans_dist::ReadExResp              146                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         1950                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                   1950                       # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        62400                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total               62400                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus                  62400                       # Total data (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         1948                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                   1948                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        62336                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total               62336                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus                  62336                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
 system.membus.reqLayer0.occupancy             1237000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               5.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            9059500                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             37.4                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            9035750                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             37.3                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                    6676                       # Number of BP lookups
-system.cpu.branchPred.condPredicted              3772                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect              1441                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups                 4747                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                     873                       # Number of BTB hits
+system.cpu.branchPred.lookups                    6713                       # Number of BP lookups
+system.cpu.branchPred.condPredicted              3825                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect              1484                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups                 4727                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                     847                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             18.390562                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                     886                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                179                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             17.918341                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                     896                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                174                       # Number of incorrect RAS predictions.
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                         4587                       # DTB read hits
-system.cpu.dtb.read_misses                        111                       # DTB read misses
+system.cpu.dtb.read_hits                         4562                       # DTB read hits
+system.cpu.dtb.read_misses                        106                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                     4698                       # DTB read accesses
-system.cpu.dtb.write_hits                        2013                       # DTB write hits
+system.cpu.dtb.read_accesses                     4668                       # DTB read accesses
+system.cpu.dtb.write_hits                        2031                       # DTB write hits
 system.cpu.dtb.write_misses                        86                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                    2099                       # DTB write accesses
-system.cpu.dtb.data_hits                         6600                       # DTB hits
-system.cpu.dtb.data_misses                        197                       # DTB misses
+system.cpu.dtb.write_accesses                    2117                       # DTB write accesses
+system.cpu.dtb.data_hits                         6593                       # DTB hits
+system.cpu.dtb.data_misses                        192                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                     6797                       # DTB accesses
-system.cpu.itb.fetch_hits                        5374                       # ITB hits
-system.cpu.itb.fetch_misses                        57                       # ITB misses
+system.cpu.dtb.data_accesses                     6785                       # DTB accesses
+system.cpu.itb.fetch_hits                        5378                       # ITB hits
+system.cpu.itb.fetch_misses                        56                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                    5431                       # ITB accesses
+system.cpu.itb.fetch_accesses                    5434                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -264,316 +284,316 @@ system.cpu.itb.data_acv                             0                       # DT
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload0.num_syscalls                  17                       # Number of system calls
 system.cpu.workload1.num_syscalls                  17                       # Number of system calls
-system.cpu.numCycles                            48460                       # number of cpu cycles simulated
+system.cpu.numCycles                            48392                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles               1592                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          37128                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        6676                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches               1759                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          6222                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                    1834                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                  325                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.CacheLines                      5374                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   890                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              29555                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.256234                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.686456                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles               1584                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          37241                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        6713                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches               1743                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                          6224                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                    1851                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                  283                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.CacheLines                      5378                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   894                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples              28253                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.318126                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.738229                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                    23333     78.95%     78.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                      540      1.83%     80.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      380      1.29%     82.06% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      444      1.50%     83.56% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      426      1.44%     85.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      410      1.39%     86.39% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      457      1.55%     87.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      520      1.76%     89.70% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     3045     10.30%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                    22029     77.97%     77.97% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                      543      1.92%     79.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      355      1.26%     81.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      435      1.54%     82.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      449      1.59%     84.28% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      397      1.41%     85.68% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      461      1.63%     87.31% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      536      1.90%     89.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                     3048     10.79%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                29555                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.137763                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.766158                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                    40476                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                  9889                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      5340                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                   489                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                   2737                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved                  565                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                   333                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts                  32705                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                   703                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                   2737                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                    41177                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                    6164                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           1585                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      5023                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                  2245                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  30189                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                    54                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.LSQFullEvents                  2292                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands               22672                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 37159                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            37141                       # Number of integer rename lookups
+system.cpu.fetch.rateDist::total                28253                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.138721                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.769569                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                    39403                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                  8381                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      5346                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                   468                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                   2729                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved                  576                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                   358                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts                  32540                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                   795                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                   2729                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                    40132                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                    5179                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           1042                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                      4980                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                  2265                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                  30075                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                    57                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.LSQFullEvents                  2305                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands               22490                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 37013                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            36995                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups                16                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps                  9140                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                    13532                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps                    13350                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts                 49                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts             37                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                      6114                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 2970                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                1346                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads                 9                       # Number of conflicting loads.
+system.cpu.rename.skidInsts                      6315                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads                 2908                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                1349                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads                 6                       # Number of conflicting loads.
 system.cpu.memDep0.conflictingStores                0                       # Number of conflicting stores.
-system.cpu.memDep1.insertedLoads                 3034                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep1.insertedStores                1382                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep1.insertedLoads                 3030                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep1.insertedStores                1436                       # Number of stores inserted to the mem dependence unit.
 system.cpu.memDep1.conflictingLoads                 1                       # Number of conflicting loads.
 system.cpu.memDep1.conflictingStores                0                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                      26322                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                  78                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                     21626                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued               131                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined           12553                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined         8051                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved             44                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         29555                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.731721                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.328495                       # Number of insts issued each cycle
+system.cpu.iq.iqInstsAdded                      26280                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                  79                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                     21655                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued               129                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined           12548                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined         7940                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             45                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples         28253                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.766467                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.344323                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0               20216     68.40%     68.40% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                3350     11.33%     79.74% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                2622      8.87%     88.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                1591      5.38%     93.99% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                1010      3.42%     97.41% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 474      1.60%     99.01% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 217      0.73%     99.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                  53      0.18%     99.93% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8                  22      0.07%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0               18861     66.76%     66.76% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                3387     11.99%     78.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                2636      9.33%     88.08% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                1597      5.65%     93.73% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                1020      3.61%     97.34% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 473      1.67%     99.01% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 215      0.76%     99.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                  42      0.15%     99.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                  22      0.08%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           29555                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           28253                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                       9      4.86%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      4.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                    107     57.84%     62.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                    69     37.30%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                       3      1.75%      1.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      1.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      1.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      1.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      1.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      1.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      1.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      1.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      1.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      1.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      1.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      1.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      1.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      1.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      1.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      1.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      1.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      1.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      1.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      1.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      1.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      1.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      1.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      1.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      1.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      1.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      1.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      1.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      1.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                    104     60.82%     62.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    64     37.43%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 2      0.02%      0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                  7076     65.52%     65.54% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    1      0.01%     65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     65.55% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     65.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     65.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     65.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     65.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     65.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     65.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     65.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     65.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     65.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     65.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     65.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     65.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     65.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     65.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     65.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     65.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     65.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     65.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     65.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     65.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     65.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     65.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     65.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     65.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     65.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     65.56% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 2585     23.94%     89.50% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                1134     10.50%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                  7084     66.01%     66.03% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    1      0.01%     66.04% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     66.04% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     66.05% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.05% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     66.05% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     66.05% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     66.05% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     66.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     66.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     66.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     66.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     66.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     66.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     66.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     66.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     66.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     66.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     66.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     66.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     66.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     66.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     66.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     66.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     66.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.05% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 2526     23.54%     89.59% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1117     10.41%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                  10800                       # Type of FU issued
+system.cpu.iq.FU_type_0::total                  10732                       # Type of FU issued
 system.cpu.iq.FU_type_1::No_OpClass                 2      0.02%      0.02% # Type of FU issued
-system.cpu.iq.FU_type_1::IntAlu                  7138     65.93%     65.95% # Type of FU issued
-system.cpu.iq.FU_type_1::IntMult                    1      0.01%     65.96% # Type of FU issued
-system.cpu.iq.FU_type_1::IntDiv                     0      0.00%     65.96% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatAdd                   2      0.02%     65.98% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatCmp                   0      0.00%     65.98% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatCvt                   0      0.00%     65.98% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatMult                  0      0.00%     65.98% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatDiv                   0      0.00%     65.98% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatSqrt                  0      0.00%     65.98% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdAdd                    0      0.00%     65.98% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdAddAcc                 0      0.00%     65.98% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdAlu                    0      0.00%     65.98% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdCmp                    0      0.00%     65.98% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdCvt                    0      0.00%     65.98% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdMisc                   0      0.00%     65.98% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdMult                   0      0.00%     65.98% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdMultAcc                0      0.00%     65.98% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdShift                  0      0.00%     65.98% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdShiftAcc               0      0.00%     65.98% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdSqrt                   0      0.00%     65.98% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatAdd               0      0.00%     65.98% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatAlu               0      0.00%     65.98% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatCmp               0      0.00%     65.98% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatCvt               0      0.00%     65.98% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatDiv               0      0.00%     65.98% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatMisc              0      0.00%     65.98% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatMult              0      0.00%     65.98% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatMultAcc            0      0.00%     65.98% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatSqrt              0      0.00%     65.98% # Type of FU issued
-system.cpu.iq.FU_type_1::MemRead                 2586     23.89%     89.87% # Type of FU issued
-system.cpu.iq.FU_type_1::MemWrite                1097     10.13%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_1::IntAlu                  7192     65.84%     65.86% # Type of FU issued
+system.cpu.iq.FU_type_1::IntMult                    1      0.01%     65.87% # Type of FU issued
+system.cpu.iq.FU_type_1::IntDiv                     0      0.00%     65.87% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatAdd                   2      0.02%     65.89% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatCmp                   0      0.00%     65.89% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatCvt                   0      0.00%     65.89% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatMult                  0      0.00%     65.89% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatDiv                   0      0.00%     65.89% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatSqrt                  0      0.00%     65.89% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdAdd                    0      0.00%     65.89% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdAddAcc                 0      0.00%     65.89% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdAlu                    0      0.00%     65.89% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdCmp                    0      0.00%     65.89% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdCvt                    0      0.00%     65.89% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdMisc                   0      0.00%     65.89% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdMult                   0      0.00%     65.89% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdMultAcc                0      0.00%     65.89% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdShift                  0      0.00%     65.89% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdShiftAcc               0      0.00%     65.89% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdSqrt                   0      0.00%     65.89% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatAdd               0      0.00%     65.89% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatAlu               0      0.00%     65.89% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatCmp               0      0.00%     65.89% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatCvt               0      0.00%     65.89% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatDiv               0      0.00%     65.89% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatMisc              0      0.00%     65.89% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatMult              0      0.00%     65.89% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatMultAcc            0      0.00%     65.89% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatSqrt              0      0.00%     65.89% # Type of FU issued
+system.cpu.iq.FU_type_1::MemRead                 2608     23.88%     89.76% # Type of FU issued
+system.cpu.iq.FU_type_1::MemWrite                1118     10.24%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_1::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_1::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_1::total                  10826                       # Type of FU issued
-system.cpu.iq.FU_type::total                    21626      0.00%      0.00% # Type of FU issued
-system.cpu.iq.rate                           0.446265                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt::0                       88                       # FU busy when requested
-system.cpu.iq.fu_busy_cnt::1                       97                       # FU busy when requested
-system.cpu.iq.fu_busy_cnt::total                  185                       # FU busy when requested
-system.cpu.iq.fu_busy_rate::0                0.004069                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.fu_busy_rate::1                0.004485                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.fu_busy_rate::total            0.008555                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              73081                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             38962                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses        18684                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_1::total                  10923                       # Type of FU issued
+system.cpu.iq.FU_type::total                    21655      0.00%      0.00% # Type of FU issued
+system.cpu.iq.rate                           0.447491                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt::0                       83                       # FU busy when requested
+system.cpu.iq.fu_busy_cnt::1                       88                       # FU busy when requested
+system.cpu.iq.fu_busy_cnt::total                  171                       # FU busy when requested
+system.cpu.iq.fu_busy_rate::0                0.003833                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_busy_rate::1                0.004064                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_busy_rate::total            0.007897                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              71821                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             38912                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses        18708                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                  42                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                 20                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses           20                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                  21785                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                  21800                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                      22                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads               57                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads               63                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads         1787                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads         1725                       # Number of loads squashed
 system.cpu.iew.lsq.thread0.ignoredResponses            2                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation           16                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores          481                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.memOrderViolation           13                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores          484                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            1                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked           350                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread1.forwLoads               47                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.cacheBlocked           332                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread1.forwLoads               52                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread1.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread1.squashedLoads         1851                       # Number of loads squashed
-system.cpu.iew.lsq.thread1.ignoredResponses            2                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread1.memOrderViolation           15                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread1.squashedStores          517                       # Number of stores squashed
+system.cpu.iew.lsq.thread1.squashedLoads         1847                       # Number of loads squashed
+system.cpu.iew.lsq.thread1.ignoredResponses            6                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread1.memOrderViolation           14                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread1.squashedStores          571                       # Number of stores squashed
 system.cpu.iew.lsq.thread1.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread1.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread1.rescheduledLoads            1                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread1.cacheBlocked           407                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread1.cacheBlocked           394                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                   2737                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                    2954                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                    42                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               26599                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts               599                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  6004                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                 2728                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                 78                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                     23                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                     0                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents             31                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect            236                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect         1067                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                 1303                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                 20163                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts::0               2351                       # Number of load instructions executed
-system.cpu.iew.iewExecLoadInsts::1               2365                       # Number of load instructions executed
-system.cpu.iew.iewExecLoadInsts::total           4716                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts              1463                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                   2729                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                    1818                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                    48                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts               26553                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts               614                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts                  5938                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                 2785                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                 79                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                     21                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                     3                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents             27                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect            240                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect         1081                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts                 1321                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts                 20146                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts::0               2319                       # Number of load instructions executed
+system.cpu.iew.iewExecLoadInsts::1               2367                       # Number of load instructions executed
+system.cpu.iew.iewExecLoadInsts::total           4686                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts              1509                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp::0                          0                       # number of swp insts executed
 system.cpu.iew.exec_swp::1                          0                       # number of swp insts executed
 system.cpu.iew.exec_swp::total                      0                       # number of swp insts executed
-system.cpu.iew.exec_nop::0                        109                       # number of nop insts executed
-system.cpu.iew.exec_nop::1                         90                       # number of nop insts executed
-system.cpu.iew.exec_nop::total                    199                       # number of nop insts executed
-system.cpu.iew.exec_refs::0                      3417                       # number of memory reference insts executed
-system.cpu.iew.exec_refs::1                      3412                       # number of memory reference insts executed
-system.cpu.iew.exec_refs::total                  6829                       # number of memory reference insts executed
-system.cpu.iew.exec_branches::0                  1584                       # Number of branches executed
-system.cpu.iew.exec_branches::1                  1595                       # Number of branches executed
-system.cpu.iew.exec_branches::total              3179                       # Number of branches executed
-system.cpu.iew.exec_stores::0                    1066                       # Number of stores executed
-system.cpu.iew.exec_stores::1                    1047                       # Number of stores executed
-system.cpu.iew.exec_stores::total                2113                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.416075                       # Inst execution rate
-system.cpu.iew.wb_sent::0                        9509                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_sent::1                        9507                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_sent::total                   19016                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count::0                       9333                       # cumulative count of insts written-back
-system.cpu.iew.wb_count::1                       9371                       # cumulative count of insts written-back
-system.cpu.iew.wb_count::total                  18704                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers::0                   4798                       # num instructions producing a value
-system.cpu.iew.wb_producers::1                   4830                       # num instructions producing a value
-system.cpu.iew.wb_producers::total               9628                       # num instructions producing a value
-system.cpu.iew.wb_consumers::0                   6247                       # num instructions consuming a value
-system.cpu.iew.wb_consumers::1                   6320                       # num instructions consuming a value
-system.cpu.iew.wb_consumers::total              12567                       # num instructions consuming a value
+system.cpu.iew.exec_nop::0                        105                       # number of nop insts executed
+system.cpu.iew.exec_nop::1                         89                       # number of nop insts executed
+system.cpu.iew.exec_nop::total                    194                       # number of nop insts executed
+system.cpu.iew.exec_refs::0                      3378                       # number of memory reference insts executed
+system.cpu.iew.exec_refs::1                      3437                       # number of memory reference insts executed
+system.cpu.iew.exec_refs::total                  6815                       # number of memory reference insts executed
+system.cpu.iew.exec_branches::0                  1579                       # Number of branches executed
+system.cpu.iew.exec_branches::1                  1604                       # Number of branches executed
+system.cpu.iew.exec_branches::total              3183                       # Number of branches executed
+system.cpu.iew.exec_stores::0                    1059                       # Number of stores executed
+system.cpu.iew.exec_stores::1                    1070                       # Number of stores executed
+system.cpu.iew.exec_stores::total                2129                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.416308                       # Inst execution rate
+system.cpu.iew.wb_sent::0                        9480                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_sent::1                        9551                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_sent::total                   19031                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count::0                       9310                       # cumulative count of insts written-back
+system.cpu.iew.wb_count::1                       9418                       # cumulative count of insts written-back
+system.cpu.iew.wb_count::total                  18728                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers::0                   4774                       # num instructions producing a value
+system.cpu.iew.wb_producers::1                   4832                       # num instructions producing a value
+system.cpu.iew.wb_producers::total               9606                       # num instructions producing a value
+system.cpu.iew.wb_consumers::0                   6221                       # num instructions consuming a value
+system.cpu.iew.wb_consumers::1                   6338                       # num instructions consuming a value
+system.cpu.iew.wb_consumers::total              12559                       # num instructions consuming a value
 system.cpu.iew.wb_penalized::0                      0                       # number of instrctions required to write to 'other' IQ
 system.cpu.iew.wb_penalized::1                      0                       # number of instrctions required to write to 'other' IQ
 system.cpu.iew.wb_penalized::total                  0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate::0                    0.192592                       # insts written-back per cycle
-system.cpu.iew.wb_rate::1                    0.193376                       # insts written-back per cycle
-system.cpu.iew.wb_rate::total                0.385968                       # insts written-back per cycle
-system.cpu.iew.wb_fanout::0                  0.768049                       # average fanout of values written-back
-system.cpu.iew.wb_fanout::1                  0.764241                       # average fanout of values written-back
-system.cpu.iew.wb_fanout::total              0.766134                       # average fanout of values written-back
+system.cpu.iew.wb_rate::0                    0.192387                       # insts written-back per cycle
+system.cpu.iew.wb_rate::1                    0.194619                       # insts written-back per cycle
+system.cpu.iew.wb_rate::total                0.387006                       # insts written-back per cycle
+system.cpu.iew.wb_fanout::0                  0.767401                       # average fanout of values written-back
+system.cpu.iew.wb_fanout::1                  0.762386                       # average fanout of values written-back
+system.cpu.iew.wb_fanout::total              0.764870                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate::0                 0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.iew.wb_penalized_rate::1                 0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.iew.wb_penalized_rate::total             0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts           13828                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts           13802                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              34                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts              1125                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        29488                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.433363                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.196034                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts              1144                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples        28205                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.453076                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.225022                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0        23747     80.53%     80.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1         3040     10.31%     90.84% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2         1123      3.81%     94.65% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          504      1.71%     96.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          341      1.16%     97.51% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5          269      0.91%     98.43% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6          187      0.63%     99.06% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           66      0.22%     99.28% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8          211      0.72%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0        22496     79.76%     79.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1         3008     10.66%     90.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2         1125      3.99%     94.41% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          504      1.79%     96.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          336      1.19%     97.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5          259      0.92%     98.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6          191      0.68%     98.99% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           64      0.23%     99.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8          222      0.79%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        29488                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        28205                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts::0              6390                       # Number of instructions committed
 system.cpu.commit.committedInsts::1              6389                       # Number of instructions committed
 system.cpu.commit.committedInsts::total         12779                       # Number of instructions committed
@@ -604,161 +624,161 @@ system.cpu.commit.int_insts::total              12614                       # Nu
 system.cpu.commit.function_calls::0               127                       # Number of function calls committed.
 system.cpu.commit.function_calls::1               127                       # Number of function calls committed.
 system.cpu.commit.function_calls::total           254                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events                   211                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events                   222                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited::0                     0                       # number of insts not committed due to BW limits
 system.cpu.commit.bw_limited::1                     0                       # number of insts not committed due to BW limits
 system.cpu.commit.bw_limited::total                 0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                       132697                       # The number of ROB reads
-system.cpu.rob.rob_writes                       55969                       # The number of ROB writes
-system.cpu.timesIdled                             379                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           18905                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                       130213                       # The number of ROB reads
+system.cpu.rob.rob_writes                       55909                       # The number of ROB writes
+system.cpu.timesIdled                             371                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           20139                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts::0                     6373                       # Number of Instructions Simulated
 system.cpu.committedInsts::1                     6372                       # Number of Instructions Simulated
 system.cpu.committedOps::0                       6373                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedOps::1                       6372                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total                 12745                       # Number of Instructions Simulated
-system.cpu.cpi::0                            7.603954                       # CPI: Cycles Per Instruction
-system.cpu.cpi::1                            7.605148                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         3.802275                       # CPI: Total CPI of All Threads
-system.cpu.ipc::0                            0.131511                       # IPC: Instructions Per Cycle
-system.cpu.ipc::1                            0.131490                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.263000                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    25289                       # number of integer regfile reads
-system.cpu.int_regfile_writes                   14129                       # number of integer regfile writes
+system.cpu.cpi::0                            7.593284                       # CPI: Cycles Per Instruction
+system.cpu.cpi::1                            7.594476                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         3.796940                       # CPI: Total CPI of All Threads
+system.cpu.ipc::0                            0.131695                       # IPC: Instructions Per Cycle
+system.cpu.ipc::1                            0.131675                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.263370                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                    25300                       # number of integer regfile reads
+system.cpu.int_regfile_writes                   14121                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                        4                       # number of floating regfile writes
 system.cpu.misc_regfile_reads                       2                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      2                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput              2580655812                       # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq            831                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp           831                       # Transaction distribution
+system.cpu.toL2Bus.throughput              2581637081                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq            830                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp           830                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq          146                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp          146                       # Transaction distribution
 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1252                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          702                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total              1954                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          700                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total              1952                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        40064                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        22464                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total          62528                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus             62528                       # Total data (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        22400                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total          62464                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus             62464                       # Total data (bytes)
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy         488500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.occupancy         488000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          2.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1029500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       1025000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          4.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        562500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy        559750                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          2.3                       # Layer utilization (%)
 system.cpu.icache.tags.replacements::0              6                       # number of replacements
 system.cpu.icache.tags.replacements::1              0                       # number of replacements
 system.cpu.icache.tags.replacements::total            6                       # number of replacements
-system.cpu.icache.tags.tagsinuse           312.493120                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                4320                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           312.920483                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                4342                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               626                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs              6.900958                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs              6.936102                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   312.493120                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.152585                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.152585                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   312.920483                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.152793                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.152793                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          620                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0          263                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          357                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.302734                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses             11364                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses            11364                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst         4320                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            4320                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          4320                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             4320                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         4320                       # number of overall hits
-system.cpu.icache.overall_hits::total            4320                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         1049                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          1049                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         1049                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           1049                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         1049                       # number of overall misses
-system.cpu.icache.overall_misses::total          1049                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     69934495                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     69934495                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     69934495                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     69934495                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     69934495                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     69934495                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         5369                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         5369                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         5369                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         5369                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         5369                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         5369                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.195381                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.195381                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.195381                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.195381                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.195381                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.195381                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66667.774071                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 66667.774071                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 66667.774071                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 66667.774071                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 66667.774071                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 66667.774071                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         2561                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses             11372                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses            11372                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst         4342                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            4342                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          4342                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             4342                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         4342                       # number of overall hits
+system.cpu.icache.overall_hits::total            4342                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1031                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1031                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1031                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1031                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1031                       # number of overall misses
+system.cpu.icache.overall_misses::total          1031                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     69474496                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     69474496                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     69474496                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     69474496                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     69474496                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     69474496                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         5373                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         5373                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         5373                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         5373                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         5373                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         5373                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.191885                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.191885                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.191885                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.191885                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.191885                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.191885                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67385.544132                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 67385.544132                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 67385.544132                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 67385.544132                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 67385.544132                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 67385.544132                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         2515                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                58                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                60                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    44.155172                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    41.916667                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          423                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          423                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          423                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          423                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          423                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          423                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          405                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          405                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          405                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          405                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          405                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          405                       # number of overall MSHR hits
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          626                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total          626                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst          626                       # number of demand (read+write) MSHR misses
 system.cpu.icache.demand_mshr_misses::total          626                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          626                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          626                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     46953746                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     46953746                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     46953746                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     46953746                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     46953746                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     46953746                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.116595                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.116595                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.116595                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.116595                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.116595                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.116595                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75005.984026                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75005.984026                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75005.984026                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 75005.984026                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75005.984026                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 75005.984026                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     46641746                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     46641746                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     46641746                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     46641746                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     46641746                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     46641746                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.116508                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.116508                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.116508                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.116508                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.116508                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.116508                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74507.581470                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74507.581470                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74507.581470                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 74507.581470                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74507.581470                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 74507.581470                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements::0             0                       # number of replacements
 system.cpu.l2cache.tags.replacements::1             0                       # number of replacements
 system.cpu.l2cache.tags.replacements::total            0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          433.166095                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          433.824891                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  2                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs              829                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.002413                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs              828                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.002415                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   313.001767                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   120.164328                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.009552                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.003667                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.013219                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024          829                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          337                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          492                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.025299                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses             8791                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses            8791                       # Number of data accesses
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   313.437243                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   120.387648                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.009565                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.003674                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.013239                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024          828                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          335                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          493                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.025269                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses             8782                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses            8782                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              2                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits
@@ -766,60 +786,60 @@ system.cpu.l2cache.demand_hits::total               2                       # nu
 system.cpu.l2cache.overall_hits::cpu.inst            2                       # number of overall hits
 system.cpu.l2cache.overall_hits::total              2                       # number of overall hits
 system.cpu.l2cache.ReadReq_misses::cpu.inst          624                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data          205                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total          829                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data          204                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total          828                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data          146                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total          146                       # number of ReadExReq misses
 system.cpu.l2cache.demand_misses::cpu.inst          624                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data          351                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total           975                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data          350                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total           974                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst          624                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data          351                       # number of overall misses
-system.cpu.l2cache.overall_misses::total          975                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     46304000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     16910000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     63214000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     11874500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total     11874500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     46304000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data     28784500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     75088500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     46304000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data     28784500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     75088500                       # number of overall miss cycles
+system.cpu.l2cache.overall_misses::cpu.data          350                       # number of overall misses
+system.cpu.l2cache.overall_misses::total          974                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     45992000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     16232250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     62224250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     11972000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total     11972000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     45992000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data     28204250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     74196250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     45992000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data     28204250                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     74196250                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst          626                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data          205                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total          831                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data          204                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total          830                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data          146                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total          146                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.inst          626                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data          351                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total          977                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data          350                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total          976                       # number of demand (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.inst          626                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data          351                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total          977                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data          350                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total          976                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.996805                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.997593                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.997590                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.996805                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.997953                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.997951                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996805                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.997953                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74205.128205                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82487.804878                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 76253.317250                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81332.191781                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81332.191781                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74205.128205                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82007.122507                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 77013.846154                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74205.128205                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82007.122507                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 77013.846154                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total     0.997951                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73705.128205                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79569.852941                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 75150.060386                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        82000                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total        82000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73705.128205                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80583.571429                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 76176.848049                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73705.128205                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80583.571429                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 76176.848049                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -829,163 +849,163 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets          nan
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          624                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          205                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total          829                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          204                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total          828                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          146                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total          146                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.inst          624                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data          351                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total          975                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data          350                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total          974                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          624                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data          351                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total          975                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     38522500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     14387500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     52910000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     10067500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     10067500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     38522500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     24455000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     62977500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     38522500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     24455000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     62977500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_misses::cpu.data          350                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total          974                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     38226500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     13721250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     51947750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     10170000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     10170000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     38226500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     23891250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     62117750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     38226500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     23891250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     62117750                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.996805                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.997593                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.997590                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.996805                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.997953                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.997951                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996805                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.997953                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61734.775641                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70182.926829                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63823.884198                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68955.479452                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68955.479452                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61734.775641                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69672.364672                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64592.307692                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61734.775641                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69672.364672                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64592.307692                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.997951                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61260.416667                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67261.029412                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62738.828502                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69657.534247                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69657.534247                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61260.416667                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68260.714286                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63775.924025                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61260.416667                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68260.714286                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63775.924025                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.dcache.tags.replacements::0              0                       # number of replacements
 system.cpu.dcache.tags.replacements::1              0                       # number of replacements
 system.cpu.dcache.tags.replacements::total            0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           214.018929                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                4470                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs               351                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             12.735043                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse           213.987948                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                4461                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs               350                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             12.745714                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   214.018929                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.052251                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.052251                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024          351                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           97                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          254                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.085693                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses             11365                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses            11365                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data         3448                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            3448                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data         1022                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total           1022                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data          4470                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             4470                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         4470                       # number of overall hits
-system.cpu.dcache.overall_hits::total            4470                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          329                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           329                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data          708                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total          708                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data         1037                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           1037                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         1037                       # number of overall misses
-system.cpu.dcache.overall_misses::total          1037                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     23849750                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     23849750                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     50904202                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     50904202                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     74753952                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     74753952                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     74753952                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     74753952                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         3777                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         3777                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.occ_blocks::cpu.data   213.987948                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.052243                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.052243                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          350                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           94                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          256                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.085449                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses             11334                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses            11334                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data         3441                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            3441                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data         1020                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total           1020                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data          4461                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             4461                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         4461                       # number of overall hits
+system.cpu.dcache.overall_hits::total            4461                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          321                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           321                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data          710                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total          710                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data         1031                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           1031                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         1031                       # number of overall misses
+system.cpu.dcache.overall_misses::total          1031                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     22966250                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     22966250                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     51761962                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     51761962                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     74728212                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     74728212                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     74728212                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     74728212                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         3762                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         3762                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data         1730                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total         1730                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         5507                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         5507                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         5507                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         5507                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.087106                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.087106                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.409249                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.409249                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.188306                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.188306                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.188306                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.188306                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72491.641337                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 72491.641337                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71898.590395                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 71898.590395                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 72086.742527                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 72086.742527                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 72086.742527                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 72086.742527                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs         4541                       # number of cycles access was blocked
+system.cpu.dcache.demand_accesses::cpu.data         5492                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         5492                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         5492                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         5492                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.085327                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.085327                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.410405                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.410405                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.187728                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.187728                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.187728                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.187728                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71545.950156                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 71545.950156                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72904.171831                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 72904.171831                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 72481.291950                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 72481.291950                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 72481.291950                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 72481.291950                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs         4374                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs               118                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs               106                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    38.483051                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    41.264151                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          124                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          124                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data          562                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total          562                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          686                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          686                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          686                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          686                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data          205                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          205                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          117                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          117                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data          564                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total          564                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          681                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          681                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          681                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          681                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          204                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          204                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data          146                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total          146                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data          351                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total          351                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data          351                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total          351                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     17123000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     17123000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     12022996                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total     12022996                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     29145996                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     29145996                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     29145996                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     29145996                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.054276                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.054276                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_misses::cpu.data          350                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total          350                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data          350                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total          350                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     16444750                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     16444750                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     12120496                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total     12120496                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     28565246                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     28565246                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     28565246                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     28565246                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.054226                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.054226                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.084393                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.084393                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.063737                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.063737                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.063737                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.063737                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 83526.829268                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 83526.829268                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82349.287671                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82349.287671                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 83037.025641                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 83037.025641                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83037.025641                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 83037.025641                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.063729                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.063729                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.063729                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.063729                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80611.519608                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80611.519608                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 83017.095890                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 83017.095890                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81614.988571                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 81614.988571                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81614.988571                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 81614.988571                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 4c8817e23a187f5d0255745c7b19c1143892ba18..260a10b907649d18555752f91cd04a81c62daa00 100644 (file)
@@ -1,34 +1,34 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000028                       # Number of seconds simulated
-sim_ticks                                    27705000                       # Number of ticks simulated
-final_tick                                   27705000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    27725000                       # Number of ticks simulated
+final_tick                                   27725000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  23200                       # Simulator instruction rate (inst/s)
-host_op_rate                                    23199                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               42390050                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 236824                       # Number of bytes of host memory used
-host_seconds                                     0.65                       # Real time elapsed on the host
+host_inst_rate                                  72342                       # Simulator instruction rate (inst/s)
+host_op_rate                                    72337                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              132265036                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 269700                       # Number of bytes of host memory used
+host_seconds                                     0.21                       # Real time elapsed on the host
 sim_insts                                       15162                       # Number of instructions simulated
 sim_ops                                         15162                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             19072                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst             19008                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data              8832                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                27904                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        19072                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           19072                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst                298                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total                27840                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        19008                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           19008                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                297                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                138                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                   436                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            688395596                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            318787223                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1007182819                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       688395596                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          688395596                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           688395596                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           318787223                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1007182819                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.num_reads::total                   435                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst            685590622                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            318557259                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1004147881                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       685590622                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          685590622                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           685590622                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           318557259                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1004147881                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           436                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                         436                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        27671500                       # Total gap between requests
+system.physmem.totGap                        27691500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -90,10 +90,10 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       275                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       274                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::1                       117                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        32                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        10                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        11                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
@@ -154,55 +154,76 @@ system.physmem.wrQLenPdf::28                        0                       # Wh
 system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples           64                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean             385                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     202.743118                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     502.320204                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64                21     32.81%     32.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128               10     15.62%     48.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192                5      7.81%     56.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256                8     12.50%     68.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320                2      3.12%     71.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384                2      3.12%     75.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448                2      3.12%     78.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512                1      1.56%     79.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576                1      1.56%     81.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640                1      1.56%     82.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704                1      1.56%     84.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768                1      1.56%     85.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088               2      3.12%     89.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152               2      3.12%     92.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600               1      1.56%     93.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664               1      1.56%     95.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856               2      3.12%     98.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2048               1      1.56%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total             64                       # Bytes accessed per row activation
-system.physmem.totQLat                        2393750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  10830000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples           36                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      487.111111                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     330.231493                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     390.430808                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127              3      8.33%      8.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255            9     25.00%     33.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383            8     22.22%     55.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            2      5.56%     61.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            2      5.56%     66.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            1      2.78%     69.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151           11     30.56%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total             36                       # Bytes accessed per row activation
+system.physmem.totQLat                        2136500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  10682750                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      2180000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                     6256250                       # Total ticks spent accessing banks
-system.physmem.avgQLat                        5490.25                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    14349.20                       # Average bank access latency per DRAM burst
+system.physmem.totBankLat                     6366250                       # Total ticks spent accessing banks
+system.physmem.avgQLat                        4900.23                       # Average queueing delay per DRAM burst
+system.physmem.avgBankLat                    14601.49                       # Average bank access latency per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  24839.45                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        1007.18                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  24501.72                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        1006.46                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     1007.18                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     1006.46                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           7.87                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       7.87                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           7.86                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       7.86                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         0.39                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.48                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                        372                       # Number of row buffer hits during reads
+system.physmem.readRowHits                        362                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   85.32                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   83.03                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        63466.74                       # Average gap between requests
-system.physmem.pageHitRate                      85.32                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               4.29                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                   1004872767                       # Throughput (bytes/s)
+system.physmem.avgGap                        63512.61                       # Average gap between requests
+system.physmem.pageHitRate                      83.03                       # Row buffer hit rate, read and write combined
+system.physmem.prechargeAllPercent               4.51                       # Percentage of time for which DRAM has all the banks in precharge state
+system.membus.throughput                   1004147881                       # Throughput (bytes/s)
 system.membus.trans_dist::ReadReq                 351                       # Transaction distribution
 system.membus.trans_dist::ReadResp                350                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                85                       # Transaction distribution
@@ -213,9 +234,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
 system.membus.tot_pkt_size::total               27840                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.data_through_bus                  27840                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy              519000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy              519500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               1.9                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            4048750                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy            4047500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization             14.6                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                    5146                       # Number of BP lookups
@@ -228,7 +249,7 @@ system.cpu.branchPred.BTBHitPct             66.317073                       # BT
 system.cpu.branchPred.usedRAS                     174                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                  5                       # Number of incorrect RAS predictions.
 system.cpu.workload.num_syscalls                   18                       # Number of system calls
-system.cpu.numCycles                            55411                       # number of cpu cycles simulated
+system.cpu.numCycles                            55451                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.branch_predictor.predictedTaken         2893                       # Number of Branches Predicted As Taken (True).
@@ -250,12 +271,12 @@ system.cpu.execution_unit.executions            11045                       # Nu
 system.cpu.mult_div_unit.multiplies                 0                       # Number of Multipy Operations Executed
 system.cpu.mult_div_unit.divides                    0                       # Number of Divide Operations Executed
 system.cpu.contextSwitches                          1                       # Number of context switches
-system.cpu.threadCycles                         21832                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles                         21862                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
 system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled                             436                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           37843                       # Number of cycles cpu's stages were not processed
+system.cpu.timesIdled                             439                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           37883                       # Number of cycles cpu's stages were not processed
 system.cpu.runCycles                            17568                       # Number of cycles cpu stages are processed.
-system.cpu.activity                         31.704896                       # Percentage of cycles cpu is active
+system.cpu.activity                         31.682026                       # Percentage of cycles cpu is active
 system.cpu.comLoads                              2225                       # Number of Load instructions committed
 system.cpu.comStores                             1448                       # Number of Store instructions committed
 system.cpu.comBranches                           3358                       # Number of Branches instructions committed
@@ -267,39 +288,39 @@ system.cpu.committedInsts                       15162                       # Nu
 system.cpu.committedOps                         15162                       # Number of Ops committed (Per-Thread)
 system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
 system.cpu.committedInsts_total                 15162                       # Number of Instructions committed (Total)
-system.cpu.cpi                               3.654597                       # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi                               3.657235                       # CPI: Cycles Per Instruction (Per-Thread)
 system.cpu.smt_cpi                                nan                       # CPI: Total SMT-CPI
-system.cpu.cpi_total                         3.654597                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.273628                       # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.cpi_total                         3.657235                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.273431                       # IPC: Instructions Per Cycle (Per-Thread)
 system.cpu.smt_ipc                                nan                       # IPC: Total SMT-IPC
-system.cpu.ipc_total                         0.273628                       # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles                    41985                       # Number of cycles 0 instructions are processed.
+system.cpu.ipc_total                         0.273431                       # IPC: Total IPC of All Threads
+system.cpu.stage0.idleCycles                    42025                       # Number of cycles 0 instructions are processed.
 system.cpu.stage0.runCycles                     13426                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization               24.229846                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles                    46058                       # Number of cycles 0 instructions are processed.
+system.cpu.stage0.utilization               24.212368                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles                    46098                       # Number of cycles 0 instructions are processed.
 system.cpu.stage1.runCycles                      9353                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization               16.879320                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles                    46608                       # Number of cycles 0 instructions are processed.
+system.cpu.stage1.utilization               16.867144                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles                    46648                       # Number of cycles 0 instructions are processed.
 system.cpu.stage2.runCycles                      8803                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization               15.886737                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage3.idleCycles                    52533                       # Number of cycles 0 instructions are processed.
+system.cpu.stage2.utilization               15.875277                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles                    52573                       # Number of cycles 0 instructions are processed.
 system.cpu.stage3.runCycles                      2878                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage3.utilization                5.193915                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles                    46102                       # Number of cycles 0 instructions are processed.
+system.cpu.stage3.utilization                5.190168                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles                    46142                       # Number of cycles 0 instructions are processed.
 system.cpu.stage4.runCycles                      9309                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization               16.799913                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.utilization               16.787795                       # Percentage of cycles stage was utilized (processing insts).
 system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse           169.234439                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse           168.846335                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                3004                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               299                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs             10.046823                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   169.234439                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.082634                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.082634                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   168.846335                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.082444                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.082444                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          299                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           78                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          221                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           79                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          220                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.145996                       # Percentage of cache occupancy per task id
 system.cpu.icache.tags.tag_accesses              7069                       # Number of tag accesses
 system.cpu.icache.tags.data_accesses             7069                       # Number of data accesses
@@ -315,12 +336,12 @@ system.cpu.icache.demand_misses::cpu.inst          381                       # n
 system.cpu.icache.demand_misses::total            381                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          381                       # number of overall misses
 system.cpu.icache.overall_misses::total           381                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     26803000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     26803000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     26803000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     26803000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     26803000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     26803000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     25942000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     25942000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     25942000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     25942000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     25942000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     25942000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst         3385                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total         3385                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst         3385                       # number of demand (read+write) accesses
@@ -333,12 +354,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.112555
 system.cpu.icache.demand_miss_rate::total     0.112555                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.112555                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.112555                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70349.081365                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 70349.081365                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 70349.081365                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 70349.081365                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 70349.081365                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 70349.081365                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68089.238845                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 68089.238845                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 68089.238845                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 68089.238845                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 68089.238845                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 68089.238845                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -359,26 +380,26 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          301
 system.cpu.icache.demand_mshr_misses::total          301                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          301                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          301                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     20772000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     20772000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     20772000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     20772000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     20772000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     20772000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     20512000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     20512000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     20512000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     20512000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     20512000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     20512000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.088922                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.088922                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.088922                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.088922                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.088922                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.088922                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69009.966777                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69009.966777                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69009.966777                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 69009.966777                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69009.966777                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 69009.966777                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68146.179402                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68146.179402                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68146.179402                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 68146.179402                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68146.179402                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 68146.179402                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.throughput              1009492871                       # Throughput (bytes/s)
+system.cpu.toL2Bus.throughput              1008764653                       # Throughput (bytes/s)
 system.cpu.toL2Bus.trans_dist::ReadReq            354                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp           352                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           85                       # Transaction distribution
@@ -393,21 +414,21 @@ system.cpu.toL2Bus.data_through_bus             27968                       # To
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
 system.cpu.toL2Bus.reqLayer0.occupancy         219500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.8                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        501000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy        499500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          1.8                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        221750                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy        221500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.8                       # Layer utilization (%)
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          200.306060                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          199.869816                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  2                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              350                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.005714                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   168.564740                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    31.741320                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005144                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.000969                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.006113                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   168.179067                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    31.690749                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005132                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.000967                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.006100                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          350                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           90                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          260                       # Occupied blocks per task id
@@ -431,17 +452,17 @@ system.cpu.l2cache.demand_misses::total           437                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          299                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          138                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          437                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     20448500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      3701250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     24149750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      5902500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      5902500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     20448500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data      9603750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     30052250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     20448500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data      9603750                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     30052250                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     20188500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      3701000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     23889500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      6006500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      6006500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     20188500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      9707500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     29896000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     20188500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      9707500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     29896000                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst          301                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data           53                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total          354                       # number of ReadReq accesses(hits+misses)
@@ -464,17 +485,17 @@ system.cpu.l2cache.demand_miss_rate::total     0.995444                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.993355                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.995444                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68389.632107                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69834.905660                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 68607.244318                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69441.176471                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69441.176471                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68389.632107                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69592.391304                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 68769.450801                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68389.632107                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69592.391304                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 68769.450801                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67520.066890                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69830.188679                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 67867.897727                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70664.705882                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70664.705882                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67520.066890                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70344.202899                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 68411.899314                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67520.066890                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70344.202899                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 68411.899314                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -494,17 +515,17 @@ system.cpu.l2cache.demand_mshr_misses::total          437
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          299                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          138                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          437                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     16729000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      3042250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     19771250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      4860000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      4860000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     16729000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      7902250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     24631250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     16729000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      7902250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     24631250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     16473000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      3042500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     19515500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      4962500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      4962500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     16473000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      8005000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     24478000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     16473000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      8005000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     24478000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.993355                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.994350                       # mshr miss rate for ReadReq accesses
@@ -516,27 +537,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.995444
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.993355                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.995444                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55949.832776                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57400.943396                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56168.323864                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57176.470588                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57176.470588                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55949.832776                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57262.681159                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56364.416476                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55949.832776                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57262.681159                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56364.416476                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55093.645485                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57405.660377                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55441.761364                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58382.352941                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58382.352941                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55093.645485                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58007.246377                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56013.729977                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55093.645485                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58007.246377                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56013.729977                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            98.671839                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse            98.543212                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs                3193                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               138                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs             23.137681                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    98.671839                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.024090                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.024090                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data    98.543212                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.024058                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.024058                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          138                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           16                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          122                       # Occupied blocks per task id
@@ -561,14 +582,14 @@ system.cpu.dcache.demand_misses::cpu.data          480                       # n
 system.cpu.dcache.demand_misses::total            480                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data          480                       # number of overall misses
 system.cpu.dcache.overall_misses::total           480                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      4274250                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      4274250                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     25400750                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     25400750                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     29675000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     29675000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     29675000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     29675000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      4273500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      4273500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     25910250                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     25910250                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     30183750                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     30183750                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     30183750                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     30183750                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data         2225                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total         2225                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data         1442                       # number of WriteReq accesses(hits+misses)
@@ -587,19 +608,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.130897
 system.cpu.dcache.demand_miss_rate::total     0.130897                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.130897                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.130897                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73693.965517                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 73693.965517                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60191.350711                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 60191.350711                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 61822.916667                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 61822.916667                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 61822.916667                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 61822.916667                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs         1022                       # number of cycles access was blocked
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73681.034483                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 73681.034483                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61398.696682                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 61398.696682                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 62882.812500                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 62882.812500                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 62882.812500                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 62882.812500                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs         1097                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                33                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    30.969697                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    33.242424                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
@@ -619,14 +640,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          138
 system.cpu.dcache.demand_mshr_misses::total          138                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          138                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          138                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      3755750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      3755750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      5990500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      5990500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      9746250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      9746250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      9746250                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      9746250                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      3755500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      3755500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      6094500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      6094500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      9850000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      9850000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      9850000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      9850000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.023820                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.023820                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.058946                       # mshr miss rate for WriteReq accesses
@@ -635,14 +656,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.037633
 system.cpu.dcache.demand_mshr_miss_rate::total     0.037633                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.037633                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.037633                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70863.207547                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70863.207547                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70476.470588                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70476.470588                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        70625                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total        70625                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        70625                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total        70625                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70858.490566                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70858.490566                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        71700                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        71700                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71376.811594                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 71376.811594                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71376.811594                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 71376.811594                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 7bcabaaf65e9956bff5f394a29df60cde45e164c..48a264b11942b8245b8bd3645372bba861df78aa 100644 (file)
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000027                       # Number of seconds simulated
-sim_ticks                                    26616500                       # Number of ticks simulated
-final_tick                                   26616500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    26743500                       # Number of ticks simulated
+final_tick                                   26743500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  19079                       # Simulator instruction rate (inst/s)
-host_op_rate                                    19079                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               35176168                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 237844                       # Number of bytes of host memory used
-host_seconds                                     0.76                       # Real time elapsed on the host
+host_inst_rate                                  53060                       # Simulator instruction rate (inst/s)
+host_op_rate                                    53057                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               98286640                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 272776                       # Number of bytes of host memory used
+host_seconds                                     0.27                       # Real time elapsed on the host
 sim_insts                                       14436                       # Number of instructions simulated
 sim_ops                                         14436                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total           21440                       # Nu
 system.physmem.num_reads::cpu.inst                335                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                147                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   482                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            805515376                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            353464956                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1158980332                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       805515376                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          805515376                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           805515376                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           353464956                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1158980332                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            801690130                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            351786415                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1153476546                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       801690130                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          801690130                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           801690130                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           351786415                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1153476546                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           482                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                         482                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                        26455500                       # Total gap between requests
+system.physmem.totGap                        26582500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -90,9 +90,9 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       287                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       133                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        51                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       283                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       140                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        48                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         7                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         3                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
@@ -154,55 +154,77 @@ system.physmem.wrQLenPdf::28                        0                       # Wh
 system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples           69                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      386.782609                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     201.135099                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     508.628284                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64                23     33.33%     33.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128               10     14.49%     47.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192                9     13.04%     60.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256                6      8.70%     69.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320                2      2.90%     72.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384                2      2.90%     75.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512                2      2.90%     78.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640                2      2.90%     81.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704                1      1.45%     82.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768                1      1.45%     84.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832                2      2.90%     86.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024               1      1.45%     88.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088               2      2.90%     91.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344               1      1.45%     92.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600               1      1.45%     94.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1792               1      1.45%     95.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856               2      2.90%     98.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2176               1      1.45%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total             69                       # Bytes accessed per row activation
-system.physmem.totQLat                        2423000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  11611750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples           41                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean             448                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     298.774659                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     377.002918                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127              5     12.20%     12.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           12     29.27%     41.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383            7     17.07%     58.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            2      4.88%     63.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            2      4.88%     68.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            1      2.44%     70.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            2      4.88%     75.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151           10     24.39%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total             41                       # Bytes accessed per row activation
+system.physmem.totQLat                        2269000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  11609000                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      2410000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                     6778750                       # Total ticks spent accessing banks
-system.physmem.avgQLat                        5026.97                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    14063.80                       # Average bank access latency per DRAM burst
+system.physmem.totBankLat                     6930000                       # Total ticks spent accessing banks
+system.physmem.avgQLat                        4707.47                       # Average queueing delay per DRAM burst
+system.physmem.avgBankLat                    14377.59                       # Average bank access latency per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  24090.77                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                        1158.98                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  24085.06                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                        1153.48                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                     1158.98                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                     1153.48                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           9.05                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       9.05                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           9.01                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       9.01                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         0.44                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.51                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                        413                       # Number of row buffer hits during reads
+system.physmem.readRowHits                        403                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   85.68                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   83.61                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                        54886.93                       # Average gap between requests
-system.physmem.pageHitRate                      85.68                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               5.39                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                   1158980332                       # Throughput (bytes/s)
+system.physmem.avgGap                        55150.41                       # Average gap between requests
+system.physmem.pageHitRate                      83.61                       # Row buffer hit rate, read and write combined
+system.physmem.prechargeAllPercent               5.72                       # Percentage of time for which DRAM has all the banks in precharge state
+system.membus.throughput                   1153476546                       # Throughput (bytes/s)
 system.membus.trans_dist::ReadReq                 399                       # Transaction distribution
 system.membus.trans_dist::ReadResp                399                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                83                       # Transaction distribution
@@ -213,105 +235,105 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
 system.membus.tot_pkt_size::total               30848                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.data_through_bus                  30848                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy              610000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy              607500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               2.3                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            4495750                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization             16.9                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            4495000                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             16.8                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.branchPred.lookups                    6713                       # Number of BP lookups
-system.cpu.branchPred.condPredicted              4454                       # Number of conditional branches predicted
+system.cpu.branchPred.lookups                    6710                       # Number of BP lookups
+system.cpu.branchPred.condPredicted              4453                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect              1076                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups                 5019                       # Number of BTB lookups
+system.cpu.branchPred.BTBLookups                 5017                       # Number of BTB lookups
 system.cpu.branchPred.BTBHits                    2432                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             48.455868                       # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct             48.475184                       # BTB Hit Percentage
 system.cpu.branchPred.usedRAS                     444                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                168                       # Number of incorrect RAS predictions.
 system.cpu.workload.num_syscalls                   18                       # Number of system calls
-system.cpu.numCycles                            53234                       # number of cpu cycles simulated
+system.cpu.numCycles                            53488                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles              12410                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          31113                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        6713                       # Number of branches that fetch encountered
+system.cpu.fetch.icacheStallCycles              12425                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          31097                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        6710                       # Number of branches that fetch encountered
 system.cpu.fetch.predictedBranches               2876                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          9131                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                    3044                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles                   8795                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.Cycles                          9129                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                    3043                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles                   9229                       # Number of cycles fetch has spent blocked
 system.cpu.fetch.MiscStallCycles                    4                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingTrapStallCycles           921                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                      5379                       # Number of cache lines fetched
+system.cpu.fetch.CacheLines                      5378                       # Number of cache lines fetched
 system.cpu.fetch.IcacheSquashes                   469                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              33133                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.939034                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.131220                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples              33579                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.926085                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.119056                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                    24002     72.44%     72.44% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                     4510     13.61%     86.05% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      474      1.43%     87.48% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      392      1.18%     88.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      680      2.05%     90.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      706      2.13%     92.85% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      235      0.71%     93.56% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      253      0.76%     94.32% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     1881      5.68%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                    24450     72.81%     72.81% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                     4510     13.43%     86.24% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      474      1.41%     87.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      392      1.17%     88.82% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      680      2.03%     90.85% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      706      2.10%     92.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      235      0.70%     93.65% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      253      0.75%     94.40% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                     1879      5.60%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                33133                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.126104                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.584457                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                    12933                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                  9787                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      8343                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                   198                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                   1872                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts                  29008                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles                   1872                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                    13575                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                     503                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           8758                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      7952                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                   473                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  26657                       # Number of instructions processed by rename
+system.cpu.fetch.rateDist::total                33579                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.125449                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.581383                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                    12934                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                 10235                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      8342                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                   197                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                   1871                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts                  28992                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles                   1871                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                    13577                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                     435                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           9274                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                      7946                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                   476                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                  26641                       # Number of instructions processed by rename
 system.cpu.rename.IQFullEvents                      2                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents                   147                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands               23951                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 49456                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            40918                       # Number of integer rename lookups
+system.cpu.rename.LSQFullEvents                   148                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands               23939                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 49429                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            40899                       # Number of integer rename lookups
 system.cpu.rename.CommittedMaps                 13819                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                    10132                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps                    10120                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts                691                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts            694                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                      2734                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 3529                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                2285                       # Number of stores inserted to the mem dependence unit.
+system.cpu.rename.skidInsts                      2745                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads                 3528                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                2282                       # Number of stores inserted to the mem dependence unit.
 system.cpu.memDep0.conflictingLoads                 4                       # Number of conflicting loads.
 system.cpu.memDep0.conflictingStores                0                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                      22518                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsAdded                      22511                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqNonSpecInstsAdded                 655                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                     21122                       # Number of instructions issued
+system.cpu.iq.iqInstsIssued                     21117                       # Number of instructions issued
 system.cpu.iq.iqSquashedInstsIssued                97                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined            7904                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined         5498                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedInstsExamined            7892                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined         5484                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved            180                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         33133                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.637491                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.262113                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples         33579                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.628875                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.255627                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0               23891     72.11%     72.11% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                3555     10.73%     82.84% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                2321      7.01%     89.84% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                1704      5.14%     94.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 887      2.68%     97.66% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 470      1.42%     99.08% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 240      0.72%     99.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                  45      0.14%     99.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0               24339     72.48%     72.48% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                3553     10.58%     83.06% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                2322      6.92%     89.98% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                1704      5.07%     95.05% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 887      2.64%     97.69% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 469      1.40%     99.09% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 240      0.71%     99.81% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                  45      0.13%     99.94% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                  20      0.06%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           33133                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           33579                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntAlu                      46     31.29%     31.29% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                      0      0.00%     31.29% # attempts to use FU when none available
@@ -347,7 +369,7 @@ system.cpu.iq.fu_full::MemWrite                    75     51.02%    100.00% # at
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                 15651     74.10%     74.10% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                 15648     74.10%     74.10% # Type of FU issued
 system.cpu.iq.FU_type_0::IntMult                    0      0.00%     74.10% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     74.10% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     74.10% # Type of FU issued
@@ -377,39 +399,39 @@ system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     74.10% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     74.10% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     74.10% # Type of FU issued
 system.cpu.iq.FU_type_0::MemRead                 3362     15.92%     90.02% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                2109      9.98%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                2107      9.98%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                  21122                       # Type of FU issued
-system.cpu.iq.rate                           0.396776                       # Inst issue rate
+system.cpu.iq.FU_type_0::total                  21117                       # Type of FU issued
+system.cpu.iq.rate                           0.394799                       # Inst issue rate
 system.cpu.iq.fu_busy_cnt                         147                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.006960                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              75621                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             31103                       # Number of integer instruction queue writes
+system.cpu.iq.fu_busy_rate                   0.006961                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              76057                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             31084                       # Number of integer instruction queue writes
 system.cpu.iq.int_inst_queue_wakeup_accesses        19522                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                   0                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                  0                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                  21269                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                  21264                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                       0                       # Number of floating point alu accesses
 system.cpu.iew.lsq.thread0.forwLoads               29                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads         1304                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads         1303                       # Number of loads squashed
 system.cpu.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread0.memOrderViolation           26                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores          837                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores          834                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            1                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked            28                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked            26                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                   1872                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                     359                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                    19                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               24307                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                   1871                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                     286                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                    14                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts               24299                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts               399                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  3529                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                 2285                       # Number of dispatched store instructions
+system.cpu.iew.iewDispLoadInsts                  3528                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                 2282                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts                655                       # Number of dispatched non-speculative instructions
 system.cpu.iew.iewIQFullEvents                      3                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewLSQFullEvents                     0                       # Number of times the LSQ has become full, causing a stall
@@ -419,41 +441,41 @@ system.cpu.iew.predictedNotTakenIncorrect          946                       # N
 system.cpu.iew.branchMispredicts                 1210                       # Number of branch mispredicts detected at execute
 system.cpu.iew.iewExecutedInsts                 20074                       # Number of executed instructions
 system.cpu.iew.iewExecLoadInsts                  3202                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts              1048                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecSquashedInsts              1043                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                          1134                       # number of nop insts executed
+system.cpu.iew.exec_nop                          1133                       # number of nop insts executed
 system.cpu.iew.exec_refs                         5224                       # number of memory reference insts executed
 system.cpu.iew.exec_branches                     4239                       # Number of branches executed
 system.cpu.iew.exec_stores                       2022                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.377090                       # Inst execution rate
+system.cpu.iew.exec_rate                     0.375299                       # Inst execution rate
 system.cpu.iew.wb_sent                          19749                       # cumulative count of insts sent to commit
 system.cpu.iew.wb_count                         19522                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                      9120                       # num instructions producing a value
-system.cpu.iew.wb_consumers                     11235                       # num instructions consuming a value
+system.cpu.iew.wb_producers                      9122                       # num instructions producing a value
+system.cpu.iew.wb_consumers                     11233                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.366721                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.811749                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.364979                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.812072                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts            9047                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts            9039                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             475                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts              1076                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        31261                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.485013                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.183057                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples        31708                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.478176                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.176132                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0        23946     76.60%     76.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1         4068     13.01%     89.61% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2         1358      4.34%     93.96% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          764      2.44%     96.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          348      1.11%     97.51% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5          270      0.86%     98.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6          322      1.03%     99.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           68      0.22%     99.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0        24394     76.93%     76.93% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1         4067     12.83%     89.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2         1357      4.28%     94.04% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          765      2.41%     96.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          348      1.10%     97.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5          270      0.85%     98.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6          322      1.02%     99.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           68      0.21%     99.63% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::8          117      0.37%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        31261                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total        31708                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts                15162                       # Number of instructions committed
 system.cpu.commit.committedOps                  15162                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -466,22 +488,22 @@ system.cpu.commit.int_insts                     12174                       # Nu
 system.cpu.commit.function_calls                  187                       # Number of function calls committed.
 system.cpu.commit.bw_lim_events                   117                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                        54530                       # The number of ROB reads
-system.cpu.rob.rob_writes                       50298                       # The number of ROB writes
-system.cpu.timesIdled                             216                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           20101                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads                        54969                       # The number of ROB reads
+system.cpu.rob.rob_writes                       50281                       # The number of ROB writes
+system.cpu.timesIdled                             211                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           19909                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                       14436                       # Number of Instructions Simulated
 system.cpu.committedOps                         14436                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total                 14436                       # Number of Instructions Simulated
-system.cpu.cpi                               3.687587                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         3.687587                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.271180                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.271180                       # IPC: Total IPC of All Threads
+system.cpu.cpi                               3.705181                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         3.705181                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.269892                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.269892                       # IPC: Total IPC of All Threads
 system.cpu.int_regfile_reads                    32043                       # number of integer regfile reads
 system.cpu.int_regfile_writes                   17841                       # number of integer regfile writes
 system.cpu.misc_regfile_reads                    6919                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                    569                       # number of misc regfile writes
-system.cpu.toL2Bus.throughput              1163789379                       # Throughput (bytes/s)
+system.cpu.toL2Bus.throughput              1158262755                       # Throughput (bytes/s)
 system.cpu.toL2Bus.trans_dist::ReadReq            401                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadResp           401                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           83                       # Transaction distribution
@@ -496,61 +518,61 @@ system.cpu.toL2Bus.data_through_bus             30976                       # To
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
 system.cpu.toL2Bus.reqLayer0.occupancy         242000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.9                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy        564500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy        562250                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          2.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy        234250                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy        233750                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.9                       # Layer utilization (%)
 system.cpu.icache.tags.replacements                 0                       # number of replacements
-system.cpu.icache.tags.tagsinuse           187.514405                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                4872                       # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           187.339200                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                4870                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs               337                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             14.456973                       # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs             14.451039                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   187.514405                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.091560                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.091560                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   187.339200                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.091474                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.091474                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          337                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           92                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          245                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.164551                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses             11095                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses            11095                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst         4872                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            4872                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          4872                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             4872                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         4872                       # number of overall hits
-system.cpu.icache.overall_hits::total            4872                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          507                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           507                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          507                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            507                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          507                       # number of overall misses
-system.cpu.icache.overall_misses::total           507                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     31694500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     31694500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     31694500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     31694500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     31694500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     31694500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         5379                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         5379                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         5379                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         5379                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         5379                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         5379                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.094255                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.094255                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.094255                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.094255                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.094255                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.094255                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62513.806706                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 62513.806706                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 62513.806706                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 62513.806706                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 62513.806706                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 62513.806706                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses             11093                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses            11093                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst         4870                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            4870                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          4870                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             4870                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         4870                       # number of overall hits
+system.cpu.icache.overall_hits::total            4870                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          508                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           508                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          508                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            508                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          508                       # number of overall misses
+system.cpu.icache.overall_misses::total           508                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     31654500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     31654500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     31654500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     31654500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     31654500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     31654500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         5378                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         5378                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         5378                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         5378                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         5378                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         5378                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.094459                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.094459                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.094459                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.094459                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.094459                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.094459                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62312.007874                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 62312.007874                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 62312.007874                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 62312.007874                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 62312.007874                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 62312.007874                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -559,48 +581,48 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          170                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          170                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          170                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          170                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          170                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          170                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          171                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          171                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          171                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          171                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          171                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          171                       # number of overall MSHR hits
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          337                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total          337                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst          337                       # number of demand (read+write) MSHR misses
 system.cpu.icache.demand_mshr_misses::total          337                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          337                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          337                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     22488500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     22488500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     22488500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     22488500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     22488500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     22488500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.062651                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.062651                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.062651                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.062651                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.062651                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.062651                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66731.454006                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66731.454006                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66731.454006                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 66731.454006                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66731.454006                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 66731.454006                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     22543250                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     22543250                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     22543250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     22543250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     22543250                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     22543250                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.062663                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.062663                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.062663                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.062663                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.062663                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.062663                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66893.916914                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66893.916914                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66893.916914                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 66893.916914                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66893.916914                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 66893.916914                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse          221.363231                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse          221.171170                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  2                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs              399                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.005013                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   186.907225                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data    34.456006                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005704                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.001052                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.006755                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   186.732473                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    34.438696                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005699                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.001051                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.006750                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          399                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          111                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          288                       # Occupied blocks per task id
@@ -624,17 +646,17 @@ system.cpu.l2cache.demand_misses::total           482                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          335                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          147                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          482                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     22131500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      5102250                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     27233750                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      5727000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      5727000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     22131500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data     10829250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     32960750                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     22131500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data     10829250                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     32960750                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     22186250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      4642250                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     26828500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      6101000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      6101000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     22186250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data     10743250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     32929500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     22186250                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data     10743250                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     32929500                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst          337                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data           64                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total          401                       # number of ReadReq accesses(hits+misses)
@@ -657,17 +679,17 @@ system.cpu.l2cache.demand_miss_rate::total     0.995868                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.994065                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.995868                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66064.179104                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79722.656250                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 68255.012531                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        69000                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total        69000                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66064.179104                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73668.367347                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 68383.298755                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66064.179104                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73668.367347                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 68383.298755                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66227.611940                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72535.156250                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 67239.348371                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73506.024096                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73506.024096                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66227.611940                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73083.333333                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 68318.464730                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66227.611940                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73083.333333                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 68318.464730                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -687,17 +709,17 @@ system.cpu.l2cache.demand_mshr_misses::total          482
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          335                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          147                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          482                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     17918000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      4316250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     22234250                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      4712000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      4712000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     17918000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      9028250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     26946250                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     17918000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      9028250                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     26946250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     17979250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      3856250                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     21835500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      5083000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      5083000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     17979250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      8939250                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     26918500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     17979250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      8939250                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     26918500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.994065                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.995012                       # mshr miss rate for ReadReq accesses
@@ -709,27 +731,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.995868
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.994065                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.995868                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53486.567164                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67441.406250                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55724.937343                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56771.084337                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56771.084337                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53486.567164                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61416.666667                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55905.082988                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53486.567164                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61416.666667                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55905.082988                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53669.402985                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60253.906250                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54725.563910                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61240.963855                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61240.963855                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53669.402985                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60811.224490                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55847.510373                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53669.402985                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60811.224490                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55847.510373                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse            99.106073                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse            99.038544                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs                4001                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs               147                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs             27.217687                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data    99.106073                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.024196                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.024196                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data    99.038544                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.024179                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.024179                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          147                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           23                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          124                       # Occupied blocks per task id
@@ -754,14 +776,14 @@ system.cpu.dcache.demand_misses::cpu.data          535                       # n
 system.cpu.dcache.demand_misses::total            535                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data          535                       # number of overall misses
 system.cpu.dcache.overall_misses::total           535                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      8431750                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      8431750                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     24708724                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     24708724                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     33140474                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     33140474                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     33140474                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     33140474                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      7972250                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      7972250                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     25777976                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     25777976                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     33750226                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     33750226                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     33750226                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     33750226                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data         3088                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total         3088                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data         1442                       # number of WriteReq accesses(hits+misses)
@@ -780,19 +802,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.118102
 system.cpu.dcache.demand_miss_rate::total     0.118102                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.118102                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.118102                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66918.650794                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 66918.650794                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60412.528117                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 60412.528117                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 61944.811215                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 61944.811215                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 61944.811215                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 61944.811215                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs          729                       # number of cycles access was blocked
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63271.825397                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 63271.825397                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63026.836186                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 63026.836186                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 63084.534579                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 63084.534579                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 63084.534579                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 63084.534579                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs          792                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                28                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                26                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    26.035714                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    30.461538                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
@@ -812,14 +834,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          147
 system.cpu.dcache.demand_mshr_misses::total          147                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          147                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          147                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      5166750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      5166750                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      5811000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      5811000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     10977750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     10977750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     10977750                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     10977750                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4706750                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      4706750                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      6185000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      6185000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     10891750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     10891750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     10891750                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     10891750                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.020725                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.020725                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.057559                       # mshr miss rate for WriteReq accesses
@@ -828,14 +850,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.032450
 system.cpu.dcache.demand_mshr_miss_rate::total     0.032450                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.032450                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.032450                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80730.468750                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80730.468750                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70012.048193                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70012.048193                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74678.571429                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 74678.571429                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74678.571429                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 74678.571429                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73542.968750                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73542.968750                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74518.072289                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74518.072289                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74093.537415                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 74093.537415                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74093.537415                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 74093.537415                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index db4434e5e60a8b57b1a4a9dd4321dc739f740b26..7012b3f19c85f4b16fe970bc60c3502ef5bee293 100644 (file)
@@ -1,64 +1,64 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000111                       # Number of seconds simulated
-sim_ticks                                   111025500                       # Number of ticks simulated
-final_tick                                  111025500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                   110955500                       # Number of ticks simulated
+final_tick                                  110955500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  93081                       # Simulator instruction rate (inst/s)
-host_op_rate                                    93081                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                9906240                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 253180                       # Number of bytes of host memory used
-host_seconds                                    11.21                       # Real time elapsed on the host
-sim_insts                                     1043212                       # Number of instructions simulated
-sim_ops                                       1043212                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 120250                       # Simulator instruction rate (inst/s)
+host_op_rate                                   120250                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               12800201                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 288992                       # Number of bytes of host memory used
+host_seconds                                     8.67                       # Real time elapsed on the host
+sim_insts                                     1042358                       # Number of instructions simulated
+sim_ops                                       1042358                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu0.inst            22784                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.data            10752                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.inst              640                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.data              832                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst             4672                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst             4608                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu2.data             1280                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.inst              384                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.inst              448                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu3.data              832                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                42176                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read::cpu0.inst        22784                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::cpu1.inst          640                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst         4672                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu3.inst          384                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst         4608                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu3.inst          448                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total           28480                       # Number of instructions bytes read from this memory
 system.physmem.num_reads::cpu0.inst               356                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.data               168                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.inst                10                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.data                13                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst                73                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst                72                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu2.data                20                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.inst                 6                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.inst                 7                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu3.data                13                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   659                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu0.inst           205214117                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            96842617                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst             5764442                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             7493774                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst            42080423                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data            11528883                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst             3458665                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data             7493774                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               379876695                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst      205214117                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst        5764442                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst       42080423                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst        3458665                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          256517647                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst          205214117                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           96842617                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst            5764442                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            7493774                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst           42080423                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data           11528883                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst            3458665                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data            7493774                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              379876695                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst           205343584                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data            96903714                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst             5768078                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             7498502                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst            41530163                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data            11536156                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.inst             4037655                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.data             7498502                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               380116353                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst      205343584                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst        5768078                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst       41530163                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu3.inst        4037655                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          256679480                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst          205343584                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           96903714                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst            5768078                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            7498502                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst           41530163                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data           11536156                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.inst            4037655                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.data            7498502                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              380116353                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           660                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                         660                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -70,7 +70,7 @@ system.physmem.bytesReadSys                     42240                       # To
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs             76                       # Number of requests that are neither read nor write
+system.physmem.neitherReadNorWriteReqs             77                       # Number of requests that are neither read nor write
 system.physmem.perBankRdBursts::0                 115                       # Per bank write bursts
 system.physmem.perBankRdBursts::1                  39                       # Per bank write bursts
 system.physmem.perBankRdBursts::2                  29                       # Per bank write bursts
@@ -105,7 +105,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                       110997500                       # Total gap between requests
+system.physmem.totGap                       110927500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -120,9 +120,9 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                       408                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       191                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        49                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                       409                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       188                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        51                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                        10                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -184,148 +184,172 @@ system.physmem.wrQLenPdf::28                        0                       # Wh
 system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          151                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      260.662252                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     168.685653                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     287.368727                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64                56     37.09%     37.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128               15      9.93%     47.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192               26     17.22%     64.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256                9      5.96%     70.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320               10      6.62%     76.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384                7      4.64%     81.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448                4      2.65%     84.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512                6      3.97%     88.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576                3      1.99%     90.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640                3      1.99%     92.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704                2      1.32%     93.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768                2      1.32%     94.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832                3      1.99%     96.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024               2      1.32%     98.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152               1      0.66%     98.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536               1      0.66%     99.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984               1      0.66%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            151                       # Bytes accessed per row activation
-system.physmem.totQLat                        4008250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                  18157000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples           89                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      285.483146                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     186.878201                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     280.642368                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127             28     31.46%     31.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255           26     29.21%     60.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           13     14.61%     75.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511            5      5.62%     80.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639            5      5.62%     86.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767            3      3.37%     89.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895            2      2.25%     92.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023            1      1.12%     93.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151            6      6.74%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total             89                       # Bytes accessed per row activation
+system.physmem.totQLat                        3793500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  17983500                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                      3300000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                    10848750                       # Total ticks spent accessing banks
-system.physmem.avgQLat                        6073.11                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    16437.50                       # Average bank access latency per DRAM burst
+system.physmem.totBankLat                    10890000                       # Total ticks spent accessing banks
+system.physmem.avgQLat                        5747.73                       # Average queueing delay per DRAM burst
+system.physmem.avgBankLat                    16500.00                       # Average bank access latency per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  27510.61                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         380.45                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  27247.73                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         380.69                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      380.45                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      380.69                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           2.97                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       2.97                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         0.16                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.21                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                        509                       # Number of row buffer hits during reads
+system.physmem.readRowHits                        505                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   77.12                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   76.52                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                       168178.03                       # Average gap between requests
-system.physmem.pageHitRate                      77.12                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent              11.34                       # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput                    379876695                       # Throughput (bytes/s)
+system.physmem.avgGap                       168071.97                       # Average gap between requests
+system.physmem.pageHitRate                      76.52                       # Row buffer hit rate, read and write combined
+system.physmem.prechargeAllPercent               9.12                       # Percentage of time for which DRAM has all the banks in precharge state
+system.membus.throughput                    380116353                       # Throughput (bytes/s)
 system.membus.trans_dist::ReadReq                 529                       # Transaction distribution
 system.membus.trans_dist::ReadResp                528                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              289                       # Transaction distribution
-system.membus.trans_dist::UpgradeResp              76                       # Transaction distribution
-system.membus.trans_dist::ReadExReq               164                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq              287                       # Transaction distribution
+system.membus.trans_dist::UpgradeResp              77                       # Transaction distribution
+system.membus.trans_dist::ReadExReq               163                       # Transaction distribution
 system.membus.trans_dist::ReadExResp              131                       # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port         1717                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                   1717                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port         1715                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                   1715                       # Packet count per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port        42176                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size::total               42176                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.data_through_bus                  42176                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy              932000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy              925000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.8                       # Layer utilization (%)
-system.membus.respLayer1.occupancy            6290425                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy            6291924                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              5.7                       # Layer utilization (%)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.l2c.tags.replacements                        0                       # number of replacements
-system.l2c.tags.tagsinuse                  417.163639                       # Cycle average of tags in use
-system.l2c.tags.total_refs                       1442                       # Total number of references to valid blocks.
+system.l2c.tags.tagsinuse                  417.123879                       # Cycle average of tags in use
+system.l2c.tags.total_refs                       1443                       # Total number of references to valid blocks.
 system.l2c.tags.sampled_refs                      526                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                     2.741445                       # Average number of references to valid blocks.
+system.l2c.tags.avg_refs                     2.743346                       # Average number of references to valid blocks.
 system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks       0.799798                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst      285.086488                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data       58.417431                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst        7.543236                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data        0.694746                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst       55.417060                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data        5.409300                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.inst        3.063366                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.data        0.732215                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::writebacks       0.799384                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst      285.051208                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data       58.412458                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst        7.037952                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data        0.694517                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst       55.368542                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data        5.407900                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.inst        3.619836                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.data        0.732082                       # Average occupied blocks per requestor
 system.l2c.tags.occ_percent::writebacks      0.000012                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.inst       0.004350                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu0.data       0.000891                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst       0.000115                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.000107                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu1.data       0.000011                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst       0.000846                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.inst       0.000845                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu2.data       0.000083                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.inst       0.000047                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu3.inst       0.000055                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::cpu3.data       0.000011                       # Average percentage of cache occupancy
 system.l2c.tags.occ_percent::total           0.006365                       # Average percentage of cache occupancy
 system.l2c.tags.occ_task_id_blocks::1024          526                       # Occupied blocks per task id
 system.l2c.tags.age_task_id_blocks_1024::0           51                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1          293                       # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2          182                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1          295                       # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2          180                       # Occupied blocks per task id
 system.l2c.tags.occ_task_id_percent::1024     0.008026                       # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses                    18228                       # Number of tag accesses
-system.l2c.tags.data_accesses                   18228                       # Number of data accesses
+system.l2c.tags.tag_accesses                    18244                       # Number of tag accesses
+system.l2c.tags.data_accesses                   18244                       # Number of data accesses
 system.l2c.ReadReq_hits::cpu0.inst                229                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu0.data                  5                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst                412                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst                413                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu1.data                 11                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu2.inst                349                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu2.data                  5                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu3.inst                420                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu3.data                 11                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                   1442                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                   1443                       # number of ReadReq hits
 system.l2c.Writeback_hits::writebacks               1                       # number of Writeback hits
 system.l2c.Writeback_hits::total                    1                       # number of Writeback hits
 system.l2c.UpgradeReq_hits::cpu0.data               3                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::total                   3                       # number of UpgradeReq hits
 system.l2c.demand_hits::cpu0.inst                 229                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu0.data                   5                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst                 412                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst                 413                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu1.data                  11                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu2.inst                 349                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu2.data                   5                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu3.inst                 420                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu3.data                  11                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                    1442                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                    1443                       # number of demand (read+write) hits
 system.l2c.overall_hits::cpu0.inst                229                       # number of overall hits
 system.l2c.overall_hits::cpu0.data                  5                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst                412                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst                413                       # number of overall hits
 system.l2c.overall_hits::cpu1.data                 11                       # number of overall hits
 system.l2c.overall_hits::cpu2.inst                349                       # number of overall hits
 system.l2c.overall_hits::cpu2.data                  5                       # number of overall hits
 system.l2c.overall_hits::cpu3.inst                420                       # number of overall hits
 system.l2c.overall_hits::cpu3.data                 11                       # number of overall hits
-system.l2c.overall_hits::total                   1442                       # number of overall hits
+system.l2c.overall_hits::total                   1443                       # number of overall hits
 system.l2c.ReadReq_misses::cpu0.inst              359                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu0.data               74                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst               16                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst               15                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu1.data                1                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu2.inst               76                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu2.data                7                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3.inst                9                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu3.inst               10                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu3.data                1                       # number of ReadReq misses
 system.l2c.ReadReq_misses::total                  543                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data            21                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data            20                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2.data            17                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu3.data            18                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total                76                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu0.data            22                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data            19                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu2.data            16                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu3.data            20                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total                77                       # number of UpgradeReq misses
 system.l2c.ReadExReq_misses::cpu0.data             94                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::cpu1.data             12                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::cpu2.data             13                       # number of ReadExReq misses
@@ -333,70 +357,70 @@ system.l2c.ReadExReq_misses::cpu3.data             12                       # nu
 system.l2c.ReadExReq_misses::total                131                       # number of ReadExReq misses
 system.l2c.demand_misses::cpu0.inst               359                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu0.data               168                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst                16                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst                15                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu1.data                13                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu2.inst                76                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu2.data                20                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.inst                 9                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu3.inst                10                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu3.data                13                       # number of demand (read+write) misses
 system.l2c.demand_misses::total                   674                       # number of demand (read+write) misses
 system.l2c.overall_misses::cpu0.inst              359                       # number of overall misses
 system.l2c.overall_misses::cpu0.data              168                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst               16                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst               15                       # number of overall misses
 system.l2c.overall_misses::cpu1.data               13                       # number of overall misses
 system.l2c.overall_misses::cpu2.inst               76                       # number of overall misses
 system.l2c.overall_misses::cpu2.data               20                       # number of overall misses
-system.l2c.overall_misses::cpu3.inst                9                       # number of overall misses
+system.l2c.overall_misses::cpu3.inst               10                       # number of overall misses
 system.l2c.overall_misses::cpu3.data               13                       # number of overall misses
 system.l2c.overall_misses::total                  674                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.inst     24802000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.inst     24538000                       # number of ReadReq miss cycles
 system.l2c.ReadReq_miss_latency::cpu0.data      5612000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst      1162500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst      1134000                       # number of ReadReq miss cycles
 system.l2c.ReadReq_miss_latency::cpu1.data        74500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.inst      5361500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.inst      5318500                       # number of ReadReq miss cycles
 system.l2c.ReadReq_miss_latency::cpu2.data       495250                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu3.inst       583750                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu3.inst       658250                       # number of ReadReq miss cycles
 system.l2c.ReadReq_miss_latency::cpu3.data        74500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total       38166000                       # number of ReadReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data      6725000                       # number of ReadExReq miss cycles
+system.l2c.ReadReq_miss_latency::total       37905000                       # number of ReadReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data      6786000                       # number of ReadExReq miss cycles
 system.l2c.ReadExReq_miss_latency::cpu1.data       852250                       # number of ReadExReq miss cycles
 system.l2c.ReadExReq_miss_latency::cpu2.data      1087000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu3.data       957750                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total      9622000                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.inst     24802000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data     12337000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst      1162500                       # number of demand (read+write) miss cycles
+system.l2c.ReadExReq_miss_latency::cpu3.data       978750                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total      9704000                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu0.inst     24538000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data     12398000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst      1134000                       # number of demand (read+write) miss cycles
 system.l2c.demand_miss_latency::cpu1.data       926750                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.inst      5361500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.inst      5318500                       # number of demand (read+write) miss cycles
 system.l2c.demand_miss_latency::cpu2.data      1582250                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.inst       583750                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.data      1032250                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total        47788000                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.inst     24802000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data     12337000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst      1162500                       # number of overall miss cycles
+system.l2c.demand_miss_latency::cpu3.inst       658250                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3.data      1053250                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total        47609000                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.inst     24538000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data     12398000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst      1134000                       # number of overall miss cycles
 system.l2c.overall_miss_latency::cpu1.data       926750                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.inst      5361500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.inst      5318500                       # number of overall miss cycles
 system.l2c.overall_miss_latency::cpu2.data      1582250                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.inst       583750                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.data      1032250                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total       47788000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.inst       658250                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.data      1053250                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total       47609000                       # number of overall miss cycles
 system.l2c.ReadReq_accesses::cpu0.inst            588                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::cpu0.data             79                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::cpu1.inst            428                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::cpu1.data             12                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::cpu2.inst            425                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::cpu2.data             12                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu3.inst            429                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu3.inst            430                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::cpu3.data             12                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total               1985                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total               1986                       # number of ReadReq accesses(hits+misses)
 system.l2c.Writeback_accesses::writebacks            1                       # number of Writeback accesses(hits+misses)
 system.l2c.Writeback_accesses::total                1                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data           24                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data           20                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2.data           17                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu3.data           18                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total              79                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data           25                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data           19                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu2.data           16                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu3.data           20                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total              80                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::cpu0.data           94                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::cpu1.data           12                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::cpu2.data           13                       # number of ReadExReq accesses(hits+misses)
@@ -408,32 +432,32 @@ system.l2c.demand_accesses::cpu1.inst             428                       # nu
 system.l2c.demand_accesses::cpu1.data              24                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::cpu2.inst             425                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::cpu2.data              25                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.inst             429                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.inst             430                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::cpu3.data              24                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total                2116                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total                2117                       # number of demand (read+write) accesses
 system.l2c.overall_accesses::cpu0.inst            588                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::cpu0.data            173                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::cpu1.inst            428                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::cpu1.data             24                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::cpu2.inst            425                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::cpu2.data             25                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.inst            429                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.inst            430                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::cpu3.data             24                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total               2116                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total               2117                       # number of overall (read+write) accesses
 system.l2c.ReadReq_miss_rate::cpu0.inst      0.610544                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu0.data      0.936709                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.037383                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst      0.035047                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu1.data      0.083333                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu2.inst      0.178824                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu2.data      0.583333                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu3.inst      0.020979                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu3.inst      0.023256                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu3.data      0.083333                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.273552                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.875000                       # miss rate for UpgradeReq accesses
+system.l2c.ReadReq_miss_rate::total          0.273414                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.880000                       # miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_miss_rate::cpu2.data            1                       # miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_miss_rate::cpu3.data            1                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.962025                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.962500                       # miss rate for UpgradeReq accesses
 system.l2c.ReadExReq_miss_rate::cpu0.data            1                       # miss rate for ReadExReq accesses
 system.l2c.ReadExReq_miss_rate::cpu1.data            1                       # miss rate for ReadExReq accesses
 system.l2c.ReadExReq_miss_rate::cpu2.data            1                       # miss rate for ReadExReq accesses
@@ -441,54 +465,54 @@ system.l2c.ReadExReq_miss_rate::cpu3.data            1                       # m
 system.l2c.ReadExReq_miss_rate::total               1                       # miss rate for ReadExReq accesses
 system.l2c.demand_miss_rate::cpu0.inst       0.610544                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu0.data       0.971098                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.037383                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.035047                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu1.data       0.541667                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu2.inst       0.178824                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu2.data       0.800000                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.inst       0.020979                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.inst       0.023256                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu3.data       0.541667                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.318526                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.318375                       # miss rate for demand accesses
 system.l2c.overall_miss_rate::cpu0.inst      0.610544                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu0.data      0.971098                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.037383                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.035047                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu1.data      0.541667                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu2.inst      0.178824                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu2.data      0.800000                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.inst      0.020979                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.inst      0.023256                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu3.data      0.541667                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.318526                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 69086.350975                       # average ReadReq miss latency
+system.l2c.overall_miss_rate::total          0.318375                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu0.inst 68350.974930                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu0.data 75837.837838                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72656.250000                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst        75600                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu1.data        74500                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.inst 70546.052632                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.inst 69980.263158                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu2.data        70750                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu3.inst 64861.111111                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu3.inst        65825                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu3.data        74500                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 70287.292818                       # average ReadReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 71542.553191                       # average ReadExReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 69806.629834                       # average ReadReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 72191.489362                       # average ReadExReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::cpu1.data 71020.833333                       # average ReadExReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::cpu2.data 83615.384615                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu3.data 79812.500000                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 73450.381679                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 69086.350975                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 73434.523810                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 72656.250000                       # average overall miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu3.data 81562.500000                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 74076.335878                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 68350.974930                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 73797.619048                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst        75600                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu1.data 71288.461538                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.inst 70546.052632                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.inst 69980.263158                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu2.data 79112.500000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.inst 64861.111111                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.data 79403.846154                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 70902.077151                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 69086.350975                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 73434.523810                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 72656.250000                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.inst        65825                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.data 81019.230769                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 70636.498516                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 68350.974930                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 73797.619048                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst        75600                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu1.data 71288.461538                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.inst 70546.052632                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.inst 69980.263158                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu2.data 79112.500000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.inst 64861.111111                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.data 79403.846154                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 70902.077151                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.inst        65825                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.data 81019.230769                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 70636.498516                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -498,34 +522,34 @@ system.l2c.avg_blocked_cycles::no_targets          nan                       # a
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
 system.l2c.ReadReq_mshr_hits::cpu0.inst             2                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.inst             6                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu2.inst             3                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu1.inst             5                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu2.inst             4                       # number of ReadReq MSHR hits
 system.l2c.ReadReq_mshr_hits::cpu3.inst             3                       # number of ReadReq MSHR hits
 system.l2c.ReadReq_mshr_hits::total                14                       # number of ReadReq MSHR hits
 system.l2c.demand_mshr_hits::cpu0.inst              2                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst              6                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu2.inst              3                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.inst              5                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu2.inst              4                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_hits::cpu3.inst              3                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_hits::total                 14                       # number of demand (read+write) MSHR hits
 system.l2c.overall_mshr_hits::cpu0.inst             2                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst             6                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu2.inst             3                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.inst             5                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu2.inst             4                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::cpu3.inst             3                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::total                14                       # number of overall MSHR hits
 system.l2c.ReadReq_mshr_misses::cpu0.inst          357                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu0.data           74                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu1.inst           10                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu1.data            1                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.inst           73                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.inst           72                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu2.data            7                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu3.inst            6                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu3.inst            7                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu3.data            1                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::total             529                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data           21                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data           20                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu2.data           17                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu3.data           18                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total           76                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data           22                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data           19                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu2.data           16                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu3.data           20                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total           77                       # number of UpgradeReq MSHR misses
 system.l2c.ReadExReq_mshr_misses::cpu0.data           94                       # number of ReadExReq MSHR misses
 system.l2c.ReadExReq_mshr_misses::cpu1.data           12                       # number of ReadExReq MSHR misses
 system.l2c.ReadExReq_mshr_misses::cpu2.data           13                       # number of ReadExReq MSHR misses
@@ -535,71 +559,71 @@ system.l2c.demand_mshr_misses::cpu0.inst          357                       # nu
 system.l2c.demand_mshr_misses::cpu0.data          168                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu1.inst           10                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu1.data           13                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.inst           73                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.inst           72                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu2.data           20                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu3.inst            6                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu3.inst            7                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu3.data           13                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::total              660                       # number of demand (read+write) MSHR misses
 system.l2c.overall_mshr_misses::cpu0.inst          357                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu0.data          168                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu1.inst           10                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu1.data           13                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.inst           73                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.inst           72                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu2.data           20                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu3.inst            6                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu3.inst            7                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu3.data           13                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::total             660                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst     20238250                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst     19975750                       # number of ReadReq MSHR miss cycles
 system.l2c.ReadReq_mshr_miss_latency::cpu0.data      4701500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst       676500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst       711000                       # number of ReadReq MSHR miss cycles
 system.l2c.ReadReq_mshr_miss_latency::cpu1.data        62500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.inst      4287250                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.inst      4193250                       # number of ReadReq MSHR miss cycles
 system.l2c.ReadReq_mshr_miss_latency::cpu2.data       408750                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu3.inst       369250                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu3.inst       431250                       # number of ReadReq MSHR miss cycles
 system.l2c.ReadReq_mshr_miss_latency::cpu3.data        62500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total     30806500                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data       210021                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data       217519                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data       170017                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data       180018                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total       777575                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data      5552000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total     30546500                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data       220022                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data       199518                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data       160016                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data       200020                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total       779576                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data      5616500                       # number of ReadExReq MSHR miss cycles
 system.l2c.ReadExReq_mshr_miss_latency::cpu1.data       701750                       # number of ReadExReq MSHR miss cycles
 system.l2c.ReadExReq_mshr_miss_latency::cpu2.data       928000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu3.data       807250                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total      7989000                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst     20238250                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data     10253500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst       676500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu3.data       828750                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total      8075000                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst     19975750                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data     10318000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst       711000                       # number of demand (read+write) MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu1.data       764250                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.inst      4287250                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.inst      4193250                       # number of demand (read+write) MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu2.data      1336750                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.inst       369250                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.data       869750                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total     38795500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst     20238250                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data     10253500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst       676500                       # number of overall MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.inst       431250                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.data       891250                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total     38621500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst     19975750                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data     10318000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst       711000                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu1.data       764250                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.inst      4287250                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.inst      4193250                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu2.data      1336750                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.inst       369250                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.data       869750                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total     38795500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.inst       431250                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.data       891250                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total     38621500                       # number of overall MSHR miss cycles
 system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.607143                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.936709                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.023364                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.083333                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.171765                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.169412                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.583333                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu3.inst     0.013986                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu3.inst     0.016279                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::cpu3.data     0.083333                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.266499                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.875000                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.266365                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.880000                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.962025                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.962500                       # mshr miss rate for UpgradeReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for ReadExReq accesses
@@ -609,420 +633,419 @@ system.l2c.demand_mshr_miss_rate::cpu0.inst     0.607143                       #
 system.l2c.demand_mshr_miss_rate::cpu0.data     0.971098                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu1.inst     0.023364                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu1.data     0.541667                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.inst     0.171765                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst     0.169412                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu2.data     0.800000                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.inst     0.013986                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.inst     0.016279                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu3.data     0.541667                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.311909                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.311762                       # mshr miss rate for demand accesses
 system.l2c.overall_mshr_miss_rate::cpu0.inst     0.607143                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu0.data     0.971098                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu1.inst     0.023364                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu1.data     0.541667                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.inst     0.171765                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst     0.169412                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu2.data     0.800000                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.inst     0.013986                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.inst     0.016279                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu3.data     0.541667                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.311909                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 56689.775910                       # average ReadReq mshr miss latency
+system.l2c.overall_mshr_miss_rate::total     0.311762                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 55954.481793                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 63533.783784                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst        67650                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst        71100                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data        62500                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 58729.452055                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 58239.583333                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 58392.857143                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 61541.666667                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 61607.142857                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data        62500                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 58235.349716                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 57743.856333                       # average ReadReq mshr miss latency
 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data        10001                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10875.950000                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10500.947368                       # average UpgradeReq mshr miss latency
 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data        10001                       # average UpgradeReq mshr miss latency
 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data        10001                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10231.250000                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 59063.829787                       # average ReadExReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10124.363636                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data        59750                       # average ReadExReq mshr miss latency
 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58479.166667                       # average ReadExReq mshr miss latency
 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 71384.615385                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 67270.833333                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 60984.732824                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 56689.775910                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61032.738095                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst        67650                       # average overall mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 69062.500000                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 61641.221374                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 55954.481793                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61416.666667                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst        71100                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58788.461538                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 58729.452055                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 58239.583333                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu2.data 66837.500000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 61541.666667                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.data 66903.846154                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 58781.060606                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 56689.775910                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61032.738095                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst        67650                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 61607.142857                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.data 68557.692308                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 58517.424242                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 55954.481793                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61416.666667                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst        71100                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58788.461538                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 58729.452055                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 58239.583333                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu2.data 66837.500000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 61541.666667                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.data 66903.846154                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 58781.060606                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 61607.142857                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.data 68557.692308                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 58517.424242                       # average overall mshr miss latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.toL2Bus.throughput                  1689557804                       # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq               2542                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp              2541                       # Transaction distribution
+system.toL2Bus.throughput                  1688893295                       # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq               2536                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp              2535                       # Transaction distribution
 system.toL2Bus.trans_dist::Writeback                1                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq             292                       # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp            292                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq              389                       # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp             389                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq             290                       # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp            290                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq              392                       # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp             392                       # Transaction distribution
 system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side         1175                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side          591                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side          587                       # Packet count per connected master and slave (bytes)
 system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side          856                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side          373                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side          360                       # Packet count per connected master and slave (bytes)
 system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side          850                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side          367                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side          858                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side          348                       # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total                  5418                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side          371                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side          860                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side          356                       # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total                  5415                       # Packet count per connected master and slave (bytes)
 system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side        37568                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side        11136                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side        27392                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side         1536                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side        27200                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side         1600                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side        27456                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side        27520                       # Cumulative packet size per connected master and slave (bytes)
 system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side         1536                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size::total             135424                       # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus                135424                       # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus           52160                       # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy            1628974                       # Layer occupancy (ticks)
+system.toL2Bus.tot_pkt_size::total             135488                       # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus                135488                       # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus           51904                       # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy            1624976                       # Layer occupancy (ticks)
 system.toL2Bus.reqLayer0.utilization              1.5                       # Layer utilization (%)
 system.toL2Bus.respLayer0.occupancy           2704748                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer0.utilization             2.4                       # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy           1475514                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy           1464514                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer1.utilization             1.3                       # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy           1928994                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy           1928496                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer2.utilization             1.7                       # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy           1199245                       # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization             1.1                       # Layer utilization (%)
-system.toL2Bus.respLayer4.occupancy           1926995                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy           1148249                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.utilization             1.0                       # Layer utilization (%)
+system.toL2Bus.respLayer4.occupancy           1927493                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer4.utilization             1.7                       # Layer utilization (%)
-system.toL2Bus.respLayer5.occupancy           1183748                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer5.occupancy           1209236                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer5.utilization             1.1                       # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy           1932245                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer6.occupancy           1936745                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer6.utilization             1.7                       # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy           1115744                       # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.occupancy           1133252                       # Layer occupancy (ticks)
 system.toL2Bus.respLayer7.utilization             1.0                       # Layer utilization (%)
-system.cpu0.branchPred.lookups                  83087                       # Number of BP lookups
-system.cpu0.branchPred.condPredicted            80860                       # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect             1219                       # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups               80377                       # Number of BTB lookups
-system.cpu0.branchPred.BTBHits                  78332                       # Number of BTB hits
+system.cpu0.branchPred.lookups                  83023                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted            80825                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect             1218                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups               80352                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits                  78307                       # Number of BTB hits
 system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct            97.455740                       # BTB Hit Percentage
+system.cpu0.branchPred.BTBHitPct            97.454948                       # BTB Hit Percentage
 system.cpu0.branchPred.usedRAS                    512                       # Number of times the RAS was used to get a target.
 system.cpu0.branchPred.RASInCorrect               132                       # Number of incorrect RAS predictions.
 system.cpu0.workload.num_syscalls                  89                       # Number of system calls
-system.cpu0.numCycles                          222052                       # number of cpu cycles simulated
+system.cpu0.numCycles                          221912                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles             17259                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                        493192                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                      83087                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches             78844                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                       161829                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles                   3807                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.BlockedCycles                 13993                       # Number of cycles fetch has spent blocked
+system.cpu0.fetch.icacheStallCycles             17233                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                        492726                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                      83023                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches             78819                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                       161746                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles                   3811                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.BlockedCycles                 13929                       # Number of cycles fetch has spent blocked
 system.cpu0.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu0.fetch.PendingTrapStallCycles         1512                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.CacheLines                     5869                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes                  488                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.rateDist::samples            197038                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             2.503030                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            2.216871                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.CacheLines                     5835                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes                  493                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.rateDist::samples            196870                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             2.502799                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            2.215097                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0                   35209     17.87%     17.87% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                   80150     40.68%     58.55% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                     582      0.30%     58.84% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                     988      0.50%     59.34% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4                     452      0.23%     59.57% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5                   76210     38.68%     98.25% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6                     578      0.29%     98.54% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7                     364      0.18%     98.73% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8                    2505      1.27%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0                   35124     17.84%     17.84% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                   80120     40.70%     58.54% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                     578      0.29%     58.83% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                     973      0.49%     59.33% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4                     477      0.24%     59.57% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5                   76224     38.72%     98.29% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6                     570      0.29%     98.58% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7                     349      0.18%     98.75% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8                    2455      1.25%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total              197038                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.374178                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       2.221065                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles                   17851                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles                15597                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                   160862                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles                  288                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles                  2440                       # Number of cycles decode is squashing
-system.cpu0.decode.DecodedInsts                490280                       # Number of instructions handled by decode
-system.cpu0.rename.SquashCycles                  2440                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles                   18507                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles                    827                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles         14176                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                   160527                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles                  561                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts                487444                       # Number of instructions processed by rename
-system.cpu0.rename.IQFullEvents                     4                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LSQFullEvents                  187                       # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.RenamedOperands             333388                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups               972038                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups          734246                       # Number of integer rename lookups
-system.cpu0.rename.CommittedMaps               320411                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                   12977                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts               872                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts           895                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                     3641                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads              155927                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores              78789                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads            76026                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores           75860                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                    407640                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded                922                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                   405044                       # Number of instructions issued
+system.cpu0.fetch.rateDist::total              196870                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.374126                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       2.220367                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles                   17821                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles                15547                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                   160777                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles                  280                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles                  2445                       # Number of cycles decode is squashing
+system.cpu0.decode.DecodedInsts                489900                       # Number of instructions handled by decode
+system.cpu0.rename.SquashCycles                  2445                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles                   18476                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles                    865                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles         14063                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                   160426                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles                  595                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts                487057                       # Number of instructions processed by rename
+system.cpu0.rename.LSQFullEvents                  216                       # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.RenamedOperands             333048                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups               971305                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups          733660                       # Number of integer rename lookups
+system.cpu0.rename.CommittedMaps               320079                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                   12969                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts               866                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts           886                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                     3628                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads              155827                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores              78749                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads            76001                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores           75817                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                    407304                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded                910                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                   404579                       # Number of instructions issued
 system.cpu0.iq.iqSquashedInstsIssued              133                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined          10720                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined         9396                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved           363                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples       197038                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        2.055664                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.097184                       # Number of insts issued each cycle
+system.cpu0.iq.iqSquashedInstsExamined          10771                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined         9747                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved           351                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples       196870                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        2.055057                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.097769                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0              34076     17.29%     17.29% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1               4941      2.51%     19.80% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2              78065     39.62%     59.42% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3              77371     39.27%     98.69% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4               1552      0.79%     99.48% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5                667      0.34%     99.81% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6                262      0.13%     99.95% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0              34107     17.32%     17.32% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1               4943      2.51%     19.84% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2              77928     39.58%     59.42% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3              77295     39.26%     98.68% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4               1579      0.80%     99.48% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5                650      0.33%     99.81% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6                264      0.13%     99.95% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::7                 87      0.04%     99.99% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::8                 17      0.01%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total         197038                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total         196870                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu                     57     27.01%     27.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                     0      0.00%     27.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                      0      0.00%     27.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     27.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     27.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     27.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%     27.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     27.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     27.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     27.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     27.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     27.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     27.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     27.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     27.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%     27.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     27.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%     27.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     27.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     27.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     27.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     27.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     27.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     27.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     27.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     27.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     27.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     27.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     27.01% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead                    42     19.91%     46.92% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite                  112     53.08%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu                     57     25.68%     25.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                     0      0.00%     25.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                      0      0.00%     25.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     25.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     25.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     25.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%     25.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     25.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     25.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     25.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     25.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     25.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     25.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     25.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     25.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%     25.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     25.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%     25.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     25.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     25.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     25.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     25.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     25.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     25.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     25.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     25.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     25.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     25.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     25.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead                    53     23.87%     49.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite                  112     50.45%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu               171308     42.29%     42.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult                   0      0.00%     42.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     42.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     42.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     42.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     42.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     42.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     42.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     42.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     42.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     42.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     42.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     42.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     42.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     42.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     42.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     42.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     42.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     42.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     42.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     42.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     42.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     42.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     42.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     42.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     42.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     42.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     42.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     42.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead              155505     38.39%     80.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite              78231     19.31%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu               171055     42.28%     42.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult                   0      0.00%     42.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     42.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     42.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     42.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     42.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     42.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     42.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     42.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     42.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     42.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     42.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     42.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     42.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     42.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     42.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     42.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     42.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     42.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     42.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     42.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     42.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     42.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     42.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     42.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     42.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     42.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     42.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     42.28% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead              155363     38.40%     80.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite              78161     19.32%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total                405044                       # Type of FU issued
-system.cpu0.iq.rate                          1.824095                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                        211                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.000521                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads           1007470                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes           419326                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses       403231                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.FU_type_0::total                404579                       # Type of FU issued
+system.cpu0.iq.rate                          1.823151                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                        222                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.000549                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads           1006383                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes           419039                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses       402754                       # Number of integer instruction queue wakeup accesses
 system.cpu0.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
 system.cpu0.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
 system.cpu0.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses                405255                       # Number of integer alu accesses
+system.cpu0.iq.int_alu_accesses                404801                       # Number of integer alu accesses
 system.cpu0.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads           75609                       # Number of loads that had data forwarded from stores
+system.cpu0.iew.lsq.thread0.forwLoads           75529                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads         2132                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.squashedLoads         2198                       # Number of loads squashed
 system.cpu0.iew.lsq.thread0.ignoredResponses            4                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation           44                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores         1385                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation           54                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores         1428                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu0.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked           19                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.cacheBlocked           15                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles                  2440                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles                    371                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles                   29                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts             485139                       # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts              313                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts               155927                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts               78789                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts               806                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                    30                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewSquashCycles                  2445                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles                    405                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles                   36                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts             484766                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts              308                       # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts               155827                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts               78749                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts               798                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                    40                       # Number of times the IQ has become full, causing a stall
 system.cpu0.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents            44                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect           328                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect         1114                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts                1442                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts               403978                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts               155175                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts             1066                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.memOrderViolationEvents            54                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect           343                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect         1106                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts                1449                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts               403510                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts               155033                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts             1069                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                        76577                       # number of nop insts executed
-system.cpu0.iew.exec_refs                      233309                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches                   80250                       # Number of branches executed
-system.cpu0.iew.exec_stores                     78134                       # Number of stores executed
-system.cpu0.iew.exec_rate                    1.819295                       # Inst execution rate
-system.cpu0.iew.wb_sent                        403557                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                       403231                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                   238890                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                   241357                       # num instructions consuming a value
+system.cpu0.iew.exec_nop                        76552                       # number of nop insts executed
+system.cpu0.iew.exec_refs                      233092                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches                   80162                       # Number of branches executed
+system.cpu0.iew.exec_stores                     78059                       # Number of stores executed
+system.cpu0.iew.exec_rate                    1.818333                       # Inst execution rate
+system.cpu0.iew.wb_sent                        403084                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                       402754                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                   238663                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                   241120                       # num instructions consuming a value
 system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate                      1.815931                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.989779                       # average fanout of values written-back
+system.cpu0.iew.wb_rate                      1.814927                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.989810                       # average fanout of values written-back
 system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts          12132                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitSquashedInsts          12269                       # The number of squashed insts skipped by commit
 system.cpu0.commit.commitNonSpecStalls            559                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts             1219                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples       194598                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     2.430487                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     2.136021                       # Number of insts commited each cycle
+system.cpu0.commit.branchMispredicts             1218                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples       194425                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     2.430089                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     2.136483                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0        34535     17.75%     17.75% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1        80010     41.12%     58.86% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2         2413      1.24%     60.10% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0        34537     17.76%     17.76% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1        79950     41.12%     58.88% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2         2378      1.22%     60.11% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::3          690      0.35%     60.46% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4          532      0.27%     60.73% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5        75417     38.76%     99.49% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6          460      0.24%     99.72% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7          239      0.12%     99.84% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8          302      0.16%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4          530      0.27%     60.74% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5        75328     38.74%     99.48% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6          457      0.24%     99.71% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7          248      0.13%     99.84% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8          307      0.16%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total       194598                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts              472968                       # Number of instructions committed
-system.cpu0.commit.committedOps                472968                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total       194425                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts              472470                       # Number of instructions committed
+system.cpu0.commit.committedOps                472470                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                        231199                       # Number of memory references committed
-system.cpu0.commit.loads                       153795                       # Number of loads committed
+system.cpu0.commit.refs                        230950                       # Number of memory references committed
+system.cpu0.commit.loads                       153629                       # Number of loads committed
 system.cpu0.commit.membars                         84                       # Number of memory barriers committed
-system.cpu0.commit.branches                     79291                       # Number of branches committed
+system.cpu0.commit.branches                     79208                       # Number of branches committed
 system.cpu0.commit.fp_insts                         0                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                   318742                       # Number of committed integer instructions.
+system.cpu0.commit.int_insts                   318410                       # Number of committed integer instructions.
 system.cpu0.commit.function_calls                 223                       # Number of function calls committed.
-system.cpu0.commit.bw_lim_events                  302                       # number cycles where commit BW limit reached
+system.cpu0.commit.bw_lim_events                  307                       # number cycles where commit BW limit reached
 system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads                      678235                       # The number of ROB reads
-system.cpu0.rob.rob_writes                     972657                       # The number of ROB writes
-system.cpu0.timesIdled                            325                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                          25014                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.committedInsts                     396861                       # Number of Instructions Simulated
-system.cpu0.committedOps                       396861                       # Number of Ops (including micro ops) Simulated
-system.cpu0.committedInsts_total               396861                       # Number of Instructions Simulated
-system.cpu0.cpi                              0.559521                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        0.559521                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              1.787244                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        1.787244                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads                  722661                       # number of integer regfile reads
-system.cpu0.int_regfile_writes                 325753                       # number of integer regfile writes
+system.cpu0.rob.rob_reads                      677696                       # The number of ROB reads
+system.cpu0.rob.rob_writes                     971940                       # The number of ROB writes
+system.cpu0.timesIdled                            327                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                          25042                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.committedInsts                     396446                       # Number of Instructions Simulated
+system.cpu0.committedOps                       396446                       # Number of Ops (including micro ops) Simulated
+system.cpu0.committedInsts_total               396446                       # Number of Instructions Simulated
+system.cpu0.cpi                              0.559753                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        0.559753                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              1.786501                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        1.786501                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads                  721878                       # number of integer regfile reads
+system.cpu0.int_regfile_writes                 325337                       # number of integer regfile writes
 system.cpu0.fp_regfile_reads                      192                       # number of floating regfile reads
-system.cpu0.misc_regfile_reads                 235146                       # number of misc regfile reads
+system.cpu0.misc_regfile_reads                 234915                       # number of misc regfile reads
 system.cpu0.misc_regfile_writes                   564                       # number of misc regfile writes
 system.cpu0.icache.tags.replacements              297                       # number of replacements
-system.cpu0.icache.tags.tagsinuse          241.312438                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs               5113                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.tagsinuse          241.280038                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs               5079                       # Total number of references to valid blocks.
 system.cpu0.icache.tags.sampled_refs              587                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs             8.710392                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.avg_refs             8.652470                       # Average number of references to valid blocks.
 system.cpu0.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst   241.312438                       # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst     0.471313                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total     0.471313                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_blocks::cpu0.inst   241.280038                       # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst     0.471250                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.471250                       # Average percentage of cache occupancy
 system.cpu0.icache.tags.occ_task_id_blocks::1024          290                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::0           60                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::1          145                       # Occupied blocks per task id
 system.cpu0.icache.tags.age_task_id_blocks_1024::2           85                       # Occupied blocks per task id
 system.cpu0.icache.tags.occ_task_id_percent::1024     0.566406                       # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses             6456                       # Number of tag accesses
-system.cpu0.icache.tags.data_accesses            6456                       # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst         5113                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total           5113                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst         5113                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total            5113                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst         5113                       # number of overall hits
-system.cpu0.icache.overall_hits::total           5113                       # number of overall hits
+system.cpu0.icache.tags.tag_accesses             6422                       # Number of tag accesses
+system.cpu0.icache.tags.data_accesses            6422                       # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst         5079                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total           5079                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst         5079                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total            5079                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst         5079                       # number of overall hits
+system.cpu0.icache.overall_hits::total           5079                       # number of overall hits
 system.cpu0.icache.ReadReq_misses::cpu0.inst          756                       # number of ReadReq misses
 system.cpu0.icache.ReadReq_misses::total          756                       # number of ReadReq misses
 system.cpu0.icache.demand_misses::cpu0.inst          756                       # number of demand (read+write) misses
 system.cpu0.icache.demand_misses::total           756                       # number of demand (read+write) misses
 system.cpu0.icache.overall_misses::cpu0.inst          756                       # number of overall misses
 system.cpu0.icache.overall_misses::total          756                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst     35939745                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total     35939745                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst     35939745                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total     35939745                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst     35939745                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total     35939745                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst         5869                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total         5869                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst         5869                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total         5869                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst         5869                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total         5869                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.128812                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.128812                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.128812                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.128812                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.128812                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.128812                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 47539.345238                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 47539.345238                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 47539.345238                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 47539.345238                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 47539.345238                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 47539.345238                       # average overall miss latency
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst     35676245                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total     35676245                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst     35676245                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total     35676245                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst     35676245                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total     35676245                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst         5835                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total         5835                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst         5835                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total         5835                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst         5835                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total         5835                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.129563                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.129563                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.129563                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.129563                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.129563                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.129563                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 47190.800265                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 47190.800265                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 47190.800265                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 47190.800265                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 47190.800265                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 47190.800265                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1043,254 +1066,254 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst          588
 system.cpu0.icache.demand_mshr_misses::total          588                       # number of demand (read+write) MSHR misses
 system.cpu0.icache.overall_mshr_misses::cpu0.inst          588                       # number of overall MSHR misses
 system.cpu0.icache.overall_mshr_misses::total          588                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst     27686752                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total     27686752                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst     27686752                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total     27686752                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst     27686752                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total     27686752                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.100187                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.100187                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.100187                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.100187                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.100187                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.100187                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 47086.312925                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 47086.312925                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 47086.312925                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 47086.312925                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 47086.312925                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 47086.312925                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst     27430752                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total     27430752                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst     27430752                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total     27430752                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst     27430752                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total     27430752                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.100771                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.100771                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.100771                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.100771                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.100771                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.100771                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 46650.938776                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 46650.938776                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 46650.938776                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 46650.938776                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 46650.938776                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 46650.938776                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu0.dcache.tags.replacements                2                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse          142.026071                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs             155821                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.tagsinuse          142.009454                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs             155675                       # Total number of references to valid blocks.
 system.cpu0.dcache.tags.sampled_refs              170                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs           916.594118                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs           915.735294                       # Average number of references to valid blocks.
 system.cpu0.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data   142.026071                       # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data     0.277395                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total     0.277395                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data   142.009454                       # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data     0.277362                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.277362                       # Average percentage of cache occupancy
 system.cpu0.dcache.tags.occ_task_id_blocks::1024          168                       # Occupied blocks per task id
 system.cpu0.dcache.tags.age_task_id_blocks_1024::0           17                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1           51                       # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2          100                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1           52                       # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2           99                       # Occupied blocks per task id
 system.cpu0.dcache.tags.occ_task_id_percent::1024     0.328125                       # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses           627950                       # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses          627950                       # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data        79085                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total          79085                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data        76817                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total         76817                       # number of WriteReq hits
+system.cpu0.dcache.tags.tag_accesses           627368                       # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses          627368                       # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data        79025                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total          79025                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data        76734                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total         76734                       # number of WriteReq hits
 system.cpu0.dcache.SwapReq_hits::cpu0.data           21                       # number of SwapReq hits
 system.cpu0.dcache.SwapReq_hits::total             21                       # number of SwapReq hits
-system.cpu0.dcache.demand_hits::cpu0.data       155902                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total          155902                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data       155902                       # number of overall hits
-system.cpu0.dcache.overall_hits::total         155902                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data          420                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total          420                       # number of ReadReq misses
+system.cpu0.dcache.demand_hits::cpu0.data       155759                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total          155759                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data       155759                       # number of overall hits
+system.cpu0.dcache.overall_hits::total         155759                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data          418                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total          418                       # number of ReadReq misses
 system.cpu0.dcache.WriteReq_misses::cpu0.data          545                       # number of WriteReq misses
 system.cpu0.dcache.WriteReq_misses::total          545                       # number of WriteReq misses
 system.cpu0.dcache.SwapReq_misses::cpu0.data           21                       # number of SwapReq misses
 system.cpu0.dcache.SwapReq_misses::total           21                       # number of SwapReq misses
-system.cpu0.dcache.demand_misses::cpu0.data          965                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total           965                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data          965                       # number of overall misses
-system.cpu0.dcache.overall_misses::total          965                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data     13542707                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total     13542707                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data     32279504                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total     32279504                       # number of WriteReq miss cycles
+system.cpu0.dcache.demand_misses::cpu0.data          963                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total           963                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data          963                       # number of overall misses
+system.cpu0.dcache.overall_misses::total          963                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data     13454697                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total     13454697                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data     32621759                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total     32621759                       # number of WriteReq miss cycles
 system.cpu0.dcache.SwapReq_miss_latency::cpu0.data       404750                       # number of SwapReq miss cycles
 system.cpu0.dcache.SwapReq_miss_latency::total       404750                       # number of SwapReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data     45822211                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total     45822211                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data     45822211                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total     45822211                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data        79505                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total        79505                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data        77362                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total        77362                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.demand_miss_latency::cpu0.data     46076456                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total     46076456                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data     46076456                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total     46076456                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data        79443                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total        79443                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data        77279                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total        77279                       # number of WriteReq accesses(hits+misses)
 system.cpu0.dcache.SwapReq_accesses::cpu0.data           42                       # number of SwapReq accesses(hits+misses)
 system.cpu0.dcache.SwapReq_accesses::total           42                       # number of SwapReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data       156867                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total       156867                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data       156867                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total       156867                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.005283                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.005283                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.007045                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.007045                       # miss rate for WriteReq accesses
+system.cpu0.dcache.demand_accesses::cpu0.data       156722                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total       156722                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data       156722                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total       156722                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.005262                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.005262                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.007052                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.007052                       # miss rate for WriteReq accesses
 system.cpu0.dcache.SwapReq_miss_rate::cpu0.data     0.500000                       # miss rate for SwapReq accesses
 system.cpu0.dcache.SwapReq_miss_rate::total     0.500000                       # miss rate for SwapReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.006152                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.006152                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.006152                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.006152                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 32244.540476                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 32244.540476                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 59228.447706                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 59228.447706                       # average WriteReq miss latency
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.006145                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.006145                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.006145                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.006145                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 32188.270335                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 32188.270335                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 59856.438532                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 59856.438532                       # average WriteReq miss latency
 system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19273.809524                       # average SwapReq miss latency
 system.cpu0.dcache.SwapReq_avg_miss_latency::total 19273.809524                       # average SwapReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 47484.156477                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 47484.156477                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 47484.156477                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 47484.156477                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs          503                       # number of cycles access was blocked
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 47846.787124                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 47846.787124                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 47846.787124                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 47846.787124                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs          524                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs               21                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs               20                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs    23.952381                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs    26.200000                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.dcache.writebacks::writebacks            1                       # number of writebacks
 system.cpu0.dcache.writebacks::total                1                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data          227                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total          227                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data          373                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total          373                       # number of WriteReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data          230                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total          230                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data          370                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total          370                       # number of WriteReq MSHR hits
 system.cpu0.dcache.demand_mshr_hits::cpu0.data          600                       # number of demand (read+write) MSHR hits
 system.cpu0.dcache.demand_mshr_hits::total          600                       # number of demand (read+write) MSHR hits
 system.cpu0.dcache.overall_mshr_hits::cpu0.data          600                       # number of overall MSHR hits
 system.cpu0.dcache.overall_mshr_hits::total          600                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data          193                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total          193                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data          172                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total          172                       # number of WriteReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data          188                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total          188                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data          175                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total          175                       # number of WriteReq MSHR misses
 system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data           21                       # number of SwapReq MSHR misses
 system.cpu0.dcache.SwapReq_mshr_misses::total           21                       # number of SwapReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data          365                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total          365                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data          365                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total          365                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data      6251507                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total      6251507                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data      7188729                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total      7188729                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_misses::cpu0.data          363                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total          363                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data          363                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total          363                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data      6237508                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total      6237508                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data      7264228                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total      7264228                       # number of WriteReq MSHR miss cycles
 system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data       361250                       # number of SwapReq MSHR miss cycles
 system.cpu0.dcache.SwapReq_mshr_miss_latency::total       361250                       # number of SwapReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data     13440236                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total     13440236                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data     13440236                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total     13440236                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.002428                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.002428                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.002223                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.002223                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data     13501736                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total     13501736                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data     13501736                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total     13501736                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.002366                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.002366                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.002265                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.002265                       # mshr miss rate for WriteReq accesses
 system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data     0.500000                       # mshr miss rate for SwapReq accesses
 system.cpu0.dcache.SwapReq_mshr_miss_rate::total     0.500000                       # mshr miss rate for SwapReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.002327                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.002327                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.002327                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.002327                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 32391.227979                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 32391.227979                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41794.936047                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41794.936047                       # average WriteReq mshr miss latency
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.002316                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.002316                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.002316                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.002316                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 33178.234043                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 33178.234043                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41509.874286                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41509.874286                       # average WriteReq mshr miss latency
 system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17202.380952                       # average SwapReq mshr miss latency
 system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17202.380952                       # average SwapReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 36822.564384                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 36822.564384                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 36822.564384                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 36822.564384                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 37194.865014                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 37194.865014                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 37194.865014                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 37194.865014                       # average overall mshr miss latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups                  47485                       # Number of BP lookups
-system.cpu1.branchPred.condPredicted            44754                       # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect             1270                       # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups               41396                       # Number of BTB lookups
-system.cpu1.branchPred.BTBHits                  40599                       # Number of BTB hits
+system.cpu1.branchPred.lookups                  49230                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted            46482                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect             1275                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups               43125                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits                  42318                       # Number of BTB hits
 system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct            98.074693                       # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS                    654                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.BTBHitPct            98.128696                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS                    644                       # Number of times the RAS was used to get a target.
 system.cpu1.branchPred.RASInCorrect               232                       # Number of incorrect RAS predictions.
-system.cpu1.numCycles                          177933                       # number of cpu cycles simulated
+system.cpu1.numCycles                          177729                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles             31734                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                        260080                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                      47485                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches             41253                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                        95164                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles                   3727                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.BlockedCycles                 37889                       # Number of cycles fetch has spent blocked
+system.cpu1.fetch.icacheStallCycles             30707                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                        271510                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                      49230                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches             42962                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                        98061                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles                   3712                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.BlockedCycles                 35852                       # Number of cycles fetch has spent blocked
 system.cpu1.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.NoActiveThreadStallCycles         7775                       # Number of stall cycles due to no active thread to fetch from
+system.cpu1.fetch.NoActiveThreadStallCycles         7757                       # Number of stall cycles due to no active thread to fetch from
 system.cpu1.fetch.PendingTrapStallCycles          775                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.CacheLines                    23379                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes                  257                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.rateDist::samples            175722                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             1.480065                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            2.059330                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.CacheLines                    22354                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes                  259                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.rateDist::samples            175517                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             1.546916                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            2.089154                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0                   80558     45.84%     45.84% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                   49339     28.08%     73.92% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                    7969      4.54%     78.46% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                    3191      1.82%     80.27% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4                     687      0.39%     80.66% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5                   28723     16.35%     97.01% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6                    1207      0.69%     97.70% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7                     759      0.43%     98.13% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8                    3289      1.87%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0                   77456     44.13%     44.13% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                   50516     28.78%     72.91% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                    7423      4.23%     77.14% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                    3189      1.82%     78.96% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4                     704      0.40%     79.36% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5                   30974     17.65%     97.01% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6                    1193      0.68%     97.69% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7                     759      0.43%     98.12% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8                    3303      1.88%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total              175722                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.266870                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       1.461674                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                   38713                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles                32553                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                    87468                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles                 6833                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles                  2380                       # Number of cycles decode is squashing
-system.cpu1.decode.DecodedInsts                256418                       # Number of instructions handled by decode
-system.cpu1.rename.SquashCycles                  2380                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles                   39395                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles                  20083                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles         11723                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                    80903                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles                13463                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts                254199                       # Number of instructions processed by rename
+system.cpu1.fetch.rateDist::total              175517                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.276995                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       1.527663                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles                   37188                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles                31008                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                    90874                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles                 6330                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles                  2360                       # Number of cycles decode is squashing
+system.cpu1.decode.DecodedInsts                267842                       # Number of instructions handled by decode
+system.cpu1.rename.SquashCycles                  2360                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles                   37871                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles                  18552                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles         11702                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                    84813                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles                12462                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts                265527                       # Number of instructions processed by rename
 system.cpu1.rename.IQFullEvents                     1                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LSQFullEvents                   22                       # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.RenamedOperands             175957                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups               477753                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups          373133                       # Number of integer rename lookups
-system.cpu1.rename.CommittedMaps               162997                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                   12960                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts              1085                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts          1202                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                    16072                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads               69810                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores              31966                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads            34021                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores           26934                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                    208112                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded               8163                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                   211912                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued               84                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined          10867                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined        10947                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved           602                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples       175722                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        1.205950                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.291467                       # Number of insts issued each cycle
+system.cpu1.rename.LSQFullEvents                   21                       # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.RenamedOperands             184379                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups               502490                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups          391665                       # Number of integer rename lookups
+system.cpu1.rename.CommittedMaps               171551                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                   12828                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts              1100                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts          1220                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                    15186                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads               73774                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores              34232                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads            35732                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores           29187                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                    218298                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded               7639                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                   221677                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued               99                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined          10737                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined        10712                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved           591                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples       175517                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        1.262994                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.299330                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0              78073     44.43%     44.43% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1              27855     15.85%     60.28% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2              32175     18.31%     78.59% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3              32813     18.67%     97.26% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4               3279      1.87%     99.13% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5               1173      0.67%     99.80% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6                248      0.14%     99.94% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7                 49      0.03%     99.97% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0              74868     42.66%     42.66% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1              26303     14.99%     57.64% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2              34475     19.64%     77.28% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3              35103     20.00%     97.28% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4               3248      1.85%     99.13% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5               1161      0.66%     99.80% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6                252      0.14%     99.94% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7                 50      0.03%     99.97% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::8                 57      0.03%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total         175722                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total         175517                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IntAlu                     12      4.51%      4.51% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IntMult                     0      0.00%      4.51% # attempts to use FU when none available
@@ -1326,193 +1349,193 @@ system.cpu1.iq.fu_full::MemWrite                  210     78.95%    100.00% # at
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu               104746     49.43%     49.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult                   0      0.00%     49.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     49.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     49.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     49.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     49.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     49.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     49.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     49.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     49.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     49.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     49.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     49.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     49.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     49.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     49.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     49.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     49.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     49.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     49.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     49.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     49.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     49.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     49.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     49.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     49.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     49.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     49.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     49.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead               75888     35.81%     85.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite              31278     14.76%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu               108767     49.07%     49.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult                   0      0.00%     49.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     49.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     49.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     49.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     49.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     49.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     49.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     49.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     49.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     49.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     49.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     49.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     49.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     49.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     49.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     49.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     49.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     49.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     49.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     49.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     49.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     49.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     49.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     49.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     49.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     49.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     49.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     49.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead               79372     35.81%     84.87% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite              33538     15.13%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total                211912                       # Type of FU issued
-system.cpu1.iq.rate                          1.190965                       # Inst issue rate
+system.cpu1.iq.FU_type_0::total                221677                       # Type of FU issued
+system.cpu1.iq.rate                          1.247275                       # Inst issue rate
 system.cpu1.iq.fu_busy_cnt                        266                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.001255                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads            599896                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes           227186                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses       210068                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fu_busy_rate                  0.001200                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads            619236                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes           236717                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses       219849                       # Number of integer instruction queue wakeup accesses
 system.cpu1.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
 system.cpu1.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
 system.cpu1.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses                212178                       # Number of integer alu accesses
+system.cpu1.iq.int_alu_accesses                221943                       # Number of integer alu accesses
 system.cpu1.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads           26664                       # Number of loads that had data forwarded from stores
+system.cpu1.iew.lsq.thread0.forwLoads           28929                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads         2449                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.squashedLoads         2394                       # Number of loads squashed
 system.cpu1.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation           44                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores         1447                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation           43                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores         1444                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu1.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
 system.cpu1.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles                  2380                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles                    699                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles                   40                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts             251202                       # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts              408                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts                69810                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts               31966                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts              1044                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                    40                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewSquashCycles                  2360                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles                    686                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles                   42                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts             262595                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts              349                       # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts                73774                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts               34232                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts              1056                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                    42                       # Number of times the IQ has become full, causing a stall
 system.cpu1.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents            44                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect           470                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect          919                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts                1389                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts               210729                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts                68768                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts             1183                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.memOrderViolationEvents            43                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect           467                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect          918                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts                1385                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts               220501                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts                72766                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts             1176                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                        34927                       # number of nop insts executed
-system.cpu1.iew.exec_refs                       99964                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches                   44131                       # Number of branches executed
-system.cpu1.iew.exec_stores                     31196                       # Number of stores executed
-system.cpu1.iew.exec_rate                    1.184317                       # Inst execution rate
-system.cpu1.iew.wb_sent                        210356                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                       210068                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                   116711                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                   121376                       # num instructions consuming a value
+system.cpu1.iew.exec_nop                        36658                       # number of nop insts executed
+system.cpu1.iew.exec_refs                      106223                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches                   45902                       # Number of branches executed
+system.cpu1.iew.exec_stores                     33457                       # Number of stores executed
+system.cpu1.iew.exec_rate                    1.240659                       # Inst execution rate
+system.cpu1.iew.wb_sent                        220134                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                       219849                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                   122957                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                   127616                       # num instructions consuming a value
 system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate                      1.180602                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.961566                       # average fanout of values written-back
+system.cpu1.iew.wb_rate                      1.236990                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.963492                       # average fanout of values written-back
 system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts          12479                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls           7561                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts             1270                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples       165567                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     1.441743                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.939965                       # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts          12326                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls           7048                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts             1275                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples       165400                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     1.513005                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.970213                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0        77636     46.89%     46.89% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1        42274     25.53%     72.42% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2         6096      3.68%     76.11% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3         8474      5.12%     81.22% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4         1557      0.94%     82.16% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5        27207     16.43%     98.60% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6          510      0.31%     98.90% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7         1010      0.61%     99.51% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8          803      0.49%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0        73929     44.70%     44.70% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1        44053     26.63%     71.33% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2         6103      3.69%     75.02% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3         7962      4.81%     79.83% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4         1564      0.95%     80.78% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5        29500     17.84%     98.62% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6          477      0.29%     98.90% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7         1008      0.61%     99.51% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8          804      0.49%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total       165567                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts              238705                       # Number of instructions committed
-system.cpu1.commit.committedOps                238705                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total       165400                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts              250251                       # Number of instructions committed
+system.cpu1.commit.committedOps                250251                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                         97880                       # Number of memory references committed
-system.cpu1.commit.loads                        67361                       # Number of loads committed
-system.cpu1.commit.membars                       6845                       # Number of memory barriers committed
-system.cpu1.commit.branches                     43327                       # Number of branches committed
+system.cpu1.commit.refs                        104168                       # Number of memory references committed
+system.cpu1.commit.loads                        71380                       # Number of loads committed
+system.cpu1.commit.membars                       6331                       # Number of memory barriers committed
+system.cpu1.commit.branches                     45080                       # Number of branches committed
 system.cpu1.commit.fp_insts                         0                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                   163326                       # Number of committed integer instructions.
+system.cpu1.commit.int_insts                   171367                       # Number of committed integer instructions.
 system.cpu1.commit.function_calls                 322                       # Number of function calls committed.
-system.cpu1.commit.bw_lim_events                  803                       # number cycles where commit BW limit reached
+system.cpu1.commit.bw_lim_events                  804                       # number cycles where commit BW limit reached
 system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads                      415361                       # The number of ROB reads
-system.cpu1.rob.rob_writes                     504754                       # The number of ROB writes
-system.cpu1.timesIdled                            217                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                           2211                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                       44117                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                     197745                       # Number of Instructions Simulated
-system.cpu1.committedOps                       197745                       # Number of Ops (including micro ops) Simulated
-system.cpu1.committedInsts_total               197745                       # Number of Instructions Simulated
-system.cpu1.cpi                              0.899810                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        0.899810                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              1.111345                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        1.111345                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads                  358439                       # number of integer regfile reads
-system.cpu1.int_regfile_writes                 167768                       # number of integer regfile writes
+system.cpu1.rob.rob_reads                      426586                       # The number of ROB reads
+system.cpu1.rob.rob_writes                     527520                       # The number of ROB writes
+system.cpu1.timesIdled                            216                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                           2212                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                       44181                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                     208053                       # Number of Instructions Simulated
+system.cpu1.committedOps                       208053                       # Number of Ops (including micro ops) Simulated
+system.cpu1.committedInsts_total               208053                       # Number of Instructions Simulated
+system.cpu1.cpi                              0.854249                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        0.854249                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              1.170619                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        1.170619                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads                  377223                       # number of integer regfile reads
+system.cpu1.int_regfile_writes                 176309                       # number of integer regfile writes
 system.cpu1.fp_regfile_writes                      64                       # number of floating regfile writes
-system.cpu1.misc_regfile_reads                 101509                       # number of misc regfile reads
+system.cpu1.misc_regfile_reads                 107781                       # number of misc regfile reads
 system.cpu1.misc_regfile_writes                   648                       # number of misc regfile writes
 system.cpu1.icache.tags.replacements              318                       # number of replacements
-system.cpu1.icache.tags.tagsinuse           76.730517                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs              22903                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.tagsinuse           76.722565                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs              21879                       # Total number of references to valid blocks.
 system.cpu1.icache.tags.sampled_refs              428                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs            53.511682                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            51.119159                       # Average number of references to valid blocks.
 system.cpu1.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst    76.730517                       # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst     0.149864                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total     0.149864                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_blocks::cpu1.inst    76.722565                       # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst     0.149849                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.149849                       # Average percentage of cache occupancy
 system.cpu1.icache.tags.occ_task_id_blocks::1024          110                       # Occupied blocks per task id
 system.cpu1.icache.tags.age_task_id_blocks_1024::0           11                       # Occupied blocks per task id
 system.cpu1.icache.tags.age_task_id_blocks_1024::1           99                       # Occupied blocks per task id
 system.cpu1.icache.tags.occ_task_id_percent::1024     0.214844                       # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses            23807                       # Number of tag accesses
-system.cpu1.icache.tags.data_accesses           23807                       # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst        22903                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total          22903                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst        22903                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total           22903                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst        22903                       # number of overall hits
-system.cpu1.icache.overall_hits::total          22903                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst          476                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total          476                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst          476                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total           476                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst          476                       # number of overall misses
-system.cpu1.icache.overall_misses::total          476                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst      7186493                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total      7186493                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst      7186493                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total      7186493                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst      7186493                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total      7186493                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst        23379                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total        23379                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst        23379                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total        23379                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst        23379                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total        23379                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.020360                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.020360                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.020360                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.020360                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.020360                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.020360                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15097.674370                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 15097.674370                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15097.674370                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 15097.674370                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15097.674370                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 15097.674370                       # average overall miss latency
+system.cpu1.icache.tags.tag_accesses            22782                       # Number of tag accesses
+system.cpu1.icache.tags.data_accesses           22782                       # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst        21879                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total          21879                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst        21879                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total           21879                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst        21879                       # number of overall hits
+system.cpu1.icache.overall_hits::total          21879                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst          475                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total          475                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst          475                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total           475                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst          475                       # number of overall misses
+system.cpu1.icache.overall_misses::total          475                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst      7157495                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total      7157495                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst      7157495                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total      7157495                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst      7157495                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total      7157495                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst        22354                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total        22354                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst        22354                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total        22354                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst        22354                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total        22354                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.021249                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.021249                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.021249                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.021249                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.021249                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.021249                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15068.410526                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 15068.410526                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15068.410526                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 15068.410526                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15068.410526                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 15068.410526                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs           26                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                2                       # number of cycles access was blocked
@@ -1521,112 +1544,111 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs           13
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst           48                       # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total           48                       # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst           48                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total           48                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst           48                       # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total           48                       # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst           47                       # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total           47                       # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst           47                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total           47                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst           47                       # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total           47                       # number of overall MSHR hits
 system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst          428                       # number of ReadReq MSHR misses
 system.cpu1.icache.ReadReq_mshr_misses::total          428                       # number of ReadReq MSHR misses
 system.cpu1.icache.demand_mshr_misses::cpu1.inst          428                       # number of demand (read+write) MSHR misses
 system.cpu1.icache.demand_mshr_misses::total          428                       # number of demand (read+write) MSHR misses
 system.cpu1.icache.overall_mshr_misses::cpu1.inst          428                       # number of overall MSHR misses
 system.cpu1.icache.overall_mshr_misses::total          428                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst      5726506                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total      5726506                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst      5726506                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total      5726506                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst      5726506                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total      5726506                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.018307                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.018307                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.018307                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.018307                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.018307                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.018307                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13379.686916                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13379.686916                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13379.686916                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 13379.686916                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13379.686916                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 13379.686916                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst      5706004                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total      5706004                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst      5706004                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total      5706004                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst      5706004                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total      5706004                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.019146                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.019146                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.019146                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.019146                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.019146                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.019146                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13331.785047                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13331.785047                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13331.785047                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 13331.785047                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13331.785047                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 13331.785047                       # average overall mshr miss latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dcache.tags.replacements                0                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse           23.664777                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs              36646                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs               29                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs          1263.655172                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.tagsinuse           23.630187                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs              38790                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs               28                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs          1385.357143                       # Average number of references to valid blocks.
 system.cpu1.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data    23.664777                       # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data     0.046220                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total     0.046220                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024           29                       # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0            1                       # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_blocks::cpu1.data    23.630187                       # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data     0.046153                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.046153                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024           28                       # Occupied blocks per task id
 system.cpu1.dcache.tags.age_task_id_blocks_1024::1           28                       # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024     0.056641                       # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses           290684                       # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses          290684                       # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data        41736                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total          41736                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data        30310                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total         30310                       # number of WriteReq hits
-system.cpu1.dcache.SwapReq_hits::cpu1.data           13                       # number of SwapReq hits
-system.cpu1.dcache.SwapReq_hits::total             13                       # number of SwapReq hits
-system.cpu1.dcache.demand_hits::cpu1.data        72046                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total           72046                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data        72046                       # number of overall hits
-system.cpu1.dcache.overall_hits::total          72046                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data          352                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total          352                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data          139                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total          139                       # number of WriteReq misses
+system.cpu1.dcache.tags.occ_task_id_percent::1024     0.054688                       # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses           306681                       # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses          306681                       # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data        43485                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total          43485                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data        32585                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total         32585                       # number of WriteReq hits
+system.cpu1.dcache.SwapReq_hits::cpu1.data           14                       # number of SwapReq hits
+system.cpu1.dcache.SwapReq_hits::total             14                       # number of SwapReq hits
+system.cpu1.dcache.demand_hits::cpu1.data        76070                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total           76070                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data        76070                       # number of overall hits
+system.cpu1.dcache.overall_hits::total          76070                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data          336                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total          336                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data          132                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total          132                       # number of WriteReq misses
 system.cpu1.dcache.SwapReq_misses::cpu1.data           57                       # number of SwapReq misses
 system.cpu1.dcache.SwapReq_misses::total           57                       # number of SwapReq misses
-system.cpu1.dcache.demand_misses::cpu1.data          491                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total           491                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data          491                       # number of overall misses
-system.cpu1.dcache.overall_misses::total          491                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data      4404095                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total      4404095                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data      2802760                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total      2802760                       # number of WriteReq miss cycles
-system.cpu1.dcache.SwapReq_miss_latency::cpu1.data       563508                       # number of SwapReq miss cycles
-system.cpu1.dcache.SwapReq_miss_latency::total       563508                       # number of SwapReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data      7206855                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total      7206855                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data      7206855                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total      7206855                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data        42088                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total        42088                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data        30449                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total        30449                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SwapReq_accesses::cpu1.data           70                       # number of SwapReq accesses(hits+misses)
-system.cpu1.dcache.SwapReq_accesses::total           70                       # number of SwapReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data        72537                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total        72537                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data        72537                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total        72537                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.008363                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.008363                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.004565                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.004565                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SwapReq_miss_rate::cpu1.data     0.814286                       # miss rate for SwapReq accesses
-system.cpu1.dcache.SwapReq_miss_rate::total     0.814286                       # miss rate for SwapReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.006769                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.006769                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.006769                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.006769                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12511.633523                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 12511.633523                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20163.741007                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 20163.741007                       # average WriteReq miss latency
-system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data  9886.105263                       # average SwapReq miss latency
-system.cpu1.dcache.SwapReq_avg_miss_latency::total  9886.105263                       # average SwapReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14677.912424                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 14677.912424                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14677.912424                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 14677.912424                       # average overall miss latency
+system.cpu1.dcache.demand_misses::cpu1.data          468                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total           468                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data          468                       # number of overall misses
+system.cpu1.dcache.overall_misses::total          468                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data      4179135                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total      4179135                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data      2763761                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total      2763761                       # number of WriteReq miss cycles
+system.cpu1.dcache.SwapReq_miss_latency::cpu1.data       521507                       # number of SwapReq miss cycles
+system.cpu1.dcache.SwapReq_miss_latency::total       521507                       # number of SwapReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data      6942896                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total      6942896                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data      6942896                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total      6942896                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data        43821                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total        43821                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data        32717                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total        32717                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SwapReq_accesses::cpu1.data           71                       # number of SwapReq accesses(hits+misses)
+system.cpu1.dcache.SwapReq_accesses::total           71                       # number of SwapReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data        76538                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total        76538                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data        76538                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total        76538                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.007668                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.007668                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.004035                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.004035                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SwapReq_miss_rate::cpu1.data     0.802817                       # miss rate for SwapReq accesses
+system.cpu1.dcache.SwapReq_miss_rate::total     0.802817                       # miss rate for SwapReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.006115                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.006115                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.006115                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.006115                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12437.901786                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 12437.901786                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20937.583333                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 20937.583333                       # average WriteReq miss latency
+system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data  9149.245614                       # average SwapReq miss latency
+system.cpu1.dcache.SwapReq_avg_miss_latency::total  9149.245614                       # average SwapReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14835.247863                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 14835.247863                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14835.247863                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 14835.247863                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1635,370 +1657,370 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          187                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total          187                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data           32                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total           32                       # number of WriteReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data          219                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total          219                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data          219                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total          219                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data          165                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total          165                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data          107                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total          107                       # number of WriteReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          178                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total          178                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data           30                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total           30                       # number of WriteReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data          208                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total          208                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data          208                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total          208                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data          158                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total          158                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data          102                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total          102                       # number of WriteReq MSHR misses
 system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data           57                       # number of SwapReq MSHR misses
 system.cpu1.dcache.SwapReq_mshr_misses::total           57                       # number of SwapReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data          272                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total          272                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data          272                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total          272                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data      1130523                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total      1130523                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data      1329240                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total      1329240                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data       449492                       # number of SwapReq MSHR miss cycles
-system.cpu1.dcache.SwapReq_mshr_miss_latency::total       449492                       # number of SwapReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data      2459763                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total      2459763                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data      2459763                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total      2459763                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.003920                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.003920                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.003514                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.003514                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data     0.814286                       # mshr miss rate for SwapReq accesses
-system.cpu1.dcache.SwapReq_mshr_miss_rate::total     0.814286                       # mshr miss rate for SwapReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.003750                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.003750                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.003750                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.003750                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data  6851.654545                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total  6851.654545                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12422.803738                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12422.803738                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data  7885.824561                       # average SwapReq mshr miss latency
-system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total  7885.824561                       # average SwapReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data  9043.246324                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total  9043.246324                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data  9043.246324                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total  9043.246324                       # average overall mshr miss latency
+system.cpu1.dcache.demand_mshr_misses::cpu1.data          260                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total          260                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data          260                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total          260                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data      1078019                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total      1078019                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data      1313739                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total      1313739                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data       407493                       # number of SwapReq MSHR miss cycles
+system.cpu1.dcache.SwapReq_mshr_miss_latency::total       407493                       # number of SwapReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data      2391758                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total      2391758                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data      2391758                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total      2391758                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.003606                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.003606                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.003118                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.003118                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data     0.802817                       # mshr miss rate for SwapReq accesses
+system.cpu1.dcache.SwapReq_mshr_miss_rate::total     0.802817                       # mshr miss rate for SwapReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.003397                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.003397                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.003397                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.003397                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data  6822.905063                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total  6822.905063                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12879.794118                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12879.794118                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data         7149                       # average SwapReq mshr miss latency
+system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total         7149                       # average SwapReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data  9199.069231                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total  9199.069231                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data  9199.069231                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total  9199.069231                       # average overall mshr miss latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu2.branchPred.lookups                  51289                       # Number of BP lookups
-system.cpu2.branchPred.condPredicted            48575                       # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect             1303                       # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups               45091                       # Number of BTB lookups
-system.cpu2.branchPred.BTBHits                  44400                       # Number of BTB hits
+system.cpu2.branchPred.lookups                  47736                       # Number of BP lookups
+system.cpu2.branchPred.condPredicted            45029                       # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect             1300                       # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups               41576                       # Number of BTB lookups
+system.cpu2.branchPred.BTBHits                  40869                       # Number of BTB hits
 system.cpu2.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct            98.467543                       # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS                    684                       # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.BTBHitPct            98.299500                       # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS                    682                       # Number of times the RAS was used to get a target.
 system.cpu2.branchPred.RASInCorrect               232                       # Number of incorrect RAS predictions.
-system.cpu2.numCycles                          177568                       # number of cpu cycles simulated
+system.cpu2.numCycles                          177364                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles             28811                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts                        286582                       # Number of instructions fetch has processed
-system.cpu2.fetch.Branches                      51289                       # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches             45084                       # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles                       100994                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles                   3797                       # Number of cycles fetch has spent squashing
-system.cpu2.fetch.BlockedCycles                 31174                       # Number of cycles fetch has spent blocked
+system.cpu2.fetch.icacheStallCycles             30843                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts                        263253                       # Number of instructions fetch has processed
+system.cpu2.fetch.Branches                      47736                       # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches             41551                       # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles                        94921                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles                   3824                       # Number of cycles fetch has spent squashing
+system.cpu2.fetch.BlockedCycles                 35042                       # Number of cycles fetch has spent blocked
 system.cpu2.fetch.MiscStallCycles                   4                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.NoActiveThreadStallCycles         7777                       # Number of stall cycles due to no active thread to fetch from
-system.cpu2.fetch.PendingTrapStallCycles          828                       # Number of stall cycles due to pending traps
-system.cpu2.fetch.CacheLines                    19751                       # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes                  271                       # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.rateDist::samples            172005                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean             1.666126                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev            2.139968                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.NoActiveThreadStallCycles         7755                       # Number of stall cycles due to no active thread to fetch from
+system.cpu2.fetch.PendingTrapStallCycles          807                       # Number of stall cycles due to pending traps
+system.cpu2.fetch.CacheLines                    21784                       # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes                  264                       # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.rateDist::samples            171818                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean             1.532162                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev            2.088026                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0                   71011     41.28%     41.28% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1                   51378     29.87%     71.15% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2                    6118      3.56%     74.71% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3                    3176      1.85%     76.56% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4                     688      0.40%     76.96% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5                   34434     20.02%     96.98% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6                    1153      0.67%     97.65% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7                     776      0.45%     98.10% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8                    3271      1.90%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0                   76897     44.75%     44.75% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1                   48842     28.43%     73.18% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2                    7151      4.16%     77.34% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3                    3183      1.85%     79.20% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4                     686      0.40%     79.60% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5                   29853     17.37%     96.97% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6                    1160      0.68%     97.65% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7                     777      0.45%     98.10% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8                    3269      1.90%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total              172005                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate                 0.288841                       # Number of branch fetches per cycle
-system.cpu2.fetch.rate                       1.613928                       # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles                   33784                       # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles                27886                       # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles                    95100                       # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles                 5041                       # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles                  2417                       # Number of cycles decode is squashing
-system.cpu2.decode.DecodedInsts                283075                       # Number of instructions handled by decode
-system.cpu2.rename.SquashCycles                  2417                       # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles                   34494                       # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles                  14868                       # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles         12252                       # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles                    90315                       # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles                 9882                       # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts                280839                       # Number of instructions processed by rename
-system.cpu2.rename.LSQFullEvents                   23                       # Number of times rename has blocked due to LSQ full
-system.cpu2.rename.RenamedOperands             196811                       # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups               538430                       # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups          418650                       # Number of integer rename lookups
-system.cpu2.rename.CommittedMaps               183802                       # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps                   13009                       # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts              1113                       # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts          1241                       # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts                    12535                       # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads               79329                       # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores              37643                       # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads            37867                       # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores           32593                       # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded                    232899                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded               6340                       # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued                   234900                       # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued              101                       # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined          11011                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined        10850                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved           602                       # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples       172005                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean        1.365658                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev       1.313804                       # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total              171818                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate                 0.269141                       # Number of branch fetches per cycle
+system.cpu2.fetch.rate                       1.484253                       # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles                   36742                       # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles                30807                       # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles                    88098                       # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles                 5970                       # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles                  2446                       # Number of cycles decode is squashing
+system.cpu2.decode.DecodedInsts                259780                       # Number of instructions handled by decode
+system.cpu2.rename.SquashCycles                  2446                       # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles                   37466                       # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles                  17719                       # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles         12322                       # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles                    82368                       # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles                11742                       # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts                257506                       # Number of instructions processed by rename
+system.cpu2.rename.LSQFullEvents                   21                       # Number of times rename has blocked due to LSQ full
+system.cpu2.rename.RenamedOperands             179566                       # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups               487666                       # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups          380584                       # Number of integer rename lookups
+system.cpu2.rename.CommittedMaps               166435                       # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps                   13131                       # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts              1114                       # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts          1238                       # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts                    14439                       # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads               71199                       # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores              33061                       # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads            34327                       # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores           28016                       # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded                    212074                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded               7370                       # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued                   214906                       # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued              106                       # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined          11214                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined        11199                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved           648                       # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples       171818                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean        1.250777                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev       1.303706                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0              68443     39.79%     39.79% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1              22432     13.04%     52.83% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2              37853     22.01%     74.84% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3              38470     22.37%     97.21% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4               3247      1.89%     99.09% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5               1167      0.68%     99.77% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6                279      0.16%     99.93% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7                 57      0.03%     99.97% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0              74494     43.36%     43.36% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1              25338     14.75%     58.10% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2              33284     19.37%     77.48% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3              33913     19.74%     97.21% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4               3241      1.89%     99.10% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5               1161      0.68%     99.77% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6                274      0.16%     99.93% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7                 56      0.03%     99.97% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::8                 57      0.03%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total         172005                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total         171818                       # Number of insts issued each cycle
 system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu                     17      6.01%      6.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult                     0      0.00%      6.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv                      0      0.00%      6.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd                    0      0.00%      6.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp                    0      0.00%      6.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt                    0      0.00%      6.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult                   0      0.00%      6.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv                    0      0.00%      6.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%      6.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd                     0      0.00%      6.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%      6.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu                     0      0.00%      6.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp                     0      0.00%      6.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt                     0      0.00%      6.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc                    0      0.00%      6.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult                    0      0.00%      6.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%      6.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift                   0      0.00%      6.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%      6.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%      6.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%      6.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%      6.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%      6.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%      6.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%      6.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%      6.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%      6.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%      6.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%      6.01% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead                    56     19.79%     25.80% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite                  210     74.20%    100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu                     17      6.18%      6.18% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult                     0      0.00%      6.18% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv                      0      0.00%      6.18% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd                    0      0.00%      6.18% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp                    0      0.00%      6.18% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt                    0      0.00%      6.18% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult                   0      0.00%      6.18% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv                    0      0.00%      6.18% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%      6.18% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd                     0      0.00%      6.18% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%      6.18% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu                     0      0.00%      6.18% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp                     0      0.00%      6.18% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt                     0      0.00%      6.18% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc                    0      0.00%      6.18% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult                    0      0.00%      6.18% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%      6.18% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift                   0      0.00%      6.18% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%      6.18% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%      6.18% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%      6.18% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%      6.18% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%      6.18% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%      6.18% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%      6.18% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%      6.18% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%      6.18% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%      6.18% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%      6.18% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead                    48     17.45%     23.64% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite                  210     76.36%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu2.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu               114350     48.68%     48.68% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult                   0      0.00%     48.68% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     48.68% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     48.68% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     48.68% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     48.68% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     48.68% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     48.68% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     48.68% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     48.68% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     48.68% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     48.68% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     48.68% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     48.68% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     48.68% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     48.68% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     48.68% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     48.68% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     48.68% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     48.68% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     48.68% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     48.68% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     48.68% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     48.68% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     48.68% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     48.68% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     48.68% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     48.68% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     48.68% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead               83592     35.59%     84.27% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite              36958     15.73%    100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu               106166     49.40%     49.40% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult                   0      0.00%     49.40% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     49.40% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     49.40% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     49.40% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     49.40% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     49.40% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     49.40% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     49.40% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     49.40% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     49.40% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     49.40% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     49.40% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     49.40% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     49.40% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     49.40% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     49.40% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     49.40% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     49.40% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     49.40% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     49.40% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     49.40% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     49.40% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     49.40% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     49.40% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     49.40% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     49.40% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     49.40% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     49.40% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead               76377     35.54%     84.94% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite              32363     15.06%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total                234900                       # Type of FU issued
-system.cpu2.iq.rate                          1.322873                       # Inst issue rate
-system.cpu2.iq.fu_busy_cnt                        283                       # FU busy when requested
-system.cpu2.iq.fu_busy_rate                  0.001205                       # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads            642189                       # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes           250297                       # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses       233099                       # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.FU_type_0::total                214906                       # Type of FU issued
+system.cpu2.iq.rate                          1.211666                       # Inst issue rate
+system.cpu2.iq.fu_busy_cnt                        275                       # FU busy when requested
+system.cpu2.iq.fu_busy_rate                  0.001280                       # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads            602011                       # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes           230706                       # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses       213087                       # Number of integer instruction queue wakeup accesses
 system.cpu2.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
 system.cpu2.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
 system.cpu2.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses                235183                       # Number of integer alu accesses
+system.cpu2.iq.int_alu_accesses                215181                       # Number of integer alu accesses
 system.cpu2.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads           32324                       # Number of loads that had data forwarded from stores
+system.cpu2.iew.lsq.thread0.forwLoads           27728                       # Number of loads that had data forwarded from stores
 system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads         2477                       # Number of loads squashed
+system.cpu2.iew.lsq.thread0.squashedLoads         2543                       # Number of loads squashed
 system.cpu2.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation           47                       # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores         1468                       # Number of stores squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation           48                       # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores         1469                       # Number of stores squashed
 system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu2.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
 system.cpu2.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles                  2417                       # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles                    878                       # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles                   50                       # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts             278010                       # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts              351                       # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts                79329                       # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts               37643                       # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts              1071                       # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents                    50                       # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewSquashCycles                  2446                       # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles                    917                       # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles                   52                       # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts             254656                       # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts              365                       # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts                71199                       # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts               33061                       # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts              1074                       # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents                    52                       # Number of times the IQ has become full, causing a stall
 system.cpu2.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents            47                       # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect           457                       # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect          973                       # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts                1430                       # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts               233765                       # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts                78300                       # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts             1135                       # Number of squashed instructions skipped in execute
+system.cpu2.iew.memOrderViolationEvents            48                       # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect           458                       # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect          967                       # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts                1425                       # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts               213756                       # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts                70098                       # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts             1150                       # Number of squashed instructions skipped in execute
 system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu2.iew.exec_nop                        38771                       # number of nop insts executed
-system.cpu2.iew.exec_refs                      115173                       # number of memory reference insts executed
-system.cpu2.iew.exec_branches                   48001                       # Number of branches executed
-system.cpu2.iew.exec_stores                     36873                       # Number of stores executed
-system.cpu2.iew.exec_rate                    1.316482                       # Inst execution rate
-system.cpu2.iew.wb_sent                        233385                       # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count                       233099                       # cumulative count of insts written-back
-system.cpu2.iew.wb_producers                   131933                       # num instructions producing a value
-system.cpu2.iew.wb_consumers                   136641                       # num instructions consuming a value
+system.cpu2.iew.exec_nop                        35212                       # number of nop insts executed
+system.cpu2.iew.exec_refs                      102378                       # number of memory reference insts executed
+system.cpu2.iew.exec_branches                   44395                       # Number of branches executed
+system.cpu2.iew.exec_stores                     32280                       # Number of stores executed
+system.cpu2.iew.exec_rate                    1.205183                       # Inst execution rate
+system.cpu2.iew.wb_sent                        213374                       # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count                       213087                       # cumulative count of insts written-back
+system.cpu2.iew.wb_producers                   119148                       # num instructions producing a value
+system.cpu2.iew.wb_consumers                   123853                       # num instructions consuming a value
 system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate                      1.312731                       # insts written-back per cycle
-system.cpu2.iew.wb_fanout                    0.965545                       # average fanout of values written-back
+system.cpu2.iew.wb_rate                      1.201411                       # insts written-back per cycle
+system.cpu2.iew.wb_fanout                    0.962011                       # average fanout of values written-back
 system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts          12656                       # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls           5738                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts             1303                       # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples       161811                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean     1.639889                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev     2.021157                       # Number of insts commited each cycle
+system.cpu2.commit.commitSquashedInsts          12898                       # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls           6722                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts             1300                       # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples       161617                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean     1.495857                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev     1.966536                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0        66196     40.91%     40.91% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1        46128     28.51%     69.42% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2         6098      3.77%     73.19% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3         6657      4.11%     77.30% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4         1558      0.96%     78.26% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5        32865     20.31%     98.57% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6          486      0.30%     98.87% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7         1000      0.62%     99.49% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8          823      0.51%    100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0        73208     45.30%     45.30% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1        42532     26.32%     71.61% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2         6095      3.77%     75.39% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3         7628      4.72%     80.10% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4         1558      0.96%     81.07% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5        28303     17.51%     98.58% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6          470      0.29%     98.87% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7         1001      0.62%     99.49% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8          822      0.51%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total       161811                       # Number of insts commited each cycle
-system.cpu2.commit.committedInsts              265352                       # Number of instructions committed
-system.cpu2.commit.committedOps                265352                       # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total       161617                       # Number of insts commited each cycle
+system.cpu2.commit.committedInsts              241756                       # Number of instructions committed
+system.cpu2.commit.committedOps                241756                       # Number of ops (including micro ops) committed
 system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu2.commit.refs                        113027                       # Number of memory references committed
-system.cpu2.commit.loads                        76852                       # Number of loads committed
-system.cpu2.commit.membars                       5022                       # Number of memory barriers committed
-system.cpu2.commit.branches                     47160                       # Number of branches committed
+system.cpu2.commit.refs                        100248                       # Number of memory references committed
+system.cpu2.commit.loads                        68656                       # Number of loads committed
+system.cpu2.commit.membars                       6003                       # Number of memory barriers committed
+system.cpu2.commit.branches                     43556                       # Number of branches committed
 system.cpu2.commit.fp_insts                         0                       # Number of committed floating point instructions.
-system.cpu2.commit.int_insts                   182307                       # Number of committed integer instructions.
+system.cpu2.commit.int_insts                   165922                       # Number of committed integer instructions.
 system.cpu2.commit.function_calls                 322                       # Number of function calls committed.
-system.cpu2.commit.bw_lim_events                  823                       # number cycles where commit BW limit reached
+system.cpu2.commit.bw_lim_events                  822                       # number cycles where commit BW limit reached
 system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu2.rob.rob_reads                      438409                       # The number of ROB reads
-system.cpu2.rob.rob_writes                     558438                       # The number of ROB writes
-system.cpu2.timesIdled                            223                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles                           5563                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles                       44482                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts                     222382                       # Number of Instructions Simulated
-system.cpu2.committedOps                       222382                       # Number of Ops (including micro ops) Simulated
-system.cpu2.committedInsts_total               222382                       # Number of Instructions Simulated
-system.cpu2.cpi                              0.798482                       # CPI: Cycles Per Instruction
-system.cpu2.cpi_total                        0.798482                       # CPI: Total CPI of All Threads
-system.cpu2.ipc                              1.252377                       # IPC: Instructions Per Cycle
-system.cpu2.ipc_total                        1.252377                       # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads                  404230                       # number of integer regfile reads
-system.cpu2.int_regfile_writes                 188772                       # number of integer regfile writes
+system.cpu2.rob.rob_reads                      414862                       # The number of ROB reads
+system.cpu2.rob.rob_writes                     511759                       # The number of ROB writes
+system.cpu2.timesIdled                            225                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles                           5546                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles                       44546                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts                     201412                       # Number of Instructions Simulated
+system.cpu2.committedOps                       201412                       # Number of Ops (including micro ops) Simulated
+system.cpu2.committedInsts_total               201412                       # Number of Instructions Simulated
+system.cpu2.cpi                              0.880603                       # CPI: Cycles Per Instruction
+system.cpu2.cpi_total                        0.880603                       # CPI: Total CPI of All Threads
+system.cpu2.ipc                              1.135586                       # IPC: Instructions Per Cycle
+system.cpu2.ipc_total                        1.135586                       # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads                  365854                       # number of integer regfile reads
+system.cpu2.int_regfile_writes                 171387                       # number of integer regfile writes
 system.cpu2.fp_regfile_writes                      64                       # number of floating regfile writes
-system.cpu2.misc_regfile_reads                 116736                       # number of misc regfile reads
+system.cpu2.misc_regfile_reads                 103940                       # number of misc regfile reads
 system.cpu2.misc_regfile_writes                   648                       # number of misc regfile writes
 system.cpu2.icache.tags.replacements              317                       # number of replacements
-system.cpu2.icache.tags.tagsinuse           82.236554                       # Cycle average of tags in use
-system.cpu2.icache.tags.total_refs              19258                       # Total number of references to valid blocks.
+system.cpu2.icache.tags.tagsinuse           82.194037                       # Cycle average of tags in use
+system.cpu2.icache.tags.total_refs              21297                       # Total number of references to valid blocks.
 system.cpu2.icache.tags.sampled_refs              425                       # Sample count of references to valid blocks.
-system.cpu2.icache.tags.avg_refs            45.312941                       # Average number of references to valid blocks.
+system.cpu2.icache.tags.avg_refs            50.110588                       # Average number of references to valid blocks.
 system.cpu2.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu2.icache.tags.occ_blocks::cpu2.inst    82.236554                       # Average occupied blocks per requestor
-system.cpu2.icache.tags.occ_percent::cpu2.inst     0.160618                       # Average percentage of cache occupancy
-system.cpu2.icache.tags.occ_percent::total     0.160618                       # Average percentage of cache occupancy
+system.cpu2.icache.tags.occ_blocks::cpu2.inst    82.194037                       # Average occupied blocks per requestor
+system.cpu2.icache.tags.occ_percent::cpu2.inst     0.160535                       # Average percentage of cache occupancy
+system.cpu2.icache.tags.occ_percent::total     0.160535                       # Average percentage of cache occupancy
 system.cpu2.icache.tags.occ_task_id_blocks::1024          108                       # Occupied blocks per task id
 system.cpu2.icache.tags.age_task_id_blocks_1024::0           11                       # Occupied blocks per task id
 system.cpu2.icache.tags.age_task_id_blocks_1024::1           97                       # Occupied blocks per task id
 system.cpu2.icache.tags.occ_task_id_percent::1024     0.210938                       # Percentage of cache occupancy per task id
-system.cpu2.icache.tags.tag_accesses            20176                       # Number of tag accesses
-system.cpu2.icache.tags.data_accesses           20176                       # Number of data accesses
-system.cpu2.icache.ReadReq_hits::cpu2.inst        19258                       # number of ReadReq hits
-system.cpu2.icache.ReadReq_hits::total          19258                       # number of ReadReq hits
-system.cpu2.icache.demand_hits::cpu2.inst        19258                       # number of demand (read+write) hits
-system.cpu2.icache.demand_hits::total           19258                       # number of demand (read+write) hits
-system.cpu2.icache.overall_hits::cpu2.inst        19258                       # number of overall hits
-system.cpu2.icache.overall_hits::total          19258                       # number of overall hits
-system.cpu2.icache.ReadReq_misses::cpu2.inst          493                       # number of ReadReq misses
-system.cpu2.icache.ReadReq_misses::total          493                       # number of ReadReq misses
-system.cpu2.icache.demand_misses::cpu2.inst          493                       # number of demand (read+write) misses
-system.cpu2.icache.demand_misses::total           493                       # number of demand (read+write) misses
-system.cpu2.icache.overall_misses::cpu2.inst          493                       # number of overall misses
-system.cpu2.icache.overall_misses::total          493                       # number of overall misses
-system.cpu2.icache.ReadReq_miss_latency::cpu2.inst     11621241                       # number of ReadReq miss cycles
-system.cpu2.icache.ReadReq_miss_latency::total     11621241                       # number of ReadReq miss cycles
-system.cpu2.icache.demand_miss_latency::cpu2.inst     11621241                       # number of demand (read+write) miss cycles
-system.cpu2.icache.demand_miss_latency::total     11621241                       # number of demand (read+write) miss cycles
-system.cpu2.icache.overall_miss_latency::cpu2.inst     11621241                       # number of overall miss cycles
-system.cpu2.icache.overall_miss_latency::total     11621241                       # number of overall miss cycles
-system.cpu2.icache.ReadReq_accesses::cpu2.inst        19751                       # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.ReadReq_accesses::total        19751                       # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.demand_accesses::cpu2.inst        19751                       # number of demand (read+write) accesses
-system.cpu2.icache.demand_accesses::total        19751                       # number of demand (read+write) accesses
-system.cpu2.icache.overall_accesses::cpu2.inst        19751                       # number of overall (read+write) accesses
-system.cpu2.icache.overall_accesses::total        19751                       # number of overall (read+write) accesses
-system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.024961                       # miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_miss_rate::total     0.024961                       # miss rate for ReadReq accesses
-system.cpu2.icache.demand_miss_rate::cpu2.inst     0.024961                       # miss rate for demand accesses
-system.cpu2.icache.demand_miss_rate::total     0.024961                       # miss rate for demand accesses
-system.cpu2.icache.overall_miss_rate::cpu2.inst     0.024961                       # miss rate for overall accesses
-system.cpu2.icache.overall_miss_rate::total     0.024961                       # miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23572.496957                       # average ReadReq miss latency
-system.cpu2.icache.ReadReq_avg_miss_latency::total 23572.496957                       # average ReadReq miss latency
-system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23572.496957                       # average overall miss latency
-system.cpu2.icache.demand_avg_miss_latency::total 23572.496957                       # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23572.496957                       # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency::total 23572.496957                       # average overall miss latency
+system.cpu2.icache.tags.tag_accesses            22209                       # Number of tag accesses
+system.cpu2.icache.tags.data_accesses           22209                       # Number of data accesses
+system.cpu2.icache.ReadReq_hits::cpu2.inst        21297                       # number of ReadReq hits
+system.cpu2.icache.ReadReq_hits::total          21297                       # number of ReadReq hits
+system.cpu2.icache.demand_hits::cpu2.inst        21297                       # number of demand (read+write) hits
+system.cpu2.icache.demand_hits::total           21297                       # number of demand (read+write) hits
+system.cpu2.icache.overall_hits::cpu2.inst        21297                       # number of overall hits
+system.cpu2.icache.overall_hits::total          21297                       # number of overall hits
+system.cpu2.icache.ReadReq_misses::cpu2.inst          487                       # number of ReadReq misses
+system.cpu2.icache.ReadReq_misses::total          487                       # number of ReadReq misses
+system.cpu2.icache.demand_misses::cpu2.inst          487                       # number of demand (read+write) misses
+system.cpu2.icache.demand_misses::total           487                       # number of demand (read+write) misses
+system.cpu2.icache.overall_misses::cpu2.inst          487                       # number of overall misses
+system.cpu2.icache.overall_misses::total          487                       # number of overall misses
+system.cpu2.icache.ReadReq_miss_latency::cpu2.inst     11553239                       # number of ReadReq miss cycles
+system.cpu2.icache.ReadReq_miss_latency::total     11553239                       # number of ReadReq miss cycles
+system.cpu2.icache.demand_miss_latency::cpu2.inst     11553239                       # number of demand (read+write) miss cycles
+system.cpu2.icache.demand_miss_latency::total     11553239                       # number of demand (read+write) miss cycles
+system.cpu2.icache.overall_miss_latency::cpu2.inst     11553239                       # number of overall miss cycles
+system.cpu2.icache.overall_miss_latency::total     11553239                       # number of overall miss cycles
+system.cpu2.icache.ReadReq_accesses::cpu2.inst        21784                       # number of ReadReq accesses(hits+misses)
+system.cpu2.icache.ReadReq_accesses::total        21784                       # number of ReadReq accesses(hits+misses)
+system.cpu2.icache.demand_accesses::cpu2.inst        21784                       # number of demand (read+write) accesses
+system.cpu2.icache.demand_accesses::total        21784                       # number of demand (read+write) accesses
+system.cpu2.icache.overall_accesses::cpu2.inst        21784                       # number of overall (read+write) accesses
+system.cpu2.icache.overall_accesses::total        21784                       # number of overall (read+write) accesses
+system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.022356                       # miss rate for ReadReq accesses
+system.cpu2.icache.ReadReq_miss_rate::total     0.022356                       # miss rate for ReadReq accesses
+system.cpu2.icache.demand_miss_rate::cpu2.inst     0.022356                       # miss rate for demand accesses
+system.cpu2.icache.demand_miss_rate::total     0.022356                       # miss rate for demand accesses
+system.cpu2.icache.overall_miss_rate::cpu2.inst     0.022356                       # miss rate for overall accesses
+system.cpu2.icache.overall_miss_rate::total     0.022356                       # miss rate for overall accesses
+system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23723.283368                       # average ReadReq miss latency
+system.cpu2.icache.ReadReq_avg_miss_latency::total 23723.283368                       # average ReadReq miss latency
+system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23723.283368                       # average overall miss latency
+system.cpu2.icache.demand_avg_miss_latency::total 23723.283368                       # average overall miss latency
+system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23723.283368                       # average overall miss latency
+system.cpu2.icache.overall_avg_miss_latency::total 23723.283368                       # average overall miss latency
 system.cpu2.icache.blocked_cycles::no_mshrs           85                       # number of cycles access was blocked
 system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu2.icache.blocked::no_mshrs                1                       # number of cycles access was blocked
@@ -2007,111 +2029,112 @@ system.cpu2.icache.avg_blocked_cycles::no_mshrs           85
 system.cpu2.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu2.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu2.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst           68                       # number of ReadReq MSHR hits
-system.cpu2.icache.ReadReq_mshr_hits::total           68                       # number of ReadReq MSHR hits
-system.cpu2.icache.demand_mshr_hits::cpu2.inst           68                       # number of demand (read+write) MSHR hits
-system.cpu2.icache.demand_mshr_hits::total           68                       # number of demand (read+write) MSHR hits
-system.cpu2.icache.overall_mshr_hits::cpu2.inst           68                       # number of overall MSHR hits
-system.cpu2.icache.overall_mshr_hits::total           68                       # number of overall MSHR hits
+system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst           62                       # number of ReadReq MSHR hits
+system.cpu2.icache.ReadReq_mshr_hits::total           62                       # number of ReadReq MSHR hits
+system.cpu2.icache.demand_mshr_hits::cpu2.inst           62                       # number of demand (read+write) MSHR hits
+system.cpu2.icache.demand_mshr_hits::total           62                       # number of demand (read+write) MSHR hits
+system.cpu2.icache.overall_mshr_hits::cpu2.inst           62                       # number of overall MSHR hits
+system.cpu2.icache.overall_mshr_hits::total           62                       # number of overall MSHR hits
 system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst          425                       # number of ReadReq MSHR misses
 system.cpu2.icache.ReadReq_mshr_misses::total          425                       # number of ReadReq MSHR misses
 system.cpu2.icache.demand_mshr_misses::cpu2.inst          425                       # number of demand (read+write) MSHR misses
 system.cpu2.icache.demand_mshr_misses::total          425                       # number of demand (read+write) MSHR misses
 system.cpu2.icache.overall_mshr_misses::cpu2.inst          425                       # number of overall MSHR misses
 system.cpu2.icache.overall_mshr_misses::total          425                       # number of overall MSHR misses
-system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst      9301005                       # number of ReadReq MSHR miss cycles
-system.cpu2.icache.ReadReq_mshr_miss_latency::total      9301005                       # number of ReadReq MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst      9301005                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency::total      9301005                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst      9301005                       # number of overall MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::total      9301005                       # number of overall MSHR miss cycles
-system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.021518                       # mshr miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_mshr_miss_rate::total     0.021518                       # mshr miss rate for ReadReq accesses
-system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst     0.021518                       # mshr miss rate for demand accesses
-system.cpu2.icache.demand_mshr_miss_rate::total     0.021518                       # mshr miss rate for demand accesses
-system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst     0.021518                       # mshr miss rate for overall accesses
-system.cpu2.icache.overall_mshr_miss_rate::total     0.021518                       # mshr miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21884.717647                       # average ReadReq mshr miss latency
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21884.717647                       # average ReadReq mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21884.717647                       # average overall mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::total 21884.717647                       # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21884.717647                       # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::total 21884.717647                       # average overall mshr miss latency
+system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst      9258007                       # number of ReadReq MSHR miss cycles
+system.cpu2.icache.ReadReq_mshr_miss_latency::total      9258007                       # number of ReadReq MSHR miss cycles
+system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst      9258007                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.demand_mshr_miss_latency::total      9258007                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst      9258007                       # number of overall MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_latency::total      9258007                       # number of overall MSHR miss cycles
+system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.019510                       # mshr miss rate for ReadReq accesses
+system.cpu2.icache.ReadReq_mshr_miss_rate::total     0.019510                       # mshr miss rate for ReadReq accesses
+system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst     0.019510                       # mshr miss rate for demand accesses
+system.cpu2.icache.demand_mshr_miss_rate::total     0.019510                       # mshr miss rate for demand accesses
+system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst     0.019510                       # mshr miss rate for overall accesses
+system.cpu2.icache.overall_mshr_miss_rate::total     0.019510                       # mshr miss rate for overall accesses
+system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21783.545882                       # average ReadReq mshr miss latency
+system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21783.545882                       # average ReadReq mshr miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21783.545882                       # average overall mshr miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency::total 21783.545882                       # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21783.545882                       # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency::total 21783.545882                       # average overall mshr miss latency
 system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu2.dcache.tags.replacements                0                       # number of replacements
-system.cpu2.dcache.tags.tagsinuse           26.142591                       # Cycle average of tags in use
-system.cpu2.dcache.tags.total_refs              42207                       # Total number of references to valid blocks.
-system.cpu2.dcache.tags.sampled_refs               28                       # Sample count of references to valid blocks.
-system.cpu2.dcache.tags.avg_refs          1507.392857                       # Average number of references to valid blocks.
+system.cpu2.dcache.tags.tagsinuse           26.156826                       # Cycle average of tags in use
+system.cpu2.dcache.tags.total_refs              37738                       # Total number of references to valid blocks.
+system.cpu2.dcache.tags.sampled_refs               29                       # Sample count of references to valid blocks.
+system.cpu2.dcache.tags.avg_refs          1301.310345                       # Average number of references to valid blocks.
 system.cpu2.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu2.dcache.tags.occ_blocks::cpu2.data    26.142591                       # Average occupied blocks per requestor
-system.cpu2.dcache.tags.occ_percent::cpu2.data     0.051060                       # Average percentage of cache occupancy
-system.cpu2.dcache.tags.occ_percent::total     0.051060                       # Average percentage of cache occupancy
-system.cpu2.dcache.tags.occ_task_id_blocks::1024           28                       # Occupied blocks per task id
+system.cpu2.dcache.tags.occ_blocks::cpu2.data    26.156826                       # Average occupied blocks per requestor
+system.cpu2.dcache.tags.occ_percent::cpu2.data     0.051088                       # Average percentage of cache occupancy
+system.cpu2.dcache.tags.occ_percent::total     0.051088                       # Average percentage of cache occupancy
+system.cpu2.dcache.tags.occ_task_id_blocks::1024           29                       # Occupied blocks per task id
+system.cpu2.dcache.tags.age_task_id_blocks_1024::0            1                       # Occupied blocks per task id
 system.cpu2.dcache.tags.age_task_id_blocks_1024::1           28                       # Occupied blocks per task id
-system.cpu2.dcache.tags.occ_task_id_percent::1024     0.054688                       # Percentage of cache occupancy per task id
-system.cpu2.dcache.tags.tag_accesses           328789                       # Number of tag accesses
-system.cpu2.dcache.tags.data_accesses          328789                       # Number of data accesses
-system.cpu2.dcache.ReadReq_hits::cpu2.data        45613                       # number of ReadReq hits
-system.cpu2.dcache.ReadReq_hits::total          45613                       # number of ReadReq hits
-system.cpu2.dcache.WriteReq_hits::cpu2.data        35966                       # number of WriteReq hits
-system.cpu2.dcache.WriteReq_hits::total         35966                       # number of WriteReq hits
-system.cpu2.dcache.SwapReq_hits::cpu2.data           13                       # number of SwapReq hits
-system.cpu2.dcache.SwapReq_hits::total             13                       # number of SwapReq hits
-system.cpu2.dcache.demand_hits::cpu2.data        81579                       # number of demand (read+write) hits
-system.cpu2.dcache.demand_hits::total           81579                       # number of demand (read+write) hits
-system.cpu2.dcache.overall_hits::cpu2.data        81579                       # number of overall hits
-system.cpu2.dcache.overall_hits::total          81579                       # number of overall hits
-system.cpu2.dcache.ReadReq_misses::cpu2.data          346                       # number of ReadReq misses
-system.cpu2.dcache.ReadReq_misses::total          346                       # number of ReadReq misses
-system.cpu2.dcache.WriteReq_misses::cpu2.data          139                       # number of WriteReq misses
-system.cpu2.dcache.WriteReq_misses::total          139                       # number of WriteReq misses
-system.cpu2.dcache.SwapReq_misses::cpu2.data           57                       # number of SwapReq misses
-system.cpu2.dcache.SwapReq_misses::total           57                       # number of SwapReq misses
-system.cpu2.dcache.demand_misses::cpu2.data          485                       # number of demand (read+write) misses
-system.cpu2.dcache.demand_misses::total           485                       # number of demand (read+write) misses
-system.cpu2.dcache.overall_misses::cpu2.data          485                       # number of overall misses
-system.cpu2.dcache.overall_misses::total          485                       # number of overall misses
-system.cpu2.dcache.ReadReq_miss_latency::cpu2.data      5532140                       # number of ReadReq miss cycles
-system.cpu2.dcache.ReadReq_miss_latency::total      5532140                       # number of ReadReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency::cpu2.data      3131011                       # number of WriteReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency::total      3131011                       # number of WriteReq miss cycles
-system.cpu2.dcache.SwapReq_miss_latency::cpu2.data       555006                       # number of SwapReq miss cycles
-system.cpu2.dcache.SwapReq_miss_latency::total       555006                       # number of SwapReq miss cycles
-system.cpu2.dcache.demand_miss_latency::cpu2.data      8663151                       # number of demand (read+write) miss cycles
-system.cpu2.dcache.demand_miss_latency::total      8663151                       # number of demand (read+write) miss cycles
-system.cpu2.dcache.overall_miss_latency::cpu2.data      8663151                       # number of overall miss cycles
-system.cpu2.dcache.overall_miss_latency::total      8663151                       # number of overall miss cycles
-system.cpu2.dcache.ReadReq_accesses::cpu2.data        45959                       # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.ReadReq_accesses::total        45959                       # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::cpu2.data        36105                       # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::total        36105                       # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.SwapReq_accesses::cpu2.data           70                       # number of SwapReq accesses(hits+misses)
-system.cpu2.dcache.SwapReq_accesses::total           70                       # number of SwapReq accesses(hits+misses)
-system.cpu2.dcache.demand_accesses::cpu2.data        82064                       # number of demand (read+write) accesses
-system.cpu2.dcache.demand_accesses::total        82064                       # number of demand (read+write) accesses
-system.cpu2.dcache.overall_accesses::cpu2.data        82064                       # number of overall (read+write) accesses
-system.cpu2.dcache.overall_accesses::total        82064                       # number of overall (read+write) accesses
-system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.007528                       # miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_miss_rate::total     0.007528                       # miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.003850                       # miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::total     0.003850                       # miss rate for WriteReq accesses
-system.cpu2.dcache.SwapReq_miss_rate::cpu2.data     0.814286                       # miss rate for SwapReq accesses
-system.cpu2.dcache.SwapReq_miss_rate::total     0.814286                       # miss rate for SwapReq accesses
-system.cpu2.dcache.demand_miss_rate::cpu2.data     0.005910                       # miss rate for demand accesses
-system.cpu2.dcache.demand_miss_rate::total     0.005910                       # miss rate for demand accesses
-system.cpu2.dcache.overall_miss_rate::cpu2.data     0.005910                       # miss rate for overall accesses
-system.cpu2.dcache.overall_miss_rate::total     0.005910                       # miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 15988.843931                       # average ReadReq miss latency
-system.cpu2.dcache.ReadReq_avg_miss_latency::total 15988.843931                       # average ReadReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 22525.258993                       # average WriteReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency::total 22525.258993                       # average WriteReq miss latency
-system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data  9736.947368                       # average SwapReq miss latency
-system.cpu2.dcache.SwapReq_avg_miss_latency::total  9736.947368                       # average SwapReq miss latency
-system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17862.167010                       # average overall miss latency
-system.cpu2.dcache.demand_avg_miss_latency::total 17862.167010                       # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17862.167010                       # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::total 17862.167010                       # average overall miss latency
+system.cpu2.dcache.tags.occ_task_id_percent::1024     0.056641                       # Percentage of cache occupancy per task id
+system.cpu2.dcache.tags.tag_accesses           296038                       # Number of tag accesses
+system.cpu2.dcache.tags.data_accesses          296038                       # Number of data accesses
+system.cpu2.dcache.ReadReq_hits::cpu2.data        42011                       # number of ReadReq hits
+system.cpu2.dcache.ReadReq_hits::total          42011                       # number of ReadReq hits
+system.cpu2.dcache.WriteReq_hits::cpu2.data        31379                       # number of WriteReq hits
+system.cpu2.dcache.WriteReq_hits::total         31379                       # number of WriteReq hits
+system.cpu2.dcache.SwapReq_hits::cpu2.data           14                       # number of SwapReq hits
+system.cpu2.dcache.SwapReq_hits::total             14                       # number of SwapReq hits
+system.cpu2.dcache.demand_hits::cpu2.data        73390                       # number of demand (read+write) hits
+system.cpu2.dcache.demand_hits::total           73390                       # number of demand (read+write) hits
+system.cpu2.dcache.overall_hits::cpu2.data        73390                       # number of overall hits
+system.cpu2.dcache.overall_hits::total          73390                       # number of overall hits
+system.cpu2.dcache.ReadReq_misses::cpu2.data          342                       # number of ReadReq misses
+system.cpu2.dcache.ReadReq_misses::total          342                       # number of ReadReq misses
+system.cpu2.dcache.WriteReq_misses::cpu2.data          140                       # number of WriteReq misses
+system.cpu2.dcache.WriteReq_misses::total          140                       # number of WriteReq misses
+system.cpu2.dcache.SwapReq_misses::cpu2.data           59                       # number of SwapReq misses
+system.cpu2.dcache.SwapReq_misses::total           59                       # number of SwapReq misses
+system.cpu2.dcache.demand_misses::cpu2.data          482                       # number of demand (read+write) misses
+system.cpu2.dcache.demand_misses::total           482                       # number of demand (read+write) misses
+system.cpu2.dcache.overall_misses::cpu2.data          482                       # number of overall misses
+system.cpu2.dcache.overall_misses::total          482                       # number of overall misses
+system.cpu2.dcache.ReadReq_miss_latency::cpu2.data      5441573                       # number of ReadReq miss cycles
+system.cpu2.dcache.ReadReq_miss_latency::total      5441573                       # number of ReadReq miss cycles
+system.cpu2.dcache.WriteReq_miss_latency::cpu2.data      3139010                       # number of WriteReq miss cycles
+system.cpu2.dcache.WriteReq_miss_latency::total      3139010                       # number of WriteReq miss cycles
+system.cpu2.dcache.SwapReq_miss_latency::cpu2.data       574505                       # number of SwapReq miss cycles
+system.cpu2.dcache.SwapReq_miss_latency::total       574505                       # number of SwapReq miss cycles
+system.cpu2.dcache.demand_miss_latency::cpu2.data      8580583                       # number of demand (read+write) miss cycles
+system.cpu2.dcache.demand_miss_latency::total      8580583                       # number of demand (read+write) miss cycles
+system.cpu2.dcache.overall_miss_latency::cpu2.data      8580583                       # number of overall miss cycles
+system.cpu2.dcache.overall_miss_latency::total      8580583                       # number of overall miss cycles
+system.cpu2.dcache.ReadReq_accesses::cpu2.data        42353                       # number of ReadReq accesses(hits+misses)
+system.cpu2.dcache.ReadReq_accesses::total        42353                       # number of ReadReq accesses(hits+misses)
+system.cpu2.dcache.WriteReq_accesses::cpu2.data        31519                       # number of WriteReq accesses(hits+misses)
+system.cpu2.dcache.WriteReq_accesses::total        31519                       # number of WriteReq accesses(hits+misses)
+system.cpu2.dcache.SwapReq_accesses::cpu2.data           73                       # number of SwapReq accesses(hits+misses)
+system.cpu2.dcache.SwapReq_accesses::total           73                       # number of SwapReq accesses(hits+misses)
+system.cpu2.dcache.demand_accesses::cpu2.data        73872                       # number of demand (read+write) accesses
+system.cpu2.dcache.demand_accesses::total        73872                       # number of demand (read+write) accesses
+system.cpu2.dcache.overall_accesses::cpu2.data        73872                       # number of overall (read+write) accesses
+system.cpu2.dcache.overall_accesses::total        73872                       # number of overall (read+write) accesses
+system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.008075                       # miss rate for ReadReq accesses
+system.cpu2.dcache.ReadReq_miss_rate::total     0.008075                       # miss rate for ReadReq accesses
+system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.004442                       # miss rate for WriteReq accesses
+system.cpu2.dcache.WriteReq_miss_rate::total     0.004442                       # miss rate for WriteReq accesses
+system.cpu2.dcache.SwapReq_miss_rate::cpu2.data     0.808219                       # miss rate for SwapReq accesses
+system.cpu2.dcache.SwapReq_miss_rate::total     0.808219                       # miss rate for SwapReq accesses
+system.cpu2.dcache.demand_miss_rate::cpu2.data     0.006525                       # miss rate for demand accesses
+system.cpu2.dcache.demand_miss_rate::total     0.006525                       # miss rate for demand accesses
+system.cpu2.dcache.overall_miss_rate::cpu2.data     0.006525                       # miss rate for overall accesses
+system.cpu2.dcache.overall_miss_rate::total     0.006525                       # miss rate for overall accesses
+system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 15911.032164                       # average ReadReq miss latency
+system.cpu2.dcache.ReadReq_avg_miss_latency::total 15911.032164                       # average ReadReq miss latency
+system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 22421.500000                       # average WriteReq miss latency
+system.cpu2.dcache.WriteReq_avg_miss_latency::total 22421.500000                       # average WriteReq miss latency
+system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data  9737.372881                       # average SwapReq miss latency
+system.cpu2.dcache.SwapReq_avg_miss_latency::total  9737.372881                       # average SwapReq miss latency
+system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17802.039419                       # average overall miss latency
+system.cpu2.dcache.demand_avg_miss_latency::total 17802.039419                       # average overall miss latency
+system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17802.039419                       # average overall miss latency
+system.cpu2.dcache.overall_avg_miss_latency::total 17802.039419                       # average overall miss latency
 system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -2120,371 +2143,371 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu2.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu2.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data          184                       # number of ReadReq MSHR hits
-system.cpu2.dcache.ReadReq_mshr_hits::total          184                       # number of ReadReq MSHR hits
-system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data           33                       # number of WriteReq MSHR hits
-system.cpu2.dcache.WriteReq_mshr_hits::total           33                       # number of WriteReq MSHR hits
-system.cpu2.dcache.demand_mshr_hits::cpu2.data          217                       # number of demand (read+write) MSHR hits
-system.cpu2.dcache.demand_mshr_hits::total          217                       # number of demand (read+write) MSHR hits
-system.cpu2.dcache.overall_mshr_hits::cpu2.data          217                       # number of overall MSHR hits
-system.cpu2.dcache.overall_mshr_hits::total          217                       # number of overall MSHR hits
-system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data          162                       # number of ReadReq MSHR misses
-system.cpu2.dcache.ReadReq_mshr_misses::total          162                       # number of ReadReq MSHR misses
+system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data          177                       # number of ReadReq MSHR hits
+system.cpu2.dcache.ReadReq_mshr_hits::total          177                       # number of ReadReq MSHR hits
+system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data           34                       # number of WriteReq MSHR hits
+system.cpu2.dcache.WriteReq_mshr_hits::total           34                       # number of WriteReq MSHR hits
+system.cpu2.dcache.demand_mshr_hits::cpu2.data          211                       # number of demand (read+write) MSHR hits
+system.cpu2.dcache.demand_mshr_hits::total          211                       # number of demand (read+write) MSHR hits
+system.cpu2.dcache.overall_mshr_hits::cpu2.data          211                       # number of overall MSHR hits
+system.cpu2.dcache.overall_mshr_hits::total          211                       # number of overall MSHR hits
+system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data          165                       # number of ReadReq MSHR misses
+system.cpu2.dcache.ReadReq_mshr_misses::total          165                       # number of ReadReq MSHR misses
 system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data          106                       # number of WriteReq MSHR misses
 system.cpu2.dcache.WriteReq_mshr_misses::total          106                       # number of WriteReq MSHR misses
-system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data           57                       # number of SwapReq MSHR misses
-system.cpu2.dcache.SwapReq_mshr_misses::total           57                       # number of SwapReq MSHR misses
-system.cpu2.dcache.demand_mshr_misses::cpu2.data          268                       # number of demand (read+write) MSHR misses
-system.cpu2.dcache.demand_mshr_misses::total          268                       # number of demand (read+write) MSHR misses
-system.cpu2.dcache.overall_mshr_misses::cpu2.data          268                       # number of overall MSHR misses
-system.cpu2.dcache.overall_mshr_misses::total          268                       # number of overall MSHR misses
-system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data      1488769                       # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_latency::total      1488769                       # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data      1526989                       # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::total      1526989                       # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data       440994                       # number of SwapReq MSHR miss cycles
-system.cpu2.dcache.SwapReq_mshr_miss_latency::total       440994                       # number of SwapReq MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data      3015758                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::total      3015758                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data      3015758                       # number of overall MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::total      3015758                       # number of overall MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.003525                       # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_mshr_miss_rate::total     0.003525                       # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.002936                       # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate::total     0.002936                       # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data     0.814286                       # mshr miss rate for SwapReq accesses
-system.cpu2.dcache.SwapReq_mshr_miss_rate::total     0.814286                       # mshr miss rate for SwapReq accesses
-system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data     0.003266                       # mshr miss rate for demand accesses
-system.cpu2.dcache.demand_mshr_miss_rate::total     0.003266                       # mshr miss rate for demand accesses
-system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data     0.003266                       # mshr miss rate for overall accesses
-system.cpu2.dcache.overall_mshr_miss_rate::total     0.003266                       # mshr miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data  9189.932099                       # average ReadReq mshr miss latency
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total  9189.932099                       # average ReadReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 14405.556604                       # average WriteReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 14405.556604                       # average WriteReq mshr miss latency
-system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data  7736.736842                       # average SwapReq mshr miss latency
-system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total  7736.736842                       # average SwapReq mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11252.828358                       # average overall mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11252.828358                       # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11252.828358                       # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11252.828358                       # average overall mshr miss latency
+system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data           59                       # number of SwapReq MSHR misses
+system.cpu2.dcache.SwapReq_mshr_misses::total           59                       # number of SwapReq MSHR misses
+system.cpu2.dcache.demand_mshr_misses::cpu2.data          271                       # number of demand (read+write) MSHR misses
+system.cpu2.dcache.demand_mshr_misses::total          271                       # number of demand (read+write) MSHR misses
+system.cpu2.dcache.overall_mshr_misses::cpu2.data          271                       # number of overall MSHR misses
+system.cpu2.dcache.overall_mshr_misses::total          271                       # number of overall MSHR misses
+system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data      1516779                       # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_latency::total      1516779                       # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data      1527990                       # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_latency::total      1527990                       # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data       456495                       # number of SwapReq MSHR miss cycles
+system.cpu2.dcache.SwapReq_mshr_miss_latency::total       456495                       # number of SwapReq MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data      3044769                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency::total      3044769                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data      3044769                       # number of overall MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::total      3044769                       # number of overall MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.003896                       # mshr miss rate for ReadReq accesses
+system.cpu2.dcache.ReadReq_mshr_miss_rate::total     0.003896                       # mshr miss rate for ReadReq accesses
+system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.003363                       # mshr miss rate for WriteReq accesses
+system.cpu2.dcache.WriteReq_mshr_miss_rate::total     0.003363                       # mshr miss rate for WriteReq accesses
+system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data     0.808219                       # mshr miss rate for SwapReq accesses
+system.cpu2.dcache.SwapReq_mshr_miss_rate::total     0.808219                       # mshr miss rate for SwapReq accesses
+system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data     0.003669                       # mshr miss rate for demand accesses
+system.cpu2.dcache.demand_mshr_miss_rate::total     0.003669                       # mshr miss rate for demand accesses
+system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data     0.003669                       # mshr miss rate for overall accesses
+system.cpu2.dcache.overall_mshr_miss_rate::total     0.003669                       # mshr miss rate for overall accesses
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data  9192.600000                       # average ReadReq mshr miss latency
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total  9192.600000                       # average ReadReq mshr miss latency
+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data        14415                       # average WriteReq mshr miss latency
+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total        14415                       # average WriteReq mshr miss latency
+system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data  7737.203390                       # average SwapReq mshr miss latency
+system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total  7737.203390                       # average SwapReq mshr miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11235.309963                       # average overall mshr miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11235.309963                       # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11235.309963                       # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11235.309963                       # average overall mshr miss latency
 system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu3.branchPred.lookups                  52302                       # Number of BP lookups
-system.cpu3.branchPred.condPredicted            49590                       # Number of conditional branches predicted
-system.cpu3.branchPred.condIncorrect             1266                       # Number of conditional branches incorrect
-system.cpu3.branchPred.BTBLookups               46219                       # Number of BTB lookups
-system.cpu3.branchPred.BTBHits                  45467                       # Number of BTB hits
+system.cpu3.branchPred.lookups                  53969                       # Number of BP lookups
+system.cpu3.branchPred.condPredicted            51237                       # Number of conditional branches predicted
+system.cpu3.branchPred.condIncorrect             1265                       # Number of conditional branches incorrect
+system.cpu3.branchPred.BTBLookups               47879                       # Number of BTB lookups
+system.cpu3.branchPred.BTBHits                  47122                       # Number of BTB hits
 system.cpu3.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu3.branchPred.BTBHitPct            98.372963                       # BTB Hit Percentage
-system.cpu3.branchPred.usedRAS                    659                       # Number of times the RAS was used to get a target.
+system.cpu3.branchPred.BTBHitPct            98.418931                       # BTB Hit Percentage
+system.cpu3.branchPred.usedRAS                    645                       # Number of times the RAS was used to get a target.
 system.cpu3.branchPred.RASInCorrect               232                       # Number of incorrect RAS predictions.
-system.cpu3.numCycles                          177222                       # number of cpu cycles simulated
+system.cpu3.numCycles                          177018                       # number of cpu cycles simulated
 system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu3.fetch.icacheStallCycles             28851                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu3.fetch.Insts                        291591                       # Number of instructions fetch has processed
-system.cpu3.fetch.Branches                      52302                       # Number of branches that fetch encountered
-system.cpu3.fetch.predictedBranches             46126                       # Number of branches that fetch has predicted taken
-system.cpu3.fetch.Cycles                       103443                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu3.fetch.SquashCycles                   3689                       # Number of cycles fetch has spent squashing
-system.cpu3.fetch.BlockedCycles                 32601                       # Number of cycles fetch has spent blocked
+system.cpu3.fetch.icacheStallCycles             27849                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu3.fetch.Insts                        302683                       # Number of instructions fetch has processed
+system.cpu3.fetch.Branches                      53969                       # Number of branches that fetch encountered
+system.cpu3.fetch.predictedBranches             47767                       # Number of branches that fetch has predicted taken
+system.cpu3.fetch.Cycles                       106238                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu3.fetch.SquashCycles                   3643                       # Number of cycles fetch has spent squashing
+system.cpu3.fetch.BlockedCycles                 30687                       # Number of cycles fetch has spent blocked
 system.cpu3.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu3.fetch.NoActiveThreadStallCycles         7775                       # Number of stall cycles due to no active thread to fetch from
+system.cpu3.fetch.NoActiveThreadStallCycles         7755                       # Number of stall cycles due to no active thread to fetch from
 system.cpu3.fetch.PendingTrapStallCycles          799                       # Number of stall cycles due to pending traps
-system.cpu3.fetch.CacheLines                    20565                       # Number of cache lines fetched
-system.cpu3.fetch.IcacheSquashes                  250                       # Number of outstanding Icache misses that were squashed
-system.cpu3.fetch.rateDist::samples            175820                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::mean             1.658463                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::stdev            2.129406                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.CacheLines                    19589                       # Number of cache lines fetched
+system.cpu3.fetch.IcacheSquashes                  266                       # Number of outstanding Icache misses that were squashed
+system.cpu3.fetch.rateDist::samples            175633                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::mean             1.723383                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::stdev            2.153093                       # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::0                   72377     41.17%     41.17% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::1                   52818     30.04%     71.21% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::2                    6573      3.74%     74.94% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::3                    3193      1.82%     76.76% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::4                     659      0.37%     77.14% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::5                   35007     19.91%     97.05% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::6                    1204      0.68%     97.73% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::7                     759      0.43%     98.16% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::8                    3230      1.84%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::0                   69395     39.51%     39.51% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::1                   53961     30.72%     70.24% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::2                    6037      3.44%     73.67% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::3                    3206      1.83%     75.50% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::4                     696      0.40%     75.89% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::5                   37090     21.12%     97.01% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::6                    1217      0.69%     97.70% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::7                     754      0.43%     98.13% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::8                    3277      1.87%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::total              175820                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.branchRate                 0.295121                       # Number of branch fetches per cycle
-system.cpu3.fetch.rate                       1.645343                       # Number of inst fetches per cycle
-system.cpu3.decode.IdleCycles                   34477                       # Number of cycles decode is idle
-system.cpu3.decode.BlockedCycles                28631                       # Number of cycles decode is blocked
-system.cpu3.decode.RunCycles                    97078                       # Number of cycles decode is running
-system.cpu3.decode.UnblockCycles                 5513                       # Number of cycles decode is unblocking
-system.cpu3.decode.SquashCycles                  2346                       # Number of cycles decode is squashing
-system.cpu3.decode.DecodedInsts                288057                       # Number of instructions handled by decode
-system.cpu3.rename.SquashCycles                  2346                       # Number of cycles rename is squashing
-system.cpu3.rename.IdleCycles                   35172                       # Number of cycles rename is idle
-system.cpu3.rename.BlockCycles                  16067                       # Number of cycles rename is blocking
-system.cpu3.rename.serializeStallCycles         11804                       # count of cycles rename stalled for serializing inst
-system.cpu3.rename.RunCycles                    91834                       # Number of cycles rename is running
-system.cpu3.rename.UnblockCycles                10822                       # Number of cycles rename is unblocking
-system.cpu3.rename.RenamedInsts                285905                       # Number of instructions processed by rename
+system.cpu3.fetch.rateDist::total              175633                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.branchRate                 0.304879                       # Number of branch fetches per cycle
+system.cpu3.fetch.rate                       1.709900                       # Number of inst fetches per cycle
+system.cpu3.decode.IdleCycles                   32991                       # Number of cycles decode is idle
+system.cpu3.decode.BlockedCycles                27180                       # Number of cycles decode is blocked
+system.cpu3.decode.RunCycles                   100358                       # Number of cycles decode is running
+system.cpu3.decode.UnblockCycles                 5049                       # Number of cycles decode is unblocking
+system.cpu3.decode.SquashCycles                  2300                       # Number of cycles decode is squashing
+system.cpu3.decode.DecodedInsts                299127                       # Number of instructions handled by decode
+system.cpu3.rename.SquashCycles                  2300                       # Number of cycles rename is squashing
+system.cpu3.rename.IdleCycles                   33666                       # Number of cycles rename is idle
+system.cpu3.rename.BlockCycles                  14636                       # Number of cycles rename is blocking
+system.cpu3.rename.serializeStallCycles         11796                       # count of cycles rename stalled for serializing inst
+system.cpu3.rename.RunCycles                    95593                       # Number of cycles rename is running
+system.cpu3.rename.UnblockCycles                 9887                       # Number of cycles rename is unblocking
+system.cpu3.rename.RenamedInsts                297010                       # Number of instructions processed by rename
 system.cpu3.rename.IQFullEvents                     4                       # Number of times rename has blocked due to IQ full
-system.cpu3.rename.LSQFullEvents                   21                       # Number of times rename has blocked due to LSQ full
-system.cpu3.rename.RenamedOperands             199357                       # Number of destination operands rename has renamed
-system.cpu3.rename.RenameLookups               546724                       # Number of register rename lookups that rename has made
-system.cpu3.rename.int_rename_lookups          424837                       # Number of integer rename lookups
-system.cpu3.rename.CommittedMaps               186591                       # Number of HB maps that are committed
-system.cpu3.rename.UndoneMaps                   12766                       # Number of HB maps that are undone due to squashing
+system.cpu3.rename.LSQFullEvents                   23                       # Number of times rename has blocked due to LSQ full
+system.cpu3.rename.RenamedOperands             207704                       # Number of destination operands rename has renamed
+system.cpu3.rename.RenameLookups               570857                       # Number of register rename lookups that rename has made
+system.cpu3.rename.int_rename_lookups          442944                       # Number of integer rename lookups
+system.cpu3.rename.CommittedMaps               195081                       # Number of HB maps that are committed
+system.cpu3.rename.UndoneMaps                   12623                       # Number of HB maps that are undone due to squashing
 system.cpu3.rename.serializingInsts              1101                       # count of serializing insts renamed
-system.cpu3.rename.tempSerializingInsts          1226                       # count of temporary serializing insts renamed
-system.cpu3.rename.skidInsts                    13474                       # count of insts added to the skid buffer
-system.cpu3.memDep0.insertedLoads               80900                       # Number of loads inserted to the mem dependence unit.
-system.cpu3.memDep0.insertedStores              38213                       # Number of stores inserted to the mem dependence unit.
-system.cpu3.memDep0.conflictingLoads            38893                       # Number of conflicting loads.
-system.cpu3.memDep0.conflictingStores           33161                       # Number of conflicting stores.
-system.cpu3.iq.iqInstsAdded                    236458                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu3.iq.iqNonSpecInstsAdded               6797                       # Number of non-speculative instructions added to the IQ
-system.cpu3.iq.iqInstsIssued                   238990                       # Number of instructions issued
-system.cpu3.iq.iqSquashedInstsIssued              102                       # Number of squashed instructions issued
-system.cpu3.iq.iqSquashedInstsExamined          10736                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu3.iq.iqSquashedOperandsExamined        10730                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu3.iq.iqSquashedNonSpecRemoved           584                       # Number of squashed non-spec instructions that were removed
-system.cpu3.iq.issued_per_cycle::samples       175820                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::mean        1.359288                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::stdev       1.308373                       # Number of insts issued each cycle
+system.cpu3.rename.tempSerializingInsts          1224                       # count of temporary serializing insts renamed
+system.cpu3.rename.skidInsts                    12502                       # count of insts added to the skid buffer
+system.cpu3.memDep0.insertedLoads               84726                       # Number of loads inserted to the mem dependence unit.
+system.cpu3.memDep0.insertedStores              40382                       # Number of stores inserted to the mem dependence unit.
+system.cpu3.memDep0.conflictingLoads            40460                       # Number of conflicting loads.
+system.cpu3.memDep0.conflictingStores           35337                       # Number of conflicting stores.
+system.cpu3.iq.iqInstsAdded                    246420                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu3.iq.iqNonSpecInstsAdded               6261                       # Number of non-speculative instructions added to the IQ
+system.cpu3.iq.iqInstsIssued                   248749                       # Number of instructions issued
+system.cpu3.iq.iqSquashedInstsIssued               57                       # Number of squashed instructions issued
+system.cpu3.iq.iqSquashedInstsExamined          10413                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu3.iq.iqSquashedOperandsExamined         9956                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu3.iq.iqSquashedNonSpecRemoved           566                       # Number of squashed non-spec instructions that were removed
+system.cpu3.iq.issued_per_cycle::samples       175633                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::mean        1.416300                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::stdev       1.309117                       # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::0              69781     39.69%     39.69% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::1              23810     13.54%     53.23% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::2              38390     21.83%     75.07% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::3              39046     22.21%     97.27% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::4               3247      1.85%     99.12% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::5               1173      0.67%     99.79% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::6                261      0.15%     99.94% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::7                 53      0.03%     99.97% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::0              66575     37.91%     37.91% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::1              22292     12.69%     50.60% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::2              40685     23.16%     73.76% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::3              41298     23.51%     97.28% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::4               3252      1.85%     99.13% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::5               1166      0.66%     99.79% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::6                259      0.15%     99.94% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::7                 47      0.03%     99.97% # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::8                 59      0.03%    100.00% # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::total         175820                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::total         175633                       # Number of insts issued each cycle
 system.cpu3.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntAlu                     17      6.20%      6.20% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntMult                     0      0.00%      6.20% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntDiv                      0      0.00%      6.20% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatAdd                    0      0.00%      6.20% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCmp                    0      0.00%      6.20% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCvt                    0      0.00%      6.20% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatMult                   0      0.00%      6.20% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatDiv                    0      0.00%      6.20% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%      6.20% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAdd                     0      0.00%      6.20% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%      6.20% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAlu                     0      0.00%      6.20% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCmp                     0      0.00%      6.20% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCvt                     0      0.00%      6.20% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMisc                    0      0.00%      6.20% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMult                    0      0.00%      6.20% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%      6.20% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShift                   0      0.00%      6.20% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%      6.20% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%      6.20% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%      6.20% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%      6.20% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%      6.20% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%      6.20% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%      6.20% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%      6.20% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%      6.20% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%      6.20% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%      6.20% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemRead                    47     17.15%     23.36% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemWrite                  210     76.64%    100.00% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntAlu                     17      6.46%      6.46% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntMult                     0      0.00%      6.46% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntDiv                      0      0.00%      6.46% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatAdd                    0      0.00%      6.46% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCmp                    0      0.00%      6.46% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCvt                    0      0.00%      6.46% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatMult                   0      0.00%      6.46% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatDiv                    0      0.00%      6.46% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%      6.46% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAdd                     0      0.00%      6.46% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%      6.46% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAlu                     0      0.00%      6.46% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCmp                     0      0.00%      6.46% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCvt                     0      0.00%      6.46% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMisc                    0      0.00%      6.46% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMult                    0      0.00%      6.46% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%      6.46% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShift                   0      0.00%      6.46% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%      6.46% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%      6.46% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%      6.46% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%      6.46% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%      6.46% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%      6.46% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%      6.46% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%      6.46% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%      6.46% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%      6.46% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%      6.46% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemRead                    36     13.69%     20.15% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemWrite                  210     79.85%    100.00% # attempts to use FU when none available
 system.cpu3.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu3.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu3.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntAlu               115815     48.46%     48.46% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntMult                   0      0.00%     48.46% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntDiv                    0      0.00%     48.46% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatAdd                  0      0.00%     48.46% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     48.46% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     48.46% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     48.46% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     48.46% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     48.46% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     48.46% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     48.46% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     48.46% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCmp                   0      0.00%     48.46% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     48.46% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     48.46% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     48.46% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMultAcc               0      0.00%     48.46% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     48.46% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     48.46% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     48.46% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     48.46% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     48.46% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     48.46% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     48.46% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     48.46% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMisc             0      0.00%     48.46% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     48.46% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     48.46% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     48.46% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemRead               85668     35.85%     84.31% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemWrite              37507     15.69%    100.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntAlu               119915     48.21%     48.21% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntMult                   0      0.00%     48.21% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntDiv                    0      0.00%     48.21% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatAdd                  0      0.00%     48.21% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     48.21% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     48.21% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     48.21% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     48.21% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     48.21% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     48.21% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     48.21% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     48.21% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCmp                   0      0.00%     48.21% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     48.21% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     48.21% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     48.21% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMultAcc               0      0.00%     48.21% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     48.21% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     48.21% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     48.21% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     48.21% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     48.21% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     48.21% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     48.21% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     48.21% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMisc             0      0.00%     48.21% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     48.21% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     48.21% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     48.21% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemRead               89111     35.82%     84.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemWrite              39723     15.97%    100.00% # Type of FU issued
 system.cpu3.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu3.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::total                238990                       # Type of FU issued
-system.cpu3.iq.rate                          1.348535                       # Inst issue rate
-system.cpu3.iq.fu_busy_cnt                        274                       # FU busy when requested
-system.cpu3.iq.fu_busy_rate                  0.001146                       # FU busy rate (busy events/executed inst)
-system.cpu3.iq.int_inst_queue_reads            654176                       # Number of integer instruction queue reads
-system.cpu3.iq.int_inst_queue_writes           254038                       # Number of integer instruction queue writes
-system.cpu3.iq.int_inst_queue_wakeup_accesses       237197                       # Number of integer instruction queue wakeup accesses
+system.cpu3.iq.FU_type_0::total                248749                       # Type of FU issued
+system.cpu3.iq.rate                          1.405219                       # Inst issue rate
+system.cpu3.iq.fu_busy_cnt                        263                       # FU busy when requested
+system.cpu3.iq.fu_busy_rate                  0.001057                       # FU busy rate (busy events/executed inst)
+system.cpu3.iq.int_inst_queue_reads            673451                       # Number of integer instruction queue reads
+system.cpu3.iq.int_inst_queue_writes           263132                       # Number of integer instruction queue writes
+system.cpu3.iq.int_inst_queue_wakeup_accesses       246950                       # Number of integer instruction queue wakeup accesses
 system.cpu3.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
 system.cpu3.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
 system.cpu3.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu3.iq.int_alu_accesses                239264                       # Number of integer alu accesses
+system.cpu3.iq.int_alu_accesses                249012                       # Number of integer alu accesses
 system.cpu3.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
-system.cpu3.iew.lsq.thread0.forwLoads           32896                       # Number of loads that had data forwarded from stores
+system.cpu3.iew.lsq.thread0.forwLoads           35153                       # Number of loads that had data forwarded from stores
 system.cpu3.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu3.iew.lsq.thread0.squashedLoads         2413                       # Number of loads squashed
+system.cpu3.iew.lsq.thread0.squashedLoads         2247                       # Number of loads squashed
 system.cpu3.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
-system.cpu3.iew.lsq.thread0.memOrderViolation           47                       # Number of memory ordering violations
-system.cpu3.iew.lsq.thread0.squashedStores         1461                       # Number of stores squashed
+system.cpu3.iew.lsq.thread0.memOrderViolation           38                       # Number of memory ordering violations
+system.cpu3.iew.lsq.thread0.squashedStores         1385                       # Number of stores squashed
 system.cpu3.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu3.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu3.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
 system.cpu3.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu3.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu3.iew.iewSquashCycles                  2346                       # Number of cycles IEW is squashing
-system.cpu3.iew.iewBlockCycles                    674                       # Number of cycles IEW is blocking
-system.cpu3.iew.iewUnblockCycles                   43                       # Number of cycles IEW is unblocking
-system.cpu3.iew.iewDispatchedInsts             283043                       # Number of instructions dispatched to IQ
-system.cpu3.iew.iewDispSquashedInsts              388                       # Number of squashed instructions skipped by dispatch
-system.cpu3.iew.iewDispLoadInsts                80900                       # Number of dispatched load instructions
-system.cpu3.iew.iewDispStoreInsts               38213                       # Number of dispatched store instructions
-system.cpu3.iew.iewDispNonSpecInsts              1061                       # Number of dispatched non-speculative instructions
-system.cpu3.iew.iewIQFullEvents                    42                       # Number of times the IQ has become full, causing a stall
+system.cpu3.iew.iewSquashCycles                  2300                       # Number of cycles IEW is squashing
+system.cpu3.iew.iewBlockCycles                    645                       # Number of cycles IEW is blocking
+system.cpu3.iew.iewUnblockCycles                   39                       # Number of cycles IEW is unblocking
+system.cpu3.iew.iewDispatchedInsts             294144                       # Number of instructions dispatched to IQ
+system.cpu3.iew.iewDispSquashedInsts              354                       # Number of squashed instructions skipped by dispatch
+system.cpu3.iew.iewDispLoadInsts                84726                       # Number of dispatched load instructions
+system.cpu3.iew.iewDispStoreInsts               40382                       # Number of dispatched store instructions
+system.cpu3.iew.iewDispNonSpecInsts              1060                       # Number of dispatched non-speculative instructions
+system.cpu3.iew.iewIQFullEvents                    38                       # Number of times the IQ has become full, causing a stall
 system.cpu3.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
-system.cpu3.iew.memOrderViolationEvents            47                       # Number of memory order violations
-system.cpu3.iew.predictedTakenIncorrect           456                       # Number of branches that were predicted taken incorrectly
-system.cpu3.iew.predictedNotTakenIncorrect          929                       # Number of branches that were predicted not taken incorrectly
-system.cpu3.iew.branchMispredicts                1385                       # Number of branch mispredicts detected at execute
-system.cpu3.iew.iewExecutedInsts               237848                       # Number of executed instructions
-system.cpu3.iew.iewExecLoadInsts                79902                       # Number of load instructions executed
-system.cpu3.iew.iewExecSquashedInsts             1142                       # Number of squashed instructions skipped in execute
+system.cpu3.iew.memOrderViolationEvents            38                       # Number of memory order violations
+system.cpu3.iew.predictedTakenIncorrect           459                       # Number of branches that were predicted taken incorrectly
+system.cpu3.iew.predictedNotTakenIncorrect          919                       # Number of branches that were predicted not taken incorrectly
+system.cpu3.iew.branchMispredicts                1378                       # Number of branch mispredicts detected at execute
+system.cpu3.iew.iewExecutedInsts               247595                       # Number of executed instructions
+system.cpu3.iew.iewExecLoadInsts                83855                       # Number of load instructions executed
+system.cpu3.iew.iewExecSquashedInsts             1154                       # Number of squashed instructions skipped in execute
 system.cpu3.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu3.iew.exec_nop                        39788                       # number of nop insts executed
-system.cpu3.iew.exec_refs                      117326                       # number of memory reference insts executed
-system.cpu3.iew.exec_branches                   49028                       # Number of branches executed
-system.cpu3.iew.exec_stores                     37424                       # Number of stores executed
-system.cpu3.iew.exec_rate                    1.342091                       # Inst execution rate
-system.cpu3.iew.wb_sent                        237481                       # cumulative count of insts sent to commit
-system.cpu3.iew.wb_count                       237197                       # cumulative count of insts written-back
-system.cpu3.iew.wb_producers                   134032                       # num instructions producing a value
-system.cpu3.iew.wb_consumers                   138708                       # num instructions consuming a value
+system.cpu3.iew.exec_nop                        41463                       # number of nop insts executed
+system.cpu3.iew.exec_refs                      123509                       # number of memory reference insts executed
+system.cpu3.iew.exec_branches                   50804                       # Number of branches executed
+system.cpu3.iew.exec_stores                     39654                       # Number of stores executed
+system.cpu3.iew.exec_rate                    1.398700                       # Inst execution rate
+system.cpu3.iew.wb_sent                        247239                       # cumulative count of insts sent to commit
+system.cpu3.iew.wb_count                       246950                       # cumulative count of insts written-back
+system.cpu3.iew.wb_producers                   140249                       # num instructions producing a value
+system.cpu3.iew.wb_consumers                   144916                       # num instructions consuming a value
 system.cpu3.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu3.iew.wb_rate                      1.338417                       # insts written-back per cycle
-system.cpu3.iew.wb_fanout                    0.966289                       # average fanout of values written-back
+system.cpu3.iew.wb_rate                      1.395056                       # insts written-back per cycle
+system.cpu3.iew.wb_fanout                    0.967795                       # average fanout of values written-back
 system.cpu3.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu3.commit.commitSquashedInsts          12298                       # The number of squashed insts skipped by commit
-system.cpu3.commit.commitNonSpecStalls           6213                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu3.commit.branchMispredicts             1266                       # The number of times a branch was mispredicted
-system.cpu3.commit.committed_per_cycle::samples       165699                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::mean     1.633836                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::stdev     2.016583                       # Number of insts commited each cycle
+system.cpu3.commit.commitSquashedInsts          11951                       # The number of squashed insts skipped by commit
+system.cpu3.commit.commitNonSpecStalls           5695                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu3.commit.branchMispredicts             1265                       # The number of times a branch was mispredicted
+system.cpu3.commit.committed_per_cycle::samples       165578                       # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::mean     1.704170                       # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::stdev     2.038930                       # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::0        68017     41.05%     41.05% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::1        47143     28.45%     69.50% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::2         6068      3.66%     73.16% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::3         7148      4.31%     77.48% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::4         1577      0.95%     78.43% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::5        33420     20.17%     98.60% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::6          508      0.31%     98.90% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::7          998      0.60%     99.51% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::8          820      0.49%    100.00% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::0        64386     38.89%     38.89% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::1        48906     29.54%     68.42% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::2         6087      3.68%     72.10% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::3         6642      4.01%     76.11% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::4         1574      0.95%     77.06% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::5        35662     21.54%     98.60% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::6          504      0.30%     98.90% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::7          999      0.60%     99.51% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::8          818      0.49%    100.00% # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::total       165699                       # Number of insts commited each cycle
-system.cpu3.commit.committedInsts              270725                       # Number of instructions committed
-system.cpu3.commit.committedOps                270725                       # Number of ops (including micro ops) committed
+system.cpu3.commit.committed_per_cycle::total       165578                       # Number of insts commited each cycle
+system.cpu3.commit.committedInsts              282173                       # Number of instructions committed
+system.cpu3.commit.committedOps                282173                       # Number of ops (including micro ops) committed
 system.cpu3.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu3.commit.refs                        115239                       # Number of memory references committed
-system.cpu3.commit.loads                        78487                       # Number of loads committed
-system.cpu3.commit.membars                       5499                       # Number of memory barriers committed
-system.cpu3.commit.branches                     48212                       # Number of branches committed
+system.cpu3.commit.refs                        121476                       # Number of memory references committed
+system.cpu3.commit.loads                        82479                       # Number of loads committed
+system.cpu3.commit.membars                       4985                       # Number of memory barriers committed
+system.cpu3.commit.branches                     49947                       # Number of branches committed
 system.cpu3.commit.fp_insts                         0                       # Number of committed floating point instructions.
-system.cpu3.commit.int_insts                   185574                       # Number of committed integer instructions.
+system.cpu3.commit.int_insts                   193548                       # Number of committed integer instructions.
 system.cpu3.commit.function_calls                 322                       # Number of function calls committed.
-system.cpu3.commit.bw_lim_events                  820                       # number cycles where commit BW limit reached
+system.cpu3.commit.bw_lim_events                  818                       # number cycles where commit BW limit reached
 system.cpu3.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu3.rob.rob_reads                      447315                       # The number of ROB reads
-system.cpu3.rob.rob_writes                     568397                       # The number of ROB writes
-system.cpu3.timesIdled                            211                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu3.idleCycles                           1402                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu3.quiesceCycles                       44828                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu3.committedInsts                     226224                       # Number of Instructions Simulated
-system.cpu3.committedOps                       226224                       # Number of Ops (including micro ops) Simulated
-system.cpu3.committedInsts_total               226224                       # Number of Instructions Simulated
-system.cpu3.cpi                              0.783392                       # CPI: Cycles Per Instruction
-system.cpu3.cpi_total                        0.783392                       # CPI: Total CPI of All Threads
-system.cpu3.ipc                              1.276501                       # IPC: Instructions Per Cycle
-system.cpu3.ipc_total                        1.276501                       # IPC: Total IPC of All Threads
-system.cpu3.int_regfile_reads                  410473                       # number of integer regfile reads
-system.cpu3.int_regfile_writes                 191353                       # number of integer regfile writes
+system.cpu3.rob.rob_reads                      458297                       # The number of ROB reads
+system.cpu3.rob.rob_writes                     590554                       # The number of ROB writes
+system.cpu3.timesIdled                            210                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu3.idleCycles                           1385                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu3.quiesceCycles                       44892                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu3.committedInsts                     236447                       # Number of Instructions Simulated
+system.cpu3.committedOps                       236447                       # Number of Ops (including micro ops) Simulated
+system.cpu3.committedInsts_total               236447                       # Number of Instructions Simulated
+system.cpu3.cpi                              0.748658                       # CPI: Cycles Per Instruction
+system.cpu3.cpi_total                        0.748658                       # CPI: Total CPI of All Threads
+system.cpu3.ipc                              1.335723                       # IPC: Instructions Per Cycle
+system.cpu3.ipc_total                        1.335723                       # IPC: Total IPC of All Threads
+system.cpu3.int_regfile_reads                  429146                       # number of integer regfile reads
+system.cpu3.int_regfile_writes                 199911                       # number of integer regfile writes
 system.cpu3.fp_regfile_writes                      64                       # number of floating regfile writes
-system.cpu3.misc_regfile_reads                 118878                       # number of misc regfile reads
+system.cpu3.misc_regfile_reads                 125103                       # number of misc regfile reads
 system.cpu3.misc_regfile_writes                   648                       # number of misc regfile writes
 system.cpu3.icache.tags.replacements              319                       # number of replacements
-system.cpu3.icache.tags.tagsinuse           79.942822                       # Cycle average of tags in use
-system.cpu3.icache.tags.total_refs              20090                       # Total number of references to valid blocks.
-system.cpu3.icache.tags.sampled_refs              429                       # Sample count of references to valid blocks.
-system.cpu3.icache.tags.avg_refs            46.829837                       # Average number of references to valid blocks.
+system.cpu3.icache.tags.tagsinuse           80.480006                       # Cycle average of tags in use
+system.cpu3.icache.tags.total_refs              19114                       # Total number of references to valid blocks.
+system.cpu3.icache.tags.sampled_refs              430                       # Sample count of references to valid blocks.
+system.cpu3.icache.tags.avg_refs            44.451163                       # Average number of references to valid blocks.
 system.cpu3.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu3.icache.tags.occ_blocks::cpu3.inst    79.942822                       # Average occupied blocks per requestor
-system.cpu3.icache.tags.occ_percent::cpu3.inst     0.156138                       # Average percentage of cache occupancy
-system.cpu3.icache.tags.occ_percent::total     0.156138                       # Average percentage of cache occupancy
-system.cpu3.icache.tags.occ_task_id_blocks::1024          110                       # Occupied blocks per task id
+system.cpu3.icache.tags.occ_blocks::cpu3.inst    80.480006                       # Average occupied blocks per requestor
+system.cpu3.icache.tags.occ_percent::cpu3.inst     0.157188                       # Average percentage of cache occupancy
+system.cpu3.icache.tags.occ_percent::total     0.157188                       # Average percentage of cache occupancy
+system.cpu3.icache.tags.occ_task_id_blocks::1024          111                       # Occupied blocks per task id
 system.cpu3.icache.tags.age_task_id_blocks_1024::0           10                       # Occupied blocks per task id
-system.cpu3.icache.tags.age_task_id_blocks_1024::1          100                       # Occupied blocks per task id
-system.cpu3.icache.tags.occ_task_id_percent::1024     0.214844                       # Percentage of cache occupancy per task id
-system.cpu3.icache.tags.tag_accesses            20994                       # Number of tag accesses
-system.cpu3.icache.tags.data_accesses           20994                       # Number of data accesses
-system.cpu3.icache.ReadReq_hits::cpu3.inst        20090                       # number of ReadReq hits
-system.cpu3.icache.ReadReq_hits::total          20090                       # number of ReadReq hits
-system.cpu3.icache.demand_hits::cpu3.inst        20090                       # number of demand (read+write) hits
-system.cpu3.icache.demand_hits::total           20090                       # number of demand (read+write) hits
-system.cpu3.icache.overall_hits::cpu3.inst        20090                       # number of overall hits
-system.cpu3.icache.overall_hits::total          20090                       # number of overall hits
+system.cpu3.icache.tags.age_task_id_blocks_1024::1          101                       # Occupied blocks per task id
+system.cpu3.icache.tags.occ_task_id_percent::1024     0.216797                       # Percentage of cache occupancy per task id
+system.cpu3.icache.tags.tag_accesses            20019                       # Number of tag accesses
+system.cpu3.icache.tags.data_accesses           20019                       # Number of data accesses
+system.cpu3.icache.ReadReq_hits::cpu3.inst        19114                       # number of ReadReq hits
+system.cpu3.icache.ReadReq_hits::total          19114                       # number of ReadReq hits
+system.cpu3.icache.demand_hits::cpu3.inst        19114                       # number of demand (read+write) hits
+system.cpu3.icache.demand_hits::total           19114                       # number of demand (read+write) hits
+system.cpu3.icache.overall_hits::cpu3.inst        19114                       # number of overall hits
+system.cpu3.icache.overall_hits::total          19114                       # number of overall hits
 system.cpu3.icache.ReadReq_misses::cpu3.inst          475                       # number of ReadReq misses
 system.cpu3.icache.ReadReq_misses::total          475                       # number of ReadReq misses
 system.cpu3.icache.demand_misses::cpu3.inst          475                       # number of demand (read+write) misses
 system.cpu3.icache.demand_misses::total           475                       # number of demand (read+write) misses
 system.cpu3.icache.overall_misses::cpu3.inst          475                       # number of overall misses
 system.cpu3.icache.overall_misses::total          475                       # number of overall misses
-system.cpu3.icache.ReadReq_miss_latency::cpu3.inst      6449745                       # number of ReadReq miss cycles
-system.cpu3.icache.ReadReq_miss_latency::total      6449745                       # number of ReadReq miss cycles
-system.cpu3.icache.demand_miss_latency::cpu3.inst      6449745                       # number of demand (read+write) miss cycles
-system.cpu3.icache.demand_miss_latency::total      6449745                       # number of demand (read+write) miss cycles
-system.cpu3.icache.overall_miss_latency::cpu3.inst      6449745                       # number of overall miss cycles
-system.cpu3.icache.overall_miss_latency::total      6449745                       # number of overall miss cycles
-system.cpu3.icache.ReadReq_accesses::cpu3.inst        20565                       # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.ReadReq_accesses::total        20565                       # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.demand_accesses::cpu3.inst        20565                       # number of demand (read+write) accesses
-system.cpu3.icache.demand_accesses::total        20565                       # number of demand (read+write) accesses
-system.cpu3.icache.overall_accesses::cpu3.inst        20565                       # number of overall (read+write) accesses
-system.cpu3.icache.overall_accesses::total        20565                       # number of overall (read+write) accesses
-system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.023097                       # miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_miss_rate::total     0.023097                       # miss rate for ReadReq accesses
-system.cpu3.icache.demand_miss_rate::cpu3.inst     0.023097                       # miss rate for demand accesses
-system.cpu3.icache.demand_miss_rate::total     0.023097                       # miss rate for demand accesses
-system.cpu3.icache.overall_miss_rate::cpu3.inst     0.023097                       # miss rate for overall accesses
-system.cpu3.icache.overall_miss_rate::total     0.023097                       # miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13578.410526                       # average ReadReq miss latency
-system.cpu3.icache.ReadReq_avg_miss_latency::total 13578.410526                       # average ReadReq miss latency
-system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13578.410526                       # average overall miss latency
-system.cpu3.icache.demand_avg_miss_latency::total 13578.410526                       # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13578.410526                       # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency::total 13578.410526                       # average overall miss latency
+system.cpu3.icache.ReadReq_miss_latency::cpu3.inst      6525745                       # number of ReadReq miss cycles
+system.cpu3.icache.ReadReq_miss_latency::total      6525745                       # number of ReadReq miss cycles
+system.cpu3.icache.demand_miss_latency::cpu3.inst      6525745                       # number of demand (read+write) miss cycles
+system.cpu3.icache.demand_miss_latency::total      6525745                       # number of demand (read+write) miss cycles
+system.cpu3.icache.overall_miss_latency::cpu3.inst      6525745                       # number of overall miss cycles
+system.cpu3.icache.overall_miss_latency::total      6525745                       # number of overall miss cycles
+system.cpu3.icache.ReadReq_accesses::cpu3.inst        19589                       # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.ReadReq_accesses::total        19589                       # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.demand_accesses::cpu3.inst        19589                       # number of demand (read+write) accesses
+system.cpu3.icache.demand_accesses::total        19589                       # number of demand (read+write) accesses
+system.cpu3.icache.overall_accesses::cpu3.inst        19589                       # number of overall (read+write) accesses
+system.cpu3.icache.overall_accesses::total        19589                       # number of overall (read+write) accesses
+system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.024248                       # miss rate for ReadReq accesses
+system.cpu3.icache.ReadReq_miss_rate::total     0.024248                       # miss rate for ReadReq accesses
+system.cpu3.icache.demand_miss_rate::cpu3.inst     0.024248                       # miss rate for demand accesses
+system.cpu3.icache.demand_miss_rate::total     0.024248                       # miss rate for demand accesses
+system.cpu3.icache.overall_miss_rate::cpu3.inst     0.024248                       # miss rate for overall accesses
+system.cpu3.icache.overall_miss_rate::total     0.024248                       # miss rate for overall accesses
+system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13738.410526                       # average ReadReq miss latency
+system.cpu3.icache.ReadReq_avg_miss_latency::total 13738.410526                       # average ReadReq miss latency
+system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13738.410526                       # average overall miss latency
+system.cpu3.icache.demand_avg_miss_latency::total 13738.410526                       # average overall miss latency
+system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13738.410526                       # average overall miss latency
+system.cpu3.icache.overall_avg_miss_latency::total 13738.410526                       # average overall miss latency
 system.cpu3.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -2493,111 +2516,111 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu3.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu3.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu3.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst           46                       # number of ReadReq MSHR hits
-system.cpu3.icache.ReadReq_mshr_hits::total           46                       # number of ReadReq MSHR hits
-system.cpu3.icache.demand_mshr_hits::cpu3.inst           46                       # number of demand (read+write) MSHR hits
-system.cpu3.icache.demand_mshr_hits::total           46                       # number of demand (read+write) MSHR hits
-system.cpu3.icache.overall_mshr_hits::cpu3.inst           46                       # number of overall MSHR hits
-system.cpu3.icache.overall_mshr_hits::total           46                       # number of overall MSHR hits
-system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst          429                       # number of ReadReq MSHR misses
-system.cpu3.icache.ReadReq_mshr_misses::total          429                       # number of ReadReq MSHR misses
-system.cpu3.icache.demand_mshr_misses::cpu3.inst          429                       # number of demand (read+write) MSHR misses
-system.cpu3.icache.demand_mshr_misses::total          429                       # number of demand (read+write) MSHR misses
-system.cpu3.icache.overall_mshr_misses::cpu3.inst          429                       # number of overall MSHR misses
-system.cpu3.icache.overall_mshr_misses::total          429                       # number of overall MSHR misses
-system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst      5223755                       # number of ReadReq MSHR miss cycles
-system.cpu3.icache.ReadReq_mshr_miss_latency::total      5223755                       # number of ReadReq MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst      5223755                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_latency::total      5223755                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst      5223755                       # number of overall MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_latency::total      5223755                       # number of overall MSHR miss cycles
-system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.020861                       # mshr miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_mshr_miss_rate::total     0.020861                       # mshr miss rate for ReadReq accesses
-system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst     0.020861                       # mshr miss rate for demand accesses
-system.cpu3.icache.demand_mshr_miss_rate::total     0.020861                       # mshr miss rate for demand accesses
-system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst     0.020861                       # mshr miss rate for overall accesses
-system.cpu3.icache.overall_mshr_miss_rate::total     0.020861                       # mshr miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12176.585082                       # average ReadReq mshr miss latency
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12176.585082                       # average ReadReq mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12176.585082                       # average overall mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency::total 12176.585082                       # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12176.585082                       # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency::total 12176.585082                       # average overall mshr miss latency
+system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst           45                       # number of ReadReq MSHR hits
+system.cpu3.icache.ReadReq_mshr_hits::total           45                       # number of ReadReq MSHR hits
+system.cpu3.icache.demand_mshr_hits::cpu3.inst           45                       # number of demand (read+write) MSHR hits
+system.cpu3.icache.demand_mshr_hits::total           45                       # number of demand (read+write) MSHR hits
+system.cpu3.icache.overall_mshr_hits::cpu3.inst           45                       # number of overall MSHR hits
+system.cpu3.icache.overall_mshr_hits::total           45                       # number of overall MSHR hits
+system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst          430                       # number of ReadReq MSHR misses
+system.cpu3.icache.ReadReq_mshr_misses::total          430                       # number of ReadReq MSHR misses
+system.cpu3.icache.demand_mshr_misses::cpu3.inst          430                       # number of demand (read+write) MSHR misses
+system.cpu3.icache.demand_mshr_misses::total          430                       # number of demand (read+write) MSHR misses
+system.cpu3.icache.overall_mshr_misses::cpu3.inst          430                       # number of overall MSHR misses
+system.cpu3.icache.overall_mshr_misses::total          430                       # number of overall MSHR misses
+system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst      5298255                       # number of ReadReq MSHR miss cycles
+system.cpu3.icache.ReadReq_mshr_miss_latency::total      5298255                       # number of ReadReq MSHR miss cycles
+system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst      5298255                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.icache.demand_mshr_miss_latency::total      5298255                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst      5298255                       # number of overall MSHR miss cycles
+system.cpu3.icache.overall_mshr_miss_latency::total      5298255                       # number of overall MSHR miss cycles
+system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.021951                       # mshr miss rate for ReadReq accesses
+system.cpu3.icache.ReadReq_mshr_miss_rate::total     0.021951                       # mshr miss rate for ReadReq accesses
+system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst     0.021951                       # mshr miss rate for demand accesses
+system.cpu3.icache.demand_mshr_miss_rate::total     0.021951                       # mshr miss rate for demand accesses
+system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst     0.021951                       # mshr miss rate for overall accesses
+system.cpu3.icache.overall_mshr_miss_rate::total     0.021951                       # mshr miss rate for overall accesses
+system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12321.523256                       # average ReadReq mshr miss latency
+system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12321.523256                       # average ReadReq mshr miss latency
+system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12321.523256                       # average overall mshr miss latency
+system.cpu3.icache.demand_avg_mshr_miss_latency::total 12321.523256                       # average overall mshr miss latency
+system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12321.523256                       # average overall mshr miss latency
+system.cpu3.icache.overall_avg_mshr_miss_latency::total 12321.523256                       # average overall mshr miss latency
 system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu3.dcache.tags.replacements                0                       # number of replacements
-system.cpu3.dcache.tags.tagsinuse           24.692248                       # Cycle average of tags in use
-system.cpu3.dcache.tags.total_refs              42769                       # Total number of references to valid blocks.
+system.cpu3.dcache.tags.tagsinuse           24.751493                       # Cycle average of tags in use
+system.cpu3.dcache.tags.total_refs              44991                       # Total number of references to valid blocks.
 system.cpu3.dcache.tags.sampled_refs               28                       # Sample count of references to valid blocks.
-system.cpu3.dcache.tags.avg_refs          1527.464286                       # Average number of references to valid blocks.
+system.cpu3.dcache.tags.avg_refs          1606.821429                       # Average number of references to valid blocks.
 system.cpu3.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu3.dcache.tags.occ_blocks::cpu3.data    24.692248                       # Average occupied blocks per requestor
-system.cpu3.dcache.tags.occ_percent::cpu3.data     0.048227                       # Average percentage of cache occupancy
-system.cpu3.dcache.tags.occ_percent::total     0.048227                       # Average percentage of cache occupancy
+system.cpu3.dcache.tags.occ_blocks::cpu3.data    24.751493                       # Average occupied blocks per requestor
+system.cpu3.dcache.tags.occ_percent::cpu3.data     0.048343                       # Average percentage of cache occupancy
+system.cpu3.dcache.tags.occ_percent::total     0.048343                       # Average percentage of cache occupancy
 system.cpu3.dcache.tags.occ_task_id_blocks::1024           28                       # Occupied blocks per task id
 system.cpu3.dcache.tags.age_task_id_blocks_1024::1           28                       # Occupied blocks per task id
 system.cpu3.dcache.tags.occ_task_id_percent::1024     0.054688                       # Percentage of cache occupancy per task id
-system.cpu3.dcache.tags.tag_accesses           335202                       # Number of tag accesses
-system.cpu3.dcache.tags.data_accesses          335202                       # Number of data accesses
-system.cpu3.dcache.ReadReq_hits::cpu3.data        46656                       # number of ReadReq hits
-system.cpu3.dcache.ReadReq_hits::total          46656                       # number of ReadReq hits
-system.cpu3.dcache.WriteReq_hits::cpu3.data        36553                       # number of WriteReq hits
-system.cpu3.dcache.WriteReq_hits::total         36553                       # number of WriteReq hits
-system.cpu3.dcache.SwapReq_hits::cpu3.data           14                       # number of SwapReq hits
-system.cpu3.dcache.SwapReq_hits::total             14                       # number of SwapReq hits
-system.cpu3.dcache.demand_hits::cpu3.data        83209                       # number of demand (read+write) hits
-system.cpu3.dcache.demand_hits::total           83209                       # number of demand (read+write) hits
-system.cpu3.dcache.overall_hits::cpu3.data        83209                       # number of overall hits
-system.cpu3.dcache.overall_hits::total          83209                       # number of overall hits
-system.cpu3.dcache.ReadReq_misses::cpu3.data          333                       # number of ReadReq misses
-system.cpu3.dcache.ReadReq_misses::total          333                       # number of ReadReq misses
-system.cpu3.dcache.WriteReq_misses::cpu3.data          131                       # number of WriteReq misses
-system.cpu3.dcache.WriteReq_misses::total          131                       # number of WriteReq misses
-system.cpu3.dcache.SwapReq_misses::cpu3.data           54                       # number of SwapReq misses
-system.cpu3.dcache.SwapReq_misses::total           54                       # number of SwapReq misses
-system.cpu3.dcache.demand_misses::cpu3.data          464                       # number of demand (read+write) misses
-system.cpu3.dcache.demand_misses::total           464                       # number of demand (read+write) misses
-system.cpu3.dcache.overall_misses::cpu3.data          464                       # number of overall misses
-system.cpu3.dcache.overall_misses::total          464                       # number of overall misses
-system.cpu3.dcache.ReadReq_miss_latency::cpu3.data      4248100                       # number of ReadReq miss cycles
-system.cpu3.dcache.ReadReq_miss_latency::total      4248100                       # number of ReadReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency::cpu3.data      3351512                       # number of WriteReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency::total      3351512                       # number of WriteReq miss cycles
-system.cpu3.dcache.SwapReq_miss_latency::cpu3.data       492006                       # number of SwapReq miss cycles
-system.cpu3.dcache.SwapReq_miss_latency::total       492006                       # number of SwapReq miss cycles
-system.cpu3.dcache.demand_miss_latency::cpu3.data      7599612                       # number of demand (read+write) miss cycles
-system.cpu3.dcache.demand_miss_latency::total      7599612                       # number of demand (read+write) miss cycles
-system.cpu3.dcache.overall_miss_latency::cpu3.data      7599612                       # number of overall miss cycles
-system.cpu3.dcache.overall_miss_latency::total      7599612                       # number of overall miss cycles
-system.cpu3.dcache.ReadReq_accesses::cpu3.data        46989                       # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.ReadReq_accesses::total        46989                       # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::cpu3.data        36684                       # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::total        36684                       # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.SwapReq_accesses::cpu3.data           68                       # number of SwapReq accesses(hits+misses)
-system.cpu3.dcache.SwapReq_accesses::total           68                       # number of SwapReq accesses(hits+misses)
-system.cpu3.dcache.demand_accesses::cpu3.data        83673                       # number of demand (read+write) accesses
-system.cpu3.dcache.demand_accesses::total        83673                       # number of demand (read+write) accesses
-system.cpu3.dcache.overall_accesses::cpu3.data        83673                       # number of overall (read+write) accesses
-system.cpu3.dcache.overall_accesses::total        83673                       # number of overall (read+write) accesses
-system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.007087                       # miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_miss_rate::total     0.007087                       # miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.003571                       # miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_miss_rate::total     0.003571                       # miss rate for WriteReq accesses
-system.cpu3.dcache.SwapReq_miss_rate::cpu3.data     0.794118                       # miss rate for SwapReq accesses
-system.cpu3.dcache.SwapReq_miss_rate::total     0.794118                       # miss rate for SwapReq accesses
-system.cpu3.dcache.demand_miss_rate::cpu3.data     0.005545                       # miss rate for demand accesses
-system.cpu3.dcache.demand_miss_rate::total     0.005545                       # miss rate for demand accesses
-system.cpu3.dcache.overall_miss_rate::cpu3.data     0.005545                       # miss rate for overall accesses
-system.cpu3.dcache.overall_miss_rate::total     0.005545                       # miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12757.057057                       # average ReadReq miss latency
-system.cpu3.dcache.ReadReq_avg_miss_latency::total 12757.057057                       # average ReadReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 25584.061069                       # average WriteReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::total 25584.061069                       # average WriteReq miss latency
-system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data  9111.222222                       # average SwapReq miss latency
-system.cpu3.dcache.SwapReq_avg_miss_latency::total  9111.222222                       # average SwapReq miss latency
-system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 16378.474138                       # average overall miss latency
-system.cpu3.dcache.demand_avg_miss_latency::total 16378.474138                       # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 16378.474138                       # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::total 16378.474138                       # average overall miss latency
+system.cpu3.dcache.tags.tag_accesses           350966                       # Number of tag accesses
+system.cpu3.dcache.tags.data_accesses          350966                       # Number of data accesses
+system.cpu3.dcache.ReadReq_hits::cpu3.data        48333                       # number of ReadReq hits
+system.cpu3.dcache.ReadReq_hits::total          48333                       # number of ReadReq hits
+system.cpu3.dcache.WriteReq_hits::cpu3.data        38794                       # number of WriteReq hits
+system.cpu3.dcache.WriteReq_hits::total         38794                       # number of WriteReq hits
+system.cpu3.dcache.SwapReq_hits::cpu3.data           12                       # number of SwapReq hits
+system.cpu3.dcache.SwapReq_hits::total             12                       # number of SwapReq hits
+system.cpu3.dcache.demand_hits::cpu3.data        87127                       # number of demand (read+write) hits
+system.cpu3.dcache.demand_hits::total           87127                       # number of demand (read+write) hits
+system.cpu3.dcache.overall_hits::cpu3.data        87127                       # number of overall hits
+system.cpu3.dcache.overall_hits::total          87127                       # number of overall hits
+system.cpu3.dcache.ReadReq_misses::cpu3.data          351                       # number of ReadReq misses
+system.cpu3.dcache.ReadReq_misses::total          351                       # number of ReadReq misses
+system.cpu3.dcache.WriteReq_misses::cpu3.data          139                       # number of WriteReq misses
+system.cpu3.dcache.WriteReq_misses::total          139                       # number of WriteReq misses
+system.cpu3.dcache.SwapReq_misses::cpu3.data           52                       # number of SwapReq misses
+system.cpu3.dcache.SwapReq_misses::total           52                       # number of SwapReq misses
+system.cpu3.dcache.demand_misses::cpu3.data          490                       # number of demand (read+write) misses
+system.cpu3.dcache.demand_misses::total           490                       # number of demand (read+write) misses
+system.cpu3.dcache.overall_misses::cpu3.data          490                       # number of overall misses
+system.cpu3.dcache.overall_misses::total          490                       # number of overall misses
+system.cpu3.dcache.ReadReq_miss_latency::cpu3.data      4639136                       # number of ReadReq miss cycles
+system.cpu3.dcache.ReadReq_miss_latency::total      4639136                       # number of ReadReq miss cycles
+system.cpu3.dcache.WriteReq_miss_latency::cpu3.data      3479012                       # number of WriteReq miss cycles
+system.cpu3.dcache.WriteReq_miss_latency::total      3479012                       # number of WriteReq miss cycles
+system.cpu3.dcache.SwapReq_miss_latency::cpu3.data       512008                       # number of SwapReq miss cycles
+system.cpu3.dcache.SwapReq_miss_latency::total       512008                       # number of SwapReq miss cycles
+system.cpu3.dcache.demand_miss_latency::cpu3.data      8118148                       # number of demand (read+write) miss cycles
+system.cpu3.dcache.demand_miss_latency::total      8118148                       # number of demand (read+write) miss cycles
+system.cpu3.dcache.overall_miss_latency::cpu3.data      8118148                       # number of overall miss cycles
+system.cpu3.dcache.overall_miss_latency::total      8118148                       # number of overall miss cycles
+system.cpu3.dcache.ReadReq_accesses::cpu3.data        48684                       # number of ReadReq accesses(hits+misses)
+system.cpu3.dcache.ReadReq_accesses::total        48684                       # number of ReadReq accesses(hits+misses)
+system.cpu3.dcache.WriteReq_accesses::cpu3.data        38933                       # number of WriteReq accesses(hits+misses)
+system.cpu3.dcache.WriteReq_accesses::total        38933                       # number of WriteReq accesses(hits+misses)
+system.cpu3.dcache.SwapReq_accesses::cpu3.data           64                       # number of SwapReq accesses(hits+misses)
+system.cpu3.dcache.SwapReq_accesses::total           64                       # number of SwapReq accesses(hits+misses)
+system.cpu3.dcache.demand_accesses::cpu3.data        87617                       # number of demand (read+write) accesses
+system.cpu3.dcache.demand_accesses::total        87617                       # number of demand (read+write) accesses
+system.cpu3.dcache.overall_accesses::cpu3.data        87617                       # number of overall (read+write) accesses
+system.cpu3.dcache.overall_accesses::total        87617                       # number of overall (read+write) accesses
+system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.007210                       # miss rate for ReadReq accesses
+system.cpu3.dcache.ReadReq_miss_rate::total     0.007210                       # miss rate for ReadReq accesses
+system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.003570                       # miss rate for WriteReq accesses
+system.cpu3.dcache.WriteReq_miss_rate::total     0.003570                       # miss rate for WriteReq accesses
+system.cpu3.dcache.SwapReq_miss_rate::cpu3.data     0.812500                       # miss rate for SwapReq accesses
+system.cpu3.dcache.SwapReq_miss_rate::total     0.812500                       # miss rate for SwapReq accesses
+system.cpu3.dcache.demand_miss_rate::cpu3.data     0.005593                       # miss rate for demand accesses
+system.cpu3.dcache.demand_miss_rate::total     0.005593                       # miss rate for demand accesses
+system.cpu3.dcache.overall_miss_rate::cpu3.data     0.005593                       # miss rate for overall accesses
+system.cpu3.dcache.overall_miss_rate::total     0.005593                       # miss rate for overall accesses
+system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 13216.911681                       # average ReadReq miss latency
+system.cpu3.dcache.ReadReq_avg_miss_latency::total 13216.911681                       # average ReadReq miss latency
+system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 25028.863309                       # average WriteReq miss latency
+system.cpu3.dcache.WriteReq_avg_miss_latency::total 25028.863309                       # average WriteReq miss latency
+system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data  9846.307692                       # average SwapReq miss latency
+system.cpu3.dcache.SwapReq_avg_miss_latency::total  9846.307692                       # average SwapReq miss latency
+system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 16567.648980                       # average overall miss latency
+system.cpu3.dcache.demand_avg_miss_latency::total 16567.648980                       # average overall miss latency
+system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 16567.648980                       # average overall miss latency
+system.cpu3.dcache.overall_avg_miss_latency::total 16567.648980                       # average overall miss latency
 system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -2606,54 +2629,54 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu3.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu3.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data          181                       # number of ReadReq MSHR hits
-system.cpu3.dcache.ReadReq_mshr_hits::total          181                       # number of ReadReq MSHR hits
-system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data           31                       # number of WriteReq MSHR hits
-system.cpu3.dcache.WriteReq_mshr_hits::total           31                       # number of WriteReq MSHR hits
-system.cpu3.dcache.demand_mshr_hits::cpu3.data          212                       # number of demand (read+write) MSHR hits
-system.cpu3.dcache.demand_mshr_hits::total          212                       # number of demand (read+write) MSHR hits
-system.cpu3.dcache.overall_mshr_hits::cpu3.data          212                       # number of overall MSHR hits
-system.cpu3.dcache.overall_mshr_hits::total          212                       # number of overall MSHR hits
-system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data          152                       # number of ReadReq MSHR misses
-system.cpu3.dcache.ReadReq_mshr_misses::total          152                       # number of ReadReq MSHR misses
-system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data          100                       # number of WriteReq MSHR misses
-system.cpu3.dcache.WriteReq_mshr_misses::total          100                       # number of WriteReq MSHR misses
-system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data           54                       # number of SwapReq MSHR misses
-system.cpu3.dcache.SwapReq_mshr_misses::total           54                       # number of SwapReq MSHR misses
-system.cpu3.dcache.demand_mshr_misses::cpu3.data          252                       # number of demand (read+write) MSHR misses
-system.cpu3.dcache.demand_mshr_misses::total          252                       # number of demand (read+write) MSHR misses
-system.cpu3.dcache.overall_mshr_misses::cpu3.data          252                       # number of overall MSHR misses
-system.cpu3.dcache.overall_mshr_misses::total          252                       # number of overall MSHR misses
-system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data      1002524                       # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.ReadReq_mshr_miss_latency::total      1002524                       # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data      1408238                       # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_latency::total      1408238                       # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data       383994                       # number of SwapReq MSHR miss cycles
-system.cpu3.dcache.SwapReq_mshr_miss_latency::total       383994                       # number of SwapReq MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data      2410762                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_latency::total      2410762                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data      2410762                       # number of overall MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency::total      2410762                       # number of overall MSHR miss cycles
-system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.003235                       # mshr miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_mshr_miss_rate::total     0.003235                       # mshr miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.002726                       # mshr miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_mshr_miss_rate::total     0.002726                       # mshr miss rate for WriteReq accesses
-system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data     0.794118                       # mshr miss rate for SwapReq accesses
-system.cpu3.dcache.SwapReq_mshr_miss_rate::total     0.794118                       # mshr miss rate for SwapReq accesses
-system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data     0.003012                       # mshr miss rate for demand accesses
-system.cpu3.dcache.demand_mshr_miss_rate::total     0.003012                       # mshr miss rate for demand accesses
-system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data     0.003012                       # mshr miss rate for overall accesses
-system.cpu3.dcache.overall_mshr_miss_rate::total     0.003012                       # mshr miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data  6595.552632                       # average ReadReq mshr miss latency
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total  6595.552632                       # average ReadReq mshr miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 14082.380000                       # average WriteReq mshr miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 14082.380000                       # average WriteReq mshr miss latency
-system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data         7111                       # average SwapReq mshr miss latency
-system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total         7111                       # average SwapReq mshr miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data  9566.515873                       # average overall mshr miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency::total  9566.515873                       # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data  9566.515873                       # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency::total  9566.515873                       # average overall mshr miss latency
+system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data          197                       # number of ReadReq MSHR hits
+system.cpu3.dcache.ReadReq_mshr_hits::total          197                       # number of ReadReq MSHR hits
+system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data           33                       # number of WriteReq MSHR hits
+system.cpu3.dcache.WriteReq_mshr_hits::total           33                       # number of WriteReq MSHR hits
+system.cpu3.dcache.demand_mshr_hits::cpu3.data          230                       # number of demand (read+write) MSHR hits
+system.cpu3.dcache.demand_mshr_hits::total          230                       # number of demand (read+write) MSHR hits
+system.cpu3.dcache.overall_mshr_hits::cpu3.data          230                       # number of overall MSHR hits
+system.cpu3.dcache.overall_mshr_hits::total          230                       # number of overall MSHR hits
+system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data          154                       # number of ReadReq MSHR misses
+system.cpu3.dcache.ReadReq_mshr_misses::total          154                       # number of ReadReq MSHR misses
+system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data          106                       # number of WriteReq MSHR misses
+system.cpu3.dcache.WriteReq_mshr_misses::total          106                       # number of WriteReq MSHR misses
+system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data           52                       # number of SwapReq MSHR misses
+system.cpu3.dcache.SwapReq_mshr_misses::total           52                       # number of SwapReq MSHR misses
+system.cpu3.dcache.demand_mshr_misses::cpu3.data          260                       # number of demand (read+write) MSHR misses
+system.cpu3.dcache.demand_mshr_misses::total          260                       # number of demand (read+write) MSHR misses
+system.cpu3.dcache.overall_mshr_misses::cpu3.data          260                       # number of overall MSHR misses
+system.cpu3.dcache.overall_mshr_misses::total          260                       # number of overall MSHR misses
+system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data      1051018                       # number of ReadReq MSHR miss cycles
+system.cpu3.dcache.ReadReq_mshr_miss_latency::total      1051018                       # number of ReadReq MSHR miss cycles
+system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data      1439238                       # number of WriteReq MSHR miss cycles
+system.cpu3.dcache.WriteReq_mshr_miss_latency::total      1439238                       # number of WriteReq MSHR miss cycles
+system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data       407992                       # number of SwapReq MSHR miss cycles
+system.cpu3.dcache.SwapReq_mshr_miss_latency::total       407992                       # number of SwapReq MSHR miss cycles
+system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data      2490256                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.dcache.demand_mshr_miss_latency::total      2490256                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data      2490256                       # number of overall MSHR miss cycles
+system.cpu3.dcache.overall_mshr_miss_latency::total      2490256                       # number of overall MSHR miss cycles
+system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.003163                       # mshr miss rate for ReadReq accesses
+system.cpu3.dcache.ReadReq_mshr_miss_rate::total     0.003163                       # mshr miss rate for ReadReq accesses
+system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.002723                       # mshr miss rate for WriteReq accesses
+system.cpu3.dcache.WriteReq_mshr_miss_rate::total     0.002723                       # mshr miss rate for WriteReq accesses
+system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data     0.812500                       # mshr miss rate for SwapReq accesses
+system.cpu3.dcache.SwapReq_mshr_miss_rate::total     0.812500                       # mshr miss rate for SwapReq accesses
+system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data     0.002967                       # mshr miss rate for demand accesses
+system.cpu3.dcache.demand_mshr_miss_rate::total     0.002967                       # mshr miss rate for demand accesses
+system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data     0.002967                       # mshr miss rate for overall accesses
+system.cpu3.dcache.overall_mshr_miss_rate::total     0.002967                       # mshr miss rate for overall accesses
+system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data  6824.792208                       # average ReadReq mshr miss latency
+system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total  6824.792208                       # average ReadReq mshr miss latency
+system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 13577.716981                       # average WriteReq mshr miss latency
+system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 13577.716981                       # average WriteReq mshr miss latency
+system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data         7846                       # average SwapReq mshr miss latency
+system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total         7846                       # average SwapReq mshr miss latency
+system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data  9577.907692                       # average overall mshr miss latency
+system.cpu3.dcache.demand_avg_mshr_miss_latency::total  9577.907692                       # average overall mshr miss latency
+system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data  9577.907692                       # average overall mshr miss latency
+system.cpu3.dcache.overall_avg_mshr_miss_latency::total  9577.907692                       # average overall mshr miss latency
 system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 9a5e1cab06472b86c8264dbbedd811709ab174af..c44d33a13b7462b092b425ebffd2685047c42c66 100644 (file)
@@ -4,9 +4,9 @@ sim_seconds                                  0.100000                       # Nu
 sim_ticks                                100000000000                       # Number of ticks simulated
 final_tick                               100000000000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_tick_rate                            33856013702                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 195468                       # Number of bytes of host memory used
-host_seconds                                     2.95                       # Real time elapsed on the host
+host_tick_rate                            24940417343                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 228644                       # Number of bytes of host memory used
+host_seconds                                     4.01                       # Real time elapsed on the host
 system.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu              213331136                       # Number of bytes read from this memory
@@ -78,18 +78,18 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   3150208                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     42074                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                   2967921                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    224361                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                     12823                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     16917                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     15990                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                     17049                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                     12952                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                     13879                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                     17179                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                     12823                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                     16917                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                     15990                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::9                     17049                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::10                    12820                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                     4489                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                     5416                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
@@ -142,118 +142,51 @@ system.physmem.wrQLenPdf::28                        0                       # Wh
 system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        38918                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean     5478.771982                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean    4240.637477                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev    2732.249719                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64-65            284      0.73%      0.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-129          264      0.68%      1.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192-193          268      0.69%      2.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320-321          268      0.69%      2.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-385          266      0.68%      3.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448-449          271      0.70%      4.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576-577          268      0.69%      4.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-641          264      0.68%      5.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704-705          268      0.69%      6.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832-833          270      0.69%      6.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-897          267      0.69%      7.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960-961          268      0.69%      8.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088-1089          268      0.69%      8.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152-1153          264      0.68%      9.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216-1217          270      0.69%     10.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280-1281            3      0.01%     10.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344-1345          268      0.69%     11.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408-1409          264      0.68%     11.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472-1473          268      0.69%     12.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600-1601          268      0.69%     13.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664-1665          267      0.69%     13.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1728-1729          271      0.70%     14.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856-1857          268      0.69%     15.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1920-1921          264      0.68%     15.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984-1985          268      0.69%     16.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112-2113          271      0.70%     17.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2176-2177          266      0.68%     17.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2240-2241          268      0.69%     18.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2368-2369          268      0.69%     19.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2432-2433          264      0.68%     19.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2496-2497          271      0.70%     20.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2560-2561            2      0.01%     20.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2624-2625          268      0.69%     21.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2688-2689          264      0.68%     22.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2752-2753          268      0.69%     22.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2880-2881          268      0.69%     23.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2944-2945          267      0.69%     24.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3008-3009          270      0.69%     24.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3136-3137          268      0.69%     25.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3200-3201          264      0.68%     26.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3264-3265          268      0.69%     26.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3392-3393          349      0.90%     27.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3456-3457          264      0.68%     28.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3520-3521          268      0.69%     29.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3648-3649          268      0.69%     29.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3712-3713          264      0.68%     30.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3776-3777          268      0.69%     31.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3904-3905          268      0.69%     31.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3968-3969          264      0.68%     32.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4032-4033          268      0.69%     33.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4160-4161          268      0.69%     33.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4224-4225          264      0.68%     34.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4288-4289          268      0.69%     35.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4416-4417          268      0.69%     35.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4480-4481          264      0.68%     36.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4544-4545          268      0.69%     37.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4672-4673          268      0.69%     38.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4736-4737          264      0.68%     38.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4800-4801          268      0.69%     39.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4928-4929          268      0.69%     40.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4992-4993          264      0.68%     40.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5056-5057          268      0.69%     41.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5184-5185          267      0.69%     42.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5248-5249          264      0.68%     42.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5312-5313          268      0.69%     43.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5440-5441          267      0.69%     44.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5504-5505          264      0.68%     44.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5568-5569          268      0.69%     45.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5696-5697          267      0.69%     46.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5760-5761          264      0.68%     46.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5824-5825          268      0.69%     47.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::5952-5953          267      0.69%     48.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6016-6017          264      0.68%     48.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6080-6081          268      0.69%     49.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6208-6209          267      0.69%     50.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6272-6273          264      0.68%     51.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6336-6337          268      0.69%     51.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6464-6465          267      0.69%     52.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6528-6529          264      0.68%     53.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6592-6593          268      0.69%     53.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6720-6721          267      0.69%     54.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6784-6785          264      0.68%     55.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6848-6849          268      0.69%     55.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6976-6977          267      0.69%     56.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7040-7041          264      0.68%     57.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7104-7105          268      0.69%     57.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7232-7233          268      0.69%     58.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7296-7297          264      0.68%     59.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7360-7361          268      0.69%     59.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7488-7489          268      0.69%     60.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7552-7553          264      0.68%     61.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7616-7617          268      0.69%     61.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7744-7745          268      0.69%     62.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7808-7809          264      0.68%     63.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7872-7873          268      0.69%     64.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8000-8001          268      0.69%     64.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8064-8065          264      0.68%     65.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8128-8129          268      0.69%     66.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8192-8193        13193     33.90%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          38918                       # Bytes accessed per row activation
-system.physmem.totQLat                    27766345550                       # Total ticks spent queuing
-system.physmem.totMemAccLat               88702111800                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples       195487                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean            1024                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean    1024.000000                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151       195487    100.00%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         195487                       # Bytes accessed per row activation
+system.physmem.totQLat                    27932046800                       # Total ticks spent queuing
+system.physmem.totMemAccLat               91374259300                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                  16666500000                       # Total ticks spent in databus transfers
-system.physmem.totBankLat                 44269266250                       # Total ticks spent accessing banks
-system.physmem.avgQLat                        8329.99                       # Average queueing delay per DRAM burst
-system.physmem.avgBankLat                    13280.91                       # Average bank access latency per DRAM burst
+system.physmem.totBankLat                 46775712500                       # Total ticks spent accessing banks
+system.physmem.avgQLat                        8379.70                       # Average queueing delay per DRAM burst
+system.physmem.avgBankLat                    14032.85                       # Average bank access latency per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  26610.90                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  27412.55                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                        2133.31                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                     2133.31                       # Average system read bandwidth in MiByte/s
@@ -262,15 +195,15 @@ system.physmem.peakBW                        12800.00                       # Th
 system.physmem.busUtil                          16.67                       # Data bus utilization in percentage
 system.physmem.busUtilRead                      16.67                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         0.89                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.33                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                    3294382                       # Number of row buffer hits during reads
+system.physmem.readRowHits                    3112095                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   98.83                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   93.36                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
 system.physmem.avgGap                        30000.29                       # Average gap between requests
-system.physmem.pageHitRate                      98.83                       # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent               0.00                       # Percentage of time for which DRAM has all the banks in precharge state
+system.physmem.pageHitRate                      93.36                       # Row buffer hit rate, read and write combined
+system.physmem.prechargeAllPercent               0.11                       # Percentage of time for which DRAM has all the banks in precharge state
 system.membus.throughput                   2133311360                       # Throughput (bytes/s)
 system.membus.trans_dist::ReadReq             3333300                       # Transaction distribution
 system.membus.trans_dist::ReadResp            3333299                       # Transaction distribution
@@ -281,7 +214,7 @@ system.membus.tot_pkt_size::total           213331136                       # Cu
 system.membus.data_through_bus              213331136                       # Total data (bytes)
 system.membus.reqLayer0.occupancy          6333270000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               6.3                       # Layer utilization (%)
-system.membus.respLayer0.occupancy        17154822550                       # Layer occupancy (ticks)
+system.membus.respLayer0.occupancy        17200626050                       # Layer occupancy (ticks)
 system.membus.respLayer0.utilization             17.2                       # Layer utilization (%)
 system.monitor.readBurstLengthHist::samples      3333300                       # Histogram of burst lengths of transmitted packets
 system.monitor.readBurstLengthHist::mean           64                       # Histogram of burst lengths of transmitted packets
@@ -335,8 +268,8 @@ system.monitor.writeBurstLengthHist::19             0                       # Hi
 system.monitor.writeBurstLengthHist::total            0                       # Histogram of burst lengths of transmitted packets
 system.monitor.readBandwidthHist::samples          100                       # Histogram of read bandwidth per sample period (bytes/s)
 system.monitor.readBandwidthHist::mean     2133311360                       # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::gmean  2133311357.398473                       # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::stdev  105886.111402                       # Histogram of read bandwidth per sample period (bytes/s)
+system.monitor.readBandwidthHist::gmean  2133311357.360062                       # Histogram of read bandwidth per sample period (bytes/s)
+system.monitor.readBandwidthHist::stdev  106664.726883                       # Histogram of read bandwidth per sample period (bytes/s)
 system.monitor.readBandwidthHist::0-1.34218e+08            0      0.00%      0.00% # Histogram of read bandwidth per sample period (bytes/s)
 system.monitor.readBandwidthHist::1.34218e+08-2.68435e+08            0      0.00%      0.00% # Histogram of read bandwidth per sample period (bytes/s)
 system.monitor.readBandwidthHist::2.68435e+08-4.02653e+08            0      0.00%      0.00% # Histogram of read bandwidth per sample period (bytes/s)
@@ -388,19 +321,19 @@ system.monitor.writeBandwidthHist::total          100                       # Hi
 system.monitor.averageWriteBandwidth                0                       # Average write bandwidth (bytes/s)
 system.monitor.totalWrittenBytes                    0                       # Number of bytes written
 system.monitor.readLatencyHist::samples       3333299                       # Read request-response latency
-system.monitor.readLatencyHist::mean     46636.264419                       # Read request-response latency
-system.monitor.readLatencyHist::gmean    41775.198419                       # Read request-response latency
-system.monitor.readLatencyHist::stdev    39874.537130                       # Read request-response latency
+system.monitor.readLatencyHist::mean     47438.751234                       # Read request-response latency
+system.monitor.readLatencyHist::gmean    42490.722724                       # Read request-response latency
+system.monitor.readLatencyHist::stdev    40033.411924                       # Read request-response latency
 system.monitor.readLatencyHist::0-32767             0      0.00%      0.00% # Read request-response latency
-system.monitor.readLatencyHist::32768-65535      3183561     95.51%     95.51% # Read request-response latency
-system.monitor.readLatencyHist::65536-98303        17049      0.51%     96.02% # Read request-response latency
-system.monitor.readLatencyHist::98304-131071        17311      0.52%     96.54% # Read request-response latency
-system.monitor.readLatencyHist::131072-163839        16920      0.51%     97.05% # Read request-response latency
-system.monitor.readLatencyHist::163840-196607        17049      0.51%     97.56% # Read request-response latency
-system.monitor.readLatencyHist::196608-229375        17311      0.52%     98.08% # Read request-response latency
-system.monitor.readLatencyHist::229376-262143        16917      0.51%     98.58% # Read request-response latency
-system.monitor.readLatencyHist::262144-294911        17052      0.51%     99.10% # Read request-response latency
-system.monitor.readLatencyHist::294912-327679        12954      0.39%     99.48% # Read request-response latency
+system.monitor.readLatencyHist::32768-65535      3182634     95.48%     95.48% # Read request-response latency
+system.monitor.readLatencyHist::65536-98303        17049      0.51%     95.99% # Read request-response latency
+system.monitor.readLatencyHist::98304-131071        18238      0.55%     96.54% # Read request-response latency
+system.monitor.readLatencyHist::131072-163839        15993      0.48%     97.02% # Read request-response latency
+system.monitor.readLatencyHist::163840-196607        17049      0.51%     97.53% # Read request-response latency
+system.monitor.readLatencyHist::196608-229375        18238      0.55%     98.08% # Read request-response latency
+system.monitor.readLatencyHist::229376-262143        15990      0.48%     98.56% # Read request-response latency
+system.monitor.readLatencyHist::262144-294911        17052      0.51%     99.07% # Read request-response latency
+system.monitor.readLatencyHist::294912-327679        13881      0.42%     99.48% # Read request-response latency
 system.monitor.readLatencyHist::327680-360447        17175      0.52%    100.00% # Read request-response latency
 system.monitor.readLatencyHist::360448-393215            0      0.00%    100.00% # Read request-response latency
 system.monitor.readLatencyHist::393216-425983            0      0.00%    100.00% # Read request-response latency
@@ -522,12 +455,12 @@ system.monitor.ittReqReq::min_value             30000                       # Re
 system.monitor.ittReqReq::max_value             40000                       # Request-to-request inter transaction time
 system.monitor.ittReqReq::total               3333299                       # Request-to-request inter transaction time
 system.monitor.outstandingReadsHist::samples          100                       # Outstanding read transactions
-system.monitor.outstandingReadsHist::mean     1.270000                       # Outstanding read transactions
-system.monitor.outstandingReadsHist::gmean     1.105133                       # Outstanding read transactions
-system.monitor.outstandingReadsHist::stdev     1.135782                       # Outstanding read transactions
+system.monitor.outstandingReadsHist::mean     1.290000                       # Outstanding read transactions
+system.monitor.outstandingReadsHist::gmean     1.120561                       # Outstanding read transactions
+system.monitor.outstandingReadsHist::stdev     1.139688                       # Outstanding read transactions
 system.monitor.outstandingReadsHist::0              0      0.00%      0.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::1             94     94.00%     94.00% # Outstanding read transactions
-system.monitor.outstandingReadsHist::2              0      0.00%     94.00% # Outstanding read transactions
+system.monitor.outstandingReadsHist::1             92     92.00%     92.00% # Outstanding read transactions
+system.monitor.outstandingReadsHist::2              2      2.00%     94.00% # Outstanding read transactions
 system.monitor.outstandingReadsHist::3              0      0.00%     94.00% # Outstanding read transactions
 system.monitor.outstandingReadsHist::4              3      3.00%     97.00% # Outstanding read transactions
 system.monitor.outstandingReadsHist::5              0      0.00%     97.00% # Outstanding read transactions